From nobody Wed Apr 15 01:30:11 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3857C19F2C for ; Thu, 28 Jul 2022 14:53:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232604AbiG1OxJ (ORCPT ); Thu, 28 Jul 2022 10:53:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60932 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232246AbiG1OxF (ORCPT ); Thu, 28 Jul 2022 10:53:05 -0400 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::223]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 579236050A; Thu, 28 Jul 2022 07:53:02 -0700 (PDT) Received: (Authenticated sender: maxime.chevallier@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 0114760004; Thu, 28 Jul 2022 14:52:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1659019980; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9EcP+9/stfB5EXECkZZmXmTw+rS+fOUz4yGICEAjfH8=; b=KzhElMPONR6+NIurGD5gkalAb09py/fu3eojj4JomY45vNUMiCL22n14frh3xePoj1IUkJ t5IYFf0kTkDfsl2esrdkLFHjuWZld120suUITNrcjTsiSvFv9AmCXTjTqPDnAfHP5CZD6C SqcK6ZmVICBrU6HfSnxXX3rQTjXZ//B3xpERrYJkN1yHKDUSD3abCfG6kn9szq9Atqv0cg 5PXq+qDGC5NTnyrG5v84UB5rzDZRlGBxbHYv/HhPt8h8FK7UIFlf6cObLKPD9S9GWc6nKk FTgFHraNbu4ysljHM9gzzxNoA+3J4sb9Qgn99R7atdIS1lGLcl0CBKTbRlDLuw== From: Maxime Chevallier To: davem@davemloft.net, Rob Herring Cc: Maxime Chevallier , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, thomas.petazzoni@bootlin.com, Andrew Lunn , Florian Fainelli , Heiner Kallweit , Russell King , linux-arm-kernel@lists.infradead.org, Horatiu.Vultur@microchip.com, Allan.Nielsen@microchip.com, UNGLinuxDriver@microchip.com Subject: [PATCH net-next 1/4] net: phy: Introduce QUSGMII PHY mode Date: Thu, 28 Jul 2022 16:52:49 +0200 Message-Id: <20220728145252.439201-2-maxime.chevallier@bootlin.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220728145252.439201-1-maxime.chevallier@bootlin.com> References: <20220728145252.439201-1-maxime.chevallier@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The QUSGMII mode is a derivative of Cisco's USXGMII standard. This standard is pretty similar to SGMII, but allows for faster speeds, and has the build-in bits for Quad and Octa variants (like QSGMII). The main difference with SGMII/QSGMII is that USXGMII/QUSGMII re-uses the preamble to carry various information, named 'Extensions'. As of today, the USXGMII standard only mentions the "PCH" extension, which is used to convey timestamps, allowing in-band signaling of PTP timestamps without having to modify the frame itself. This commit adds support for that mode. When no extension is in use, it behaves exactly like QSGMII, although it's not compatible with QSGMII. Signed-off-by: Maxime Chevallier --- V1->V2 : No changes Documentation/networking/phy.rst | 9 +++++++++ drivers/net/phy/phylink.c | 3 +++ include/linux/phy.h | 3 +++ 3 files changed, 15 insertions(+) diff --git a/Documentation/networking/phy.rst b/Documentation/networking/ph= y.rst index 704f31da5167..712e44caebd0 100644 --- a/Documentation/networking/phy.rst +++ b/Documentation/networking/phy.rst @@ -308,6 +308,15 @@ Some of the interface modes are described below: rate of 125Mpbs using a 4B/5B encoding scheme, resulting in an underly= ing data rate of 100Mpbs. =20 +``PHY_INTERFACE_MODE_QUSGMII`` + This defines the Cisco the Quad USGMII mode, which is the Quad variant= of + the USGMII (Universal SGMII) link. It's very similar to QSGMII, but us= es + a Packet Control Header (PCH) instead of the 7 bytes preamble to carry= not + only the port id, but also so-called "extensions". The only documented + extension so-far in the specification is the inclusion of timestamps, = for + PTP-enabled PHYs. This mode isn't compatible with QSGMII, but offers t= he + same capabilities in terms of link speed and negociation. + Pause frames / flow control =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D =20 diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index 9bd69328dc4d..d2455df1d8d2 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -321,6 +321,7 @@ void phylink_get_linkmodes(unsigned long *linkmodes, ph= y_interface_t interface, case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_QSGMII: + case PHY_INTERFACE_MODE_QUSGMII: case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_GMII: caps |=3D MAC_1000HD | MAC_1000FD; @@ -632,6 +633,7 @@ static int phylink_parse_mode(struct phylink *pl, struc= t fwnode_handle *fwnode) switch (pl->link_config.interface) { case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_QSGMII: + case PHY_INTERFACE_MODE_QUSGMII: phylink_set(pl->supported, 10baseT_Half); phylink_set(pl->supported, 10baseT_Full); phylink_set(pl->supported, 100baseT_Half); @@ -2929,6 +2931,7 @@ void phylink_mii_c22_pcs_decode_state(struct phylink_= link_state *state, =20 case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_QSGMII: + case PHY_INTERFACE_MODE_QUSGMII: phylink_decode_sgmii_word(state, lpa); break; =20 diff --git a/include/linux/phy.h b/include/linux/phy.h index 87638c55d844..6b96b810a4d8 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -152,6 +152,7 @@ typedef enum { PHY_INTERFACE_MODE_USXGMII, /* 10GBASE-KR - with Clause 73 AN */ PHY_INTERFACE_MODE_10GKR, + PHY_INTERFACE_MODE_QUSGMII, PHY_INTERFACE_MODE_MAX, } phy_interface_t; =20 @@ -267,6 +268,8 @@ static inline const char *phy_modes(phy_interface_t int= erface) return "10gbase-kr"; case PHY_INTERFACE_MODE_100BASEX: return "100base-x"; + case PHY_INTERFACE_MODE_QUSGMII: + return "qusgmii"; default: return "unknown"; } --=20 2.37.1 From nobody Wed Apr 15 01:30:11 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D252EC04A68 for ; Thu, 28 Jul 2022 14:53:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229796AbiG1OxT (ORCPT ); Thu, 28 Jul 2022 10:53:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232458AbiG1OxJ (ORCPT ); Thu, 28 Jul 2022 10:53:09 -0400 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::223]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4D62A5D0FA; Thu, 28 Jul 2022 07:53:05 -0700 (PDT) Received: (Authenticated sender: maxime.chevallier@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id ABBF56000B; Thu, 28 Jul 2022 14:53:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1659019982; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=bfRFgIm9TD823qNLzMMh6i2HmzOFrr2qvhJOGCSLGw8=; b=LvInS2Igr/SwKW/LEc8udAuBQkdClSN/n/IysqCQ6t5P73M8SlYHqK6iBh/QT5BWb5LZMW yuWATT+wzFU2K7GVMQ/RlErmHItWsL3grrRdxaO+50sg0467qjDLW+8tzHRYBSohPXSaQs uc/rrZV3UWkSM9cciPc0Z6lY14TRs9tKw62fEPfhA2tMy2b8QcZKUU7RXCtLO6R4IFqtLn KXza+WxrPfRQWSJWCAhRVWwTZjh4/swlkwRDD8rI22BxPcWjj9eUOebT5U0H2V4w1ccQEa VK+LRY2zNPpTLzG3zFKu5cRJvZCk3+F0FKUeoF5wROP61KLsIeuW+0JGAlIfSA== From: Maxime Chevallier To: davem@davemloft.net, Rob Herring Cc: Maxime Chevallier , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, thomas.petazzoni@bootlin.com, Andrew Lunn , Florian Fainelli , Heiner Kallweit , Russell King , linux-arm-kernel@lists.infradead.org, Horatiu.Vultur@microchip.com, Allan.Nielsen@microchip.com, UNGLinuxDriver@microchip.com, Rob Herring Subject: [PATCH net-next 2/4] dt-bindings: net: ethernet-controller: add QUSGMII mode Date: Thu, 28 Jul 2022 16:52:50 +0200 Message-Id: <20220728145252.439201-3-maxime.chevallier@bootlin.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220728145252.439201-1-maxime.chevallier@bootlin.com> References: <20220728145252.439201-1-maxime.chevallier@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a new QUSGMII mode, standing for "Quad Universal Serial Gigabit Media Independent Interface", a derivative of USGMII which, similarly to QSGMII, allows to multiplex 4 1Gbps links to a Quad-PHY. The main difference with QSGMII is that QUSGMII can include an extension instead of the standard 7bytes ethernet preamble, allowing to convey arbitrary data such as Timestamps. Signed-off-by: Maxime Chevallier Acked-by: Rob Herring --- V1->V2 : Added Rob's acked-by Documentation/devicetree/bindings/net/ethernet-controller.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml= b/Documentation/devicetree/bindings/net/ethernet-controller.yaml index 56d9aca8c954..eb69a720575f 100644 --- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml @@ -67,6 +67,7 @@ properties: - gmii - sgmii - qsgmii + - qusgmii - tbi - rev-mii - rmii --=20 2.37.1 From nobody Wed Apr 15 01:30:11 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01C23C04A68 for ; Thu, 28 Jul 2022 14:53:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233057AbiG1Ox2 (ORCPT ); Thu, 28 Jul 2022 10:53:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232322AbiG1OxG (ORCPT ); Thu, 28 Jul 2022 10:53:06 -0400 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::223]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0CFBF60685; Thu, 28 Jul 2022 07:53:04 -0700 (PDT) Received: (Authenticated sender: maxime.chevallier@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 3A2176000F; Thu, 28 Jul 2022 14:53:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1659019983; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=L+CWF+J4cRRiFmB2flx5GMZW1XQc4zExLZaoJy9LT40=; b=nvnqr8FJJAKaVF9DjobusWmfb6RjhfF2qCqrbTic3X8f0y7lXv6DCC8s24jPupB5ei0/Qy uJqRPmMJLlHY2k03f2YnDYqr0QntRh439QR2uwefIN7V3nr546StvArfHJZG/Tp/odjaZd W2aIY3SvZDW4sceKBKMEIstlC8ZslddL2V+lW9RGzop26PkCcqA3y+0AI9Fk2o87DJX09K 47YEoWT94LL3Ym0SD5YHgCqUji4jDAWw2UgUdiayTpAzT9hnRuAcePAI3bpMs/4BXN0B2U 6edNuWvbfJNkSsrMJHCwrGWU0sY9bTobACUqzRTXU6VZZ2zPC48JMMq4RmKedA== From: Maxime Chevallier To: davem@davemloft.net, Rob Herring Cc: Maxime Chevallier , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, thomas.petazzoni@bootlin.com, Andrew Lunn , Florian Fainelli , Heiner Kallweit , Russell King , linux-arm-kernel@lists.infradead.org, Horatiu.Vultur@microchip.com, Allan.Nielsen@microchip.com, UNGLinuxDriver@microchip.com Subject: [PATCH net-next 3/4] net: phy: Add helper to derive the number of ports from a phy mode Date: Thu, 28 Jul 2022 16:52:51 +0200 Message-Id: <20220728145252.439201-4-maxime.chevallier@bootlin.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220728145252.439201-1-maxime.chevallier@bootlin.com> References: <20220728145252.439201-1-maxime.chevallier@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Some phy modes such as QSGMII multiplex several MAC<->PHY links on one single physical interface. QSGMII used to be the only one supported, but other modes such as QUSGMII also carry multiple links. This helper allows getting the number of links that are multiplexed on a given interface. Signed-off-by: Maxime Chevallier --- V1->V2 : New patch drivers/net/phy/phy-core.c | 52 ++++++++++++++++++++++++++++++++++++++ include/linux/phy.h | 2 ++ 2 files changed, 54 insertions(+) diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c index 1f2531a1a876..6029583f367d 100644 --- a/drivers/net/phy/phy-core.c +++ b/drivers/net/phy/phy-core.c @@ -74,6 +74,58 @@ const char *phy_duplex_to_str(unsigned int duplex) } EXPORT_SYMBOL_GPL(phy_duplex_to_str); =20 +/** + * phy_interface_num_ports - Return the number of links that can be carrie= d by + * a given MAC-PHY physical link. Returns 0 if this is + * unknown, the number of links else. + * + * @interface: The interface mode we want to get the number of ports + */ +int phy_interface_num_ports(phy_interface_t interface) +{ + switch (interface) { + case PHY_INTERFACE_MODE_NA: + case PHY_INTERFACE_MODE_INTERNAL: + return 0; + + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_GMII: + case PHY_INTERFACE_MODE_TBI: + case PHY_INTERFACE_MODE_REVMII: + case PHY_INTERFACE_MODE_RMII: + case PHY_INTERFACE_MODE_REVRMII: + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RTBI: + case PHY_INTERFACE_MODE_XGMII: + case PHY_INTERFACE_MODE_XLGMII: + case PHY_INTERFACE_MODE_MOCA: + case PHY_INTERFACE_MODE_TRGMII: + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_SMII: + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: + case PHY_INTERFACE_MODE_5GBASER: + case PHY_INTERFACE_MODE_10GBASER: + case PHY_INTERFACE_MODE_25GBASER: + case PHY_INTERFACE_MODE_10GKR: + case PHY_INTERFACE_MODE_100BASEX: + case PHY_INTERFACE_MODE_RXAUI: + case PHY_INTERFACE_MODE_XAUI: + return 1; + case PHY_INTERFACE_MODE_QSGMII: + case PHY_INTERFACE_MODE_QUSGMII: + return 4; + + default: + return 0; + } +} +EXPORT_SYMBOL_GPL(phy_interface_num_ports); + /* A mapping of all SUPPORTED settings to speed/duplex. This table * must be grouped by speed and sorted in descending match priority * - iow, descending speed. diff --git a/include/linux/phy.h b/include/linux/phy.h index 6b96b810a4d8..77e4b60bb9ab 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -967,6 +967,8 @@ struct phy_fixup { const char *phy_speed_to_str(int speed); const char *phy_duplex_to_str(unsigned int duplex); =20 +int phy_interface_num_ports(phy_interface_t interface); + /* A structure for mapping a particular speed and duplex * combination to a particular SUPPORTED and ADVERTISED value */ --=20 2.37.1 From nobody Wed Apr 15 01:30:11 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 518C5C04A68 for ; Thu, 28 Jul 2022 14:53:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232828AbiG1OxY (ORCPT ); Thu, 28 Jul 2022 10:53:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32860 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232730AbiG1OxJ (ORCPT ); Thu, 28 Jul 2022 10:53:09 -0400 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::223]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E8FDE6069F; Thu, 28 Jul 2022 07:53:06 -0700 (PDT) Received: (Authenticated sender: maxime.chevallier@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 9C15860007; Thu, 28 Jul 2022 14:53:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1659019984; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=i6ixpedV57yhN8lJ4519v1XA35dTMW/Roc+IABYUoNc=; b=PfI2rfazBYUivvLzCdMAOGchPRLUBBGck7wt4NaDSNeacSGWEXrDjRkYM9r0VTimNMR5DT 4v2xe4nTzlQrY/hiYOhVyEcpNTOSnsegMHHMewQ1HZ3Di/0m7h0P7tfay2cQL0K6hA1j9w 9H2W9mVuJZOX+O6jQrlsdzFceEQzSlMRTdioDRaQrRohgINzqN3jXYuqD0qRDBb97QHRm1 0f0GW/uj68bJzXn4GjIGxWvqSqNpuyF4jLzd/8fFWe9wPw5tUBKboNRvD38Vlhwh60/tAv D4+1fmENrP+La1NGB0oXuQ4J5QFeU6bng21S7tXiIw6jGJW6Tm+uXdwTzu4eyw== From: Maxime Chevallier To: davem@davemloft.net, Rob Herring Cc: Maxime Chevallier , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, thomas.petazzoni@bootlin.com, Andrew Lunn , Florian Fainelli , Heiner Kallweit , Russell King , linux-arm-kernel@lists.infradead.org, Horatiu.Vultur@microchip.com, Allan.Nielsen@microchip.com, UNGLinuxDriver@microchip.com Subject: [PATCH net-next 4/4] net: lan966x: Add QUSGMII support for lan966x Date: Thu, 28 Jul 2022 16:52:52 +0200 Message-Id: <20220728145252.439201-5-maxime.chevallier@bootlin.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220728145252.439201-1-maxime.chevallier@bootlin.com> References: <20220728145252.439201-1-maxime.chevallier@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Lan996x controller supports the QUSGMII mode, which is very similar to QSGMII in the way it's configured and the autonegociation capababilities it provides. This commit adds support for that mode, treating it most of the time like QSGMII, making sure that we do configure the PCS how we should. Signed-off-by: Maxime Chevallier --- V1->V2 : Pass the QUSGMII mode as-is to the generic PHY driver, and use phy_interface_num_ports, as per Russell's review .../ethernet/microchip/lan966x/lan966x_main.c | 2 ++ .../microchip/lan966x/lan966x_phylink.c | 3 ++- .../ethernet/microchip/lan966x/lan966x_port.c | 22 ++++++++++++++----- .../ethernet/microchip/lan966x/lan966x_regs.h | 6 +++++ 4 files changed, 26 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.c index 1d6e3b641b2e..1e604e8db20c 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.c @@ -778,6 +778,8 @@ static int lan966x_probe_port(struct lan966x *lan966x, = u32 p, port->phylink_config.supported_interfaces); __set_bit(PHY_INTERFACE_MODE_QSGMII, port->phylink_config.supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_QUSGMII, + port->phylink_config.supported_interfaces); __set_bit(PHY_INTERFACE_MODE_1000BASEX, port->phylink_config.supported_interfaces); __set_bit(PHY_INTERFACE_MODE_2500BASEX, diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_phylink.c b/dri= vers/net/ethernet/microchip/lan966x/lan966x_phylink.c index 38a7e95d69b4..87f3d3a57aed 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_phylink.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_phylink.c @@ -28,11 +28,12 @@ static int lan966x_phylink_mac_prepare(struct phylink_c= onfig *config, phy_interface_t iface) { struct lan966x_port *port =3D netdev_priv(to_net_dev(config->dev)); + phy_interface_t serdes_mode =3D iface; int err; =20 if (port->serdes) { err =3D phy_set_mode_ext(port->serdes, PHY_MODE_ETHERNET, - iface); + serdes_mode); if (err) { netdev_err(to_net_dev(config->dev), "Could not set mode of SerDes\n"); diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_port.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_port.c index f141644e4372..bbf42fc8c8d5 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_port.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_port.c @@ -168,7 +168,7 @@ static void lan966x_port_link_up(struct lan966x_port *p= ort) /* Also the GIGA_MODE_ENA(1) needs to be set regardless of the * port speed for QSGMII ports. */ - if (config->portmode =3D=3D PHY_INTERFACE_MODE_QSGMII) + if (phy_interface_num_ports(config->portmode) =3D=3D 4) mode =3D DEV_MAC_MODE_CFG_GIGA_MODE_ENA_SET(1); =20 lan_wr(config->duplex | mode, @@ -331,10 +331,14 @@ int lan966x_port_pcs_set(struct lan966x_port *port, struct lan966x *lan966x =3D port->lan966x; bool inband_aneg =3D false; bool outband; + bool full_preamble =3D false; + + if (config->portmode =3D=3D PHY_INTERFACE_MODE_QUSGMII) + full_preamble =3D true; =20 if (config->inband) { if (config->portmode =3D=3D PHY_INTERFACE_MODE_SGMII || - config->portmode =3D=3D PHY_INTERFACE_MODE_QSGMII) + phy_interface_num_ports(config->portmode) =3D=3D 4) inband_aneg =3D true; /* Cisco-SGMII in-band-aneg */ else if (config->portmode =3D=3D PHY_INTERFACE_MODE_1000BASEX && config->autoneg) @@ -345,9 +349,15 @@ int lan966x_port_pcs_set(struct lan966x_port *port, outband =3D true; } =20 - /* Disable or enable inband */ - lan_rmw(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(outband), - DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA, + /* Disable or enable inband. + * For QUSGMII, we rely on the preamble to transmit data such as + * timestamps, therefore force full preamble transmission, and prevent + * premable shortening + */ + lan_rmw(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(outband) | + DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(full_preamble), + DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA | + DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, lan966x, DEV_PCS1G_MODE_CFG(port->chip_port)); =20 /* Enable PCS */ @@ -396,7 +406,7 @@ void lan966x_port_init(struct lan966x_port *port) if (lan966x->fdma) lan966x_fdma_netdev_init(lan966x, port->dev); =20 - if (config->portmode !=3D PHY_INTERFACE_MODE_QSGMII) + if (phy_interface_num_ports(config->portmode) !=3D 4) return; =20 lan_rmw(DEV_CLOCK_CFG_PCS_RX_RST_SET(0) | diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_regs.h b/driver= s/net/ethernet/microchip/lan966x/lan966x_regs.h index 8265ad89f0bc..c53bae5d8dbd 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_regs.h +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_regs.h @@ -504,6 +504,12 @@ enum lan966x_target { #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\ FIELD_GET(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) =20 +#define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA BIT(1) +#define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(x)\ + FIELD_PREP(DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x) +#define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_GET(x)\ + FIELD_GET(DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x) + /* DEV:PCS1G_CFG_STATUS:PCS1G_SD_CFG */ #define DEV_PCS1G_SD_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 8,= 0, 1, 4) =20 --=20 2.37.1