From nobody Wed Apr 15 05:45:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60A7FC04A68 for ; Wed, 27 Jul 2022 22:08:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233524AbiG0WI4 (ORCPT ); Wed, 27 Jul 2022 18:08:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50694 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229628AbiG0WIt (ORCPT ); Wed, 27 Jul 2022 18:08:49 -0400 Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9677952454 for ; Wed, 27 Jul 2022 15:08:46 -0700 (PDT) Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-31f56f635a9so1234487b3.4 for ; Wed, 27 Jul 2022 15:08:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc:content-transfer-encoding; bh=kUUXCDLjUy+eFGj28ODYtAEpRC3NYIVl5cubHVClXkQ=; b=TFdtetj8ujmdj0KrUuEchAuFCGAHMD/qLX/rO8ccmOfxZOU5sgJ8aJ7Y637vnoRgJz 8wDh1Aa20dsMzniEPkqQD05EGViLrozR2/3NFvBhBhGl0VpcWMk8sPf61KV/oyqj/YaE lTb7vvWnlFXXAWR4ORgiIPVT0RUHXGnKaItpoDxMt1PdcQOujohegFYdTmVKqdN4ahRp gvcvBEL38YYvX28MCk+wwWPsNJOEiTMyeeeE38+sWEN2KYz12awT/TEtH8Y56Pc3TqCr yjX7atyggqbIfn4Cw3YSTGCcKqys3Ljpl0N5BSosvxKHWRoZ1m1yDJhuw3ZZBRC4peix dAVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc:content-transfer-encoding; bh=kUUXCDLjUy+eFGj28ODYtAEpRC3NYIVl5cubHVClXkQ=; b=gVStZVjyS466i03uugKxE7uer7RGCxqtckdpdy3SWsf4HBw3v+TQufrpUzKLXW5tzJ VrB1Xq4aLMD0PdlpFu/LDKd/GppRAWgK/Y01QXylcYI1u7vJqRovTaton1rz7qHY9o3e F83nP9VwHo6kUahrcWr+9J7bhPrBHpKH5XewvA4qZhbxbbUDq9huGDW5w6Z3ruqVG/re ZzaPSQwnm8xh+J4260hBwc4b6Vyp69sLLCpLkUrryP/Qbr88akxSwa78nlZEhXR9JdQO CSokg9jRfcSgNGbduw/y5FsTwUskPJoj/awba8jbtOb7jceMZmSitH+fkm1tTh6yaSk3 y6cg== X-Gm-Message-State: AJIora+7VjluUBMUt5iHCQTgidnVE2a0m1R8QACeK0Y1N0fl0Cln8UbO ppePiDMcl22MnygTx3qsngsBXogdhr72 X-Google-Smtp-Source: AGRyM1t1x31ZHlKqPTbDnPmP+EzkQEYtV7CUmB/lzr4ylnt1KjqlrSD7axldsQoeD0VNn+0CSG/kiiu8ilgg X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:882a:af57:8cb6:6f9e]) (user=irogers job=sendgmr) by 2002:a0d:d001:0:b0:31c:75bc:25bd with SMTP id s1-20020a0dd001000000b0031c75bc25bdmr20966471ywd.505.1658959725898; Wed, 27 Jul 2022 15:08:45 -0700 (PDT) Date: Wed, 27 Jul 2022 15:08:03 -0700 In-Reply-To: <20220727220832.2865794-1-irogers@google.com> Message-Id: <20220727220832.2865794-2-irogers@google.com> Mime-Version: 1.0 References: <20220727220832.2865794-1-irogers@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH v3 01/30] perf vendor events: Update Intel broadwellx From: Ian Rogers To: perry.taylor@intel.com, caleb.biggers@intel.com, kshipra.bopardikar@intel.com, Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Sedat Dilek Cc: Stephane Eranian , Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Update to v19, the metrics are based on TMA 4.4 full. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/downloa= d_and_gen.py to download and generate the latest events and metrics. Manually copy the broadwellx files into perf and update mapfile.csv. Tested with 'perf test': 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok 90: perf all metricgroups test : Ok 91: perf all metrics test : Skip 93: perf all PMU test : Ok Signed-off-by: Ian Rogers --- .../arch/x86/broadwellx/bdx-metrics.json | 570 ++++++++++++++++-- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 2 files changed, 518 insertions(+), 54 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json b/t= ools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json index b055947c0afe..720ee7c9332d 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json @@ -74,12 +74,6 @@ "MetricGroup": "Branches;Fed;FetchBW", "MetricName": "UpTB" }, - { - "BriefDescription": "Cycles Per Instruction (per Logical Processor= )", - "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", - "MetricGroup": "Pipeline;Mem", - "MetricName": "CPI" - }, { "BriefDescription": "Per-Logical Processor actual clocks when the = Logical Processor is active.", "MetricExpr": "CPU_CLK_UNHALTED.THREAD", @@ -130,43 +124,25 @@ "MetricName": "FLOPc_SMT" }, { - "BriefDescription": "Actual per-core usage of the Floating Point e= xecution units (regardless of the vector width)", + "BriefDescription": "Actual per-core usage of the Floating Point n= on-X87 execution units (regardless of precision or vector-width)", "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_I= NST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP= _ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_= DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * CPU_CLK_UNHALT= ED.THREAD )", "MetricGroup": "Cor;Flops;HPC", "MetricName": "FP_Arith_Utilization", - "PublicDescription": "Actual per-core usage of the Floating Point = execution units (regardless of the vector width). Values > 1 are possible d= ue to Fused-Multiply Add (FMA) counting." + "PublicDescription": "Actual per-core usage of the Floating Point = non-X87 execution units (regardless of precision or vector-width). Values >= 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; = [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less commo= n)." }, { - "BriefDescription": "Actual per-core usage of the Floating Point e= xecution units (regardless of the vector width). SMT version; use when SMT = is enabled and measuring per logical CPU.", + "BriefDescription": "Actual per-core usage of the Floating Point n= on-X87 execution units (regardless of precision or vector-width). SMT versi= on; use when SMT is enabled and measuring per logical CPU.", "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_I= NST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP= _ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_= DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * ( ( CPU_CLK_UN= HALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UN= HALTED.REF_XCLK ) ) )", "MetricGroup": "Cor;Flops;HPC_SMT", "MetricName": "FP_Arith_Utilization_SMT", - "PublicDescription": "Actual per-core usage of the Floating Point = execution units (regardless of the vector width). Values > 1 are possible d= ue to Fused-Multiply Add (FMA) counting. SMT version; use when SMT is enabl= ed and measuring per logical CPU." + "PublicDescription": "Actual per-core usage of the Floating Point = non-X87 execution units (regardless of precision or vector-width). Values >= 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; = [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less commo= n). SMT version; use when SMT is enabled and measuring per logical CPU." }, { - "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is at least 1 uop executed)", + "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per-core", "MetricExpr": "UOPS_EXECUTED.THREAD / (( cpu@UOPS_EXECUTED.CORE\\,= cmask\\=3D1@ / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, - { - "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIR= ED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.TH= READ))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_C= LK_UNHALTED.THREAD)) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETI= RED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED= .THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS= .ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_= CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_MISP_RETIRED.A= LL_BRANCHES", - "MetricGroup": "Bad;BrMispredicts", - "MetricName": "Branch_Misprediction_Cost" - }, - { - "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIR= ED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU= _CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU= _CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_D= ELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED= .ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (BR_MISP_RETIRED.ALL= _BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + B= ACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES += MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCL= ES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_C= LK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) * (4 * ( = ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE = / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BrMispredicts_SMT", - "MetricName": "Branch_Misprediction_Cost_SMT" - }, - { - "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear)", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "IpMispredict" - }, { "BriefDescription": "Core actual clocks when any Logical Processor= is active on the Physical Core", "MetricExpr": "( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_U= NHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", @@ -256,6 +232,18 @@ "MetricGroup": "Summary;TmaL1", "MetricName": "Instructions" }, + { + "BriefDescription": "Average number of Uops retired in cycles wher= e at least one uop has retired.", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE= _SLOTS\\,cmask\\=3D1@", + "MetricGroup": "Pipeline;Ret", + "MetricName": "Retire" + }, + { + "BriefDescription": "", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,c= mask\\=3D1@", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", + "MetricName": "Execute" + }, { "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MIT= E_UOPS + IDQ.MS_UOPS ) )", @@ -263,35 +251,34 @@ "MetricName": "DSB_Coverage" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load instructions (in core cycles)", - "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_= MISS + mem_load_uops_retired.hit_lfb )", - "MetricGroup": "Mem;MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency", - "PublicDescription": "Actual Average Latency for L1 data-cache mis= s demand load instructions (in core cycles). Latency may be overestimated f= or multi-load instructions - e.g. repeat strings." + "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "IpMispredict" }, { - "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", - "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLE= S", - "MetricGroup": "Mem;MemoryBound;MemoryBW", - "MetricName": "MLP" + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIR= ED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.TH= READ))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_C= LK_UNHALTED.THREAD)) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETI= RED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED= .THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS= .ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_= CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_MISP_RETIRED.A= LL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "Branch_Misprediction_Cost" }, { - "BriefDescription": "Average data fill bandwidth to the L1 data ca= che [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW" + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIR= ED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU= _CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU= _CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_D= ELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED= .ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (BR_MISP_RETIRED.ALL= _BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + B= ACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES += MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCL= ES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_C= LK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) * (4 * ( = ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE = / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts_SMT", + "MetricName": "Branch_Misprediction_Cost_SMT" }, { - "BriefDescription": "Average data fill bandwidth to the L2 cache [= GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW" + "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load operations (in core cycles)", + "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_= MISS + mem_load_uops_retired.hit_lfb )", + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "Load_Miss_Real_Latency" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW" + "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLE= S", + "MetricGroup": "Mem;MemoryBound;MemoryBW", + "MetricName": "MLP" }, { "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", @@ -306,13 +293,13 @@ "MetricName": "L2MPKI" }, { - "BriefDescription": "L2 cache misses per kilo instruction for all = request types (including speculative)", + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instru= ction for all request types (including speculative)", "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", "MetricGroup": "Mem;CacheMisses;Offcore", "MetricName": "L2MPKI_All" }, { - "BriefDescription": "L2 cache misses per kilo instruction for all = demand loads (including speculative)", + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instru= ction for all demand loads (including speculative)", "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.= ANY", "MetricGroup": "Mem;CacheMisses", "MetricName": "L2MPKI_Load" @@ -348,6 +335,48 @@ "MetricGroup": "Mem;MemoryTLB_SMT", "MetricName": "Page_Walks_Utilization_SMT" }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", + "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L1D_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 2 cache [GB / sec]", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L2_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L3_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L1 data cache [GB / sec]", + "MetricExpr": "(64 * L1D.REPLACEMENT / 1000000000 / duration_time)= ", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L1D_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L2 cache [GB / sec]", + "MetricExpr": "(64 * L2_LINES_IN.ALL / 1000000000 / duration_time)= ", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L2_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L3 cache [GB / sec]", + "MetricExpr": "(64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duratio= n_time)", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L3_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data access bandwidth to t= he L3 cache [GB / sec]", + "MetricExpr": "0", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "L3_Cache_Access_BW_1T" + }, { "BriefDescription": "Average CPU Utilization", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", @@ -364,7 +393,8 @@ "BriefDescription": "Giga Floating Point Operations Per Second", "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_= ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_= DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RET= IRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) = / 1000000000 ) / duration_time", "MetricGroup": "Cor;Flops;HPC", - "MetricName": "GFLOPs" + "MetricName": "GFLOPs", + "PublicDescription": "Giga Floating Point Operations Per Second. A= ggregate across all supported options of: FP precisions, scalar and vector = instructions, vector-width and AMX engine." }, { "BriefDescription": "Average Frequency Utilization relative nomina= l frequency", @@ -461,5 +491,439 @@ "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C7_Pkg_Residency" + }, + { + "BriefDescription": "CPU operating frequency (in GHz)", + "MetricExpr": "( CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TS= C * #SYSTEM_TSC_FREQ ) / 1000000000", + "MetricGroup": "", + "MetricName": "cpu_operating_frequency", + "ScaleUnit": "1GHz" + }, + { + "BriefDescription": "Cycles per instruction retired; indicating ho= w much time each executed instruction took; in units of cycles.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "cpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "The ratio of number of completed memory load = instructions to the total number completed instructions", + "MetricExpr": "MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "loads_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "The ratio of number of completed memory store= instructions to the total number completed instructions", + "MetricExpr": "MEM_UOPS_RETIRED.ALL_STORES / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "stores_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of requests missing L1 data c= ache (includes data+rfo w/ prefetches) to the total number of completed ins= tructions", + "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l1d_mpi_includes_data_plus_rfo_with_prefetches", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of demand load requests hitti= ng in L1 data cache to the total number of completed instructions", + "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L1_HIT / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l1d_demand_data_read_hits_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read requests missing= in L1 instruction cache (includes prefetches) to the total number of compl= eted instructions", + "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed demand load requ= ests hitting in L2 cache to the total number of completed instructions", + "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_HIT / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l2_demand_data_read_hits_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of requests missing L2 cache = (includes code+data+rfo w/ prefetches) to the total number of completed ins= tructions", + "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l2_mpi_includes_code_plus_data_plus_rfo_with_prefet= ches", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed data read reques= t missing L2 cache to the total number of completed instructions", + "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l2_demand_data_read_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read request missing = L2 cache to the total number of completed instructions", + "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l2_demand_code_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of data read requests missing= last level core cache (includes demand w/ prefetches) to the total number = of completed instructions", + "MetricExpr": "( cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\= =3D0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=3D0x192@ ) / = INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "llc_data_read_mpi_demand_plus_prefetch", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read requests missing= last level core cache (includes demand w/ prefetches) to the total number = of completed instructions", + "MetricExpr": "( cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\= =3D0x181@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=3D0x191@ ) / = INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "llc_code_read_mpi_demand_plus_prefetch", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) d= emand and prefetch data read miss (read memory access) in nano seconds", + "MetricExpr": "( 1000000000 * ( cbox@UNC_C_TOR_OCCUPANCY.MISS_OPCO= DE\\,filter_opc\\=3D0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_op= c\\=3D0x182@ ) / ( UNC_C_CLOCKTICKS / ( source_count(UNC_C_CLOCKTICKS) * #n= um_packages ) ) ) * duration_time", + "MetricGroup": "", + "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) d= emand and prefetch data read miss (read memory access) addressed to local m= emory in nano seconds", + "MetricExpr": "( 1000000000 * ( cbox@UNC_C_TOR_OCCUPANCY.MISS_LOCA= L_OPCODE\\,filter_opc\\=3D0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,fil= ter_opc\\=3D0x182@ ) / ( UNC_C_CLOCKTICKS / ( source_count(UNC_C_CLOCKTICKS= ) * #num_packages ) ) ) * duration_time", + "MetricGroup": "", + "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for= _local_requests", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) d= emand and prefetch data read miss (read memory access) addressed to remote = memory in nano seconds", + "MetricExpr": "( 1000000000 * ( cbox@UNC_C_TOR_OCCUPANCY.MISS_REMO= TE_OPCODE\\,filter_opc\\=3D0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,fi= lter_opc\\=3D0x182@ ) / ( UNC_C_CLOCKTICKS / ( source_count(UNC_C_CLOCKTICK= S) * #num_packages ) ) ) * duration_time", + "MetricGroup": "", + "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for= _remote_requests", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = all page sizes) caused by a code fetch to the total number of completed ins= tructions. This implies it missed in the ITLB (Instruction TLB) and further= levels of TLB.", + "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "itlb_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total n= umber of completed instructions. This implies it missed in the Instruction = Translation Lookaside Buffer (ITLB) and further levels of TLB.", + "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY= ", + "MetricGroup": "", + "MetricName": "itlb_large_page_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = all page sizes) caused by demand data loads to the total number of complete= d instructions. This implies it missed in the DTLB and further levels of TL= B.", + "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "dtlb_load_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = all page sizes) caused by demand data stores to the total number of complet= ed instructions. This implies it missed in the DTLB and further levels of T= LB.", + "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY= ", + "MetricGroup": "", + "MetricName": "dtlb_store_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Memory read that miss the last level cache (L= LC) addressed to local DRAM as a percentage of total memory read accesses, = does not include LLC prefetches.", + "MetricExpr": "100 * cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_o= pc\\=3D0x182@ / ( cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=3D0x182= @ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=3D0x182@ )", + "MetricGroup": "", + "MetricName": "numa_percent_reads_addressed_to_local_dram", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Memory reads that miss the last level cache (= LLC) addressed to remote DRAM as a percentage of total memory read accesses= , does not include LLC prefetches.", + "MetricExpr": "100 * cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_o= pc\\=3D0x182@ / ( cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=3D0x182= @ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=3D0x182@ )", + "MetricGroup": "", + "MetricName": "numa_percent_reads_addressed_to_remote_dram", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Uncore operating frequency in GHz", + "MetricExpr": "UNC_C_CLOCKTICKS / ( source_count(UNC_C_CLOCKTICKS)= * #num_packages ) / 1000000000", + "MetricGroup": "", + "MetricName": "uncore_frequency", + "ScaleUnit": "1GHz" + }, + { + "BriefDescription": "Intel(R) Quick Path Interconnect (QPI) data t= ransmit bandwidth (MB/sec)", + "MetricExpr": "( UNC_Q_TxL_FLITS_G0.DATA * 8 / 1000000) / duration= _time", + "MetricGroup": "", + "MetricName": "qpi_data_transmit_bw_only_data", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "DDR memory read bandwidth (MB/sec)", + "MetricExpr": "( UNC_M_CAS_COUNT.RD * 64 / 1000000) / duration_tim= e", + "MetricGroup": "", + "MetricName": "memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "DDR memory write bandwidth (MB/sec)", + "MetricExpr": "( UNC_M_CAS_COUNT.WR * 64 / 1000000) / duration_tim= e", + "MetricGroup": "", + "MetricName": "memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "DDR memory bandwidth (MB/sec)", + "MetricExpr": "(( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) * 64 /= 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "memory_bandwidth_total", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO reads that are initiated by e= nd device controllers that are requesting memory from the CPU.", + "MetricExpr": "( cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=3D0x= 19e@ * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "io_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO writes that are initiated by = end device controllers that are writing memory to the CPU.", + "MetricExpr": "(( cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=3D0= x1c8\\,filter_tid\\=3D0x3e@ + cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\= =3D0x180\\,filter_tid\\=3D0x3e@ ) * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "io_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Uops delivered from decoded instruction cache= (decoded stream buffer or DSB) as a percent of total uops delivered to Ins= truction Decode Queue", + "MetricExpr": "100 * ( IDQ.DSB_UOPS / UOPS_ISSUED.ANY )", + "MetricGroup": "", + "MetricName": "percent_uops_delivered_from_decoded_icache_dsb", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Uops delivered from legacy decode pipeline (M= icro-instruction Translation Engine or MITE) as a percent of total uops del= ivered to Instruction Decode Queue", + "MetricExpr": "100 * ( IDQ.MITE_UOPS / UOPS_ISSUED.ANY )", + "MetricGroup": "", + "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline_= mite", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Uops delivered from microcode sequencer (MS) = as a percent of total uops delivered to Instruction Decode Queue", + "MetricExpr": "100 * ( IDQ.MS_UOPS / UOPS_ISSUED.ANY )", + "MetricGroup": "", + "MetricName": "percent_uops_delivered_from_microcode_sequencer_ms", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Uops delivered from loop stream detector(LSD)= as a percent of total uops delivered to Instruction Decode Queue", + "MetricExpr": "100 * ( LSD.UOPS / UOPS_ISSUED.ANY )", + "MetricGroup": "", + "MetricName": "percent_uops_delivered_from_loop_stream_detector_ls= d", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend. Frontend denotes th= e first part of the processor core responsible to fetch operations that are= executed later on by the Backend part. Within the Frontend; a branch predi= ctor predicts the next address to fetch; cache-lines are fetched from the m= emory subsystem; parsed into instructions; and lastly decoded into micro-op= erations (uops). Ideally the Frontend can issue Machine_Width uops every cy= cle to the Backend. Frontend Bound denotes unutilized issue-slots when ther= e is no Backend stall; i.e. bubbles where Frontend delivered no uops while = Backend could have accepted them. For example; stalls due to instruction-ca= che misses would be categorized under Frontend Bound.", + "MetricExpr": "100 * ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( (= CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREA= D ) ) ) )", + "MetricGroup": "TmaL1;PGO", + "MetricName": "tma_frontend_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = CPU was stalled due to Frontend latency issues. For example; instruction-c= ache misses; iTLB misses or fetch stalls after a branch misprediction are c= ategorized under Frontend Latency. In such cases; the Frontend eventually d= elivers no uops for some period.", + "MetricExpr": "100 * ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOP= S_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on e= lse ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricGroup": "Frontend;TmaL2;m_tma_frontend_bound_percent", + "MetricName": "tma_fetch_latency_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to instruction cache misses.", + "MetricExpr": "100 * ( ICACHE.IFDATA_STALL / ( CPU_CLK_UNHALTED.TH= READ ) )", + "MetricGroup": "BigFoot;FetchLat;IcMiss;TmaL3;m_tma_fetch_latency_= percent", + "MetricName": "tma_icache_misses_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Instruction TLB (ITLB) misses.", + "MetricExpr": "100 * ( ( 14 * ITLB_MISSES.STLB_HIT + cpu@ITLB_MISS= ES.WALK_DURATION\\,cmask\\=3D0x1@ + 7 * ITLB_MISSES.WALK_COMPLETED ) / ( CP= U_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TmaL3;m_tma_fetch_laten= cy_percent", + "MetricName": "tma_itlb_misses_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Branch Resteers. Branch Resteers estimates the Fron= tend delay in fetching operations from corrected path; following all sorts = of miss-predicted branches. For example; branchy code with lots of miss-pre= dictions might get categorized under Branch Resteers. Note the value of thi= s node may overlap with its siblings.", + "MetricExpr": "100 * ( ( 12 ) * ( BR_MISP_RETIRED.ALL_BRANCHES + M= ACHINE_CLEARS.COUNT + BACLEARS.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "FetchLat;TmaL3;m_tma_fetch_latency_percent", + "MetricName": "tma_branch_resteers_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decod= ed i-cache) is a Uop Cache where the front-end directly delivers Uops (micr= o operations) avoiding heavy x86 decoding. The DSB pipeline has shorter lat= ency and delivered higher bandwidth than the MITE (legacy instruction decod= e pipeline). Switching between the two pipelines can cause penalties hence = this metric measures the exposed penalty.", + "MetricExpr": "100 * ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CL= K_UNHALTED.THREAD ) )", + "MetricGroup": "DSBmiss;FetchLat;TmaL3;m_tma_fetch_latency_percent= ", + "MetricName": "tma_dsb_switches_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU= was stalled due to Length Changing Prefixes (LCPs). Using proper compiler = flags or Intel Compiler by default will certainly avoid this. #Link: Optimi= zation Guide about LCP BKMs.", + "MetricExpr": "100 * ( ILD_STALL.LCP / ( CPU_CLK_UNHALTED.THREAD )= )", + "MetricGroup": "FetchLat;TmaL3;m_tma_fetch_latency_percent", + "MetricName": "tma_lcp_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates the fraction of cycles = when the CPU was stalled due to switches of uop delivery to the Microcode S= equencer (MS). Commonly used instructions are optimized for delivery by the= DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certa= in operations cannot be handled natively by the execution pipeline; and mus= t be performed by microcode (small programs injected into the execution str= eam). Switching to the MS too often can negatively impact performance. The = MS is designated to deliver long uop flows required by CISC instructions li= ke CPUID; or uncommon conditions like Floating Point Assists when dealing w= ith Denormals.", + "MetricExpr": "100 * ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTE= D.THREAD ) )", + "MetricGroup": "FetchLat;MicroSeq;TmaL3;m_tma_fetch_latency_percen= t", + "MetricName": "tma_ms_switches_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = CPU was stalled due to Frontend bandwidth issues. For example; inefficienc= ies at the instruction decoders; or restrictions for caching in the DSB (de= coded uops cache) are categorized under Fetch Bandwidth. In such cases; the= Frontend typically delivers suboptimal amount of uops to the Backend.", + "MetricExpr": "100 * ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * (= ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THR= EAD ) ) ) ) - ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (= ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UN= HALTED.THREAD ) ) ) ) )", + "MetricGroup": "FetchBW;Frontend;TmaL2;m_tma_frontend_bound_percen= t", + "MetricName": "tma_fetch_bandwidth_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycle= s in which CPU was likely limited due to the MITE pipeline (the legacy deco= de pipeline). This pipeline is used for code that was not pre-cached in the= DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of= long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", + "MetricExpr": "100 * ( ( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MI= TE_CYCLES_4_UOPS ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else = ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", + "MetricGroup": "DSBmiss;FetchBW;TmaL3;m_tma_fetch_bandwidth_percen= t", + "MetricName": "tma_mite_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycle= s in which CPU was likely limited due to DSB (decoded uop cache) fetch pipe= line. For example; inefficient utilization of the DSB cache structure or b= ank conflict when reading from it; are categorized here.", + "MetricExpr": "100 * ( ( IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB= _CYCLES_4_UOPS ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( = CPU_CLK_UNHALTED.THREAD ) ) / 2 )", + "MetricGroup": "DSB;FetchBW;TmaL3;m_tma_fetch_bandwidth_percent", + "MetricName": "tma_dsb_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This category represents fraction of slots wa= sted due to incorrect speculations. This include slots used to issue uops t= hat do not eventually get retired and slots for which the issue-pipeline wa= s blocked due to recovery from earlier incorrect speculation. For example; = wasted work due to miss-predicted branches are categorized under Bad Specul= ation category. Incorrect data speculation followed by Memory Ordering Nuke= s is another example.", + "MetricExpr": "100 * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_S= LOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT= _MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 )= if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricGroup": "TmaL1", + "MetricName": "tma_bad_speculation_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Branch Misprediction. These slots are either wasted = by uops fetched from an incorrectly speculated program path; or stalls when= the out-of-order part of the machine needs to recover its state from a spe= culative path.", + "MetricExpr": "100 * ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_= RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( U= OPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 )= if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHAL= TED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricGroup": "BadSpec;BrMispredicts;TmaL2;m_tma_bad_speculation_= percent", + "MetricName": "tma_branch_mispredicts_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Machine Clears. These slots are either wasted by uop= s fetched prior to the clear; or stalls the out-of-order portion of the mac= hine needs to recover its state after the clear. For example; this can happ= en due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modify= ing-Code (SMC) nukes.", + "MetricExpr": "100 * ( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE= _SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else I= NT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2= ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.= ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * = ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.= RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( = ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNH= ALTED.THREAD ) ) ) ) ) )", + "MetricGroup": "BadSpec;MachineClears;TmaL2;m_tma_bad_speculation_= percent", + "MetricName": "tma_machine_clears_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend. Backend is the portion of the processor cor= e where the out-of-order scheduler dispatches ready uops into their respect= ive execution units; and once completed these uops get retired according to= program order. For example; stalls due to data-cache misses or stalls due = to the divider unit being overloaded are both categorized under Backend Bou= nd. Backend Bound is further divided into two main categories: Memory Bound= and Core Bound.", + "MetricExpr": "100 * ( 1 - ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4= ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALT= ED.THREAD ) ) ) ) + ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + (= 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECO= VERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_o= n else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_RETIRED.RETIRE_SLOTS ) = / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK= _UNHALTED.THREAD ) ) ) ) ) )", + "MetricGroup": "TmaL1", + "MetricName": "tma_backend_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = Memory subsystem within the Backend was a bottleneck. Memory Bound estimat= es fraction of slots where pipeline is likely stalled due to demand load or= store instructions. This accounts mainly for (1) non-completed in-flight m= emory demand loads which coincides with execution units starvation; in addi= tion to (2) cases where stores could impose backpressure on the pipeline wh= en many of them get buffered at the same time (less common out of the two).= ", + "MetricExpr": "100 * ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURC= E_STALLS.SB ) / ( ( CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1= _UOP_EXEC - ( UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if ( ( INST_RETIRED.ANY /= ( CPU_CLK_UNHALTED.THREAD ) ) > 1.8 ) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_= EXEC ) - ( RS_EVENTS.EMPTY_CYCLES if ( ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYC= LES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if = #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) > 0.1 ) else 0 ) + RESOURCE_= STALLS.SB ) ) ) * ( 1 - ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU= _CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) = ) ) ) + ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( I= NT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES = ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU= _CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * = ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.TH= READ ) ) ) ) ) ) )", + "MetricGroup": "Backend;TmaL2;m_tma_backend_bound_percent", + "MetricName": "tma_memory_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was s= talled without loads missing the L1 data cache. The L1 data cache typicall= y has the shortest latency. However; in certain cases like loads blocked o= n older stores; a load might suffer due to high latency even though it is b= eing satisfied by the L1. Another example is loads who miss in the TLB. The= se cases are characterized by execution unit stalls; while some non-complet= ed demand load lives in the machine without having that demand load missing= the L1 cache.", + "MetricExpr": "100 * ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCL= E_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) )", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TmaL3;m_tma_memor= y_bound_percent", + "MetricName": "tma_l1_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was s= talled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 m= isses/L2 hits) can improve the latency and increase performance.", + "MetricExpr": "100 * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_AC= TIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TmaL3;m_tma_memor= y_bound_percent", + "MetricName": "tma_l2_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was s= talled due to loads accesses to L3 cache or contended with a sibling Core. = Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and= increase performance.", + "MetricExpr": "100 * ( ( MEM_LOAD_UOPS_RETIRED.L3_HIT / ( MEM_LOAD= _UOPS_RETIRED.L3_HIT + ( 7 ) * MEM_LOAD_UOPS_RETIRED.L3_MISS ) ) * CYCLE_AC= TIVITY.STALLS_L2_MISS / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TmaL3;m_tma_memor= y_bound_percent", + "MetricName": "tma_l3_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was s= talled on accesses to external memory (DRAM) by loads. Better caching can i= mprove the latency and increase performance.", + "MetricExpr": "100 * ( min( ( ( 1 - ( MEM_LOAD_UOPS_RETIRED.L3_HIT= / ( MEM_LOAD_UOPS_RETIRED.L3_HIT + ( 7 ) * MEM_LOAD_UOPS_RETIRED.L3_MISS )= ) ) * CYCLE_ACTIVITY.STALLS_L2_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 = ) ) )", + "MetricGroup": "MemoryBound;TmaL3mem;TmaL3;m_tma_memory_bound_perc= ent", + "MetricName": "tma_dram_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates how often CPU was stall= ed due to RFO store memory accesses; RFO store issue a read-for-ownership = request before the write. Even though store accesses do not typically stall= out-of-order CPUs; there are few cases where stores can lead to actual sta= lls. This metric will be flagged should RFO stores be a bottleneck.", + "MetricExpr": "100 * ( RESOURCE_STALLS.SB / ( CPU_CLK_UNHALTED.THR= EAD ) )", + "MetricGroup": "MemoryBound;TmaL3mem;TmaL3;m_tma_memory_bound_perc= ent", + "MetricName": "tma_store_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e Core non-memory issues were of a bottleneck. Shortage in hardware comput= e resources; or dependencies in software's instructions are both categorize= d under Core Bound. Hence it may indicate the machine ran out of an out-of-= order resource; certain execution units are overloaded or dependencies in p= rogram's data- or instruction-flow are limiting the performance (e.g. FP-ch= ained long-latency arithmetic operations).", + "MetricExpr": "100 * ( ( 1 - ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( (= 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHA= LTED.THREAD ) ) ) ) + ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) += ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RE= COVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT= _on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_RETIRED.RETIRE_SLOTS = ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_C= LK_UNHALTED.THREAD ) ) ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + RESO= URCE_STALLS.SB ) / ( ( CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_G= E_1_UOP_EXEC - ( UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if ( ( INST_RETIRED.AN= Y / ( CPU_CLK_UNHALTED.THREAD ) ) > 1.8 ) else UOPS_EXECUTED.CYCLES_GE_2_UO= PS_EXEC ) - ( RS_EVENTS.EMPTY_CYCLES if ( ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.= CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) = if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) > 0.1 ) else 0 ) + RESOUR= CE_STALLS.SB ) ) ) * ( 1 - ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( = CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD= ) ) ) ) + ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( = ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCL= ES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( = CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 )= * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED= .THREAD ) ) ) ) ) ) ) )", + "MetricGroup": "Backend;TmaL2;Compute;m_tma_backend_bound_percent", + "MetricName": "tma_core_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles whe= re the Divider unit was active. Divide and square root instructions are per= formed by the Divider unit and can take considerably longer latency than in= teger or Floating Point addition; subtraction; or multiplication.", + "MetricExpr": "100 * ( ARITH.FPU_DIV_ACTIVE / ( ( CPU_CLK_UNHALTED= .THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "TmaL3;m_tma_core_bound_percent", + "MetricName": "tma_divider_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles the = CPU performance was potentially limited due to Core computation issues (non= divider-related). Two distinct categories can be attributed into this met= ric: (1) heavy data-dependency among contiguous instructions would manifest= in this metric - such cases are often referred to as low Instruction Level= Parallelism (ILP). (2) Contention on some hardware execution unit other th= an Divider. For example; when there are too many multiply operations.", + "MetricExpr": "100 * ( ( ( ( CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EX= ECUTED.CYCLES_GE_1_UOP_EXEC - ( UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if ( ( = INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) > 1.8 ) else UOPS_EXECUTED= .CYCLES_GE_2_UOPS_EXEC ) - ( RS_EVENTS.EMPTY_CYCLES if ( ( ( 4 ) * IDQ_UOPS= _NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.TH= READ_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) > 0.1 ) el= se 0 ) + RESOURCE_STALLS.SB ) ) - RESOURCE_STALLS.SB - CYCLE_ACTIVITY.STALL= S_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "PortsUtil;TmaL3;m_tma_core_bound_percent", + "MetricName": "tma_ports_utilization_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired. Ideally= ; all pipeline slots would be attributed to the Retiring category. Retirin= g of 100% would indicate the maximum Pipeline_Width throughput was achieved= . Maximizing Retiring typically increases the Instructions-per-cycle (see = IPC metric). Note that a high Retiring value does not necessary mean there = is no room for more performance. For example; Heavy-operations or Microcod= e Assists are categorized under Retiring. They often indicate suboptimal pe= rformance and can often be optimized or avoided. ", + "MetricExpr": "100 * ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * (= ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THR= EAD ) ) ) )", + "MetricGroup": "TmaL1", + "MetricName": "tma_retiring_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring light-weight operations -- instructions that require= no more than one uop (micro-operation). This correlates with total number = of instructions used by the program. A uops-per-instruction (see UPI metric= ) ratio of 1 or less should be expected for decently optimized software run= ning on Intel Core/Xeon products. While this often indicates efficient X86 = instructions were executed; high value does not necessarily mean better per= formance cannot be achieved.", + "MetricExpr": "100 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) *= ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.T= HREAD ) ) ) ) - ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * I= DQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on els= e ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) )", + "MetricGroup": "Retire;TmaL2;m_tma_retiring_percent", + "MetricName": "tma_light_operations_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents overall arithmetic flo= ating-point (FP) operations fraction the CPU has executed (retired). Note t= his metric's value may exceed its parent due to use of \"Uops\" CountDomain= and FMA double-counting.", + "MetricExpr": "100 * ( ( INST_RETIRED.X87 * ( ( UOPS_RETIRED.RETIR= E_SLOTS ) / INST_RETIRED.ANY ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) + ( ( FP_A= RITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) / (= UOPS_RETIRED.RETIRE_SLOTS ) ) + ( min( ( ( FP_ARITH_INST_RETIRED.128B_PACK= ED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRE= D.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / ( UOPS_= RETIRED.RETIRE_SLOTS ) ) , ( 1 ) ) ) )", + "MetricGroup": "HPC;TmaL3;m_tma_light_operations_percent", + "MetricName": "tma_fp_arith_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring heavy-weight operations -- instructions that require= two or more uops or microcoded sequences. This highly-correlates with the = uop length of these instructions/sequences.", + "MetricExpr": "100 * ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_IS= SUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) = if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricGroup": "Retire;TmaL2;m_tma_retiring_percent", + "MetricName": "tma_heavy_operations_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS= is used for CISC instructions not supported by the default decoders (like = repeat move strings; or CPUID); or by microcode assists used to address som= e operation modes (like in Floating Point assists). These cases can often b= e avoided.", + "MetricExpr": "100 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSU= ED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if= #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricGroup": "MicroSeq;TmaL3;m_tma_heavy_operations_percent", + "MetricName": "tma_microcode_sequencer_percent", + "ScaleUnit": "1%" } ] diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 9852bca98d59..533bdee5e738 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -2,7 +2,7 @@ Family-model,Version,Filename,EventType GenuineIntel-6-56,v5,broadwellde,core GenuineIntel-6-3D,v17,broadwell,core GenuineIntel-6-47,v17,broadwell,core -GenuineIntel-6-4F,v10,broadwellx,core +GenuineIntel-6-4F,v19,broadwellx,core GenuineIntel-6-1C,v4,bonnell,core GenuineIntel-6-26,v4,bonnell,core GenuineIntel-6-27,v4,bonnell,core --=20 2.37.1.359.gd136c6c3e2-goog From nobody Wed Apr 15 05:45:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8163C04A68 for ; Wed, 27 Jul 2022 22:09:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233995AbiG0WJC (ORCPT ); Wed, 27 Jul 2022 18:09:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50782 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233351AbiG0WIy (ORCPT ); Wed, 27 Jul 2022 18:08:54 -0400 Received: from mail-pj1-x104a.google.com (mail-pj1-x104a.google.com [IPv6:2607:f8b0:4864:20::104a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AA2EF53D21 for ; Wed, 27 Jul 2022 15:08:49 -0700 (PDT) Received: by mail-pj1-x104a.google.com with SMTP id o3-20020a17090a0a0300b001f3112a9f1cso150221pjo.8 for ; Wed, 27 Jul 2022 15:08:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc:content-transfer-encoding; bh=5xUGZti/Bmhfuljeow7sbvv4Lck1yjFUq6hc30fZjow=; b=fS9R4u1s18eEf+1/BeNnRaFOdz2vlS6HCy88Amkvoj6LWaZ3KMWormc34j08K4jcKT /sfKSHbc884IBV0gsdCkBuhrI4AnRTCa2sjO5AFO5eg0t0Dti7OMSjdwkkC+NwiRVLcS 97Jg1RKEmcMRVE1zTiONx4lZS0sS7oiVR6fUw+XmiJ6Qr2WCMFmFhLXOGcMx28O0LPH4 0Ots8M+oWB986rW7NQAid3V+xTqyRPmeHWY/WGxr9TQAiLHQwTUKi6LENVeIylgUfaVc R7RUryfI25o1GF67mGMl/SrmANOrAAeCaDpen1ksIQDutas4P+VDmuuVSkUxMYnKFWaC onCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc:content-transfer-encoding; bh=5xUGZti/Bmhfuljeow7sbvv4Lck1yjFUq6hc30fZjow=; b=PbAd8+GTUJX7H2AKK3x1fisIDtFDk96WhDXBeerm56gzTQnjMOG5FiRqUj4O+YEBKj 1uNDUjHQS+YvueQISBOUgmbt4Szg1AiO45paehMOR8ooEavj/zbEbHv/tclDltTCGDqF +TGh528JsTzMgV/wqI5Bf2thd9fId1zNQYS+ECTrPuS/3YOK1ERPfwkkk0zvPZyd6MRK oPojb0lrqwCZBO0pTwDwA2tecVQZBu4oi6cplWJQeZYrbpeCg8xutZbFKJMwWIvcs0Rw iF+k5kFo4XFGTUyLd9nhh1+MFYLpvPuq5ywvje9SgZsHWT9MeV7+lWLY1q0zvutefcL5 zaAA== X-Gm-Message-State: AJIora9EAuITBmjP82s4TQWTE0jFsQmDwWdFBv19Ox2VExfAAJoIt5XC 483WVhxKRRA9tRAVjhxXvqXRsQwO1QjL X-Google-Smtp-Source: AGRyM1uyOTJEZsM/mkql1OAzCMs55SF5/VcitxutKGiKDhrENpOsTga+zmyYf6z8FQ6Y/fmso1aTXDLUjEGz X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:882a:af57:8cb6:6f9e]) (user=irogers job=sendgmr) by 2002:a17:90a:1117:b0:1f0:5361:1712 with SMTP id d23-20020a17090a111700b001f053611712mr6939323pja.239.1658959729048; Wed, 27 Jul 2022 15:08:49 -0700 (PDT) Date: Wed, 27 Jul 2022 15:08:04 -0700 In-Reply-To: <20220727220832.2865794-1-irogers@google.com> Message-Id: <20220727220832.2865794-3-irogers@google.com> Mime-Version: 1.0 References: <20220727220832.2865794-1-irogers@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH v3 02/30] perf vendor events: Update Intel broadwell From: Ian Rogers To: perry.taylor@intel.com, caleb.biggers@intel.com, kshipra.bopardikar@intel.com, Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Sedat Dilek Cc: Stephane Eranian , Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Update to v26, the metrics are based on TMA 4.4 full. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/downloa= d_and_gen.py to download and generate the latest events and metrics. Manually copy the broadwell files into perf and update mapfile.csv. Tested on a non-broadwell with 'perf test': 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok Signed-off-by: Ian Rogers --- .../arch/x86/broadwell/bdw-metrics.json | 130 +- .../pmu-events/arch/x86/broadwell/cache.json | 2 +- .../arch/x86/broadwell/floating-point.json | 2 +- .../arch/x86/broadwell/frontend.json | 2 +- .../pmu-events/arch/x86/broadwell/memory.json | 2 +- .../pmu-events/arch/x86/broadwell/other.json | 2 +- .../arch/x86/broadwell/pipeline.json | 2 +- .../arch/x86/broadwell/uncore-cache.json | 152 ++ .../arch/x86/broadwell/uncore-other.json | 82 ++ .../pmu-events/arch/x86/broadwell/uncore.json | 278 ---- .../arch/x86/broadwell/virtual-memory.json | 2 +- .../arch/x86/broadwellde/uncore-other.json | 1246 +++++++++++++++++ tools/perf/pmu-events/arch/x86/mapfile.csv | 3 +- 13 files changed, 1571 insertions(+), 334 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/broadwell/uncore-cache.j= son create mode 100644 tools/perf/pmu-events/arch/x86/broadwell/uncore-other.j= son delete mode 100644 tools/perf/pmu-events/arch/x86/broadwell/uncore.json create mode 100644 tools/perf/pmu-events/arch/x86/broadwellde/uncore-other= .json diff --git a/tools/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json b/to= ols/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json index 91d23341eabd..d65afe3d0b06 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json @@ -130,43 +130,25 @@ "MetricName": "FLOPc_SMT" }, { - "BriefDescription": "Actual per-core usage of the Floating Point e= xecution units (regardless of the vector width)", + "BriefDescription": "Actual per-core usage of the Floating Point n= on-X87 execution units (regardless of precision or vector-width)", "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_I= NST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP= _ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_= DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * CPU_CLK_UNHALT= ED.THREAD )", "MetricGroup": "Cor;Flops;HPC", "MetricName": "FP_Arith_Utilization", - "PublicDescription": "Actual per-core usage of the Floating Point = execution units (regardless of the vector width). Values > 1 are possible d= ue to Fused-Multiply Add (FMA) counting." + "PublicDescription": "Actual per-core usage of the Floating Point = non-X87 execution units (regardless of precision or vector-width). Values >= 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; = [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less commo= n)." }, { - "BriefDescription": "Actual per-core usage of the Floating Point e= xecution units (regardless of the vector width). SMT version; use when SMT = is enabled and measuring per logical CPU.", + "BriefDescription": "Actual per-core usage of the Floating Point n= on-X87 execution units (regardless of precision or vector-width). SMT versi= on; use when SMT is enabled and measuring per logical CPU.", "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_I= NST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP= _ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_= DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * ( ( CPU_CLK_UN= HALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UN= HALTED.REF_XCLK ) ) )", "MetricGroup": "Cor;Flops;HPC_SMT", "MetricName": "FP_Arith_Utilization_SMT", - "PublicDescription": "Actual per-core usage of the Floating Point = execution units (regardless of the vector width). Values > 1 are possible d= ue to Fused-Multiply Add (FMA) counting. SMT version; use when SMT is enabl= ed and measuring per logical CPU." + "PublicDescription": "Actual per-core usage of the Floating Point = non-X87 execution units (regardless of precision or vector-width). Values >= 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; = [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less commo= n). SMT version; use when SMT is enabled and measuring per logical CPU." }, { - "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is at least 1 uop executed)", + "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per-core", "MetricExpr": "UOPS_EXECUTED.THREAD / (( cpu@UOPS_EXECUTED.CORE\\,= cmask\\=3D1@ / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, - { - "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIR= ED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.TH= READ))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_C= LK_UNHALTED.THREAD)) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETI= RED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED= .THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS= .ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_= CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_MISP_RETIRED.A= LL_BRANCHES", - "MetricGroup": "Bad;BrMispredicts", - "MetricName": "Branch_Misprediction_Cost" - }, - { - "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIR= ED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU= _CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU= _CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_D= ELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED= .ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (BR_MISP_RETIRED.ALL= _BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + B= ACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES += MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCL= ES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_C= LK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) * (4 * ( = ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE = / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BrMispredicts_SMT", - "MetricName": "Branch_Misprediction_Cost_SMT" - }, - { - "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear)", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "IpMispredict" - }, { "BriefDescription": "Core actual clocks when any Logical Processor= is active on the Physical Core", "MetricExpr": "( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_U= NHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", @@ -256,6 +238,18 @@ "MetricGroup": "Summary;TmaL1", "MetricName": "Instructions" }, + { + "BriefDescription": "Average number of Uops retired in cycles wher= e at least one uop has retired.", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE= _SLOTS\\,cmask\\=3D1@", + "MetricGroup": "Pipeline;Ret", + "MetricName": "Retire" + }, + { + "BriefDescription": "", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,c= mask\\=3D1@", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", + "MetricName": "Execute" + }, { "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MIT= E_UOPS + IDQ.MS_UOPS ) )", @@ -263,35 +257,34 @@ "MetricName": "DSB_Coverage" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load instructions (in core cycles)", - "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_= MISS + mem_load_uops_retired.hit_lfb )", - "MetricGroup": "Mem;MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency", - "PublicDescription": "Actual Average Latency for L1 data-cache mis= s demand load instructions (in core cycles). Latency may be overestimated f= or multi-load instructions - e.g. repeat strings." + "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "IpMispredict" }, { - "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", - "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLE= S", - "MetricGroup": "Mem;MemoryBound;MemoryBW", - "MetricName": "MLP" + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIR= ED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.TH= READ))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_C= LK_UNHALTED.THREAD)) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETI= RED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED= .THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS= .ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_= CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_MISP_RETIRED.A= LL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "Branch_Misprediction_Cost" }, { - "BriefDescription": "Average data fill bandwidth to the L1 data ca= che [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW" + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIR= ED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU= _CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU= _CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_D= ELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED= .ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (BR_MISP_RETIRED.ALL= _BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + B= ACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES += MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCL= ES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_C= LK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) * (4 * ( = ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE = / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts_SMT", + "MetricName": "Branch_Misprediction_Cost_SMT" }, { - "BriefDescription": "Average data fill bandwidth to the L2 cache [= GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW" + "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load operations (in core cycles)", + "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_= MISS + mem_load_uops_retired.hit_lfb )", + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "Load_Miss_Real_Latency" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW" + "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLE= S", + "MetricGroup": "Mem;MemoryBound;MemoryBW", + "MetricName": "MLP" }, { "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", @@ -306,13 +299,13 @@ "MetricName": "L2MPKI" }, { - "BriefDescription": "L2 cache misses per kilo instruction for all = request types (including speculative)", + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instru= ction for all request types (including speculative)", "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", "MetricGroup": "Mem;CacheMisses;Offcore", "MetricName": "L2MPKI_All" }, { - "BriefDescription": "L2 cache misses per kilo instruction for all = demand loads (including speculative)", + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instru= ction for all demand loads (including speculative)", "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.= ANY", "MetricGroup": "Mem;CacheMisses", "MetricName": "L2MPKI_Load" @@ -348,6 +341,48 @@ "MetricGroup": "Mem;MemoryTLB_SMT", "MetricName": "Page_Walks_Utilization_SMT" }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", + "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L1D_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 2 cache [GB / sec]", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L2_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L3_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L1 data cache [GB / sec]", + "MetricExpr": "(64 * L1D.REPLACEMENT / 1000000000 / duration_time)= ", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L1D_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L2 cache [GB / sec]", + "MetricExpr": "(64 * L2_LINES_IN.ALL / 1000000000 / duration_time)= ", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L2_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L3 cache [GB / sec]", + "MetricExpr": "(64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duratio= n_time)", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L3_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data access bandwidth to t= he L3 cache [GB / sec]", + "MetricExpr": "0", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "L3_Cache_Access_BW_1T" + }, { "BriefDescription": "Average CPU Utilization", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", @@ -364,7 +399,8 @@ "BriefDescription": "Giga Floating Point Operations Per Second", "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_= ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_= DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RET= IRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) = / 1000000000 ) / duration_time", "MetricGroup": "Cor;Flops;HPC", - "MetricName": "GFLOPs" + "MetricName": "GFLOPs", + "PublicDescription": "Giga Floating Point Operations Per Second. A= ggregate across all supported options of: FP precisions, scalar and vector = instructions, vector-width and AMX engine." }, { "BriefDescription": "Average Frequency Utilization relative nomina= l frequency", diff --git a/tools/perf/pmu-events/arch/x86/broadwell/cache.json b/tools/pe= rf/pmu-events/arch/x86/broadwell/cache.json index 890412f02e06..f3d7fced28b6 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/cache.json @@ -3407,4 +3407,4 @@ "SampleAfterValue": "100003", "UMask": "0x10" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/broadwell/floating-point.json b= /tools/perf/pmu-events/arch/x86/broadwell/floating-point.json index 9ad37dddb354..6322116d0d46 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/floating-point.json @@ -190,4 +190,4 @@ "SampleAfterValue": "2000003", "UMask": "0x3" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/broadwell/frontend.json b/tools= /perf/pmu-events/arch/x86/broadwell/frontend.json index f0bcb945ff76..37ce8034b2ed 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/frontend.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/frontend.json @@ -292,4 +292,4 @@ "SampleAfterValue": "2000003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/broadwell/memory.json b/tools/p= erf/pmu-events/arch/x86/broadwell/memory.json index f4eebecf371f..2a7797738159 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/memory.json @@ -3050,4 +3050,4 @@ "SampleAfterValue": "2000003", "UMask": "0x40" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/broadwell/other.json b/tools/pe= rf/pmu-events/arch/x86/broadwell/other.json index 4b360fe96698..917d145d5227 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/other.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/other.json @@ -41,4 +41,4 @@ "SampleAfterValue": "2000003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/broadwell/pipeline.json b/tools= /perf/pmu-events/arch/x86/broadwell/pipeline.json index 18d21b94a4b9..e9a604e2d67c 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/pipeline.json @@ -1377,4 +1377,4 @@ "SampleAfterValue": "2000003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/broadwell/uncore-cache.json b/t= ools/perf/pmu-events/arch/x86/broadwell/uncore-cache.json new file mode 100644 index 000000000000..d1805b3a5e3d --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwell/uncore-cache.json @@ -0,0 +1,152 @@ +[ + { + "BriefDescription": "L3 Lookup any request that access cache and f= ound line in E or S-state", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES", + "PerPkg": "1", + "PublicDescription": "L3 Lookup any request that access cache and = found line in E or S-state.", + "UMask": "0x86", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup any request that access cache and f= ound line in I-state", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I", + "PerPkg": "1", + "PublicDescription": "L3 Lookup any request that access cache and = found line in I-state.", + "UMask": "0x88", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup any request that access cache and f= ound line in M-state", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M", + "PerPkg": "1", + "PublicDescription": "L3 Lookup any request that access cache and = found line in M-state.", + "UMask": "0x81", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup any request that access cache and f= ound line in MESI-state", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI", + "PerPkg": "1", + "PublicDescription": "L3 Lookup any request that access cache and = found line in MESI-state.", + "UMask": "0x8f", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup read request that access cache and = found line in E or S-state", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES", + "PerPkg": "1", + "PublicDescription": "L3 Lookup read request that access cache and= found line in E or S-state.", + "UMask": "0x16", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup read request that access cache and = found line in I-state", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I", + "PerPkg": "1", + "PublicDescription": "L3 Lookup read request that access cache and= found line in I-state.", + "UMask": "0x18", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup read request that access cache and = found line in M-state", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.READ_M", + "PerPkg": "1", + "PublicDescription": "L3 Lookup read request that access cache and= found line in M-state.", + "UMask": "0x11", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup read request that access cache and = found line in any MESI-state", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI", + "PerPkg": "1", + "PublicDescription": "L3 Lookup read request that access cache and= found line in any MESI-state.", + "UMask": "0x1f", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup write request that access cache and= found line in E or S-state", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES", + "PerPkg": "1", + "PublicDescription": "L3 Lookup write request that access cache an= d found line in E or S-state.", + "UMask": "0x26", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup write request that access cache and= found line in M-state", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M", + "PerPkg": "1", + "PublicDescription": "L3 Lookup write request that access cache an= d found line in M-state.", + "UMask": "0x21", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup write request that access cache and= found line in MESI-state", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI", + "PerPkg": "1", + "PublicDescription": "L3 Lookup write request that access cache an= d found line in MESI-state.", + "UMask": "0x2f", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop initiated by this Cbox due= to processor core memory request which hits a modified line in some proces= sor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop initiated by this Cbox du= e to processor core memory request which hits a modified line in some proce= ssor core.", + "UMask": "0x48", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop initiated by this Cbox due= to processor core memory request which hits a non-modified line in some pr= ocessor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop initiated by this Cbox du= e to processor core memory request which hits a non-modified line in some p= rocessor core.", + "UMask": "0x44", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop resulted from L3 Eviction = which misses in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop resulted from L3 Eviction= which misses in some processor core.", + "UMask": "0x81", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop initiated by this Cbox due= to processor core memory request which misses in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop initiated by this Cbox du= e to processor core memory request which misses in some processor core.", + "UMask": "0x41", + "Unit": "CBO" + } +] diff --git a/tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json b/t= ools/perf/pmu-events/arch/x86/broadwell/uncore-other.json new file mode 100644 index 000000000000..73c2261e1e94 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json @@ -0,0 +1,82 @@ +[ + { + "BriefDescription": "Number of entries allocated. Account for Any = type: e.g. Snoop, Core aperture, etc.", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", + "PerPkg": "1", + "PublicDescription": "Number of entries allocated. Account for Any= type: e.g. Snoop, Core aperture, etc.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle count number of all Core outgoing = valid entries. Such entry is defined as valid from it's allocation till fir= st of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-cohe= rent traffic.", + "Counter": "0,", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", + "PerPkg": "1", + "PublicDescription": "Each cycle count number of all Core outgoing= valid entries. Such entry is defined as valid from it's allocation till fi= rst of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coh= erent traffic.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Cycles with at least one request outstanding = is waiting for data return from memory controller. Account for coherent and= non-coherent requests initiated by IA Cores, Processor Graphics Unit, or L= LC.;", + "Counter": "0,", + "CounterMask": "1", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", + "PerPkg": "1", + "PublicDescription": "Cycles with at least one request outstanding= is waiting for data return from memory controller. Account for coherent an= d non-coherent requests initiated by IA Cores, Processor Graphics Unit, or = LLC.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle count number of 'valid' coherent D= ata Read entries that are in DirectData mode. Such entry is defined as vali= d when it is allocated till data sent to Core (first chunk, IDI0). Applicab= le for IA Cores' requests in normal case.", + "Counter": "0,", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.DRD_DIRECT", + "PerPkg": "1", + "PublicDescription": "Each cycle count number of valid coherent Da= ta Read entries that are in DirectData mode. Such entry is defined as valid= when it is allocated till data sent to Core (first chunk, IDI0). Applicabl= e for IA Cores' requests in normal case.", + "UMask": "0x02", + "Unit": "ARB" + }, + { + "BriefDescription": "Total number of Core outgoing entries allocat= ed. Accounts for Coherent and non-coherent traffic.", + "Counter": "0,1", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.ALL", + "PerPkg": "1", + "PublicDescription": "Total number of Core outgoing entries alloca= ted. Accounts for Coherent and non-coherent traffic.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of Core coherent Data Read entries all= ocated in DirectData mode", + "Counter": "0,1", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT", + "PerPkg": "1", + "PublicDescription": "Number of Core coherent Data Read entries al= located in DirectData mode.", + "UMask": "0x02", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of Writes allocated - any write transa= ctions: full/partials writes and evictions.", + "Counter": "0,1", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", + "PerPkg": "1", + "PublicDescription": "Number of Writes allocated - any write trans= actions: full/partials writes and evictions.", + "UMask": "0x20", + "Unit": "ARB" + }, + { + "BriefDescription": "This 48-bit fixed counter counts the UCLK cyc= les", + "Counter": "FIXED", + "EventCode": "0xff", + "EventName": "UNC_CLOCK.SOCKET", + "PerPkg": "1", + "PublicDescription": "This 48-bit fixed counter counts the UCLK cy= cles.", + "Unit": "CLOCK" + } +] diff --git a/tools/perf/pmu-events/arch/x86/broadwell/uncore.json b/tools/p= erf/pmu-events/arch/x86/broadwell/uncore.json deleted file mode 100644 index 28e1e159a3cb..000000000000 --- a/tools/perf/pmu-events/arch/x86/broadwell/uncore.json +++ /dev/null @@ -1,278 +0,0 @@ -[ - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x41", - "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE", - "BriefDescription": "A cross-core snoop initiated by this Cbox due to = processor core memory request which misses in some processor core.", - "PublicDescription": "A cross-core snoop initiated by this Cbox due to= processor core memory request which misses in some processor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x81", - "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION", - "BriefDescription": "A cross-core snoop resulted from L3 Eviction whic= h misses in some processor core.", - "PublicDescription": "A cross-core snoop resulted from L3 Eviction whi= ch misses in some processor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x44", - "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE", - "BriefDescription": "A cross-core snoop initiated by this Cbox due to = processor core memory request which hits a non-modified line in some proces= sor core.", - "PublicDescription": "A cross-core snoop initiated by this Cbox due to= processor core memory request which hits a non-modified line in some proce= ssor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x48", - "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE", - "BriefDescription": "A cross-core snoop initiated by this Cbox due to = processor core memory request which hits a modified line in some processor = core.", - "PublicDescription": "A cross-core snoop initiated by this Cbox due to= processor core memory request which hits a modified line in some processor= core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x11", - "EventName": "UNC_CBO_CACHE_LOOKUP.READ_M", - "BriefDescription": "L3 Lookup read request that access cache and foun= d line in M-state", - "PublicDescription": "L3 Lookup read request that access cache and fou= nd line in M-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x21", - "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M", - "BriefDescription": "L3 Lookup write request that access cache and fou= nd line in M-state", - "PublicDescription": "L3 Lookup write request that access cache and fo= und line in M-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x81", - "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M", - "BriefDescription": "L3 Lookup any request that access cache and found= line in M-state", - "PublicDescription": "L3 Lookup any request that access cache and foun= d line in M-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x18", - "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I", - "BriefDescription": "L3 Lookup read request that access cache and foun= d line in I-state", - "PublicDescription": "L3 Lookup read request that access cache and fou= nd line in I-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x88", - "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I", - "BriefDescription": "L3 Lookup any request that access cache and found= line in I-state", - "PublicDescription": "L3 Lookup any request that access cache and foun= d line in I-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x1f", - "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI", - "BriefDescription": "L3 Lookup read request that access cache and foun= d line in any MESI-state", - "PublicDescription": "L3 Lookup read request that access cache and fou= nd line in any MESI-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x2f", - "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI", - "BriefDescription": "L3 Lookup write request that access cache and fou= nd line in MESI-state", - "PublicDescription": "L3 Lookup write request that access cache and fo= und line in MESI-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x8f", - "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI", - "BriefDescription": "L3 Lookup any request that access cache and found= line in MESI-state", - "PublicDescription": "L3 Lookup any request that access cache and foun= d line in MESI-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x86", - "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES", - "BriefDescription": "L3 Lookup any request that access cache and found= line in E or S-state", - "PublicDescription": "L3 Lookup any request that access cache and foun= d line in E or S-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x16", - "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES", - "BriefDescription": "L3 Lookup read request that access cache and foun= d line in E or S-state", - "PublicDescription": "L3 Lookup read request that access cache and fou= nd line in E or S-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x26", - "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES", - "BriefDescription": "L3 Lookup write request that access cache and fou= nd line in E or S-state", - "PublicDescription": "L3 Lookup write request that access cache and fo= und line in E or S-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "iMPH-U", - "EventCode": "0x80", - "UMask": "0x01", - "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", - "BriefDescription": "Each cycle count number of all Core outgoing vali= d entries. Such entry is defined as valid from it's allocation till first o= f IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent= traffic.", - "PublicDescription": "Each cycle count number of all Core outgoing val= id entries. Such entry is defined as valid from it's allocation till first = of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coheren= t traffic.", - "Counter": "0,", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "iMPH-U", - "EventCode": "0x80", - "UMask": "0x02", - "EventName": "UNC_ARB_TRK_OCCUPANCY.DRD_DIRECT", - "BriefDescription": "Each cycle count number of 'valid' coherent Data = Read entries that are in DirectData mode. Such entry is defined as valid wh= en it is allocated till data sent to Core (first chunk, IDI0). Applicable f= or IA Cores' requests in normal case.", - "PublicDescription": "Each cycle count number of 'valid' coherent Data= Read entries that are in DirectData mode. Such entry is defined as valid w= hen it is allocated till data sent to Core (first chunk, IDI0). Applicable = for IA Cores' requests in normal case.", - "Counter": "0,", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "iMPH-U", - "EventCode": "0x81", - "UMask": "0x01", - "EventName": "UNC_ARB_TRK_REQUESTS.ALL", - "BriefDescription": "Total number of Core outgoing entries allocated. = Accounts for Coherent and non-coherent traffic.", - "PublicDescription": "Total number of Core outgoing entries allocated.= Accounts for Coherent and non-coherent traffic.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "iMPH-U", - "EventCode": "0x81", - "UMask": "0x02", - "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT", - "BriefDescription": "Number of Core coherent Data Read entries allocat= ed in DirectData mode", - "PublicDescription": "Number of Core coherent Data Read entries alloca= ted in DirectData mode.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "iMPH-U", - "EventCode": "0x81", - "UMask": "0x20", - "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", - "BriefDescription": "Number of Writes allocated - any write transactio= ns: full/partials writes and evictions.", - "PublicDescription": "Number of Writes allocated - any write transacti= ons: full/partials writes and evictions.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "iMPH-U", - "EventCode": "0x84", - "UMask": "0x01", - "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", - "BriefDescription": "Number of entries allocated. Account for Any type= : e.g. Snoop, Core aperture, etc.", - "PublicDescription": "Number of entries allocated. Account for Any typ= e: e.g. Snoop, Core aperture, etc.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "iMPH-U", - "EventCode": "0x80", - "UMask": "0x01", - "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", - "BriefDescription": "Cycles with at least one request outstanding is w= aiting for data return from memory controller. Account for coherent and non= -coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.;= ", - "PublicDescription": "Cycles with at least one request outstanding is = waiting for data return from memory controller. Account for coherent and no= n-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.= ", - "Counter": "0,", - "CounterMask": "1", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "NCU", - "EventCode": "0x0", - "UMask": "0x01", - "EventName": "UNC_CLOCK.SOCKET", - "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles", - "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles= .", - "Counter": "FIXED", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - } -] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwell/virtual-memory.json b= /tools/perf/pmu-events/arch/x86/broadwell/virtual-memory.json index 818a8b132c08..6a6de8790f25 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/virtual-memory.json @@ -385,4 +385,4 @@ "SampleAfterValue": "100007", "UMask": "0x20" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-other.json b= /tools/perf/pmu-events/arch/x86/broadwellde/uncore-other.json new file mode 100644 index 000000000000..71bdf75d8016 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-other.json @@ -0,0 +1,1246 @@ +[ + { + "BriefDescription": "Total Write Cache Occupancy; Any Source", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of reads and writes t= hat are outstanding in the uncore in each cycle. This is effectively the s= um of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests f= rom any source port.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Total Write Cache Occupancy; Select Source", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of reads and writes t= hat are outstanding in the uncore in each cycle. This is effectively the s= um of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks only those req= uests that come from the port specified in the IRP_PmonFilter.OrderingQ reg= ister. This register allows one to select one specific queue. It is not p= ossible to monitor multiple queues at a time.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Clocks in the IRP", + "Counter": "0,1", + "EventName": "UNC_I_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Number of clocks in the IRP.", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; CLFlush", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", + "PerPkg": "1", + "PublicDescription": "Counts the number of coherency related opera= tions servied by the IRP", + "UMask": "0x80", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; CRd", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_COHERENT_OPS.CRD", + "PerPkg": "1", + "PublicDescription": "Counts the number of coherency related opera= tions servied by the IRP", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; DRd", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_COHERENT_OPS.DRD", + "PerPkg": "1", + "PublicDescription": "Counts the number of coherency related opera= tions servied by the IRP", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; PCIDCAHin5t", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT", + "PerPkg": "1", + "PublicDescription": "Counts the number of coherency related opera= tions servied by the IRP", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; PCIRdCur", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "Counts the number of coherency related opera= tions servied by the IRP", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; PCIItoM", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_COHERENT_OPS.PCITOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of coherency related opera= tions servied by the IRP", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; RFO", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_COHERENT_OPS.RFO", + "PerPkg": "1", + "PublicDescription": "Counts the number of coherency related opera= tions servied by the IRP", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; WbMtoI", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_COHERENT_OPS.WBMTOI", + "PerPkg": "1", + "PublicDescription": "Counts the number of coherency related opera= tions servied by the IRP", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic = Transactions as Secondary", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Tr= ansactions as Secondary", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.2ND_RD_INSERT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write T= ransactions as Secondary", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.2ND_WR_INSERT", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Fastpath Rejects", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.FAST_REJ", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Fastpath Requests", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.FAST_REQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From = Primary to Secondary", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.FAST_XFER", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From = Primary to Secondary", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.PF_ACK_HINT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Prefetch TimeOut", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.PF_TIMEOUT", + "PerPkg": "1", + "PublicDescription": "Indicates the fetch for a previous prefetch = wasn't accepted by the prefetch. This happens in the case of a prefetch T= imeOut", + "UMask": "0x80", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Data Throttled", + "Counter": "0,1", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.DATA_THROTTLE", + "PerPkg": "1", + "PublicDescription": "IRP throttled switch data", + "UMask": "0x80", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1", + "Counter": "0,1", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.LOST_FWD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Received Invalid", + "Counter": "0,1", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", + "PerPkg": "1", + "PublicDescription": "Secondary received a transfer that did not h= ave sufficient MESI state", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Received Valid", + "Counter": "0,1", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", + "PerPkg": "1", + "PublicDescription": "Secondary received a transfer that did have = sufficient MESI state", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line", + "Counter": "0,1", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.SLOW_E", + "PerPkg": "1", + "PublicDescription": "Secondary received a transfer that did have = sufficient MESI state", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line", + "Counter": "0,1", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.SLOW_I", + "PerPkg": "1", + "PublicDescription": "Snoop took cacheline ownership before write = from data was committed.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line", + "Counter": "0,1", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.SLOW_M", + "PerPkg": "1", + "PublicDescription": "Snoop took cacheline ownership before write = from data was committed.", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line", + "Counter": "0,1", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.SLOW_S", + "PerPkg": "1", + "PublicDescription": "Secondary received a transfer that did not h= ave sufficient MESI state", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "AK Ingress Occupancy", + "Counter": "0,1", + "EventCode": "0xA", + "EventName": "UNC_I_RxR_AK_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the AK= Ingress. This queue is where the IRP receives responses from R2PCIe (the = ring).", + "Unit": "IRP" + }, + { + "Counter": "0,1", + "EventCode": "0x4", + "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the BL Ingr= ess is full. This queue is where the IRP receives data from R2PCIe (the ri= ng). It is used for data returns from read requets as well as outbound MMI= O writes.", + "Unit": "IRP" + }, + { + "BriefDescription": "BL Ingress Occupancy - DRS", + "Counter": "0,1", + "EventCode": "0x1", + "EventName": "UNC_I_RxR_BL_DRS_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the BL= Ingress. This queue is where the IRP receives data from R2PCIe (the ring)= . It is used for data returns from read requets as well as outbound MMIO w= rites.", + "Unit": "IRP" + }, + { + "Counter": "0,1", + "EventCode": "0x7", + "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the BL Ingress = in each cycles. This queue is where the IRP receives data from R2PCIe (the= ring). It is used for data returns from read requets as well as outbound = MMIO writes.", + "Unit": "IRP" + }, + { + "Counter": "0,1", + "EventCode": "0x5", + "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the BL Ingr= ess is full. This queue is where the IRP receives data from R2PCIe (the ri= ng). It is used for data returns from read requets as well as outbound MMI= O writes.", + "Unit": "IRP" + }, + { + "BriefDescription": "BL Ingress Occupancy - NCB", + "Counter": "0,1", + "EventCode": "0x2", + "EventName": "UNC_I_RxR_BL_NCB_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the BL= Ingress. This queue is where the IRP receives data from R2PCIe (the ring)= . It is used for data returns from read requets as well as outbound MMIO w= rites.", + "Unit": "IRP" + }, + { + "Counter": "0,1", + "EventCode": "0x8", + "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the BL Ingress = in each cycles. This queue is where the IRP receives data from R2PCIe (the= ring). It is used for data returns from read requets as well as outbound = MMIO writes.", + "Unit": "IRP" + }, + { + "Counter": "0,1", + "EventCode": "0x6", + "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the BL Ingr= ess is full. This queue is where the IRP receives data from R2PCIe (the ri= ng). It is used for data returns from read requets as well as outbound MMI= O writes.", + "Unit": "IRP" + }, + { + "BriefDescription": "BL Ingress Occupancy - NCS", + "Counter": "0,1", + "EventCode": "0x3", + "EventName": "UNC_I_RxR_BL_NCS_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the BL= Ingress. This queue is where the IRP receives data from R2PCIe (the ring)= . It is used for data returns from read requets as well as outbound MMIO w= rites.", + "Unit": "IRP" + }, + { + "Counter": "0,1", + "EventCode": "0x9", + "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the BL Ingress = in each cycles. This queue is where the IRP receives data from R2PCIe (the= ring). It is used for data returns from read requets as well as outbound = MMIO writes.", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; Hit E or S", + "Counter": "0,1", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.HIT_ES", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; Hit I", + "Counter": "0,1", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.HIT_I", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; Hit M", + "Counter": "0,1", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.HIT_M", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; Miss", + "Counter": "0,1", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.MISS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; SnpCode", + "Counter": "0,1", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.SNPCODE", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; SnpData", + "Counter": "0,1", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.SNPDATA", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; SnpInv", + "Counter": "0,1", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.SNPINV", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Atomic", + "Counter": "0,1", + "EventCode": "0x16", + "EventName": "UNC_I_TRANSACTIONS.ATOMIC", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions fr= om the IRP to the Uncore. This can be filtered based on request type in ad= dition to the source queue. Note the special filtering equation. We do OR= -reduction on the request type. If the SOURCE bit is set, then we also do = AND qualification based on the source portID.; Tracks the number of atomic = transactions", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Select Source", + "Counter": "0,1", + "EventCode": "0x16", + "EventName": "UNC_I_TRANSACTIONS.ORDERINGQ", + "Filter": "IRPFilter[4:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions fr= om the IRP to the Uncore. This can be filtered based on request type in ad= dition to the source queue. Note the special filtering equation. We do OR= -reduction on the request type. If the SOURCE bit is set, then we also do = AND qualification based on the source portID.; Tracks only those requests t= hat come from the port specified in the IRP_PmonFilter.OrderingQ register. = This register allows one to select one specific queue. It is not possible= to monitor multiple queues at a time. If this bit is not set, then reques= ts from all sources will be counted.", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Other", + "Counter": "0,1", + "EventCode": "0x16", + "EventName": "UNC_I_TRANSACTIONS.OTHER", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions fr= om the IRP to the Uncore. This can be filtered based on request type in ad= dition to the source queue. Note the special filtering equation. We do OR= -reduction on the request type. If the SOURCE bit is set, then we also do = AND qualification based on the source portID.; Tracks the number of 'other'= kinds of transactions.", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Read Prefetches", + "Counter": "0,1", + "EventCode": "0x16", + "EventName": "UNC_I_TRANSACTIONS.RD_PREF", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions fr= om the IRP to the Uncore. This can be filtered based on request type in ad= dition to the source queue. Note the special filtering equation. We do OR= -reduction on the request type. If the SOURCE bit is set, then we also do = AND qualification based on the source portID.; Tracks the number of read pr= efetches.", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Reads", + "Counter": "0,1", + "EventCode": "0x16", + "EventName": "UNC_I_TRANSACTIONS.READS", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions fr= om the IRP to the Uncore. This can be filtered based on request type in ad= dition to the source queue. Note the special filtering equation. We do OR= -reduction on the request type. If the SOURCE bit is set, then we also do = AND qualification based on the source portID.; Tracks only read requests (n= ot including read prefetches).", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Writes", + "Counter": "0,1", + "EventCode": "0x16", + "EventName": "UNC_I_TRANSACTIONS.WRITES", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions fr= om the IRP to the Uncore. This can be filtered based on request type in ad= dition to the source queue. Note the special filtering equation. We do OR= -reduction on the request type. If the SOURCE bit is set, then we also do = AND qualification based on the source portID.; Tracks only write requests. = Each write request should have a prefetch, so there is no need to explicit= ly track these requests.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Write Prefetches", + "Counter": "0,1", + "EventCode": "0x16", + "EventName": "UNC_I_TRANSACTIONS.WR_PREF", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions fr= om the IRP to the Uncore. This can be filtered based on request type in ad= dition to the source queue. Note the special filtering equation. We do OR= -reduction on the request type. If the SOURCE bit is set, then we also do = AND qualification based on the source portID.; Tracks the number of write p= refetches.", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "No AD Egress Credit Stalls", + "Counter": "0,1", + "EventCode": "0x18", + "EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number times when it is not possi= ble to issue a request to the R2PCIe because there are no AD Egress Credits= available.", + "Unit": "IRP" + }, + { + "BriefDescription": "No BL Egress Credit Stalls", + "Counter": "0,1", + "EventCode": "0x19", + "EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number times when it is not possi= ble to issue data to the R2PCIe because there are no BL Egress Credits avai= lable.", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", + "EventCode": "0xE", + "EventName": "UNC_I_TxR_DATA_INSERTS_NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of requests issued to the = switch (towards the devices).", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", + "EventCode": "0xF", + "EventName": "UNC_I_TxR_DATA_INSERTS_NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of requests issued to the = switch (towards the devices).", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Request Queue Occupancy", + "Counter": "0,1", + "EventCode": "0xD", + "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumultes the number of outstanding outboun= d requests from the IRP to the switch (towards the devices). This can be u= sed in conjuection with the allocations event in order to calculate average= latency of outbound requests.", + "Unit": "IRP" + }, + { + "BriefDescription": "Number of uclks in domain", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_R2_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Counts the number of uclks in the R2PCIe ucl= k domain. This could be slightly different than the count in the Ubox beca= use of enable/freeze delays. However, because the R2PCIe is close to the U= box, they generally should not diverge by more than a handful of cycles.", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credit Acquired; DRS", + "Counter": "0,1", + "EventCode": "0x33", + "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of credits that are acquir= ed in the R2PCIe agent for sending transactions into the IIO on either NCB = or NCS are in use. Transactions from the BL ring going into the IIO Agent = must first acquire a credit. These credits are for either the NCB or NCS m= essage classes. NCB, or non-coherent bypass messages are used to transmit = data without coherency (and are common). NCS is used for reads to PCIe (an= d should be used sparingly).; Credits to the IIO for the DRS message class.= ", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credit Acquired; NCB", + "Counter": "0,1", + "EventCode": "0x33", + "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of credits that are acquir= ed in the R2PCIe agent for sending transactions into the IIO on either NCB = or NCS are in use. Transactions from the BL ring going into the IIO Agent = must first acquire a credit. These credits are for either the NCB or NCS m= essage classes. NCB, or non-coherent bypass messages are used to transmit = data without coherency (and are common). NCS is used for reads to PCIe (an= d should be used sparingly).; Credits to the IIO for the NCB message class.= ", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credit Acquired; NCS", + "Counter": "0,1", + "EventCode": "0x33", + "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of credits that are acquir= ed in the R2PCIe agent for sending transactions into the IIO on either NCB = or NCS are in use. Transactions from the BL ring going into the IIO Agent = must first acquire a credit. These credits are for either the NCB or NCS m= essage classes. NCB, or non-coherent bypass messages are used to transmit = data without coherency (and are common). NCS is used for reads to PCIe (an= d should be used sparingly).; Credits to the IIO for the NCS message class.= ", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credits in Use; DRS", + "Counter": "0,1", + "EventCode": "0x32", + "EventName": "UNC_R2_IIO_CREDITS_USED.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when one or more= credits in the R2PCIe agent for sending transactions into the IIO on eithe= r NCB or NCS are in use. Transactions from the BL ring going into the IIO = Agent must first acquire a credit. These credits are for either the NCB or= NCS message classes. NCB, or non-coherent bypass messages are used to tra= nsmit data without coherency (and are common). NCS is used for reads to PC= Ie (and should be used sparingly).; Credits to the IIO for the DRS message = class.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credits in Use; NCB", + "Counter": "0,1", + "EventCode": "0x32", + "EventName": "UNC_R2_IIO_CREDITS_USED.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when one or more= credits in the R2PCIe agent for sending transactions into the IIO on eithe= r NCB or NCS are in use. Transactions from the BL ring going into the IIO = Agent must first acquire a credit. These credits are for either the NCB or= NCS message classes. NCB, or non-coherent bypass messages are used to tra= nsmit data without coherency (and are common). NCS is used for reads to PC= Ie (and should be used sparingly).; Credits to the IIO for the NCB message = class.", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credits in Use; NCS", + "Counter": "0,1", + "EventCode": "0x32", + "EventName": "UNC_R2_IIO_CREDITS_USED.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when one or more= credits in the R2PCIe agent for sending transactions into the IIO on eithe= r NCB or NCS are in use. Transactions from the BL ring going into the IIO = Agent must first acquire a credit. These credits are for either the NCB or= NCS message classes. NCB, or non-coherent bypass messages are used to tra= nsmit data without coherency (and are common). NCS is used for reads to PC= Ie (and should be used sparingly).; Credits to the IIO for the NCS message = class.", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; All", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0xF", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0xC", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Even rin= g polarity.", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Odd ring= polarity.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Clockwise", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x3", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Even ring polar= ity.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Odd ring polari= ty.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "AK Ingress Bounced; Dn", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_R2_RING_AK_BOUNCES.DN", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a request de= stined for the AK ingress bounced.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "AK Ingress Bounced; Up", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_R2_RING_AK_BOUNCES.UP", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a request de= stined for the AK ingress bounced.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; All", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0xF", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0xC", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Even rin= g polarity.", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Odd ring= polarity.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Clockwise", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x3", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Even ring polar= ity.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Odd ring polari= ty.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; All", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0xF", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0xC", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Even rin= g polarity.", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Odd ring= polarity.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Clockwise", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x3", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Even ring polar= ity.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Odd ring polari= ty.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 IV Ring in Use; Any", + "Counter": "0,1,2,3", + "EventCode": "0xA", + "EventName": "UNC_R2_RING_IV_USED.ANY", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sent, but does not include when packets are be= ing sunk into the ring stop.", + "UMask": "0xF", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 IV Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", + "EventCode": "0xA", + "EventName": "UNC_R2_RING_IV_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sent, but does not include when packets are be= ing sunk into the ring stop.", + "UMask": "0xC", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 IV Ring in Use; Clockwise", + "Counter": "0,1,2,3", + "EventCode": "0xA", + "EventName": "UNC_R2_RING_IV_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sent, but does not include when packets are be= ing sunk into the ring stop.", + "UMask": "0x3", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; NCB", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_R2_RxR_CYCLES_NE.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe = Ingress is not empty. This tracks one of the three rings that are used by = the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress = Occupancy Accumulator event in order to calculate average queue occupancy. = Multiple ingress buffers can be tracked at a given time using multiple cou= nters.; NCB Ingress Queue", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; NCS", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_R2_RxR_CYCLES_NE.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe = Ingress is not empty. This tracks one of the three rings that are used by = the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress = Occupancy Accumulator event in order to calculate average queue occupancy. = Multiple ingress buffers can be tracked at a given time using multiple cou= nters.; NCS Ingress Queue", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Allocations; NCB", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_R2_RxR_INSERTS.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the R2= PCIe Ingress. This tracks one of the three rings that are used by the R2PC= Ie agent. This can be used in conjunction with the R2PCIe Ingress Occupanc= y Accumulator event in order to calculate average queue latency. Multiple = ingress buffers can be tracked at a given time using multiple counters.; NC= B Ingress Queue", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Allocations; NCS", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_R2_RxR_INSERTS.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the R2= PCIe Ingress. This tracks one of the three rings that are used by the R2PC= Ie agent. This can be used in conjunction with the R2PCIe Ingress Occupanc= y Accumulator event in order to calculate average queue latency. Multiple = ingress buffers can be tracked at a given time using multiple counters.; NC= S Ingress Queue", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Occupancy Accumulator; DRS", + "EventCode": "0x13", + "EventName": "UNC_R2_RxR_OCCUPANCY.DRS", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given R2PCIe = Ingress queue in each cycles. This tracks one of the three ring Ingress bu= ffers. This can be used with the R2PCIe Ingress Not Empty event to calcula= te average occupancy or the R2PCIe Ingress Allocations event in order to ca= lculate average queuing latency.; DRS Ingress Queue", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "SBo0 Credits Acquired; For AD Ring", + "Counter": "0,1", + "EventCode": "0x28", + "EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.AD", + "PerPkg": "1", + "PublicDescription": "Number of Sbo 0 credits acquired in a given = cycle, per ring.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "SBo0 Credits Acquired; For BL Ring", + "Counter": "0,1", + "EventCode": "0x28", + "EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.BL", + "PerPkg": "1", + "PublicDescription": "Number of Sbo 0 credits acquired in a given = cycle, per ring.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "SBo0 Credits Occupancy; For AD Ring", + "EventCode": "0x2A", + "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.AD", + "PerPkg": "1", + "PublicDescription": "Number of Sbo 0 credits in use in a given cy= cle, per ring.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "SBo0 Credits Occupancy; For BL Ring", + "EventCode": "0x2A", + "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.BL", + "PerPkg": "1", + "PublicDescription": "Number of Sbo 0 credits in use in a given cy= cle, per ring.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring", + "Counter": "0,1", + "EventCode": "0x2C", + "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_AD", + "PerPkg": "1", + "PublicDescription": "Number of cycles Egress is stalled waiting f= or an Sbo credit to become available. Per Sbo, per Ring.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring", + "Counter": "0,1", + "EventCode": "0x2C", + "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_BL", + "PerPkg": "1", + "PublicDescription": "Number of cycles Egress is stalled waiting f= or an Sbo credit to become available. Per Sbo, per Ring.", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring", + "Counter": "0,1", + "EventCode": "0x2C", + "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD", + "PerPkg": "1", + "PublicDescription": "Number of cycles Egress is stalled waiting f= or an Sbo credit to become available. Per Sbo, per Ring.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring", + "Counter": "0,1", + "EventCode": "0x2C", + "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_BL", + "PerPkg": "1", + "PublicDescription": "Number of cycles Egress is stalled waiting f= or an Sbo credit to become available. Per Sbo, per Ring.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Full; AD", + "EventCode": "0x25", + "EventName": "UNC_R2_TxR_CYCLES_FULL.AD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe = Egress buffer is full.; AD Egress Queue", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Full; AK", + "EventCode": "0x25", + "EventName": "UNC_R2_TxR_CYCLES_FULL.AK", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe = Egress buffer is full.; AK Egress Queue", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Full; BL", + "EventCode": "0x25", + "EventName": "UNC_R2_TxR_CYCLES_FULL.BL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe = Egress buffer is full.; BL Egress Queue", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Not Empty; AD", + "EventCode": "0x23", + "EventName": "UNC_R2_TxR_CYCLES_NE.AD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe = Egress is not empty. This tracks one of the three rings that are used by t= he R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Oc= cupancy Accumulator event in order to calculate average queue occupancy. O= nly a single Egress queue can be tracked at any given time. It is not poss= ible to filter based on direction or polarity.; AD Egress Queue", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Not Empty; AK", + "EventCode": "0x23", + "EventName": "UNC_R2_TxR_CYCLES_NE.AK", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe = Egress is not empty. This tracks one of the three rings that are used by t= he R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Oc= cupancy Accumulator event in order to calculate average queue occupancy. O= nly a single Egress queue can be tracked at any given time. It is not poss= ible to filter based on direction or polarity.; AK Egress Queue", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Not Empty; BL", + "EventCode": "0x23", + "EventName": "UNC_R2_TxR_CYCLES_NE.BL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe = Egress is not empty. This tracks one of the three rings that are used by t= he R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Oc= cupancy Accumulator event in order to calculate average queue occupancy. O= nly a single Egress queue can be tracked at any given time. It is not poss= ible to filter based on direction or polarity.; BL Egress Queue", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; AD CCW", + "Counter": "0,1", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.DN_AD", + "PerPkg": "1", + "PublicDescription": "AD CounterClockwise Egress Queue", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; AK CCW", + "Counter": "0,1", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.DN_AK", + "PerPkg": "1", + "PublicDescription": "AK CounterClockwise Egress Queue", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; BL CCW", + "Counter": "0,1", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.DN_BL", + "PerPkg": "1", + "PublicDescription": "BL CounterClockwise Egress Queue", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; AK CCW", + "Counter": "0,1", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.UP_AD", + "PerPkg": "1", + "PublicDescription": "BL CounterClockwise Egress Queue", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; BL CW", + "Counter": "0,1", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.UP_AK", + "PerPkg": "1", + "PublicDescription": "AD Clockwise Egress Queue", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; BL CCW", + "Counter": "0,1", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.UP_BL", + "PerPkg": "1", + "PublicDescription": "AD CounterClockwise Egress Queue", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "VLW Received", + "Counter": "0,1", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were r= eceived from Uncore. Specify the thread to filter on using NCUPMONCTRLGLC= TR.ThreadID.", + "UMask": "0x8", + "Unit": "UBOX" + }, + { + "BriefDescription": "Filter Match", + "Counter": "0,1", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.DISABLE", + "PerPkg": "1", + "PublicDescription": "Filter match per thread (w/ or w/o Filter En= able). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "Filter Match", + "Counter": "0,1", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.ENABLE", + "Filter": "UBoxFilter[3:0]", + "PerPkg": "1", + "PublicDescription": "Filter match per thread (w/ or w/o Filter En= able). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "Filter Match", + "Counter": "0,1", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE", + "PerPkg": "1", + "PublicDescription": "Filter match per thread (w/ or w/o Filter En= able). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x8", + "Unit": "UBOX" + }, + { + "BriefDescription": "Filter Match", + "Counter": "0,1", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE", + "Filter": "UBoxFilter[3:0]", + "PerPkg": "1", + "PublicDescription": "Filter match per thread (w/ or w/o Filter En= able). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK", + "Counter": "0,1", + "EventCode": "0x45", + "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", + "PerPkg": "1", + "PublicDescription": "PHOLD cycles. Filter from source CoreID.", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "RACU Request", + "Counter": "0,1", + "EventCode": "0x46", + "EventName": "UNC_U_RACU_REQUESTS", + "PerPkg": "1", + "PublicDescription": "Number outstanding register requests within = message channel tracker", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Correctable Machine Check= ", + "Counter": "0,1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.CMC", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one= or all cores", + "UMask": "0x10", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Livelock", + "Counter": "0,1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.LIVELOCK", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one= or all cores; Filter by core", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; LTError", + "Counter": "0,1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.LTERROR", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one= or all cores; Filter by core", + "UMask": "0x8", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Monitor T0", + "Counter": "0,1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one= or all cores; Filter by core", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Monitor T1", + "Counter": "0,1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one= or all cores; Filter by core", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Other", + "Counter": "0,1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.OTHER", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one= or all cores; PREQ, PSMI, P2U, Thermal, PCUSMI, PMI", + "UMask": "0x80", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Trap", + "Counter": "0,1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.TRAP", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one= or all cores", + "UMask": "0x40", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Che= ck", + "Counter": "0,1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.UMC", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one= or all cores", + "UMask": "0x20", + "Unit": "UBOX" + } +] diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 533bdee5e738..94ef16f0207a 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -1,7 +1,6 @@ Family-model,Version,Filename,EventType GenuineIntel-6-56,v5,broadwellde,core -GenuineIntel-6-3D,v17,broadwell,core -GenuineIntel-6-47,v17,broadwell,core +GenuineIntel-6-(3D|47),v26,broadwell,core GenuineIntel-6-4F,v19,broadwellx,core GenuineIntel-6-1C,v4,bonnell,core GenuineIntel-6-26,v4,bonnell,core --=20 2.37.1.359.gd136c6c3e2-goog From nobody Wed Apr 15 05:45:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9768EC19F29 for ; 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Wed, 27 Jul 2022 15:08:51 -0700 (PDT) Date: Wed, 27 Jul 2022 15:08:05 -0700 In-Reply-To: <20220727220832.2865794-1-irogers@google.com> Message-Id: <20220727220832.2865794-4-irogers@google.com> Mime-Version: 1.0 References: <20220727220832.2865794-1-irogers@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH v3 03/30] perf vendor events: Update Intel broadwellde From: Ian Rogers To: perry.taylor@intel.com, caleb.biggers@intel.com, kshipra.bopardikar@intel.com, Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Sedat Dilek Cc: Stephane Eranian , Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Update to v7, the metrics are based on TMA 4.4 full. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/downloa= d_and_gen.py to download and generate the latest events and metrics. Manually copy the broadwellde files into perf and update mapfile.csv. Tested on a non-broadwellde with 'perf test': 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok Signed-off-by: Ian Rogers --- .../arch/x86/broadwellde/bdwde-metrics.json | 136 +- .../arch/x86/broadwellde/cache.json | 2 +- .../arch/x86/broadwellde/floating-point.json | 2 +- .../arch/x86/broadwellde/frontend.json | 2 +- .../arch/x86/broadwellde/memory.json | 2 +- .../arch/x86/broadwellde/other.json | 2 +- .../arch/x86/broadwellde/pipeline.json | 2 +- .../arch/x86/broadwellde/uncore-cache.json | 3818 ++++++++++++++++- .../arch/x86/broadwellde/uncore-memory.json | 2867 ++++++++++++- .../arch/x86/broadwellde/uncore-power.json | 492 ++- .../arch/x86/broadwellde/virtual-memory.json | 2 +- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 12 files changed, 7062 insertions(+), 267 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json = b/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json index 73b6865a769d..6789285555f0 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json @@ -47,7 +47,7 @@ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.T= HREAD)", "MetricGroup": "TopdownL1", "MetricName": "Retiring", - "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided." + "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. " }, { "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired. SMT ver= sion; use when SMT is enabled and measuring per logical CPU.", @@ -130,43 +130,25 @@ "MetricName": "FLOPc_SMT" }, { - "BriefDescription": "Actual per-core usage of the Floating Point e= xecution units (regardless of the vector width)", + "BriefDescription": "Actual per-core usage of the Floating Point n= on-X87 execution units (regardless of precision or vector-width)", "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_I= NST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP= _ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_= DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * CPU_CLK_UNHALT= ED.THREAD )", "MetricGroup": "Cor;Flops;HPC", "MetricName": "FP_Arith_Utilization", - "PublicDescription": "Actual per-core usage of the Floating Point = execution units (regardless of the vector width). Values > 1 are possible d= ue to Fused-Multiply Add (FMA) counting." + "PublicDescription": "Actual per-core usage of the Floating Point = non-X87 execution units (regardless of precision or vector-width). Values >= 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; = [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less commo= n)." }, { - "BriefDescription": "Actual per-core usage of the Floating Point e= xecution units (regardless of the vector width). SMT version; use when SMT = is enabled and measuring per logical CPU.", + "BriefDescription": "Actual per-core usage of the Floating Point n= on-X87 execution units (regardless of precision or vector-width). SMT versi= on; use when SMT is enabled and measuring per logical CPU.", "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_I= NST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP= _ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_= DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * ( ( CPU_CLK_UN= HALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UN= HALTED.REF_XCLK ) ) )", "MetricGroup": "Cor;Flops;HPC_SMT", "MetricName": "FP_Arith_Utilization_SMT", - "PublicDescription": "Actual per-core usage of the Floating Point = execution units (regardless of the vector width). Values > 1 are possible d= ue to Fused-Multiply Add (FMA) counting. SMT version; use when SMT is enabl= ed and measuring per logical CPU." + "PublicDescription": "Actual per-core usage of the Floating Point = non-X87 execution units (regardless of precision or vector-width). Values >= 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; = [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less commo= n). SMT version; use when SMT is enabled and measuring per logical CPU." }, { - "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is at least 1 uop executed)", + "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per-core", "MetricExpr": "UOPS_EXECUTED.THREAD / (( cpu@UOPS_EXECUTED.CORE\\,= cmask\\=3D1@ / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, - { - "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": "( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRE= D.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRE= D.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THR= EAD))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CL= K_UNHALTED.THREAD)) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.= THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.= ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_C= LK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_MISP_RETIRED.AL= L_BRANCHES", - "MetricGroup": "Bad;BrMispredicts", - "MetricName": "Branch_Misprediction_Cost" - }, - { - "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": "( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRE= D.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRE= D.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DE= LIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.= ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (BR_MISP_RETIRED.ALL_= BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BA= CLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + = MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLE= S_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CL= K_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) * (4 * ( (= CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE /= CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BrMispredicts_SMT", - "MetricName": "Branch_Misprediction_Cost_SMT" - }, - { - "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear)", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "IpMispredict" - }, { "BriefDescription": "Core actual clocks when any Logical Processor= is active on the Physical Core", "MetricExpr": "( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_U= NHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", @@ -204,7 +186,7 @@ "MetricName": "IpTB" }, { - "BriefDescription": "Branch instructions per taken branch.", + "BriefDescription": "Branch instructions per taken branch. ", "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR= _TAKEN", "MetricGroup": "Branches;Fed;PGO", "MetricName": "BpTkBranch" @@ -256,42 +238,53 @@ "MetricGroup": "Summary;TmaL1", "MetricName": "Instructions" }, + { + "BriefDescription": "Average number of Uops retired in cycles wher= e at least one uop has retired.", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE= _SLOTS\\,cmask\\=3D1@", + "MetricGroup": "Pipeline;Ret", + "MetricName": "Retire" + }, + { + "BriefDescription": "", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,c= mask\\=3D1@", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", + "MetricName": "Execute" + }, { "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE= _UOPS + IDQ.MS_UOPS )", + "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MIT= E_UOPS + IDQ.MS_UOPS ) )", "MetricGroup": "DSB;Fed;FetchBW", "MetricName": "DSB_Coverage" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load instructions (in core cycles)", - "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_= MISS + mem_load_uops_retired.hit_lfb )", - "MetricGroup": "Mem;MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency", - "PublicDescription": "Actual Average Latency for L1 data-cache mis= s demand load instructions (in core cycles). Latency may be overestimated f= or multi-load instructions - e.g. repeat strings." + "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "IpMispredict" }, { - "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", - "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLE= S", - "MetricGroup": "Mem;MemoryBound;MemoryBW", - "MetricName": "MLP" + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIR= ED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.TH= READ))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_C= LK_UNHALTED.THREAD)) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETI= RED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED= .THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS= .ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_= CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_MISP_RETIRED.A= LL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "Branch_Misprediction_Cost" }, { - "BriefDescription": "Average data fill bandwidth to the L1 data ca= che [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW" + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIR= ED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU= _CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU= _CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_D= ELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED= .ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (BR_MISP_RETIRED.ALL= _BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + B= ACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES += MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCL= ES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_C= LK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) * (4 * ( = ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE = / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts_SMT", + "MetricName": "Branch_Misprediction_Cost_SMT" }, { - "BriefDescription": "Average data fill bandwidth to the L2 cache [= GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW" + "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load operations (in core cycles)", + "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_= MISS + mem_load_uops_retired.hit_lfb )", + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "Load_Miss_Real_Latency" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW" + "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLE= S", + "MetricGroup": "Mem;MemoryBound;MemoryBW", + "MetricName": "MLP" }, { "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", @@ -306,13 +299,13 @@ "MetricName": "L2MPKI" }, { - "BriefDescription": "L2 cache misses per kilo instruction for all = request types (including speculative)", + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instru= ction for all request types (including speculative)", "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", "MetricGroup": "Mem;CacheMisses;Offcore", "MetricName": "L2MPKI_All" }, { - "BriefDescription": "L2 cache misses per kilo instruction for all = demand loads (including speculative)", + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instru= ction for all demand loads (including speculative)", "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.= ANY", "MetricGroup": "Mem;CacheMisses", "MetricName": "L2MPKI_Load" @@ -348,6 +341,48 @@ "MetricGroup": "Mem;MemoryTLB_SMT", "MetricName": "Page_Walks_Utilization_SMT" }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", + "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L1D_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 2 cache [GB / sec]", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L2_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L3_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L1 data cache [GB / sec]", + "MetricExpr": "(64 * L1D.REPLACEMENT / 1000000000 / duration_time)= ", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L1D_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L2 cache [GB / sec]", + "MetricExpr": "(64 * L2_LINES_IN.ALL / 1000000000 / duration_time)= ", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L2_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L3 cache [GB / sec]", + "MetricExpr": "(64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duratio= n_time)", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L3_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data access bandwidth to t= he L3 cache [GB / sec]", + "MetricExpr": "0", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "L3_Cache_Access_BW_1T" + }, { "BriefDescription": "Average CPU Utilization", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", @@ -364,7 +399,8 @@ "BriefDescription": "Giga Floating Point Operations Per Second", "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_= ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_= DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RET= IRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) = / 1000000000 ) / duration_time", "MetricGroup": "Cor;Flops;HPC", - "MetricName": "GFLOPs" + "MetricName": "GFLOPs", + "PublicDescription": "Giga Floating Point Operations Per Second. A= ggregate across all supported options of: FP precisions, scalar and vector = instructions, vector-width and AMX engine." }, { "BriefDescription": "Average Frequency Utilization relative nomina= l frequency", diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/cache.json b/tools/= perf/pmu-events/arch/x86/broadwellde/cache.json index 0f4de912d099..4b77181b2c53 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/cache.json @@ -806,4 +806,4 @@ "SampleAfterValue": "100003", "UMask": "0x10" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json= b/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json index fdf5dc40b835..46cf18490140 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json @@ -190,4 +190,4 @@ "SampleAfterValue": "2000003", "UMask": "0x3" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/frontend.json b/too= ls/perf/pmu-events/arch/x86/broadwellde/frontend.json index f0bcb945ff76..37ce8034b2ed 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/frontend.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/frontend.json @@ -292,4 +292,4 @@ "SampleAfterValue": "2000003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/memory.json b/tools= /perf/pmu-events/arch/x86/broadwellde/memory.json index 604059e7eb58..a3a5cc6dab42 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/memory.json @@ -429,4 +429,4 @@ "SampleAfterValue": "2000003", "UMask": "0x40" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/other.json b/tools/= perf/pmu-events/arch/x86/broadwellde/other.json index 4b360fe96698..917d145d5227 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/other.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/other.json @@ -41,4 +41,4 @@ "SampleAfterValue": "2000003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json b/too= ls/perf/pmu-events/arch/x86/broadwellde/pipeline.json index 7580b8af0d13..85654037b768 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json @@ -1378,4 +1378,4 @@ "SampleAfterValue": "2000003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-cache.json b= /tools/perf/pmu-events/arch/x86/broadwellde/uncore-cache.json index 58ed6d33d1f4..caadbca1b15b 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-cache.json @@ -1,316 +1,3826 @@ [ { - "BriefDescription": "Uncore cache clock ticks", + "BriefDescription": "Bounce Control", + "Counter": "0,1,2,3", + "EventCode": "0xA", + "EventName": "UNC_C_BOUNCE_CONTROL", + "PerPkg": "1", + "Unit": "CBO" + }, + { + "BriefDescription": "Uncore Clocks", "Counter": "0,1,2,3", "EventName": "UNC_C_CLOCKTICKS", "PerPkg": "1", "Unit": "CBO" }, { - "BriefDescription": "All LLC Misses (code+ data rd + data wr - inc= luding demand and prefetch)", + "BriefDescription": "Counter 0 Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0x1F", + "EventName": "UNC_C_COUNTER0_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Since occupancy counts can only be captured = in the Cbo's 0 counter, this event allows a user to capture occupancy relat= ed information by filtering the Cb0 occupancy count captured in Counter 0. = The filtering available is found in the control register - threshold, inv= ert and edge detect. E.g. setting threshold to 1 can effectively monitor = how many cycles the monitored queue has an entry.", + "Unit": "CBO" + }, + { + "BriefDescription": "FaST wire asserted", + "Counter": "0,1", + "EventCode": "0x9", + "EventName": "UNC_C_FAST_ASSERTED", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles either the local= distress or incoming distress signals are asserted. Incoming distress inc= ludes both up and dn.", + "Unit": "CBO" + }, + { + "BriefDescription": "Cache Lookups; Any Request", "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.ANY", - "Filter": "filter_state=3D0x1", + "Filter": "CBoFilter0[23:17]", "PerPkg": "1", - "ScaleUnit": "64Bytes", + "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:1= 8] bits correspond to [FMESI] state.; Filters for any transaction originati= ng from the IPQ or IRQ. This does not include lookups originating from the= ISMQ.", "UMask": "0x11", "Unit": "CBO" }, { - "BriefDescription": "M line evictions from LLC (writebacks to memo= ry)", + "BriefDescription": "Cache Lookups; Data Read Request", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.DATA_READ", + "Filter": "CBoFilter0[23:17]", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:1= 8] bits correspond to [FMESI] state.; Read transactions", + "UMask": "0x3", + "Unit": "CBO" + }, + { + "BriefDescription": "Cache Lookups; Lookups that Match NID", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.NID", + "Filter": "CBoFilter0[23:17]", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:1= 8] bits correspond to [FMESI] state.; Qualify one of the other subevents by= the Target NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In= conjunction with STATE =3D I, it is possible to monitor misses to specific= NIDs in the system.", + "UMask": "0x41", + "Unit": "CBO" + }, + { + "BriefDescription": "Cache Lookups; Any Read Request", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.READ", + "Filter": "CBoFilter0[22:18]", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:1= 8] bits correspond to [FMESI] state.; Read transactions", + "UMask": "0x21", + "Unit": "CBO" + }, + { + "BriefDescription": "Cache Lookups; External Snoop Request", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP", + "Filter": "CBoFilter0[23:17]", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:1= 8] bits correspond to [FMESI] state.; Filters for only snoop requests comin= g from the remote socket(s) through the IPQ.", + "UMask": "0x9", + "Unit": "CBO" + }, + { + "BriefDescription": "Cache Lookups; Write Requests", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.WRITE", + "Filter": "CBoFilter0[23:17]", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:1= 8] bits correspond to [FMESI] state.; Writeback transactions from L2 to the= LLC This includes all write transactions -- both Cachable and UC.", + "UMask": "0x5", + "Unit": "CBO" + }, + { + "BriefDescription": "Lines Victimized; Lines in E state", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.E_STATE", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Lines Victimized", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.F_STATE", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "Lines Victimized; Lines in S State", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.I_STATE", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Lines Victimized", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.MISS", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "Lines Victimized; Lines in M state", "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.M_STATE", "PerPkg": "1", - "ScaleUnit": "64Bytes", + "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x1", "Unit": "CBO" }, { - "BriefDescription": "LLC misses - demand and prefetch data reads -= excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode", + "BriefDescription": "Lines Victimized; Victimized Lines that Match= NID", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "LLC_MISSES.DATA_READ", - "Filter": "filter_opc=3D0x182", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.NID", + "Filter": "CBoFilter1[17:10]", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", + "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.; Qu= alify one of the other subevents by the Target NID. The NID is programmed = in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE =3D I, it is pos= sible to monitor misses to specific NIDs in the system.", + "UMask": "0x40", "Unit": "CBO" }, { - "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . D= erived from unc_c_tor_inserts.miss_opcode", + "BriefDescription": "Cbo Misc; DRd hitting non-M with raw CV=3D0", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "LLC_MISSES.UNCACHEABLE", - "Filter": "filter_opc=3D0x187", + "EventCode": "0x39", + "EventName": "UNC_C_MISC.CVZERO_PREFETCH_MISS", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", + "PublicDescription": "Miscellaneous events in the Cbo.", + "UMask": "0x20", "Unit": "CBO" }, { - "BriefDescription": "MMIO reads. Derived from unc_c_tor_inserts.mi= ss_opcode", + "BriefDescription": "Cbo Misc; Clean Victim with raw CV=3D0", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "LLC_MISSES.MMIO_READ", - "Filter": "filter_opc=3D0x187,filter_nc=3D1", + "EventCode": "0x39", + "EventName": "UNC_C_MISC.CVZERO_PREFETCH_VICTIM", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", + "PublicDescription": "Miscellaneous events in the Cbo.", + "UMask": "0x10", "Unit": "CBO" }, { - "BriefDescription": "MMIO writes. Derived from unc_c_tor_inserts.m= iss_opcode", + "BriefDescription": "Cbo Misc; RFO HitS", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "LLC_MISSES.MMIO_WRITE", - "Filter": "filter_opc=3D0x18f,filter_nc=3D1", + "EventCode": "0x39", + "EventName": "UNC_C_MISC.RFO_HIT_S", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", + "PublicDescription": "Miscellaneous events in the Cbo.; Number of = times that an RFO hit in S state. This is useful for determining if it mig= ht be good for a workload to use RspIWB instead of RspSWB.", + "UMask": "0x8", "Unit": "CBO" }, { - "BriefDescription": "LLC prefetch misses for RFO. Derived from unc= _c_tor_inserts.miss_opcode", + "BriefDescription": "Cbo Misc; Silent Snoop Eviction", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "LLC_MISSES.RFO_LLC_PREFETCH", - "Filter": "filter_opc=3D0x190", + "EventCode": "0x39", + "EventName": "UNC_C_MISC.RSPI_WAS_FSE", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", + "PublicDescription": "Miscellaneous events in the Cbo.; Counts the= number of times when a Snoop hit in FSE states and triggered a silent evic= tion. This is useful because this information is lost in the PRE encodings= .", + "UMask": "0x1", "Unit": "CBO" }, { - "BriefDescription": "LLC prefetch misses for code reads. Derived f= rom unc_c_tor_inserts.miss_opcode", + "BriefDescription": "Cbo Misc", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "LLC_MISSES.CODE_LLC_PREFETCH", - "Filter": "filter_opc=3D0x191", + "EventCode": "0x39", + "EventName": "UNC_C_MISC.STARTED", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", + "PublicDescription": "Miscellaneous events in the Cbo.", + "UMask": "0x4", "Unit": "CBO" }, { - "BriefDescription": "LLC prefetch misses for data reads. Derived f= rom unc_c_tor_inserts.miss_opcode", + "BriefDescription": "Cbo Misc; Write Combining Aliasing", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "LLC_MISSES.DATA_LLC_PREFETCH", - "Filter": "filter_opc=3D0x192", + "EventCode": "0x39", + "EventName": "UNC_C_MISC.WC_ALIASING", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", + "PublicDescription": "Miscellaneous events in the Cbo.; Counts the= number of times that a USWC write (WCIL(F)) transaction hit in the LLC in = M state, triggering a WBMtoI followed by the USWC write. This occurs when = there is WC aliasing.", + "UMask": "0x2", "Unit": "CBO" }, { - "BriefDescription": "LLC misses for PCIe read current. Derived fro= m unc_c_tor_inserts.miss_opcode", + "BriefDescription": "LRU Queue; LRU Age 0", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "LLC_MISSES.PCIE_READ", - "Filter": "filter_opc=3D0x19e", + "EventCode": "0x3C", + "EventName": "UNC_C_QLRU.AGE0", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", + "PublicDescription": "How often age was set to 0", + "UMask": "0x1", "Unit": "CBO" }, { - "BriefDescription": "ItoM write misses (as part of fast string mem= cpy stores) + PCIe full line writes. Derived from unc_c_tor_inserts.miss_op= code", + "BriefDescription": "LRU Queue; LRU Age 1", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "LLC_MISSES.PCIE_WRITE", - "Filter": "filter_opc=3D0x1c8", + "EventCode": "0x3C", + "EventName": "UNC_C_QLRU.AGE1", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", + "PublicDescription": "How often age was set to 1", + "UMask": "0x2", "Unit": "CBO" }, { - "BriefDescription": "PCIe write misses (full cache line). Derived = from unc_c_tor_inserts.miss_opcode", + "BriefDescription": "LRU Queue; LRU Age 2", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "LLC_MISSES.PCIE_NON_SNOOP_WRITE", - "Filter": "filter_opc=3D0x1c8,filter_tid=3D0x3e", + "EventCode": "0x3C", + "EventName": "UNC_C_QLRU.AGE2", + "PerPkg": "1", + "PublicDescription": "How often age was set to 2", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "LRU Queue; LRU Age 3", + "Counter": "0,1,2,3", + "EventCode": "0x3C", + "EventName": "UNC_C_QLRU.AGE3", + "PerPkg": "1", + "PublicDescription": "How often age was set to 3", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "LRU Queue; LRU Bits Decremented", + "Counter": "0,1,2,3", + "EventCode": "0x3C", + "EventName": "UNC_C_QLRU.LRU_DECREMENT", + "PerPkg": "1", + "PublicDescription": "How often all LRU bits were decremented by 1= ", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "LRU Queue; Non-0 Aged Victim", + "Counter": "0,1,2,3", + "EventCode": "0x3C", + "EventName": "UNC_C_QLRU.VICTIM_NON_ZERO", + "PerPkg": "1", + "PublicDescription": "How often we picked a victim that had a non-= zero age", + "UMask": "0x20", + "Unit": "CBO" + }, + { + "BriefDescription": "AD Ring In Use; All", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_C_RING_AD_USED.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop. We really have two rings in BDX -- a clockwis= e ring and a counter-clockwise ring. On the left side of the ring, the UP = direction is on the clockwise ring and DN is on the counter-clockwise ring.= On the right side of the ring, this is reversed. The first half of the C= Bos are on the left side of the ring, and the 2nd half are on the right sid= e of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is = NOT the same ring as CBo 2 UP AD because they are on opposite sides of the = ring.", + "UMask": "0xF", + "Unit": "CBO" + }, + { + "BriefDescription": "AD Ring In Use; Down", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_C_RING_AD_USED.CCW", "PerPkg": "1", - "ScaleUnit": "64Bytes", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop. We really have two rings in BDX -- a clockwis= e ring and a counter-clockwise ring. On the left side of the ring, the UP = direction is on the clockwise ring and DN is on the counter-clockwise ring.= On the right side of the ring, this is reversed. The first half of the C= Bos are on the left side of the ring, and the 2nd half are on the right sid= e of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is = NOT the same ring as CBo 2 UP AD because they are on opposite sides of the = ring.", + "UMask": "0xC", + "Unit": "CBO" + }, + { + "BriefDescription": "AD Ring In Use; Up", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_C_RING_AD_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop. We really have two rings in BDX -- a clockwis= e ring and a counter-clockwise ring. On the left side of the ring, the UP = direction is on the clockwise ring and DN is on the counter-clockwise ring.= On the right side of the ring, this is reversed. The first half of the C= Bos are on the left side of the ring, and the 2nd half are on the right sid= e of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is = NOT the same ring as CBo 2 UP AD because they are on opposite sides of the = ring.", "UMask": "0x3", "Unit": "CBO" }, { - "BriefDescription": "PCIe writes (partial cache line). Derived fro= m unc_c_tor_inserts.opcode", + "BriefDescription": "AD Ring In Use; Down and Even", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "LLC_REFERENCES.PCIE_NS_PARTIAL_WRITE", - "Filter": "filter_opc=3D0x180,filter_tid=3D0x3e", + "EventCode": "0x1B", + "EventName": "UNC_C_RING_AD_USED.DOWN_EVEN", "PerPkg": "1", - "UMask": "0x1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop. We really have two rings in BDX -- a clockwis= e ring and a counter-clockwise ring. On the left side of the ring, the UP = direction is on the clockwise ring and DN is on the counter-clockwise ring.= On the right side of the ring, this is reversed. The first half of the C= Bos are on the left side of the ring, and the 2nd half are on the right sid= e of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is = NOT the same ring as CBo 2 UP AD because they are on opposite sides of the = ring.; Filters for the Down and Even ring polarity.", + "UMask": "0x4", "Unit": "CBO" }, { - "BriefDescription": "L2 demand and L2 prefetch code references to = LLC. Derived from unc_c_tor_inserts.opcode", + "BriefDescription": "AD Ring In Use; Down and Odd", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "LLC_REFERENCES.CODE_LLC_PREFETCH", - "Filter": "filter_opc=3D0x181", + "EventCode": "0x1B", + "EventName": "UNC_C_RING_AD_USED.DOWN_ODD", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop. We really have two rings in BDX -- a clockwis= e ring and a counter-clockwise ring. On the left side of the ring, the UP = direction is on the clockwise ring and DN is on the counter-clockwise ring.= On the right side of the ring, this is reversed. The first half of the C= Bos are on the left side of the ring, and the 2nd half are on the right sid= e of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is = NOT the same ring as CBo 2 UP AD because they are on opposite sides of the = ring.; Filters for the Down and Odd ring polarity.", + "UMask": "0x8", "Unit": "CBO" }, { - "BriefDescription": "Streaming stores (full cache line). Derived f= rom unc_c_tor_inserts.opcode", + "BriefDescription": "AD Ring In Use; Up and Even", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "LLC_REFERENCES.STREAMING_FULL", - "Filter": "filter_opc=3D0x18c", + "EventCode": "0x1B", + "EventName": "UNC_C_RING_AD_USED.UP_EVEN", "PerPkg": "1", - "ScaleUnit": "64Bytes", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop. We really have two rings in BDX -- a clockwis= e ring and a counter-clockwise ring. On the left side of the ring, the UP = direction is on the clockwise ring and DN is on the counter-clockwise ring.= On the right side of the ring, this is reversed. The first half of the C= Bos are on the left side of the ring, and the 2nd half are on the right sid= e of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is = NOT the same ring as CBo 2 UP AD because they are on opposite sides of the = ring.; Filters for the Up and Even ring polarity.", "UMask": "0x1", "Unit": "CBO" }, { - "BriefDescription": "Streaming stores (partial cache line). Derive= d from unc_c_tor_inserts.opcode", + "BriefDescription": "AD Ring In Use; Up and Odd", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "LLC_REFERENCES.STREAMING_PARTIAL", - "Filter": "filter_opc=3D0x18d", + "EventCode": "0x1B", + "EventName": "UNC_C_RING_AD_USED.UP_ODD", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop. We really have two rings in BDX -- a clockwis= e ring and a counter-clockwise ring. On the left side of the ring, the UP = direction is on the clockwise ring and DN is on the counter-clockwise ring.= On the right side of the ring, this is reversed. The first half of the C= Bos are on the left side of the ring, and the 2nd half are on the right sid= e of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is = NOT the same ring as CBo 2 UP AD because they are on opposite sides of the = ring.; Filters for the Up and Odd ring polarity.", + "UMask": "0x2", "Unit": "CBO" }, { - "BriefDescription": "PCIe read current. Derived from unc_c_tor_ins= erts.opcode", + "BriefDescription": "AK Ring In Use; All", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "LLC_REFERENCES.PCIE_READ", - "Filter": "filter_opc=3D0x19e", + "EventCode": "0x1C", + "EventName": "UNC_C_RING_AK_USED.ALL", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in BDX -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.", + "UMask": "0xF", "Unit": "CBO" }, { - "BriefDescription": "PCIe write references (full cache line). Deri= ved from unc_c_tor_inserts.opcode", + "BriefDescription": "AK Ring In Use; Down", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "LLC_REFERENCES.PCIE_WRITE", - "Filter": "filter_opc=3D0x1c8,filter_tid=3D0x3e", + "EventCode": "0x1C", + "EventName": "UNC_C_RING_AK_USED.CCW", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in BDX -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.", + "UMask": "0xC", "Unit": "CBO" }, { - "BriefDescription": "Occupancy counter for LLC data reads (demand = and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.LLC_DATA_READ", - "Filter": "filter_opc=3D0x182", + "BriefDescription": "AK Ring In Use; Up", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_C_RING_AK_USED.CW", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in BDX -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.", "UMask": "0x3", "Unit": "CBO" }, { - "BriefDescription": "read requests to home agent", + "BriefDescription": "AK Ring In Use; Down and Even", "Counter": "0,1,2,3", - "EventCode": "0x1", - "EventName": "UNC_H_REQUESTS.READS", + "EventCode": "0x1C", + "EventName": "UNC_C_RING_AK_USED.DOWN_EVEN", "PerPkg": "1", - "UMask": "0x3", - "Unit": "HA" + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in BDX -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.; Filters for the Down and Even ring polarity.", + "UMask": "0x4", + "Unit": "CBO" }, { - "BriefDescription": "read requests to local home agent", + "BriefDescription": "AK Ring In Use; Down and Odd", "Counter": "0,1,2,3", - "EventCode": "0x1", - "EventName": "UNC_H_REQUESTS.READS_LOCAL", + "EventCode": "0x1C", + "EventName": "UNC_C_RING_AK_USED.DOWN_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in BDX -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.; Filters for the Down and Odd ring polarity.", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "AK Ring In Use; Up and Even", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_C_RING_AK_USED.UP_EVEN", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in BDX -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.; Filters for the Up and Even ring polarity.", "UMask": "0x1", - "Unit": "HA" + "Unit": "CBO" }, { - "BriefDescription": "read requests to remote home agent", + "BriefDescription": "AK Ring In Use; Up and Odd", "Counter": "0,1,2,3", - "EventCode": "0x1", - "EventName": "UNC_H_REQUESTS.READS_REMOTE", + "EventCode": "0x1C", + "EventName": "UNC_C_RING_AK_USED.UP_ODD", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in BDX -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.; Filters for the Up and Odd ring polarity.", "UMask": "0x2", - "Unit": "HA" + "Unit": "CBO" }, { - "BriefDescription": "write requests to home agent", + "BriefDescription": "BL Ring in Use; Down", "Counter": "0,1,2,3", - "EventCode": "0x1", - "EventName": "UNC_H_REQUESTS.WRITES", + "EventCode": "0x1D", + "EventName": "UNC_C_RING_BL_USED.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in BDX -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.", + "UMask": "0xF", + "Unit": "CBO" + }, + { + "BriefDescription": "BL Ring in Use; Down", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_C_RING_BL_USED.CCW", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in BDX -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.", "UMask": "0xC", - "Unit": "HA" + "Unit": "CBO" }, { - "BriefDescription": "write requests to local home agent", + "BriefDescription": "BL Ring in Use; Up", "Counter": "0,1,2,3", - "EventCode": "0x1", - "EventName": "UNC_H_REQUESTS.WRITES_LOCAL", + "EventCode": "0x1D", + "EventName": "UNC_C_RING_BL_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in BDX -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.", + "UMask": "0x3", + "Unit": "CBO" + }, + { + "BriefDescription": "BL Ring in Use; Down and Even", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_C_RING_BL_USED.DOWN_EVEN", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in BDX -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.; Filters for the Down and Even ring polarity.", "UMask": "0x4", - "Unit": "HA" + "Unit": "CBO" }, { - "BriefDescription": "write requests to remote home agent", + "BriefDescription": "BL Ring in Use; Down and Odd", "Counter": "0,1,2,3", - "EventCode": "0x1", - "EventName": "UNC_H_REQUESTS.WRITES_REMOTE", + "EventCode": "0x1D", + "EventName": "UNC_C_RING_BL_USED.DOWN_ODD", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in BDX -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.; Filters for the Down and Odd ring polarity.", "UMask": "0x8", - "Unit": "HA" + "Unit": "CBO" }, { - "BriefDescription": "Conflict requests (requests for same address = from multiple agents simultaneously)", + "BriefDescription": "BL Ring in Use; Up and Even", "Counter": "0,1,2,3", - "EventCode": "0x21", - "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT", + "EventCode": "0x1D", + "EventName": "UNC_C_RING_BL_USED.UP_EVEN", "PerPkg": "1", - "UMask": "0x40", - "Unit": "HA" + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in BDX -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.; Filters for the Up and Even ring polarity.", + "UMask": "0x1", + "Unit": "CBO" }, { - "BriefDescription": "M line forwarded from remote cache along with= writeback to memory", + "BriefDescription": "BL Ring in Use; Up and Odd", "Counter": "0,1,2,3", - "EventCode": "0x21", - "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB", + "EventCode": "0x1D", + "EventName": "UNC_C_RING_BL_USED.UP_ODD", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x20", - "Unit": "HA" + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in BDX -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.; Filters for the Up and Odd ring polarity.", + "UMask": "0x2", + "Unit": "CBO" }, { - "BriefDescription": "M line forwarded from remote cache with no wr= iteback to memory", + "BriefDescription": "Number of LLC responses that bounced on the R= ing.; AD", "Counter": "0,1,2,3", - "EventCode": "0x21", - "EventName": "UNC_H_SNOOP_RESP.RSPIFWD", + "EventCode": "0x5", + "EventName": "UNC_C_RING_BOUNCES.AD", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x4", - "Unit": "HA" + "UMask": "0x1", + "Unit": "CBO" }, { - "BriefDescription": "Shared line response from remote cache", + "BriefDescription": "Number of LLC responses that bounced on the R= ing.; AK", "Counter": "0,1,2,3", - "EventCode": "0x21", - "EventName": "UNC_H_SNOOP_RESP.RSPS", + "EventCode": "0x5", + "EventName": "UNC_C_RING_BOUNCES.AK", "PerPkg": "1", - "ScaleUnit": "64Bytes", "UMask": "0x2", - "Unit": "HA" + "Unit": "CBO" }, { - "BriefDescription": "Shared line forwarded from remote cache", + "BriefDescription": "Number of LLC responses that bounced on the R= ing.; BL", "Counter": "0,1,2,3", - "EventCode": "0x21", - "EventName": "UNC_H_SNOOP_RESP.RSPSFWD", + "EventCode": "0x5", + "EventName": "UNC_C_RING_BOUNCES.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Number of LLC responses that bounced on the R= ing.; Snoops of processor's cache.", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_C_RING_BOUNCES.IV", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "BL Ring in Use; Any", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_C_RING_IV_USED.ANY", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop. There is only 1 IV ring in BDX Therefore, if= one wants to monitor the Even ring, they should select both UP_EVEN and DN= _EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.= ; Filters any polarity", + "UMask": "0xF", + "Unit": "CBO" + }, + { + "BriefDescription": "BL Ring in Use; Any", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_C_RING_IV_USED.DN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop. There is only 1 IV ring in BDX Therefore, if= one wants to monitor the Even ring, they should select both UP_EVEN and DN= _EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.= ; Filters any polarity", + "UMask": "0xC", + "Unit": "CBO" + }, + { + "BriefDescription": "BL Ring in Use; Down", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_C_RING_IV_USED.DOWN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop. There is only 1 IV ring in BDX Therefore, if= one wants to monitor the Even ring, they should select both UP_EVEN and DN= _EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.= ; Filters for Down polarity", + "UMask": "0xCC", + "Unit": "CBO" + }, + { + "BriefDescription": "BL Ring in Use; Any", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_C_RING_IV_USED.UP", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop. There is only 1 IV ring in BDX Therefore, if= one wants to monitor the Even ring, they should select both UP_EVEN and DN= _EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.= ; Filters any polarity", + "UMask": "0x3", + "Unit": "CBO" + }, + { + "BriefDescription": "AD", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "UNC_C_RING_SINK_STARVED.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "AK", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "UNC_C_RING_SINK_STARVED.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "BL", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "UNC_C_RING_SINK_STARVED.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "IV", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "UNC_C_RING_SINK_STARVED.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "Number of cycles the Cbo is actively throttli= ng traffic onto the Ring in order to limit bounce traffic.", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_C_RING_SRC_THRTL", + "PerPkg": "1", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_C_RxR_EXT_STARVED.IPQ", + "PerPkg": "1", + "PublicDescription": "Counts cycles in external starvation. This = occurs when one of the ingress queues is being starved by the other queues.= ; IPQ is externally startved and therefore we are blocking the IRQ.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_C_RxR_EXT_STARVED.IRQ", + "PerPkg": "1", + "PublicDescription": "Counts cycles in external starvation. This = occurs when one of the ingress queues is being starved by the other queues.= ; IRQ is externally starved and therefore we are blocking the IPQ.", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_C_RxR_EXT_STARVED.ISMQ_BIDS", + "PerPkg": "1", + "PublicDescription": "Counts cycles in external starvation. This = occurs when one of the ingress queues is being starved by the other queues.= ; Number of times that the ISMQ Bid.", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Arbiter Blocking Cycles; PRQ", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_C_RxR_EXT_STARVED.PRQ", + "PerPkg": "1", + "PublicDescription": "Counts cycles in external starvation. This = occurs when one of the ingress queues is being starved by the other queues.= ", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Allocations; IPQ", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_C_RxR_INSERTS.IPQ", + "PerPkg": "1", + "PublicDescription": "Counts number of allocations per cycle into = the specified Ingress queue.", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Allocations; IRQ", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_C_RxR_INSERTS.IRQ", + "PerPkg": "1", + "PublicDescription": "Counts number of allocations per cycle into = the specified Ingress queue.", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Allocations; IRQ Rejected", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_C_RxR_INSERTS.IRQ_REJ", + "PerPkg": "1", + "PublicDescription": "Counts number of allocations per cycle into = the specified Ingress queue.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Allocations; PRQ", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_C_RxR_INSERTS.PRQ", + "PerPkg": "1", + "PublicDescription": "Counts number of allocations per cycle into = the specified Ingress queue.", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Allocations; PRQ", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_C_RxR_INSERTS.PRQ_REJ", + "PerPkg": "1", + "PublicDescription": "Counts number of allocations per cycle into = the specified Ingress queue.", + "UMask": "0x20", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Internal Starvation Cycles; IPQ", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_C_RxR_INT_STARVED.IPQ", + "PerPkg": "1", + "PublicDescription": "Counts cycles in internal starvation. This = occurs when one (or more) of the entries in the ingress queue are being sta= rved out by other entries in that queue.; Cycles with the IPQ in Internal S= tarvation.", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Internal Starvation Cycles; IRQ", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_C_RxR_INT_STARVED.IRQ", + "PerPkg": "1", + "PublicDescription": "Counts cycles in internal starvation. This = occurs when one (or more) of the entries in the ingress queue are being sta= rved out by other entries in that queue.; Cycles with the IRQ in Internal S= tarvation.", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Internal Starvation Cycles; ISMQ", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_C_RxR_INT_STARVED.ISMQ", + "PerPkg": "1", + "PublicDescription": "Counts cycles in internal starvation. This = occurs when one (or more) of the entries in the ingress queue are being sta= rved out by other entries in that queue.; Cycles with the ISMQ in Internal = Starvation.", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Internal Starvation Cycles; PRQ", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_C_RxR_INT_STARVED.PRQ", + "PerPkg": "1", + "PublicDescription": "Counts cycles in internal starvation. This = occurs when one (or more) of the entries in the ingress queue are being sta= rved out by other entries in that queue.", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "Probe Queue Retries; Address Conflict", + "Counter": "0,1,2,3", + "EventCode": "0x31", + "EventName": "UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT", + "PerPkg": "1", + "PublicDescription": "Number of times a snoop (probe) request had = to retry. Filters exist to cover some of the common cases retries.; Counts= the number of times that a request form the IPQ was retried because of a T= OR reject from an address conflicts. Address conflicts out of the IPQ shou= ld be rare. They will generally only occur if two different sockets are se= nding requests to the same address at the same time. This is a true confli= ct case, unlike the IPQ Address Conflict which is commonly caused by prefet= ching characteristics.", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Probe Queue Retries; Any Reject", + "Counter": "0,1,2,3", + "EventCode": "0x31", + "EventName": "UNC_C_RxR_IPQ_RETRY.ANY", + "PerPkg": "1", + "PublicDescription": "Number of times a snoop (probe) request had = to retry. Filters exist to cover some of the common cases retries.; Counts= the number of times that a request form the IPQ was retried because of a T= OR reject. TOR rejects from the IPQ can be caused by the Egress being full= or Address Conflicts.", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Probe Queue Retries; No Egress Credits", + "Counter": "0,1,2,3", + "EventCode": "0x31", + "EventName": "UNC_C_RxR_IPQ_RETRY.FULL", + "PerPkg": "1", + "PublicDescription": "Number of times a snoop (probe) request had = to retry. Filters exist to cover some of the common cases retries.; Counts= the number of times that a request form the IPQ was retried because of a T= OR reject from the Egress being full. IPQ requests make use of the AD Egre= ss for regular responses, the BL egress to forward data, and the AK egress = to return credits.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Probe Queue Retries; No QPI Credits", + "Counter": "0,1,2,3", + "EventCode": "0x31", + "EventName": "UNC_C_RxR_IPQ_RETRY.QPI_CREDITS", + "PerPkg": "1", + "PublicDescription": "Number of times a snoop (probe) request had = to retry. Filters exist to cover some of the common cases retries.", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "Probe Queue Retries; No AD Sbo Credits", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "UNC_C_RxR_IPQ_RETRY2.AD_SBO", + "PerPkg": "1", + "PublicDescription": "Number of times a snoop (probe) request had = to retry. Filters exist to cover some of the common cases retries.; Counts= the number of times that a request from the IPQ was retried because of it = lacked credits to send an AD packet to the Sbo.", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Probe Queue Retries; Target Node Filter", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "UNC_C_RxR_IPQ_RETRY2.TARGET", + "Filter": "CBoFilter1[15:0]", + "PerPkg": "1", + "PublicDescription": "Number of times a snoop (probe) request had = to retry. Filters exist to cover some of the common cases retries.; Counts= the number of times that a request from the IPQ was retried filtered by th= e Target NodeID as specified in the Cbox's Filter register.", + "UMask": "0x40", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Request Queue Rejects; Address Confli= ct", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that a request fr= om the IRQ was retried because of an address match in the TOR. In order to= maintain coherency, requests to the same address are not allowed to pass e= ach other up in the Cbo. Therefore, if there is an outstanding request to = a given address, one cannot issue another request to that address until it = is complete. This comes up most commonly with prefetches. Outstanding pre= fetches occasionally will not complete their memory fetch and a demand requ= est to the same address will then sit in the IRQ and get retried until the = prefetch fills the data into the LLC. Therefore, it will not be uncommon t= o see this case in high bandwidth streaming workloads when the LLC Prefetch= er in the core is enabled.", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Request Queue Rejects; Any Reject", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_C_RxR_IRQ_RETRY.ANY", + "PerPkg": "1", + "PublicDescription": "Counts the number of IRQ retries that occur.= Requests from the IRQ are retried if they are rejected from the TOR pipel= ine for a variety of reasons. Some of the most common reasons include if t= he Egress is full, there are no RTIDs, or there is a Physical Address match= to another outstanding request.", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Request Queue Rejects; No Egress Cred= its", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_C_RxR_IRQ_RETRY.FULL", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that a request fr= om the IRQ was retried because it failed to acquire an entry in the Egress.= The egress is the buffer that queues up for allocating onto the ring. IR= Q requests can make use of all four rings and all four Egresses. If any of= the queues that a given request needs to make use of are full, the request= will be retried.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Request Queue Rejects; No IIO Credits= ", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_C_RxR_IRQ_RETRY.IIO_CREDITS", + "PerPkg": "1", + "PublicDescription": "Number of times a request attempted to acqui= re the NCS/NCB credit for sending messages on BL to the IIO. There is a si= ngle credit in each CBo that is shared between the NCS and NCB message clas= ses for sending transactions on the BL ring (such as read data) to the IIO.= ", + "UMask": "0x20", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_C_RxR_IRQ_RETRY.NID", + "Filter": "CBoFilter1[15:0]", + "PerPkg": "1", + "PublicDescription": "Qualify one of the other subevents by a give= n RTID destination NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.n= id.", + "UMask": "0x40", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Request Queue Rejects; No QPI Credits= ", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_C_RxR_IRQ_RETRY.QPI_CREDITS", + "PerPkg": "1", + "PublicDescription": "Number of requests rejects because of lack o= f QPI Ingress credits. These credits are required in order to send transac= tions to the QPI agent. Please see the QPI_IGR_CREDITS events for more inf= ormation.", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Request Queue Rejects; No RTIDs", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_C_RxR_IRQ_RETRY.RTID", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that requests fro= m the IRQ were retried because there were no RTIDs available. RTIDs are re= quired after a request misses the LLC and needs to send snoops and/or reque= sts to memory. If there are no RTIDs available, requests will queue up in = the IRQ and retry until one becomes available. Note that there are multipl= e RTID pools for the different sockets. There may be cases where the local= RTIDs are all used, but requests destined for remote memory can still acqu= ire an RTID because there are remote RTIDs available. This event does not = provide any filtering for this case.", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Request Queue Rejects; No AD Sbo Cred= its", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_C_RxR_IRQ_RETRY2.AD_SBO", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that a request fr= om the IPQ was retried because of it lacked credits to send an AD packet to= the Sbo.", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Request Queue Rejects; No BL Sbo Cred= its", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_C_RxR_IRQ_RETRY2.BL_SBO", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that a request fr= om the IPQ was retried because of it lacked credits to send an BL packet to= the Sbo.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Request Queue Rejects; Target Node Fi= lter", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_C_RxR_IRQ_RETRY2.TARGET", + "Filter": "CBoFilter1[15:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that a request fr= om the IPQ was retried filtered by the Target NodeID as specified in the Cb= ox's Filter register.", + "UMask": "0x40", + "Unit": "CBO" + }, + { + "BriefDescription": "ISMQ Retries; Any Reject", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_C_RxR_ISMQ_RETRY.ANY", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.; Counts the = total number of times that a request from the ISMQ retried because of a TOR= reject. ISMQ requests generally will not need to retry (or at least ISMQ = retries are less common than IRQ retries). ISMQ requests will retry if the= y are not able to acquire a needed Egress credit to get onto the ring, or f= or cache evictions that need to acquire an RTID. Most ISMQ requests alread= y have an RTID, so eviction retries will be less common here.", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "ISMQ Retries; No Egress Credits", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_C_RxR_ISMQ_RETRY.FULL", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.; Counts the = number of times that a request from the ISMQ retried because of a TOR rejec= t caused by a lack of Egress credits. The egress is the buffer that queues = up for allocating onto the ring. If any of the Egress queues that a given = request needs to make use of are full, the request will be retried.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "ISMQ Retries; No IIO Credits", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.; Number of t= imes a request attempted to acquire the NCS/NCB credit for sending messages= on BL to the IIO. There is a single credit in each CBo that is shared bet= ween the NCS and NCB message classes for sending transactions on the BL rin= g (such as read data) to the IIO.", + "UMask": "0x20", + "Unit": "CBO" + }, + { + "BriefDescription": "ISMQ Retries", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_C_RxR_ISMQ_RETRY.NID", + "Filter": "CBoFilter1[15:0]", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.; Qualify one= of the other subevents by a given RTID destination NID. The NID is progra= mmed in Cn_MSR_PMON_BOX_FILTER1.nid.", + "UMask": "0x40", + "Unit": "CBO" + }, + { + "BriefDescription": "ISMQ Retries; No QPI Credits", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "ISMQ Retries; No RTIDs", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_C_RxR_ISMQ_RETRY.RTID", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.; Counts the = number of times that a request from the ISMQ retried because of a TOR rejec= t caused by no RTIDs. M-state cache evictions are serviced through the ISM= Q, and must acquire an RTID in order to write back to memory. If no RTIDs = are available, they will be retried.", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "ISMQ Retries", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_C_RxR_ISMQ_RETRY.WB_CREDITS", + "Filter": "CBoFilter1[15:0]", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.; Qualify one= of the other subevents by a given RTID destination NID. The NID is progra= mmed in Cn_MSR_PMON_BOX_FILTER1.nid.", + "UMask": "0x80", + "Unit": "CBO" + }, + { + "BriefDescription": "ISMQ Request Queue Rejects; No AD Sbo Credits= ", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_C_RxR_ISMQ_RETRY2.AD_SBO", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that a request fr= om the ISMQ was retried because of it lacked credits to send an AD packet t= o the Sbo.", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "ISMQ Request Queue Rejects; No BL Sbo Credits= ", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_C_RxR_ISMQ_RETRY2.BL_SBO", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that a request fr= om the ISMQ was retried because of it lacked credits to send an BL packet t= o the Sbo.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "ISMQ Request Queue Rejects; Target Node Filte= r", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_C_RxR_ISMQ_RETRY2.TARGET", + "Filter": "CBoFilter1[15:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that a request fr= om the ISMQ was retried filtered by the Target NodeID as specified in the C= box's Filter register.", + "UMask": "0x40", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Occupancy; IPQ", + "EventCode": "0x11", + "EventName": "UNC_C_RxR_OCCUPANCY.IPQ", + "PerPkg": "1", + "PublicDescription": "Counts number of entries in the specified In= gress queue in each cycle.", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Occupancy; IRQ", + "EventCode": "0x11", + "EventName": "UNC_C_RxR_OCCUPANCY.IRQ", + "PerPkg": "1", + "PublicDescription": "Counts number of entries in the specified In= gress queue in each cycle.", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Occupancy; IRQ Rejected", + "EventCode": "0x11", + "EventName": "UNC_C_RxR_OCCUPANCY.IRQ_REJ", + "PerPkg": "1", + "PublicDescription": "Counts number of entries in the specified In= gress queue in each cycle.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Occupancy; PRQ Rejects", + "EventCode": "0x11", + "EventName": "UNC_C_RxR_OCCUPANCY.PRQ_REJ", + "PerPkg": "1", + "PublicDescription": "Counts number of entries in the specified In= gress queue in each cycle.", + "UMask": "0x20", + "Unit": "CBO" + }, + { + "BriefDescription": "SBo Credits Acquired; For AD Ring", + "Counter": "0,1,2,3", + "EventCode": "0x3D", + "EventName": "UNC_C_SBO_CREDITS_ACQUIRED.AD", + "PerPkg": "1", + "PublicDescription": "Number of Sbo credits acquired in a given cy= cle, per ring. Each Cbo is assigned an Sbo it can communicate with.", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "SBo Credits Acquired; For BL Ring", + "Counter": "0,1,2,3", + "EventCode": "0x3D", + "EventName": "UNC_C_SBO_CREDITS_ACQUIRED.BL", + "PerPkg": "1", + "PublicDescription": "Number of Sbo credits acquired in a given cy= cle, per ring. Each Cbo is assigned an Sbo it can communicate with.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "SBo Credits Occupancy; For AD Ring", + "EventCode": "0x3E", + "EventName": "UNC_C_SBO_CREDIT_OCCUPANCY.AD", + "PerPkg": "1", + "PublicDescription": "Number of Sbo credits in use in a given cycl= e, per ring. Each Cbo is assigned an Sbo it can communicate with.", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "SBo Credits Occupancy; For BL Ring", + "EventCode": "0x3E", + "EventName": "UNC_C_SBO_CREDIT_OCCUPANCY.BL", + "PerPkg": "1", + "PublicDescription": "Number of Sbo credits in use in a given cycl= e, per ring. Each Cbo is assigned an Sbo it can communicate with.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; All", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted= into the TOR. This includes requests that reside in the TOR for a short= time, such as LLC Hits that do not need to snoop cores or requests that ge= t rejected and have to be retried through one of the ingress queues. The T= OR is more commonly a bottleneck in skews with smaller core counts, where t= he ratio of RTIDs to TOR entries is larger. Note that there are reserved T= OR entries for various request types, so it is possible that a given reques= t type be blocked with an occupancy that is less than 20. Also note that g= enerally requests will not be able to arbitrate into the TOR pipeline if th= ere are no available TOR slots.", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Evictions", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.EVICTION", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Eviction transactions ins= erted into the TOR. Evictions can be quick, such as when the line is in th= e F, S, or E states and no core valid bits are set. They can also be longe= r if either CV bits are set (so the cores need to be snooped) and/or if the= re is a HitM (in which case it is necessary to write the request out to mem= ory).", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Local Memory", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted= into the TOR that are satisifed by locally HOMed memory.", + "UMask": "0x28", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Local Memory - Opcode Matched", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.LOCAL_OPCODE", + "Filter": "CBoFilter1[28:20]", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisif= ed by an opcode, inserted into the TOR that are satisifed by locally HOMed= memory.", + "UMask": "0x21", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Misses to Local Memory", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserte= d into the TOR that are satisifed by locally HOMed memory.", + "UMask": "0x2A", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Misses to Local Memory - Opcode = Matched", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE", + "Filter": "CBoFilter1[28:20]", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisi= fed by an opcode, inserted into the TOR that are satisifed by locally HOMed= memory.", + "UMask": "0x23", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Miss Opcode Match", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", + "Filter": "CBoFilter1[28:20]", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserte= d into the TOR that match an opcode.", + "UMask": "0x3", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Misses to Remote Memory", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserte= d into the TOR that are satisifed by remote caches or remote memory.", + "UMask": "0x8A", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Misses to Remote Memory - Opcode= Matched", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE", + "Filter": "CBoFilter1[28:20]", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisi= fed by an opcode, inserted into the TOR that are satisifed by remote cache= s or remote memory.", + "UMask": "0x83", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; NID Matched", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.NID_ALL", + "Filter": "CBoFilter1[15:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched (matches = an RTID destination) transactions inserted into the TOR. The NID is progra= mmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE =3D I, it is= possible to monitor misses to specific NIDs in the system.", + "UMask": "0x48", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; NID Matched Evictions", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION", + "Filter": "CBoFilter1[15:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched eviction tran= sactions inserted into the TOR.", + "UMask": "0x44", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; NID Matched Miss All", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL", + "Filter": "CBoFilter1[15:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched miss requ= ests that were inserted into the TOR.", + "UMask": "0x4A", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; NID and Opcode Matched Miss", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE", + "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserte= d into the TOR that match a NID and an opcode.", + "UMask": "0x43", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; NID and Opcode Matched", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.NID_OPCODE", + "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted int= o the TOR that match a NID and an opcode.", + "UMask": "0x41", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; NID Matched Writebacks", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.NID_WB", + "Filter": "CBoFilter1[15:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched write transac= tions inserted into the TOR.", + "UMask": "0x50", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Opcode Match", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.OPCODE", + "Filter": "CBoFilter1[28:20]", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted int= o the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Remote Memory", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted= into the TOR that are satisifed by remote caches or remote memory.", + "UMask": "0x88", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Remote Memory - Opcode Matched", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.REMOTE_OPCODE", + "Filter": "CBoFilter1[28:20]", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisif= ed by an opcode, inserted into the TOR that are satisifed by remote caches= or remote memory.", + "UMask": "0x81", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Writebacks", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.WB", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Write transactions insert= ed into the TOR. This does not include RFO, but actual operations that co= ntain data being sent from the core.", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; Any", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.ALL", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All valid TO= R entries. This includes requests that reside in the TOR for a short time,= such as LLC Hits that do not need to snoop cores or requests that get reje= cted and have to be retried through one of the ingress queues. The TOR is = more commonly a bottleneck in skews with smaller core counts, where the rat= io of RTIDs to TOR entries is larger. Note that there are reserved TOR ent= ries for various request types, so it is possible that a given request type= be blocked with an occupancy that is less than 20. Also note that general= ly requests will not be able to arbitrate into the TOR pipeline if there ar= e no available TOR slots.", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; Evictions", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.EVICTION", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding eviction transactions in the TOR. Evictions can be quick, such a= s when the line is in the F, S, or E states and no core valid bits are set.= They can also be longer if either CV bits are set (so the cores need to b= e snooped) and/or if there is a HitM (in which case it is necessary to writ= e the request out to memory).", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", + "UMask": "0x28", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; Local Memory - Opcode Matched", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE", + "Filter": "CBoFilter1[28:20]", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding transactions, satisifed by an opcode, in the TOR that are satis= ifed by locally HOMed memory.", + "UMask": "0x21", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; Miss All", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.MISS_ALL", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding miss requests in the TOR. 'Miss' means the allocation requires a= n RTID. This generally means that the request was sent to memory or MMIO.", + "UMask": "0xA", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", + "UMask": "0x2A", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; Misses to Local Memory - Opcod= e Matched", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE", + "Filter": "CBoFilter1[28:20]", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding Miss transactions, satisifed by an opcode, in the TOR that are sa= tisifed by locally HOMed memory.", + "UMask": "0x23", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; Miss Opcode Match", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE", + "Filter": "CBoFilter1[28:20]", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries = for miss transactions that match an opcode. This generally means that the r= equest was sent to memory or MMIO.", + "UMask": "0x3", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", + "UMask": "0x8A", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; Misses to Remote Memory - Opco= de Matched", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE", + "Filter": "CBoFilter1[28:20]", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding Miss transactions, satisifed by an opcode, in the TOR that are sa= tisifed by remote caches or remote memory.", + "UMask": "0x83", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; NID Matched", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.NID_ALL", + "Filter": "CBoFilter1[15:0]", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of NI= D matched outstanding requests in the TOR. The NID is programmed in Cn_MSR= _PMON_BOX_FILTER.nid.In conjunction with STATE =3D I, it is possible to mon= itor misses to specific NIDs in the system.", + "UMask": "0x48", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; NID Matched Evictions", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.NID_EVICTION", + "Filter": "CBoFilter1[15:0]", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding NID matched eviction transactions in the TOR .", + "UMask": "0x44", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; NID Matched", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_ALL", + "Filter": "CBoFilter1[15:0]", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding Miss requests in the TOR that match a NID.", + "UMask": "0x4A", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; NID and Opcode Matched Miss", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE", + "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding Miss requests in the TOR that match a NID and an opcode.", + "UMask": "0x43", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; NID and Opcode Matched", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.NID_OPCODE", + "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries = that match a NID and an opcode.", + "UMask": "0x41", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; NID Matched Writebacks", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.NID_WB", + "Filter": "CBoFilter1[15:0]", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); NID matched = write transactions int the TOR.", + "UMask": "0x50", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; Opcode Match", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.OPCODE", + "Filter": "CBoFilter1[28:20]", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries = that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc).", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", + "UMask": "0x88", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; Remote Memory - Opcode Matched= ", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE_OPCODE", + "Filter": "CBoFilter1[28:20]", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding transactions, satisifed by an opcode, in the TOR that are satis= ifed by remote caches or remote memory.", + "UMask": "0x81", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; Writebacks", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.WB", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Write transa= ctions in the TOR. This does not include RFO, but actual operations that = contain data being sent from the core.", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "Onto AD Ring", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_C_TxR_ADS_USED.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Onto AK Ring", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_C_TxR_ADS_USED.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Onto BL Ring", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_C_TxR_ADS_USED.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Egress Allocations; AD - Cachebo", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_C_TxR_INSERTS.AD_CACHE", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Cbo Egress. = The Egress is used to queue up requests destined for the ring.; Ring transa= ctions from the Cachebo destined for the AD ring. Some example include out= bound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Egress Allocations; AD - Corebo", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_C_TxR_INSERTS.AD_CORE", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Cbo Egress. = The Egress is used to queue up requests destined for the ring.; Ring transa= ctions from the Corebo destined for the AD ring. This is commonly used for= outbound requests.", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "Egress Allocations; AK - Cachebo", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_C_TxR_INSERTS.AK_CACHE", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Cbo Egress. = The Egress is used to queue up requests destined for the ring.; Ring transa= ctions from the Cachebo destined for the AK ring. This is commonly used fo= r credit returns and GO responses.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Egress Allocations; AK - Corebo", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_C_TxR_INSERTS.AK_CORE", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Cbo Egress. = The Egress is used to queue up requests destined for the ring.; Ring transa= ctions from the Corebo destined for the AK ring. This is commonly used for= snoop responses coming from the core and destined for a Cachebo.", + "UMask": "0x20", + "Unit": "CBO" + }, + { + "BriefDescription": "Egress Allocations; BL - Cacheno", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_C_TxR_INSERTS.BL_CACHE", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Cbo Egress. = The Egress is used to queue up requests destined for the ring.; Ring transa= ctions from the Cachebo destined for the BL ring. This is commonly used to= send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Egress Allocations; BL - Corebo", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_C_TxR_INSERTS.BL_CORE", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Cbo Egress. = The Egress is used to queue up requests destined for the ring.; Ring transa= ctions from the Corebo destined for the BL ring. This is commonly used for= transfering writeback data to the cache.", + "UMask": "0x40", + "Unit": "CBO" + }, + { + "BriefDescription": "Egress Allocations; IV - Cachebo", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_C_TxR_INSERTS.IV_CACHE", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Cbo Egress. = The Egress is used to queue up requests destined for the ring.; Ring transa= ctions from the Cachebo destined for the IV ring. This is commonly used fo= r snoops to the cores.", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "Injection Starvation; Onto AD Ring (to core)", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_C_TxR_STARVED.AD_CORE", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the Egress cannot send a transaction onto the ring for = a long period of time.; cycles that the core AD egress spent in starvation", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "Injection Starvation; Onto AK Ring", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_C_TxR_STARVED.AK_BOTH", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the Egress cannot send a transaction onto the ring for = a long period of time.; cycles that both AK egresses spent in starvation", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Injection Starvation; Onto BL Ring", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_C_TxR_STARVED.BL_BOTH", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the Egress cannot send a transaction onto the ring for = a long period of time.; cycles that both BL egresses spent in starvation", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Injection Starvation; Onto IV Ring", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_C_TxR_STARVED.IV", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the Egress cannot send a transaction onto the ring for = a long period of time.; cycles that the cachebo IV egress spent in starvati= on", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "QPI Address/Opcode Match; AD Opcodes", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_H_ADDR_OPC_MATCH.AD", + "Filter": "HA_OpcodeMatch[5:0]", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "QPI Address/Opcode Match; Address", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_H_ADDR_OPC_MATCH.ADDR", + "Filter": "HA_AddrMatch0[31:6], HA_AddrMatch1[13:0]", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "QPI Address/Opcode Match; AK Opcodes", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_H_ADDR_OPC_MATCH.AK", + "Filter": "HA_OpcodeMatch[5:0]", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "QPI Address/Opcode Match; BL Opcodes", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_H_ADDR_OPC_MATCH.BL", + "Filter": "HA_OpcodeMatch[5:0]", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "QPI Address/Opcode Match; Address & Opcode Ma= tch", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_H_ADDR_OPC_MATCH.FILT", + "Filter": "HA_AddrMatch0[31:6], HA_AddrMatch1[13:0], HA_OpcodeMatc= h[5:0]", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "QPI Address/Opcode Match; Opcode", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_H_ADDR_OPC_MATCH.OPC", + "Filter": "HA_OpcodeMatch[5:0]", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "BT Cycles Not Empty", + "Counter": "0,1,2,3", + "EventCode": "0x42", + "EventName": "UNC_H_BT_CYCLES_NE", + "PerPkg": "1", + "PublicDescription": "Cycles the Backup Tracker (BT) is not empty.= The BT is the actual HOM tracker in IVT.", + "Unit": "HA" + }, + { + "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the HA does= not issue transaction from BT to HT.; Cycles unable to issue from BT due t= o incoming BL data hazard", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "BT to HT Not Issued; Incoming Snoop Hazard", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the HA does= not issue transaction from BT to HT.; Cycles unable to issue from BT due t= o incoming snoop hazard", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.RSPACKCFLT_HAZARD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the HA does= not issue transaction from BT to HT.; Cycles unable to issue from BT due t= o incoming BL data hazard", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.WBMDATA_HAZARD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the HA does= not issue transaction from BT to HT.; Cycles unable to issue from BT due t= o incoming BL data hazard", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "HA to iMC Bypass; Not Taken", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when the HA was a= ble to bypass was attempted. This is a latency optimization for situations= when there is light loadings on the memory subsystem. This can be filted = by when the bypass was taken and when it was not.; Filter for transactions = that could not take the bypass.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA to iMC Bypass; Taken", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_H_BYPASS_IMC.TAKEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when the HA was a= ble to bypass was attempted. This is a latency optimization for situations= when there is light loadings on the memory subsystem. This can be filted = by when the bypass was taken and when it was not.; Filter for transactions = that succeeded in taking the bypass.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "uclks", + "Counter": "0,1,2,3", + "EventName": "UNC_H_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Counts the number of uclks in the HA. This = will be slightly different than the count in the Ubox because of enable/fre= eze delays. The HA is on the other side of the die from the fixed Ubox ucl= k counter, so the drift could be somewhat larger than in units that are clo= ser like the QPI Agent.", + "Unit": "HA" + }, + { + "BriefDescription": "Direct2Core Messages Sent", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_H_DIRECT2CORE_COUNT", + "PerPkg": "1", + "PublicDescription": "Number of Direct2Core messages sent", + "Unit": "HA" + }, + { + "BriefDescription": "Cycles when Direct2Core was Disabled", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_H_DIRECT2CORE_CYCLES_DISABLED", + "PerPkg": "1", + "PublicDescription": "Number of cycles in which Direct2Core was di= sabled", + "Unit": "HA" + }, + { + "BriefDescription": "Number of Reads that had Direct2Core Overridd= en", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_H_DIRECT2CORE_TXN_OVERRIDE", + "PerPkg": "1", + "PublicDescription": "Number of Reads where Direct2Core overridden= ", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Lat Opt Return", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_H_DIRECTORY_LAT_OPT", + "PerPkg": "1", + "PublicDescription": "Directory Latency Optimization Data Return P= ath Taken. When directory mode is enabled and the directory retuned for a r= ead is Dir=3DI, then data can be returned using a faster path if certain co= nditions are met (credits, free pipeline, etc).", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Lookups; Snoop Not Needed", + "Counter": "0,1,2,3", + "EventCode": "0xC", + "EventName": "UNC_H_DIRECTORY_LOOKUP.NO_SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that looke= d up the directory. Can be filtered by requests that had to snoop and thos= e that did not have to.; Filters for transactions that did not have to send= any snoops because the directory bit was clear.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Lookups; Snoop Needed", + "Counter": "0,1,2,3", + "EventCode": "0xC", + "EventName": "UNC_H_DIRECTORY_LOOKUP.SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that looke= d up the directory. Can be filtered by requests that had to snoop and thos= e that did not have to.; Filters for transactions that had to send one or m= ore snoops because the directory bit was set.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Updates; Any Directory Update", + "Counter": "0,1,2,3", + "EventCode": "0xD", + "EventName": "UNC_H_DIRECTORY_UPDATE.ANY", + "PerPkg": "1", + "PublicDescription": "Counts the number of directory updates that = were required. These result in writes to the memory controller. This can = be filtered by directory sets and directory clears.", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Updates; Directory Clear", + "Counter": "0,1,2,3", + "EventCode": "0xD", + "EventName": "UNC_H_DIRECTORY_UPDATE.CLEAR", + "PerPkg": "1", + "PublicDescription": "Counts the number of directory updates that = were required. These result in writes to the memory controller. This can = be filtered by directory sets and directory clears.; Filter for directory c= lears. This occurs when snoops were sent and all returned with RspI.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Updates; Directory Set", + "Counter": "0,1,2,3", + "EventCode": "0xD", + "EventName": "UNC_H_DIRECTORY_UPDATE.SET", + "PerPkg": "1", + "PublicDescription": "Counts the number of directory updates that = were required. These result in writes to the memory controller. This can = be filtered by directory sets and directory clears.; Filter for directory s= ets. This occurs when a remote read transaction requests memory, bringing = it to a remote cache.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; op is A= ckCnfltWbI", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "UNC_H_HITME_HIT.ACKCNFLTWBI", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; All Req= uests", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "UNC_H_HITME_HIT.ALL", + "PerPkg": "1", + "UMask": "0xFF", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocat= ions", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "UNC_H_HITME_HIT.ALLOCS", + "PerPkg": "1", + "UMask": "0x70", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocat= ions", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "UNC_H_HITME_HIT.EVICTS", + "PerPkg": "1", + "UMask": "0x42", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; HOM Req= uests", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "UNC_H_HITME_HIT.HOM", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; Invalid= ations", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "UNC_H_HITME_HIT.INVALS", + "PerPkg": "1", + "UMask": "0x26", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; op is R= dCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "UNC_H_HITME_HIT.READ_OR_INVITOE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; op is R= spI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "UNC_H_HITME_HIT.RSP", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; op is R= spIFwd or RspIFwdWb for a local request", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "UNC_H_HITME_HIT.RSPFWDI_LOCAL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; op is R= spIFwd or RspIFwdWb for a remote request", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "UNC_H_HITME_HIT.RSPFWDI_REMOTE", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; op is R= sSFwd or RspSFwdWb", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "UNC_H_HITME_HIT.RSPFWDS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; op is W= bMtoE or WbMtoS", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "UNC_H_HITME_HIT.WBMTOE_OR_S", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; op is W= bMtoI", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "UNC_H_HITME_HIT.WBMTOI", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; op is AckCnfltWbI", + "Counter": "0,1,2,3", + "EventCode": "0x72", + "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ACKCNFLTWBI", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; All Requests", + "Counter": "0,1,2,3", + "EventCode": "0x72", + "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ALL", + "PerPkg": "1", + "UMask": "0xFF", + "Unit": "HA" + }, + { + "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; HOM Requests", + "Counter": "0,1,2,3", + "EventCode": "0x72", + "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.HOM", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "HA" + }, + { + "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE= ", + "Counter": "0,1,2,3", + "EventCode": "0x72", + "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.READ_OR_INVITOE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI", + "Counter": "0,1,2,3", + "EventCode": "0x72", + "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSP", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "HA" + }, + { + "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; op is RspIFwd or RspIFwdWb for a local request", + "Counter": "0,1,2,3", + "EventCode": "0x72", + "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_LOCAL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "HA" + }, + { + "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; op is RspIFwd or RspIFwdWb for a remote request", + "Counter": "0,1,2,3", + "EventCode": "0x72", + "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; op is RsSFwd or RspSFwdWb", + "Counter": "0,1,2,3", + "EventCode": "0x72", + "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "HA" + }, + { + "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; op is WbMtoE or WbMtoS", + "Counter": "0,1,2,3", + "EventCode": "0x72", + "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOE_OR_S", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; op is WbMtoI", + "Counter": "0,1,2,3", + "EventCode": "0x72", + "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOI", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is AckCnfltWbI", + "Counter": "0,1,2,3", + "EventCode": "0x70", + "EventName": "UNC_H_HITME_LOOKUP.ACKCNFLTWBI", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; All Requests", + "Counter": "0,1,2,3", + "EventCode": "0x70", + "EventName": "UNC_H_HITME_LOOKUP.ALL", + "PerPkg": "1", + "UMask": "0xFF", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; Allocations", + "Counter": "0,1,2,3", + "EventCode": "0x70", + "EventName": "UNC_H_HITME_LOOKUP.ALLOCS", + "PerPkg": "1", + "UMask": "0x70", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; HOM Requests", + "Counter": "0,1,2,3", + "EventCode": "0x70", + "EventName": "UNC_H_HITME_LOOKUP.HOM", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; Invalidations", + "Counter": "0,1,2,3", + "EventCode": "0x70", + "EventName": "UNC_H_HITME_LOOKUP.INVALS", + "PerPkg": "1", + "UMask": "0x26", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE", + "Counter": "0,1,2,3", + "EventCode": "0x70", + "EventName": "UNC_H_HITME_LOOKUP.READ_OR_INVITOE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI", + "Counter": "0,1,2,3", + "EventCode": "0x70", + "EventName": "UNC_H_HITME_LOOKUP.RSP", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is RspIFwd or RspIFwdWb for a local request", + "Counter": "0,1,2,3", + "EventCode": "0x70", + "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_LOCAL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is RspIFwd or RspIFwdWb for a remote request", + "Counter": "0,1,2,3", + "EventCode": "0x70", + "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_REMOTE", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is RsSFwd or RspSFwdWb", + "Counter": "0,1,2,3", + "EventCode": "0x70", + "EventName": "UNC_H_HITME_LOOKUP.RSPFWDS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is WbMtoE or WbMtoS", + "Counter": "0,1,2,3", + "EventCode": "0x70", + "EventName": "UNC_H_HITME_LOOKUP.WBMTOE_OR_S", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is WbMtoI", + "Counter": "0,1,2,3", + "EventCode": "0x70", + "EventName": "UNC_H_HITME_LOOKUP.WBMTOI", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI= Link 0", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the HA does= not have credits to send messages to the QPI Agent. This can be filtered = by the different credit pools and the different links.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI= Link 1", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the HA does= not have credits to send messages to the QPI Agent. This can be filtered = by the different credit pools and the different links.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI= Link 0", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI2", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the HA does= not have credits to send messages to the QPI Agent. This can be filtered = by the different credit pools and the different links.", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI= Link 0", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the HA does= not have credits to send messages to the QPI Agent. This can be filtered = by the different credit pools and the different links.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI= Link 1", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the HA does= not have credits to send messages to the QPI Agent. This can be filtered = by the different credit pools and the different links.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI= Link 1", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI2", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the HA does= not have credits to send messages to the QPI Agent. This can be filtered = by the different credit pools and the different links.", + "UMask": "0x20", + "Unit": "HA" + }, + { + "BriefDescription": "HA to iMC Normal Priority Reads Issued; Norma= l Priority", + "Counter": "0,1,2,3", + "EventCode": "0x17", + "EventName": "UNC_H_IMC_READS.NORMAL", + "PerPkg": "1", + "PublicDescription": "Count of the number of reads issued to any o= f the memory controller channels. This can be filtered by the priority of = the reads.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Retry Events", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_H_IMC_RETRY", + "PerPkg": "1", + "Unit": "HA" + }, + { + "BriefDescription": "HA to iMC Full Line Writes Issued; All Writes= ", + "Counter": "0,1,2,3", + "EventCode": "0x1A", + "EventName": "UNC_H_IMC_WRITES.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the total number of full line writes = issued from the HA into the memory controller. This counts for all four ch= annels. It can be filtered by full/partial and ISOCH/non-ISOCH.", + "UMask": "0xF", + "Unit": "HA" + }, + { + "BriefDescription": "HA to iMC Full Line Writes Issued; Full Line = Non-ISOCH", + "Counter": "0,1,2,3", + "EventCode": "0x1A", + "EventName": "UNC_H_IMC_WRITES.FULL", + "PerPkg": "1", + "PublicDescription": "Counts the total number of full line writes = issued from the HA into the memory controller. This counts for all four ch= annels. It can be filtered by full/partial and ISOCH/non-ISOCH.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Full= Line", + "Counter": "0,1,2,3", + "EventCode": "0x1A", + "EventName": "UNC_H_IMC_WRITES.FULL_ISOCH", + "PerPkg": "1", + "PublicDescription": "Counts the total number of full line writes = issued from the HA into the memory controller. This counts for all four ch= annels. It can be filtered by full/partial and ISOCH/non-ISOCH.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "HA to iMC Full Line Writes Issued; Partial No= n-ISOCH", + "Counter": "0,1,2,3", + "EventCode": "0x1A", + "EventName": "UNC_H_IMC_WRITES.PARTIAL", + "PerPkg": "1", + "PublicDescription": "Counts the total number of full line writes = issued from the HA into the memory controller. This counts for all four ch= annels. It can be filtered by full/partial and ISOCH/non-ISOCH.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Part= ial", + "Counter": "0,1,2,3", + "EventCode": "0x1A", + "EventName": "UNC_H_IMC_WRITES.PARTIAL_ISOCH", + "PerPkg": "1", + "PublicDescription": "Counts the total number of full line writes = issued from the HA into the memory controller. This counts for all four ch= annels. It can be filtered by full/partial and ISOCH/non-ISOCH.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "IOT Backpressure", + "Counter": "0,1,2", + "EventCode": "0x61", + "EventName": "UNC_H_IOT_BACKPRESSURE.HUB", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "IOT Backpressure", + "Counter": "0,1,2", + "EventCode": "0x61", + "EventName": "UNC_H_IOT_BACKPRESSURE.SAT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "IOT Common Trigger Sequencer - Lo", + "Counter": "0,1,2", + "EventCode": "0x64", + "EventName": "UNC_H_IOT_CTS_EAST_LO.CTS0", + "PerPkg": "1", + "PublicDescription": "Debug Mask/Match Tie-Ins", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "IOT Common Trigger Sequencer - Lo", + "Counter": "0,1,2", + "EventCode": "0x64", + "EventName": "UNC_H_IOT_CTS_EAST_LO.CTS1", + "PerPkg": "1", + "PublicDescription": "Debug Mask/Match Tie-Ins", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "IOT Common Trigger Sequencer - Hi", + "Counter": "0,1,2", + "EventCode": "0x65", + "EventName": "UNC_H_IOT_CTS_HI.CTS2", + "PerPkg": "1", + "PublicDescription": "Debug Mask/Match Tie-Ins", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "IOT Common Trigger Sequencer - Hi", + "Counter": "0,1,2", + "EventCode": "0x65", + "EventName": "UNC_H_IOT_CTS_HI.CTS3", + "PerPkg": "1", + "PublicDescription": "Debug Mask/Match Tie-Ins", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "IOT Common Trigger Sequencer - Lo", + "Counter": "0,1,2", + "EventCode": "0x62", + "EventName": "UNC_H_IOT_CTS_WEST_LO.CTS0", + "PerPkg": "1", + "PublicDescription": "Debug Mask/Match Tie-Ins", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "IOT Common Trigger Sequencer - Lo", + "Counter": "0,1,2", + "EventCode": "0x62", + "EventName": "UNC_H_IOT_CTS_WEST_LO.CTS1", + "PerPkg": "1", + "PublicDescription": "Debug Mask/Match Tie-Ins", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "OSB Snoop Broadcast; Cancelled", + "Counter": "0,1,2,3", + "EventCode": "0x53", + "EventName": "UNC_H_OSB.CANCELLED", + "PerPkg": "1", + "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 p= er request causing OSB snoops to be broadcast. Does not count all the snoop= s generated by OSB.; OSB Snoop broadcast cancelled due to D2C or Other. OSB= cancel is counted when OSB local read is not allowed even when the transac= tion in local InItoE. It also counts D2C OSB cancel, but also includes the = cases were D2C was not set in the first place for the transaction coming fr= om the ring.", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "OSB Snoop Broadcast; Local InvItoE", + "Counter": "0,1,2,3", + "EventCode": "0x53", + "EventName": "UNC_H_OSB.INVITOE_LOCAL", + "PerPkg": "1", + "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 p= er request causing OSB snoops to be broadcast. Does not count all the snoop= s generated by OSB.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "OSB Snoop Broadcast; Local Reads", + "Counter": "0,1,2,3", + "EventCode": "0x53", + "EventName": "UNC_H_OSB.READS_LOCAL", + "PerPkg": "1", + "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 p= er request causing OSB snoops to be broadcast. Does not count all the snoop= s generated by OSB.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "OSB Snoop Broadcast; Reads Local - Useful", + "Counter": "0,1,2,3", + "EventCode": "0x53", + "EventName": "UNC_H_OSB.READS_LOCAL_USEFUL", + "PerPkg": "1", + "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 p= er request causing OSB snoops to be broadcast. Does not count all the snoop= s generated by OSB.", + "UMask": "0x20", + "Unit": "HA" + }, + { + "BriefDescription": "OSB Snoop Broadcast; Remote", + "Counter": "0,1,2,3", + "EventCode": "0x53", + "EventName": "UNC_H_OSB.REMOTE", + "PerPkg": "1", + "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 p= er request causing OSB snoops to be broadcast. Does not count all the snoop= s generated by OSB.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "OSB Snoop Broadcast; Remote - Useful", + "Counter": "0,1,2,3", + "EventCode": "0x53", + "EventName": "UNC_H_OSB.REMOTE_USEFUL", + "PerPkg": "1", + "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 p= er request causing OSB snoops to be broadcast. Does not count all the snoop= s generated by OSB.", + "UMask": "0x40", + "Unit": "HA" + }, + { + "BriefDescription": "OSB Early Data Return; All", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "UNC_H_OSB_EDR.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that broad= cast snoop due to OSB, but found clean data in memory and was able to do ea= rly data return", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "OSB Early Data Return; Reads to Local I", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "UNC_H_OSB_EDR.READS_LOCAL_I", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that broad= cast snoop due to OSB, but found clean data in memory and was able to do ea= rly data return", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "OSB Early Data Return; Reads to Local S", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "UNC_H_OSB_EDR.READS_LOCAL_S", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that broad= cast snoop due to OSB, but found clean data in memory and was able to do ea= rly data return", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "OSB Early Data Return; Reads to Remote I", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "UNC_H_OSB_EDR.READS_REMOTE_I", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that broad= cast snoop due to OSB, but found clean data in memory and was able to do ea= rly data return", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "OSB Early Data Return; Reads to Remote S", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "UNC_H_OSB_EDR.READS_REMOTE_S", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that broad= cast snoop due to OSB, but found clean data in memory and was able to do ea= rly data return", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "Read and Write Requests; Local InvItoEs", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts the total number of read requests mad= e into the Home Agent. Reads include all read opcodes (including RFO). Wri= tes include all writes (streaming, evictions, HitM, etc).; This filter incl= udes only InvItoEs coming from the local socket.", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "Read and Write Requests; Remote InvItoEs", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the total number of read requests mad= e into the Home Agent. Reads include all read opcodes (including RFO). Wri= tes include all writes (streaming, evictions, HitM, etc).; This filter incl= udes only InvItoEs coming from remote sockets.", + "UMask": "0x20", + "Unit": "HA" + }, + { + "BriefDescription": "Read and Write Requests; Reads", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_H_REQUESTS.READS", + "PerPkg": "1", + "PublicDescription": "Counts the total number of read requests mad= e into the Home Agent. Reads include all read opcodes (including RFO). Wri= tes include all writes (streaming, evictions, HitM, etc).; Incoming ead req= uests. This is a good proxy for LLC Read Misses (including RFOs).", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "Read and Write Requests; Local Reads", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_H_REQUESTS.READS_LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts the total number of read requests mad= e into the Home Agent. Reads include all read opcodes (including RFO). Wri= tes include all writes (streaming, evictions, HitM, etc).; This filter incl= udes only read requests coming from the local socket. This is a good proxy= for LLC Read Misses (including RFOs) from the local socket.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Read and Write Requests; Remote Reads", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_H_REQUESTS.READS_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the total number of read requests mad= e into the Home Agent. Reads include all read opcodes (including RFO). Wri= tes include all writes (streaming, evictions, HitM, etc).; This filter incl= udes only read requests coming from the remote socket. This is a good prox= y for LLC Read Misses (including RFOs) from the remote socket.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Read and Write Requests; Writes", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_H_REQUESTS.WRITES", + "PerPkg": "1", + "PublicDescription": "Counts the total number of read requests mad= e into the Home Agent. Reads include all read opcodes (including RFO). Wri= tes include all writes (streaming, evictions, HitM, etc).; Incoming write r= equests.", + "UMask": "0xC", + "Unit": "HA" + }, + { + "BriefDescription": "Read and Write Requests; Local Writes", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_H_REQUESTS.WRITES_LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts the total number of read requests mad= e into the Home Agent. Reads include all read opcodes (including RFO). Wri= tes include all writes (streaming, evictions, HitM, etc).; This filter incl= udes only writes coming from the local socket.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "Read and Write Requests; Remote Writes", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_H_REQUESTS.WRITES_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the total number of read requests mad= e into the Home Agent. Reads include all read opcodes (including RFO). Wri= tes include all writes (streaming, evictions, HitM, etc).; This filter incl= udes only writes coming from remote sockets.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "HA AD Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", + "EventCode": "0x3E", + "EventName": "UNC_H_RING_AD_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0xC", + "Unit": "HA" + }, + { + "BriefDescription": "HA AD Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x3E", + "EventName": "UNC_H_RING_AD_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Even rin= g polarity.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x3E", + "EventName": "UNC_H_RING_AD_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Odd ring= polarity.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "HA AD Ring in Use; Clockwise", + "Counter": "0,1,2,3", + "EventCode": "0x3E", + "EventName": "UNC_H_RING_AD_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "HA AD Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x3E", + "EventName": "UNC_H_RING_AD_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Even ring polar= ity.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "HA AD Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x3E", + "EventName": "UNC_H_RING_AD_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Odd ring polari= ty.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA AK Ring in Use; All", + "Counter": "0,1,2,3", + "EventCode": "0x3F", + "EventName": "UNC_H_RING_AK_USED.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0xF", + "Unit": "HA" + }, + { + "BriefDescription": "HA AK Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", + "EventCode": "0x3F", + "EventName": "UNC_H_RING_AK_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0xC", + "Unit": "HA" + }, + { + "BriefDescription": "HA AK Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x3F", + "EventName": "UNC_H_RING_AK_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Even rin= g polarity.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x3F", + "EventName": "UNC_H_RING_AK_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Odd ring= polarity.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "HA AK Ring in Use; Clockwise", + "Counter": "0,1,2,3", + "EventCode": "0x3F", + "EventName": "UNC_H_RING_AK_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "HA AK Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x3F", + "EventName": "UNC_H_RING_AK_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Even ring polar= ity.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "HA AK Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x3F", + "EventName": "UNC_H_RING_AK_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Odd ring polari= ty.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA BL Ring in Use; All", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_H_RING_BL_USED.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0xF", + "Unit": "HA" + }, + { + "BriefDescription": "HA BL Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_H_RING_BL_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0xC", + "Unit": "HA" + }, + { + "BriefDescription": "HA BL Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_H_RING_BL_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Even rin= g polarity.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_H_RING_BL_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Odd ring= polarity.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "HA BL Ring in Use; Clockwise", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_H_RING_BL_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "HA BL Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_H_RING_BL_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Even ring polar= ity.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "HA BL Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_H_RING_BL_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Odd ring polari= ty.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o regular credits available for posting reads from the HA into the iMC. In= order to send reads into the memory controller, the HA must first acquire = a credit for the iMC's RPQ (read pending queue). This queue is broken into= regular credits/buffers that are used by general reads, and special reques= ts such as ISOCH reads. This count only tracks the regular credits Common= high banwidth workloads should be able to make use of all of the regular b= uffers, but it will be difficult (and uncommon) to make use of both the reg= ular and special buffers at the same time. One can filter based on the mem= ory controller channel. One or more channels can be tracked at a given tim= e.; Filter for memory controller channel 0 only.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o regular credits available for posting reads from the HA into the iMC. In= order to send reads into the memory controller, the HA must first acquire = a credit for the iMC's RPQ (read pending queue). This queue is broken into= regular credits/buffers that are used by general reads, and special reques= ts such as ISOCH reads. This count only tracks the regular credits Common= high banwidth workloads should be able to make use of all of the regular b= uffers, but it will be difficult (and uncommon) to make use of both the reg= ular and special buffers at the same time. One can filter based on the mem= ory controller channel. One or more channels can be tracked at a given tim= e.; Filter for memory controller channel 1 only.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o regular credits available for posting reads from the HA into the iMC. In= order to send reads into the memory controller, the HA must first acquire = a credit for the iMC's RPQ (read pending queue). This queue is broken into= regular credits/buffers that are used by general reads, and special reques= ts such as ISOCH reads. This count only tracks the regular credits Common= high banwidth workloads should be able to make use of all of the regular b= uffers, but it will be difficult (and uncommon) to make use of both the reg= ular and special buffers at the same time. One can filter based on the mem= ory controller channel. One or more channels can be tracked at a given tim= e.; Filter for memory controller channel 2 only.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o regular credits available for posting reads from the HA into the iMC. In= order to send reads into the memory controller, the HA must first acquire = a credit for the iMC's RPQ (read pending queue). This queue is broken into= regular credits/buffers that are used by general reads, and special reques= ts such as ISOCH reads. This count only tracks the regular credits Common= high banwidth workloads should be able to make use of all of the regular b= uffers, but it will be difficult (and uncommon) to make use of both the reg= ular and special buffers at the same time. One can filter based on the mem= ory controller channel. One or more channels can be tracked at a given tim= e.; Filter for memory controller channel 3 only.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x16", + "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o special credits available for posting reads from the HA into the iMC. In= order to send reads into the memory controller, the HA must first acquire = a credit for the iMC's RPQ (read pending queue). This queue is broken into= regular credits/buffers that are used by general reads, and special reques= ts such as ISOCH reads. This count only tracks the special credits. This = statistic is generally not interesting for general IA workloads, but may be= of interest for understanding the characteristics of systems using ISOCH. = One can filter based on the memory controller channel. One or more channe= ls can be tracked at a given time.; Filter for memory controller channel 0 = only.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x16", + "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o special credits available for posting reads from the HA into the iMC. In= order to send reads into the memory controller, the HA must first acquire = a credit for the iMC's RPQ (read pending queue). This queue is broken into= regular credits/buffers that are used by general reads, and special reques= ts such as ISOCH reads. This count only tracks the special credits. This = statistic is generally not interesting for general IA workloads, but may be= of interest for understanding the characteristics of systems using ISOCH. = One can filter based on the memory controller channel. One or more channe= ls can be tracked at a given time.; Filter for memory controller channel 1 = only.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x16", + "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o special credits available for posting reads from the HA into the iMC. In= order to send reads into the memory controller, the HA must first acquire = a credit for the iMC's RPQ (read pending queue). This queue is broken into= regular credits/buffers that are used by general reads, and special reques= ts such as ISOCH reads. This count only tracks the special credits. This = statistic is generally not interesting for general IA workloads, but may be= of interest for understanding the characteristics of systems using ISOCH. = One can filter based on the memory controller channel. One or more channe= ls can be tracked at a given time.; Filter for memory controller channel 2 = only.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 3", + "Counter": "0,1,2,3", + "EventCode": "0x16", + "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o special credits available for posting reads from the HA into the iMC. In= order to send reads into the memory controller, the HA must first acquire = a credit for the iMC's RPQ (read pending queue). This queue is broken into= regular credits/buffers that are used by general reads, and special reques= ts such as ISOCH reads. This count only tracks the special credits. This = statistic is generally not interesting for general IA workloads, but may be= of interest for understanding the characteristics of systems using ISOCH. = One can filter based on the memory controller channel. One or more channe= ls can be tracked at a given time.; Filter for memory controller channel 3 = only.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "SBo0 Credits Acquired; For AD Ring", + "Counter": "0,1,2,3", + "EventCode": "0x68", + "EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.AD", + "PerPkg": "1", + "PublicDescription": "Number of Sbo 0 credits acquired in a given = cycle, per ring.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "SBo0 Credits Acquired; For BL Ring", + "Counter": "0,1,2,3", + "EventCode": "0x68", + "EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.BL", + "PerPkg": "1", + "PublicDescription": "Number of Sbo 0 credits acquired in a given = cycle, per ring.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "SBo0 Credits Occupancy; For AD Ring", + "Counter": "0,1,2,3", + "EventCode": "0x6A", + "EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.AD", + "PerPkg": "1", + "PublicDescription": "Number of Sbo 0 credits in use in a given cy= cle, per ring.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "SBo0 Credits Occupancy; For BL Ring", + "Counter": "0,1,2,3", + "EventCode": "0x6A", + "EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.BL", + "PerPkg": "1", + "PublicDescription": "Number of Sbo 0 credits in use in a given cy= cle, per ring.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "SBo1 Credits Acquired; For AD Ring", + "Counter": "0,1,2,3", + "EventCode": "0x69", + "EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.AD", + "PerPkg": "1", + "PublicDescription": "Number of Sbo 1 credits acquired in a given = cycle, per ring.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "SBo1 Credits Acquired; For BL Ring", + "Counter": "0,1,2,3", + "EventCode": "0x69", + "EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.BL", + "PerPkg": "1", + "PublicDescription": "Number of Sbo 1 credits acquired in a given = cycle, per ring.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "SBo1 Credits Occupancy; For AD Ring", + "Counter": "0,1,2,3", + "EventCode": "0x6B", + "EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.AD", + "PerPkg": "1", + "PublicDescription": "Number of Sbo 1 credits in use in a given cy= cle, per ring.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "SBo1 Credits Occupancy; For BL Ring", + "Counter": "0,1,2,3", + "EventCode": "0x6B", + "EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.BL", + "PerPkg": "1", + "PublicDescription": "Number of Sbo 1 credits in use in a given cy= cle, per ring.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Data beat the Snoop Responses; Local Requests= ", + "Counter": "0,1,2,3", + "EventCode": "0xA", + "EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts the number of reads when the snoop wa= s on the critical path to the data return.; This filter includes only reque= sts coming from the local socket.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Data beat the Snoop Responses; Remote Request= s", + "Counter": "0,1,2,3", + "EventCode": "0xA", + "EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the number of reads when the snoop wa= s on the critical path to the data return.; This filter includes only reque= sts coming from remote sockets.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Cycles with Snoops Outstanding; All Requests", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_H_SNOOP_CYCLES_NE.ALL", + "PerPkg": "1", + "PublicDescription": "Counts cycles when one or more snoops are ou= tstanding.; Tracked for snoops from both local and remote sockets.", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "Cycles with Snoops Outstanding; Local Request= s", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_H_SNOOP_CYCLES_NE.LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts cycles when one or more snoops are ou= tstanding.; This filter includes only requests coming from the local socket= .", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Cycles with Snoops Outstanding; Remote Reques= ts", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_H_SNOOP_CYCLES_NE.REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts cycles when one or more snoops are ou= tstanding.; This filter includes only requests coming from remote sockets.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Tracker Snoops Outstanding Accumulator; Local= Requests", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_H_SNOOP_OCCUPANCY.LOCAL", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of either the loca= l HA tracker pool that have snoops pending in every cycle. This can be u= sed in conjection with the not empty stat to calculate average queue occupa= ncy or the allocations stat in order to calculate average queue latency. H= A trackers are allocated as soon as a request enters the HA if an HT (HomeT= racker) entry is available and this occupancy is decremented when all the s= noop responses have returned.; This filter includes only requests coming fr= om the local socket.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Tracker Snoops Outstanding Accumulator; Remot= e Requests", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_H_SNOOP_OCCUPANCY.REMOTE", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of either the loca= l HA tracker pool that have snoops pending in every cycle. This can be u= sed in conjection with the not empty stat to calculate average queue occupa= ncy or the allocations stat in order to calculate average queue latency. H= A trackers are allocated as soon as a request enters the HA if an HT (HomeT= racker) entry is available and this occupancy is decremented when all the s= noop responses have returned.; This filter includes only requests coming fr= om remote sockets.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received; RSPCNFLCT*", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT", + "PerPkg": "1", + "PublicDescription": "Counts the total number of RspI snoop respon= ses received. Whenever a snoops are issued, one or more snoop responses wi= ll be returned depending on the topology of the system. In systems larger= than 2s, when multiple snoops are returned this will count all the snoops = that are received. For example, if 3 snoops were issued and returned RspI,= RspS, and RspSFwd; then each of these sub-events would increment by 1.; Fi= lters for snoops responses of RspConflict. This is returned when a snoop f= inds an existing outstanding transaction in a remote caching agent when it = CAMs that caching agent. This triggers conflict resolution hardware. This= covers both RspCnflct and RspCnflctWbI.", + "UMask": "0x40", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received; RspI", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_H_SNOOP_RESP.RSPI", + "PerPkg": "1", + "PublicDescription": "Counts the total number of RspI snoop respon= ses received. Whenever a snoops are issued, one or more snoop responses wi= ll be returned depending on the topology of the system. In systems larger= than 2s, when multiple snoops are returned this will count all the snoops = that are received. For example, if 3 snoops were issued and returned RspI,= RspS, and RspSFwd; then each of these sub-events would increment by 1.; Fi= lters for snoops responses of RspI. RspI is returned when the remote cache= does not have the data, or when the remote cache silently evicts data (suc= h as when an RFO hits non-modified data).", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received; RspIFwd", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_H_SNOOP_RESP.RSPIFWD", + "PerPkg": "1", + "PublicDescription": "Counts the total number of RspI snoop respon= ses received. Whenever a snoops are issued, one or more snoop responses wi= ll be returned depending on the topology of the system. In systems larger= than 2s, when multiple snoops are returned this will count all the snoops = that are received. For example, if 3 snoops were issued and returned RspI,= RspS, and RspSFwd; then each of these sub-events would increment by 1.; Fi= lters for snoop responses of RspIFwd. This is returned when a remote cachi= ng agent forwards data and the requesting agent is able to acquire the data= in E or M states. This is commonly returned with RFO transactions. It ca= n be either a HitM or a HitFE.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received; RspS", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_H_SNOOP_RESP.RSPS", + "PerPkg": "1", + "PublicDescription": "Counts the total number of RspI snoop respon= ses received. Whenever a snoops are issued, one or more snoop responses wi= ll be returned depending on the topology of the system. In systems larger= than 2s, when multiple snoops are returned this will count all the snoops = that are received. For example, if 3 snoops were issued and returned RspI,= RspS, and RspSFwd; then each of these sub-events would increment by 1.; Fi= lters for snoop responses of RspS. RspS is returned when a remote cache ha= s data but is not forwarding it. It is a way to let the requesting socket = know that it cannot allocate the data in E state. No data is sent with S R= spS.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received; RspSFwd", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_H_SNOOP_RESP.RSPSFWD", + "PerPkg": "1", + "PublicDescription": "Counts the total number of RspI snoop respon= ses received. Whenever a snoops are issued, one or more snoop responses wi= ll be returned depending on the topology of the system. In systems larger= than 2s, when multiple snoops are returned this will count all the snoops = that are received. For example, if 3 snoops were issued and returned RspI,= RspS, and RspSFwd; then each of these sub-events would increment by 1.; Fi= lters for a snoop response of RspSFwd. This is returned when a remote cach= ing agent forwards data but holds on to its currentl copy. This is common = for data and code reads that hit in a remote socket in E or F state.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received; Rsp*Fwd*WB", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB", + "PerPkg": "1", + "PublicDescription": "Counts the total number of RspI snoop respon= ses received. Whenever a snoops are issued, one or more snoop responses wi= ll be returned depending on the topology of the system. In systems larger= than 2s, when multiple snoops are returned this will count all the snoops = that are received. For example, if 3 snoops were issued and returned RspI,= RspS, and RspSFwd; then each of these sub-events would increment by 1.; Fi= lters for a snoop response of Rsp*Fwd*WB. This snoop response is only used= in 4s systems. It is used when a snoop HITM's in a remote caching agent a= nd it directly forwards data to a requestor, and simultaneously returns dat= a to the home to be written back to memory.", + "UMask": "0x20", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received; Rsp*WB", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_H_SNOOP_RESP.RSP_WB", + "PerPkg": "1", + "PublicDescription": "Counts the total number of RspI snoop respon= ses received. Whenever a snoops are issued, one or more snoop responses wi= ll be returned depending on the topology of the system. In systems larger= than 2s, when multiple snoops are returned this will count all the snoops = that are received. For example, if 3 snoops were issued and returned RspI,= RspS, and RspSFwd; then each of these sub-events would increment by 1.; Fi= lters for a snoop response of RspIWB or RspSWB. This is returned when a no= n-RFO request hits in M state. Data and Code Reads can return either RspIW= B or RspSWB depending on how the system has been configured. InvItoE trans= actions will also return RspIWB because they must acquire ownership.", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received Local; Other", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.OTHER", + "PerPkg": "1", + "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for all other snoop responses.", + "UMask": "0x80", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspCnflct", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT", + "PerPkg": "1", + "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for snoops responses of RspConflict. This is returned= when a snoop finds an existing outstanding transaction in a remote caching= agent when it CAMs that caching agent. This triggers conflict resolution = hardware. This covers both RspCnflct and RspCnflctWbI.", + "UMask": "0x40", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspI", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPI", + "PerPkg": "1", + "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for snoops responses of RspI. RspI is returned when t= he remote cache does not have the data, or when the remote cache silently e= victs data (such as when an RFO hits non-modified data).", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspIFwd", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPIFWD", + "PerPkg": "1", + "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for snoop responses of RspIFwd. This is returned when= a remote caching agent forwards data and the requesting agent is able to a= cquire the data in E or M states. This is commonly returned with RFO trans= actions. It can be either a HitM or a HitFE.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspS", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPS", + "PerPkg": "1", + "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for snoop responses of RspS. RspS is returned when a = remote cache has data but is not forwarding it. It is a way to let the req= uesting socket know that it cannot allocate the data in E state. No data i= s sent with S RspS.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspSFwd", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD", + "PerPkg": "1", + "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for a snoop response of RspSFwd. This is returned whe= n a remote caching agent forwards data but holds on to its currentl copy. = This is common for data and code reads that hit in a remote socket in E or = F state.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxFWDxWB", + "PerPkg": "1", + "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for a snoop response of Rsp*Fwd*WB. This snoop respon= se is only used in 4s systems. It is used when a snoop HITM's in a remote = caching agent and it directly forwards data to a requestor, and simultaneou= sly returns data to the home to be written back to memory.", + "UMask": "0x20", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received Local; Rsp*WB", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB", + "PerPkg": "1", + "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for a snoop response of RspIWB or RspSWB. This is ret= urned when a non-RFO request hits in M state. Data and Code Reads can retu= rn either RspIWB or RspSWB depending on how the system has been configured.= InvItoE transactions will also return RspIWB because they must acquire ow= nership.", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring", + "Counter": "0,1,2,3", + "EventCode": "0x6C", + "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_AD", + "PerPkg": "1", + "PublicDescription": "Number of cycles Egress is stalled waiting f= or an Sbo credit to become available. Per Sbo, per Ring.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring", + "Counter": "0,1,2,3", + "EventCode": "0x6C", + "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_BL", + "PerPkg": "1", + "PublicDescription": "Number of cycles Egress is stalled waiting f= or an Sbo credit to become available. Per Sbo, per Ring.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring", + "Counter": "0,1,2,3", + "EventCode": "0x6C", + "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_AD", + "PerPkg": "1", + "PublicDescription": "Number of cycles Egress is stalled waiting f= or an Sbo credit to become available. Per Sbo, per Ring.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring", + "Counter": "0,1,2,3", + "EventCode": "0x6C", + "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_BL", + "PerPkg": "1", + "PublicDescription": "Number of cycles Egress is stalled waiting f= or an Sbo credit to become available. Per Sbo, per Ring.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 0", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_H_TAD_REQUESTS_G0.REGION0", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 0 to 7. This event is usef= ul for understanding how applications are using the memory that is spread a= cross the different memory regions. It is particularly useful for Monroe s= ystems that use the TAD to enable individual channels to enter self-refresh= to save power.; Filters request made to TAD Region 0", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 1", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_H_TAD_REQUESTS_G0.REGION1", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 0 to 7. This event is usef= ul for understanding how applications are using the memory that is spread a= cross the different memory regions. It is particularly useful for Monroe s= ystems that use the TAD to enable individual channels to enter self-refresh= to save power.; Filters request made to TAD Region 1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 2", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_H_TAD_REQUESTS_G0.REGION2", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 0 to 7. This event is usef= ul for understanding how applications are using the memory that is spread a= cross the different memory regions. It is particularly useful for Monroe s= ystems that use the TAD to enable individual channels to enter self-refresh= to save power.; Filters request made to TAD Region 2", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 3", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_H_TAD_REQUESTS_G0.REGION3", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 0 to 7. This event is usef= ul for understanding how applications are using the memory that is spread a= cross the different memory regions. It is particularly useful for Monroe s= ystems that use the TAD to enable individual channels to enter self-refresh= to save power.; Filters request made to TAD Region 3", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 4", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_H_TAD_REQUESTS_G0.REGION4", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 0 to 7. This event is usef= ul for understanding how applications are using the memory that is spread a= cross the different memory regions. It is particularly useful for Monroe s= ystems that use the TAD to enable individual channels to enter self-refresh= to save power.; Filters request made to TAD Region 4", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 5", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_H_TAD_REQUESTS_G0.REGION5", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 0 to 7. This event is usef= ul for understanding how applications are using the memory that is spread a= cross the different memory regions. It is particularly useful for Monroe s= ystems that use the TAD to enable individual channels to enter self-refresh= to save power.; Filters request made to TAD Region 5", + "UMask": "0x20", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 6", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_H_TAD_REQUESTS_G0.REGION6", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 0 to 7. This event is usef= ul for understanding how applications are using the memory that is spread a= cross the different memory regions. It is particularly useful for Monroe s= ystems that use the TAD to enable individual channels to enter self-refresh= to save power.; Filters request made to TAD Region 6", + "UMask": "0x40", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 7", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_H_TAD_REQUESTS_G0.REGION7", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 0 to 7. This event is usef= ul for understanding how applications are using the memory that is spread a= cross the different memory regions. It is particularly useful for Monroe s= ystems that use the TAD to enable individual channels to enter self-refresh= to save power.; Filters request made to TAD Region 7", + "UMask": "0x80", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Re= gion 10", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_H_TAD_REQUESTS_G1.REGION10", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 8 to 10. This event is use= ful for understanding how applications are using the memory that is spread = across the different memory regions. It is particularly useful for Monroe = systems that use the TAD to enable individual channels to enter self-refres= h to save power.; Filters request made to TAD Region 10", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Re= gion 11", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_H_TAD_REQUESTS_G1.REGION11", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 8 to 10. This event is use= ful for understanding how applications are using the memory that is spread = across the different memory regions. It is particularly useful for Monroe = systems that use the TAD to enable individual channels to enter self-refres= h to save power.; Filters request made to TAD Region 11", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Re= gion 8", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_H_TAD_REQUESTS_G1.REGION8", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 8 to 10. This event is use= ful for understanding how applications are using the memory that is spread = across the different memory regions. It is particularly useful for Monroe = systems that use the TAD to enable individual channels to enter self-refres= h to save power.; Filters request made to TAD Region 8", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Re= gion 9", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_H_TAD_REQUESTS_G1.REGION9", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 8 to 10. This event is use= ful for understanding how applications are using the memory that is spread = across the different memory regions. It is particularly useful for Monroe = systems that use the TAD to enable individual channels to enter self-refres= h to save power.; Filters request made to TAD Region 9", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Tracker Cycles Full; Cycles Completely Used", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_H_TRACKER_CYCLES_FULL.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the local H= A tracker pool is completely used. This can be used with edge detect to id= entify the number of situations when the pool became fully utilized. This = should not be confused with RTID credit usage -- which must be tracked insi= de each cbo individually -- but represents the actual tracker buffer struct= ure. In other words, the system could be starved for RTIDs but not fill up= the HA trackers. HA trackers are allocated as soon as a request enters th= e HA and is released after the snoop response and data return (or post in t= he case of a write) and the response is returned on the ring.; Counts the n= umber of cycles when the HA tracker pool (HT) is completely used including = reserved HT entries. It will not return valid count when BT is disabled.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Tracker Cycles Full; Cycles GP Completely Use= d", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_H_TRACKER_CYCLES_FULL.GP", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the local H= A tracker pool is completely used. This can be used with edge detect to id= entify the number of situations when the pool became fully utilized. This = should not be confused with RTID credit usage -- which must be tracked insi= de each cbo individually -- but represents the actual tracker buffer struct= ure. In other words, the system could be starved for RTIDs but not fill up= the HA trackers. HA trackers are allocated as soon as a request enters th= e HA and is released after the snoop response and data return (or post in t= he case of a write) and the response is returned on the ring.; Counts the n= umber of cycles when the general purpose (GP) HA tracker pool (HT) is compl= etely used. It will not return valid count when BT is disabled.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Tracker Cycles Not Empty; All Requests", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_H_TRACKER_CYCLES_NE.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the local H= A tracker pool is not empty. This can be used with edge detect to identify= the number of situations when the pool became empty. This should not be c= onfused with RTID credit usage -- which must be tracked inside each cbo ind= ividually -- but represents the actual tracker buffer structure. In other = words, this buffer could be completely empty, but there may still be credit= s in use by the CBos. This stat can be used in conjunction with the occupa= ncy accumulation stat in order to calculate average queue occpancy. HA tra= ckers are allocated as soon as a request enters the HA if an HT (Home Track= er) entry is available and is released after the snoop response and data re= turn (or post in the case of a write) and the response is returned on the r= ing.; Requests coming from both local and remote sockets.", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "Tracker Cycles Not Empty; Local Requests", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_H_TRACKER_CYCLES_NE.LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the local H= A tracker pool is not empty. This can be used with edge detect to identify= the number of situations when the pool became empty. This should not be c= onfused with RTID credit usage -- which must be tracked inside each cbo ind= ividually -- but represents the actual tracker buffer structure. In other = words, this buffer could be completely empty, but there may still be credit= s in use by the CBos. This stat can be used in conjunction with the occupa= ncy accumulation stat in order to calculate average queue occpancy. HA tra= ckers are allocated as soon as a request enters the HA if an HT (Home Track= er) entry is available and is released after the snoop response and data re= turn (or post in the case of a write) and the response is returned on the r= ing.; This filter includes only requests coming from the local socket.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Tracker Cycles Not Empty; Remote Requests", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_H_TRACKER_CYCLES_NE.REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the local H= A tracker pool is not empty. This can be used with edge detect to identify= the number of situations when the pool became empty. This should not be c= onfused with RTID credit usage -- which must be tracked inside each cbo ind= ividually -- but represents the actual tracker buffer structure. In other = words, this buffer could be completely empty, but there may still be credit= s in use by the CBos. This stat can be used in conjunction with the occupa= ncy accumulation stat in order to calculate average queue occpancy. HA tra= ckers are allocated as soon as a request enters the HA if an HT (Home Track= er) entry is available and is released after the snoop response and data re= turn (or post in the case of a write) and the response is returned on the r= ing.; This filter includes only requests coming from remote sockets.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Tracker Occupancy Accumultor; Local InvItoE R= equests", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_LOCAL", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the local HA tr= acker pool in every cycle. This can be used in conjection with the not emp= ty stat to calculate average queue occupancy or the allocations stat in ord= er to calculate average queue latency. HA trackers are allocated as soon a= s a request enters the HA if a HT (Home Tracker) entry is available and is = released after the snoop response and data return (or post in the case of a= write) and the response is returned on the ring.", + "UMask": "0x40", + "Unit": "HA" + }, + { + "BriefDescription": "Tracker Occupancy Accumultor; Remote InvItoE = Requests", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_REMOTE", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the local HA tr= acker pool in every cycle. This can be used in conjection with the not emp= ty stat to calculate average queue occupancy or the allocations stat in ord= er to calculate average queue latency. HA trackers are allocated as soon a= s a request enters the HA if a HT (Home Tracker) entry is available and is = released after the snoop response and data return (or post in the case of a= write) and the response is returned on the ring.", + "UMask": "0x80", + "Unit": "HA" + }, + { + "BriefDescription": "Tracker Occupancy Accumultor; Local Read Requ= ests", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_LOCAL", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the local HA tr= acker pool in every cycle. This can be used in conjection with the not emp= ty stat to calculate average queue occupancy or the allocations stat in ord= er to calculate average queue latency. HA trackers are allocated as soon a= s a request enters the HA if a HT (Home Tracker) entry is available and is = released after the snoop response and data return (or post in the case of a= write) and the response is returned on the ring.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "Tracker Occupancy Accumultor; Remote Read Req= uests", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_REMOTE", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the local HA tr= acker pool in every cycle. This can be used in conjection with the not emp= ty stat to calculate average queue occupancy or the allocations stat in ord= er to calculate average queue latency. HA trackers are allocated as soon a= s a request enters the HA if a HT (Home Tracker) entry is available and is = released after the snoop response and data return (or post in the case of a= write) and the response is returned on the ring.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "Tracker Occupancy Accumultor; Local Write Req= uests", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_LOCAL", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the local HA tr= acker pool in every cycle. This can be used in conjection with the not emp= ty stat to calculate average queue occupancy or the allocations stat in ord= er to calculate average queue latency. HA trackers are allocated as soon a= s a request enters the HA if a HT (Home Tracker) entry is available and is = released after the snoop response and data return (or post in the case of a= write) and the response is returned on the ring.", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "Tracker Occupancy Accumultor; Remote Write Re= quests", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_REMOTE", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the local HA tr= acker pool in every cycle. This can be used in conjection with the not emp= ty stat to calculate average queue occupancy or the allocations stat in ord= er to calculate average queue latency. HA trackers are allocated as soon a= s a request enters the HA if a HT (Home Tracker) entry is available and is = released after the snoop response and data return (or post in the case of a= write) and the response is returned on the ring.", + "UMask": "0x20", + "Unit": "HA" + }, + { + "BriefDescription": "Data Pending Occupancy Accumultor; Local Requ= ests", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.LOCAL", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of transactions that = have data from the memory controller until they get scheduled to the Egress= . This can be used to calculate the queuing latency for two things. (1) I= f the system is waiting for snoops, this will increase. (2) If the system = can't schedule to the Egress because of either (a) Egress Credits or (b) QP= I BL IGR credits for remote requests.; This filter includes only requests c= oming from the local socket.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Data Pending Occupancy Accumultor; Remote Req= uests", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.REMOTE", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of transactions that = have data from the memory controller until they get scheduled to the Egress= . This can be used to calculate the queuing latency for two things. (1) I= f the system is waiting for snoops, this will increase. (2) If the system = can't schedule to the Egress because of either (a) Egress Credits or (b) QP= I BL IGR credits for remote requests.; This filter includes only requests c= oming from remote sockets.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Outbound NDR Ring Transactions; Non-data Resp= onses", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "UNC_H_TxR_AD.HOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of outbound transactions o= n the AD ring. This can be filtered by the NDR and SNP message classes. S= ee the filter descriptions for more details.; Filter for outbound NDR trans= actions sent on the AD ring. NDR stands for non-data response and is gener= ally used for completions that do not include data. AD NDR is used for tra= nsactions to remote sockets.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Full; All", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_H_TxR_AD_CYCLES_FULL.ALL", + "PerPkg": "1", + "PublicDescription": "AD Egress Full; Cycles full from both schedu= lers", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Full; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED0", + "PerPkg": "1", + "PublicDescription": "AD Egress Full; Filter for cycles full from= scheduler bank 0", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Full; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED1", + "PerPkg": "1", + "PublicDescription": "AD Egress Full; Filter for cycles full from= scheduler bank 1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Not Empty; All", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_H_TxR_AD_CYCLES_NE.ALL", + "PerPkg": "1", + "PublicDescription": "AD Egress Not Empty; Cycles full from both s= chedulers", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Not Empty; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED0", + "PerPkg": "1", + "PublicDescription": "AD Egress Not Empty; Filter for cycles not e= mpty from scheduler bank 0", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Not Empty; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED1", + "PerPkg": "1", + "PublicDescription": "AD Egress Not Empty; Filter for cycles not e= mpty from scheduler bank 1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Allocations; All", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_H_TxR_AD_INSERTS.ALL", + "PerPkg": "1", + "PublicDescription": "AD Egress Allocations; Allocations from both= schedulers", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Allocations; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_H_TxR_AD_INSERTS.SCHED0", + "PerPkg": "1", + "PublicDescription": "AD Egress Allocations; Filter for allocation= s from scheduler bank 0", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Allocations; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_H_TxR_AD_INSERTS.SCHED1", + "PerPkg": "1", + "PublicDescription": "AD Egress Allocations; Filter for allocation= s from scheduler bank 1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Full; All", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_H_TxR_AK_CYCLES_FULL.ALL", + "PerPkg": "1", + "PublicDescription": "AK Egress Full; Cycles full from both schedu= lers", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Full; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED0", + "PerPkg": "1", + "PublicDescription": "AK Egress Full; Filter for cycles full from= scheduler bank 0", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Full; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED1", + "PerPkg": "1", + "PublicDescription": "AK Egress Full; Filter for cycles full from= scheduler bank 1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Not Empty; All", + "Counter": "0,1,2,3", + "EventCode": "0x31", + "EventName": "UNC_H_TxR_AK_CYCLES_NE.ALL", + "PerPkg": "1", + "PublicDescription": "AK Egress Not Empty; Cycles full from both s= chedulers", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Not Empty; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x31", + "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED0", + "PerPkg": "1", + "PublicDescription": "AK Egress Not Empty; Filter for cycles not e= mpty from scheduler bank 0", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Not Empty; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x31", + "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED1", + "PerPkg": "1", + "PublicDescription": "AK Egress Not Empty; Filter for cycles not e= mpty from scheduler bank 1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Allocations; All", + "Counter": "0,1,2,3", + "EventCode": "0x2F", + "EventName": "UNC_H_TxR_AK_INSERTS.ALL", + "PerPkg": "1", + "PublicDescription": "AK Egress Allocations; Allocations from both= schedulers", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Allocations; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x2F", + "EventName": "UNC_H_TxR_AK_INSERTS.SCHED0", + "PerPkg": "1", + "PublicDescription": "AK Egress Allocations; Filter for allocation= s from scheduler bank 0", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Allocations; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x2F", + "EventName": "UNC_H_TxR_AK_INSERTS.SCHED1", + "PerPkg": "1", + "PublicDescription": "AK Egress Allocations; Filter for allocation= s from scheduler bank 1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to Cache", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "UNC_H_TxR_BL.DRS_CACHE", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS messages sent out o= n the BL ring. This can be filtered by the destination.; Filter for data = being sent to the cache.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to Core", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "UNC_H_TxR_BL.DRS_CORE", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS messages sent out o= n the BL ring. This can be filtered by the destination.; Filter for data = being sent directly to the requesting core.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to QPI", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "UNC_H_TxR_BL.DRS_QPI", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS messages sent out o= n the BL ring. This can be filtered by the destination.; Filter for data = being sent to a remote socket over QPI.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Full; All", + "Counter": "0,1,2,3", + "EventCode": "0x36", + "EventName": "UNC_H_TxR_BL_CYCLES_FULL.ALL", + "PerPkg": "1", + "PublicDescription": "BL Egress Full; Cycles full from both schedu= lers", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Full; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x36", + "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED0", + "PerPkg": "1", + "PublicDescription": "BL Egress Full; Filter for cycles full from= scheduler bank 0", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Full; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x36", + "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED1", + "PerPkg": "1", + "PublicDescription": "BL Egress Full; Filter for cycles full from= scheduler bank 1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Not Empty; All", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_H_TxR_BL_CYCLES_NE.ALL", + "PerPkg": "1", + "PublicDescription": "BL Egress Not Empty; Cycles full from both s= chedulers", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Not Empty; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED0", + "PerPkg": "1", + "PublicDescription": "BL Egress Not Empty; Filter for cycles not e= mpty from scheduler bank 0", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Not Empty; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED1", + "PerPkg": "1", + "PublicDescription": "BL Egress Not Empty; Filter for cycles not e= mpty from scheduler bank 1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Allocations; All", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_H_TxR_BL_INSERTS.ALL", + "PerPkg": "1", + "PublicDescription": "BL Egress Allocations; Allocations from both= schedulers", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Allocations; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_H_TxR_BL_INSERTS.SCHED0", + "PerPkg": "1", + "PublicDescription": "BL Egress Allocations; Filter for allocation= s from scheduler bank 0", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Allocations; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_H_TxR_BL_INSERTS.SCHED1", + "PerPkg": "1", + "PublicDescription": "BL Egress Allocations; Filter for allocation= s from scheduler bank 1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Injection Starvation; For AK Ring", + "Counter": "0,1,2,3", + "EventCode": "0x6D", + "EventName": "UNC_H_TxR_STARVED.AK", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the Egress cannot send a transaction onto the ring for = a long period of time.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Injection Starvation; For BL Ring", + "Counter": "0,1,2,3", + "EventCode": "0x6D", + "EventName": "UNC_H_TxR_STARVED.BL", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the Egress cannot send a transaction onto the ring for = a long period of time.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Chan= nel 0", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o regular credits available for posting writes from the HA into the iMC. I= n order to send writes into the memory controller, the HA must first acquir= e a credit for the iMC's WPQ (write pending queue). This queue is broken i= nto regular credits/buffers that are used by general writes, and special re= quests such as ISOCH writes. This count only tracks the regular credits C= ommon high banwidth workloads should be able to make use of all of the regu= lar buffers, but it will be difficult (and uncommon) to make use of both th= e regular and special buffers at the same time. One can filter based on th= e memory controller channel. One or more channels can be tracked at a give= n time.; Filter for memory controller channel 0 only.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Chan= nel 1", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o regular credits available for posting writes from the HA into the iMC. I= n order to send writes into the memory controller, the HA must first acquir= e a credit for the iMC's WPQ (write pending queue). This queue is broken i= nto regular credits/buffers that are used by general writes, and special re= quests such as ISOCH writes. This count only tracks the regular credits C= ommon high banwidth workloads should be able to make use of all of the regu= lar buffers, but it will be difficult (and uncommon) to make use of both th= e regular and special buffers at the same time. One can filter based on th= e memory controller channel. One or more channels can be tracked at a give= n time.; Filter for memory controller channel 1 only.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Chan= nel 2", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o regular credits available for posting writes from the HA into the iMC. I= n order to send writes into the memory controller, the HA must first acquir= e a credit for the iMC's WPQ (write pending queue). This queue is broken i= nto regular credits/buffers that are used by general writes, and special re= quests such as ISOCH writes. This count only tracks the regular credits C= ommon high banwidth workloads should be able to make use of all of the regu= lar buffers, but it will be difficult (and uncommon) to make use of both th= e regular and special buffers at the same time. One can filter based on th= e memory controller channel. One or more channels can be tracked at a give= n time.; Filter for memory controller channel 2 only.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Chan= nel 3", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o regular credits available for posting writes from the HA into the iMC. I= n order to send writes into the memory controller, the HA must first acquir= e a credit for the iMC's WPQ (write pending queue). This queue is broken i= nto regular credits/buffers that are used by general writes, and special re= quests such as ISOCH writes. This count only tracks the regular credits C= ommon high banwidth workloads should be able to make use of all of the regu= lar buffers, but it will be difficult (and uncommon) to make use of both th= e regular and special buffers at the same time. One can filter based on th= e memory controller channel. One or more channels can be tracked at a give= n time.; Filter for memory controller channel 3 only.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Chan= nel 0", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o special credits available for posting writes from the HA into the iMC. I= n order to send writes into the memory controller, the HA must first acquir= e a credit for the iMC's WPQ (write pending queue). This queue is broken i= nto regular credits/buffers that are used by general writes, and special re= quests such as ISOCH writes. This count only tracks the special credits. = This statistic is generally not interesting for general IA workloads, but m= ay be of interest for understanding the characteristics of systems using IS= OCH. One can filter based on the memory controller channel. One or more c= hannels can be tracked at a given time.; Filter for memory controller chann= el 0 only.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Chan= nel 1", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o special credits available for posting writes from the HA into the iMC. I= n order to send writes into the memory controller, the HA must first acquir= e a credit for the iMC's WPQ (write pending queue). This queue is broken i= nto regular credits/buffers that are used by general writes, and special re= quests such as ISOCH writes. This count only tracks the special credits. = This statistic is generally not interesting for general IA workloads, but m= ay be of interest for understanding the characteristics of systems using IS= OCH. One can filter based on the memory controller channel. One or more c= hannels can be tracked at a given time.; Filter for memory controller chann= el 1 only.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Chan= nel 2", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o special credits available for posting writes from the HA into the iMC. I= n order to send writes into the memory controller, the HA must first acquir= e a credit for the iMC's WPQ (write pending queue). This queue is broken i= nto regular credits/buffers that are used by general writes, and special re= quests such as ISOCH writes. This count only tracks the special credits. = This statistic is generally not interesting for general IA workloads, but m= ay be of interest for understanding the characteristics of systems using IS= OCH. One can filter based on the memory controller channel. One or more c= hannels can be tracked at a given time.; Filter for memory controller chann= el 2 only.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Chan= nel 3", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3", "PerPkg": "1", - "ScaleUnit": "64Bytes", + "PublicDescription": "Counts the number of cycles when there are n= o special credits available for posting writes from the HA into the iMC. I= n order to send writes into the memory controller, the HA must first acquir= e a credit for the iMC's WPQ (write pending queue). This queue is broken i= nto regular credits/buffers that are used by general writes, and special re= quests such as ISOCH writes. This count only tracks the special credits. = This statistic is generally not interesting for general IA workloads, but m= ay be of interest for understanding the characteristics of systems using IS= OCH. One can filter based on the memory controller channel. One or more c= hannels can be tracked at a given time.; Filter for memory controller chann= el 3 only.", "UMask": "0x8", "Unit": "HA" } diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-memory.json = b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-memory.json index f4b0745cdbbf..83ff0542dbc0 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-memory.json @@ -1,86 +1,2915 @@ [ { - "BriefDescription": "read requests to memory controller. Derived f= rom unc_m_cas_count.rd", + "BriefDescription": "DRAM Activate Count; Activate due to Write", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_M_ACT_COUNT.BYP", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRAM Activate commands = sent on this channel. Activate commands are issued to open up a page on th= e DRAM devices so that it can be read or written to with a CAS. One can ca= lculate the number of Page Misses by subtracting the number of Page Miss pr= echarges from the number of Activates.", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Activate Count; Activate due to Read", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_M_ACT_COUNT.RD", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRAM Activate commands = sent on this channel. Activate commands are issued to open up a page on th= e DRAM devices so that it can be read or written to with a CAS. One can ca= lculate the number of Page Misses by subtracting the number of Page Miss pr= echarges from the number of Activates.", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Activate Count; Activate due to Write", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_M_ACT_COUNT.WR", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRAM Activate commands = sent on this channel. Activate commands are issued to open up a page on th= e DRAM devices so that it can be read or written to with a CAS. One can ca= lculate the number of Page Misses by subtracting the number of Page Miss pr= echarges from the number of Activates.", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "ACT command issued by 2 cycle bypass", + "Counter": "0,1,2,3", + "EventCode": "0xA1", + "EventName": "UNC_M_BYP_CMDS.ACT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "CAS command issued by 2 cycle bypass", + "Counter": "0,1,2,3", + "EventCode": "0xA1", + "EventName": "UNC_M_BYP_CMDS.CAS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "PRE command issued by 2 cycle bypass", + "Counter": "0,1,2,3", + "EventCode": "0xA1", + "EventName": "UNC_M_BYP_CMDS.PRE", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR= _CAS (w/ and w/out auto-pre)", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.ALL", + "PerPkg": "1", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the = total number of DRAM CAS commands issued on this channel.", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Re= ads (RD_CAS + Underfills)", "Counter": "0,1,2,3", "EventCode": "0x4", - "EventName": "LLC_MISSES.MEM_READ", + "EventName": "UNC_M_CAS_COUNT.RD", "PerPkg": "1", - "ScaleUnit": "64Bytes", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the = total number of DRAM Read CAS commands issued on this channel (including un= derfills).", "UMask": "0x3", "Unit": "iMC" }, { - "BriefDescription": "write requests to memory controller. Derived = from unc_m_cas_count.wr", + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD= _CAS (w/ and w/out auto-pre)", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.RD_REG", + "PerPkg": "1", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the = total number or DRAM Read CAS commands issued on this channel. This includ= es both regular RD CAS commands as well as those with implicit Precharge. = AutoPre is only used in systems that are using closed page policy. We do n= ot filter based on major mode, as RD_CAS is not issued during WMM (with the= exception of underfills).", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS is= sued in RMM", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.RD_RMM", + "PerPkg": "1", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill R= ead Issued", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", + "PerPkg": "1", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the = number of underfill reads that are issued by the memory controller. This w= ill generally be about the same as the number of partial writes, but may be= slightly less because of partials hitting in the WPQ. While it is possibl= e for underfills to be issed in both WMM and RMM, this event counts both.", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS is= sued in WMM", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.RD_WMM", + "PerPkg": "1", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR= _CAS (both Modes)", "Counter": "0,1,2,3", "EventCode": "0x4", - "EventName": "LLC_MISSES.MEM_WRITE", + "EventName": "UNC_M_CAS_COUNT.WR", "PerPkg": "1", - "ScaleUnit": "64Bytes", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the = total number of DRAM Write CAS commands issued on this channel.", "UMask": "0xC", "Unit": "iMC" }, { - "BriefDescription": "Memory controller clock ticks", + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS= (w/ and w/out auto-pre) in Read Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.WR_RMM", + "PerPkg": "1", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the = total number of Opportunistic DRAM Write CAS commands issued on this channe= l while in Read-Major-Mode.", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS= (w/ and w/out auto-pre) in Write Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.WR_WMM", + "PerPkg": "1", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the = total number or DRAM Write CAS commands issued on this channel while in Wri= te-Major-Mode.", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Clockticks", "Counter": "0,1,2,3", "EventName": "UNC_M_DCLOCKTICKS", "PerPkg": "1", "Unit": "iMC" }, { - "BriefDescription": "Cycles where DRAM ranks are in power down (CK= E) mode", + "BriefDescription": "DRAM Precharge All Commands", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "UNC_M_DRAM_PRE_ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that the precharg= e all command was sent.", + "Unit": "iMC" + }, + { + "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_M_DRAM_REFRESH.HIGH", + "PerPkg": "1", + "PublicDescription": "Counts the number of refreshes issued.", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_M_DRAM_REFRESH.PANIC", + "PerPkg": "1", + "PublicDescription": "Counts the number of refreshes issued.", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "ECC Correctable Errors", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS", + "PerPkg": "1", + "PublicDescription": "Counts the number of ECC errors detected and= corrected by the iMC on this channel. This counter is only useful with EC= C DRAM devices. This count will increment one time for each correction reg= ardless of the number of bits corrected. The iMC can correct up to 4 bit e= rrors in independent channel mode and 8 bit erros in lockstep mode.", + "Unit": "iMC" + }, + { + "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_M_MAJOR_MODES.ISOCH", + "PerPkg": "1", + "PublicDescription": "Counts the total number of cycles spent in a= major mode (selected by a filter) on the given channel. Major modea are = channel-wide, and not a per-rank (or dimm or bank) mode.; We group these tw= o modes together so that we can use four counters to track each of the majo= r modes at one time. These major modes are used whenever there is an ISOCH= txn in the memory controller. In these mode, only ISOCH transactions are = processed.", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "Cycles in a Major Mode; Partial Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_M_MAJOR_MODES.PARTIAL", + "PerPkg": "1", + "PublicDescription": "Counts the total number of cycles spent in a= major mode (selected by a filter) on the given channel. Major modea are = channel-wide, and not a per-rank (or dimm or bank) mode.; This major mode i= s used to drain starved underfill reads. Regular reads and writes are bloc= ked and only underfill reads will be processed.", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "Cycles in a Major Mode; Read Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_M_MAJOR_MODES.READ", + "PerPkg": "1", + "PublicDescription": "Counts the total number of cycles spent in a= major mode (selected by a filter) on the given channel. Major modea are = channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major Mode i= s the default mode for the iMC, as reads are generally more critical to for= ward progress than writes.", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Cycles in a Major Mode; Write Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_M_MAJOR_MODES.WRITE", + "PerPkg": "1", + "PublicDescription": "Counts the total number of cycles spent in a= major mode (selected by a filter) on the given channel. Major modea are = channel-wide, and not a per-rank (or dimm or bank) mode.; This mode is trig= gered when the WPQ hits high occupancy and causes writes to be higher prior= ity than reads. This can cause blips in the available read bandwidth in th= e system and temporarily increase read latencies in order to achieve better= bus utilizations and higher bandwidth.", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Channel DLLOFF Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_M_POWER_CHANNEL_DLLOFF", + "PerPkg": "1", + "PublicDescription": "Number of cycles when all the ranks in the c= hannel are in CKE Slow (DLLOFF) mode.", + "Unit": "iMC" + }, + { + "BriefDescription": "Channel PPD Cycles", "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M_POWER_CHANNEL_PPD", - "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_DCLOCKTICKS) * 100= .", - "MetricName": "power_channel_ppd %", "PerPkg": "1", + "PublicDescription": "Number of cycles when all the ranks in the c= hannel are in PPD mode. If IBT=3Doff is enabled, then this can be used to = count those cycles. If it is not enabled, then this can count the number o= f cycles when that could have been taken advantage of.", "Unit": "iMC" }, { - "BriefDescription": "Cycles all ranks are in critical thermal thro= ttle", + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK0", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK1", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK2", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK3", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK4", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK5", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK6", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK7", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "Critical Throttle Cycles", "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES", - "MetricExpr": "(UNC_M_POWER_CRITICAL_THROTTLE_CYCLES / UNC_M_DCLOC= KTICKS) * 100.", - "MetricName": "power_critical_throttle_cycles %", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the iMC is = in critical thermal throttling. When this happens, all traffic is blocked.= This should be rare unless something bad is going on in the platform. Th= ere is no filtering by rank for this event.", "Unit": "iMC" }, { - "BriefDescription": "Cycles Memory is in self refresh power mode", + "BriefDescription": "Clock-Enabled Self-Refresh", "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M_POWER_SELF_REFRESH", - "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_DCLOCKTICKS) * 10= 0.", - "MetricName": "power_self_refresh %", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the iMC is = in self-refresh and the iMC still has a clock. This happens in some packag= e C-states. For example, the PCU may ask the iMC to enter self-refresh eve= n though some of the cores are still processing. One use of this is for Mo= nroe technology. Self-refresh is required during package C3 and C6, but th= ere is no clock in the iMC at this time, so it is not possible to count the= se cases.", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.; Thermal throttling is performed= per DIMM. We support 3 DIMMs per channel. This ID allows us to filter by= ID.", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Preemption Count; Read over Read Preempt= ion", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD", + "PerPkg": "1", + "PublicDescription": "Counts the number of times a read in the iMC= preempts another read or write. Generally reads to an open page are issue= d ahead of requests to closed pages. This improves the page hit rate of th= e system. However, high priority requests can cause pages of active reques= ts to be closed in order to get them out. This will reduce the latency of = the high-priority request at the expense of lower bandwidth and increased o= verall average latency.; Filter for when a read preempts another read.", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Preemption Count; Read over Write Preemp= tion", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR", + "PerPkg": "1", + "PublicDescription": "Counts the number of times a read in the iMC= preempts another read or write. Generally reads to an open page are issue= d ahead of requests to closed pages. This improves the page hit rate of th= e system. However, high priority requests can cause pages of active reques= ts to be closed in order to get them out. This will reduce the latency of = the high-priority request at the expense of lower bandwidth and increased o= verall average latency.; Filter for when a read preempts a write.", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Precharge commands.; Precharge due to by= pass", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_M_PRE_COUNT.BYP", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRAM Precharge commands= sent on this channel.", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Precharge commands.; Precharge due to ti= mer expiration", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRAM Precharge commands= sent on this channel.; Counts the number of DRAM Precharge commands sent o= n this channel as a result of the page close counter expiring. This does n= ot include implicit precharge commands sent in auto-precharge mode.", + "UMask": "0x2", "Unit": "iMC" }, { - "BriefDescription": "Pre-charges due to page misses", + "BriefDescription": "DRAM Precharge commands.; Precharges due to p= age miss", "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.PAGE_MISS", "PerPkg": "1", + "PublicDescription": "Counts the number of DRAM Precharge commands= sent on this channel.; Counts the number of DRAM Precharge commands sent o= n this channel as a result of page misses. This does not include explicit = precharge commands sent with CAS commands in Auto-Precharge mode. This doe= s not include PRE commands sent as a result of the page close counter expir= ation.", "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "Pre-charge for reads", + "BriefDescription": "DRAM Precharge commands.; Precharge due to re= ad", "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.RD", "PerPkg": "1", + "PublicDescription": "Counts the number of DRAM Precharge commands= sent on this channel.", "UMask": "0x4", "Unit": "iMC" }, { - "BriefDescription": "Pre-charge for writes", + "BriefDescription": "DRAM Precharge commands.; Precharge due to wr= ite", "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.WR", "PerPkg": "1", + "PublicDescription": "Counts the number of DRAM Precharge commands= sent on this channel.", "UMask": "0x8", "Unit": "iMC" + }, + { + "BriefDescription": "Read CAS issued with HIGH priority", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_M_RD_CAS_PRIO.HIGH", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "Read CAS issued with LOW priority", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_M_RD_CAS_PRIO.LOW", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Read CAS issued with MEDIUM priority", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_M_RD_CAS_PRIO.MED", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority= (starved)", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_M_RD_CAS_PRIO.PANIC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Pending Queue Not Empty", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_M_RPQ_CYCLES_NE", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Read Pe= nding Queue is not empty. This can then be used to calculate the average o= ccupancy (in conjunction with the Read Pending Queue Occupancy count). The= RPQ is used to schedule reads out to the memory controller and to track th= e requests. Requests allocate into the RPQ soon after they enter the memor= y controller, and need credits for an entry in this buffer before being sen= t from the HA to the iMC. They deallocate after the CAS command has been i= ssued to memory. This filter is to be used in conjunction with the occupan= cy filter so that one can correctly track the average occupancies for sched= ulable entries and scheduled requests.", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Pending Queue Allocations", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "UNC_M_RPQ_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the Re= ad Pending Queue. This queue is used to schedule reads out to the memory c= ontroller and to track the requests. Requests allocate into the RPQ soon a= fter they enter the memory controller, and need credits for an entry in thi= s buffer before being sent from the HA to the iMC. They deallocate after t= he CAS command has been issued to memory. This includes both ISOCH and non= -ISOCH requests.", + "Unit": "iMC" + }, + { + "BriefDescription": "VMSE MXB write buffer occupancy", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_M_VMSE_MXB_WR_OCCUPANCY", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued i= n RMM", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_M_VMSE_WR_PUSH.RMM", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued i= n WMM", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_M_VMSE_WR_PUSH.WMM", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Transition from WMM to RMM because of low thr= eshold; Transition from WMM to RMM because of starve counter", + "Counter": "0,1,2,3", + "EventCode": "0xC0", + "EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Transition from WMM to RMM because of low thr= eshold", + "Counter": "0,1,2,3", + "EventCode": "0xC0", + "EventName": "UNC_M_WMM_TO_RMM.STARVE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Transition from WMM to RMM because of low thr= eshold", + "Counter": "0,1,2,3", + "EventCode": "0xC0", + "EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue Full Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_M_WPQ_CYCLES_FULL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the Write P= ending Queue is full. When the WPQ is full, the HA will not be able to iss= ue any additional read requests into the iMC. This count should be similar= count in the HA which tracks the number of cycles that the HA has no WPQ c= redits, just somewhat smaller to account for the credit return overhead.", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue Not Empty", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_M_WPQ_CYCLES_NE", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Write P= ending Queue is not empty. This can then be used to calculate the average = queue occupancy (in conjunction with the WPQ Occupancy Accumulation count).= The WPQ is used to schedule write out to the memory controller and to tra= ck the writes. Requests allocate into the WPQ soon after they enter the me= mory controller, and need credits for an entry in this buffer before being = sent from the HA to the iMC. They deallocate after being issued to DRAM. = Write requests themselves are able to complete (from the perspective of the= rest of the system) as soon they have posted to the iMC. This is not to b= e confused with actually performing the write to DRAM. Therefore, the aver= age latency for this queue is actually not useful for deconstruction interm= ediate write latencies.", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_M_WPQ_READ_HIT", + "PerPkg": "1", + "PublicDescription": "Counts the number of times a request hits in= the WPQ (write-pending queue). The iMC allows writes and reads to pass up= other writes to different addresses. Before a read or a write is issued, = it will first CAM the WPQ to see if there is a write pending to that addres= s. When reads hit, they are able to directly pull their data from the WPQ = instead of going to memory. Writes that hit will overwrite the existing da= ta. Partial writes that hit will not need to do underfill reads and will s= imply update their relevant sections.", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_M_WPQ_WRITE_HIT", + "PerPkg": "1", + "PublicDescription": "Counts the number of times a request hits in= the WPQ (write-pending queue). The iMC allows writes and reads to pass up= other writes to different addresses. Before a read or a write is issued, = it will first CAM the WPQ to see if there is a write pending to that addres= s. When reads hit, they are able to directly pull their data from the WPQ = instead of going to memory. Writes that hit will overwrite the existing da= ta. Partial writes that hit will not need to do underfill reads and will s= imply update their relevant sections.", + "Unit": "iMC" + }, + { + "BriefDescription": "Not getting the requested Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_M_WRONG_MM", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; 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Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" } ] diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-power.json b= /tools/perf/pmu-events/arch/x86/broadwellde/uncore-power.json index dd1b95655d1d..c3325dd61202 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-power.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-power.json @@ -1,91 +1,511 @@ [ { - "BriefDescription": "PCU clock ticks. Use to get percentages of PC= U cycles events", + "BriefDescription": "pclk Cycles", "Counter": "0,1,2,3", "EventName": "UNC_P_CLOCKTICKS", "PerPkg": "1", + "PublicDescription": "The PCU runs off a fixed 1 GHz clock. This = event counts the number of pclk cycles measured while the counter was enabl= ed. The pclk, like the Memory Controller's dclk, counts at a constant rate= making it a good measure of actual wall time.", "Unit": "PCU" }, { - "BriefDescription": "This is an occupancy event that tracks the nu= mber of cores that are in C0. It can be used by itself to get the average = number of cores in C0, with threshholding to generate histograms, or with o= ther PCU events and occupancy triggering to capture other details", + "BriefDescription": "Core C State Transition Cycles", "Counter": "0,1,2,3", - "EventCode": "0x80", - "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", - "Filter": "occ_sel=3D1", - "MetricExpr": "(UNC_P_POWER_STATE_OCCUPANCY.CORES_C0 / UNC_P_CLOCK= TICKS) * 100.", - "MetricName": "power_state_occupancy.cores_c0 %", + "EventCode": "0x60", + "EventName": "UNC_P_CORE0_TRANSITION_CYCLES", "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", "Unit": "PCU" }, { - "BriefDescription": "This is an occupancy event that tracks the nu= mber of cores that are in C3. It can be used by itself to get the average = number of cores in C0, with threshholding to generate histograms, or with o= ther PCU events and occupancy triggering to capture other details", + "BriefDescription": "Core C State Transition Cycles", "Counter": "0,1,2,3", - "EventCode": "0x80", - "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", - "Filter": "occ_sel=3D2", - "MetricExpr": "(UNC_P_POWER_STATE_OCCUPANCY.CORES_C3 / UNC_P_CLOCK= TICKS) * 100.", - "MetricName": "power_state_occupancy.cores_c3 %", + "EventCode": "0x6A", + "EventName": "UNC_P_CORE10_TRANSITION_CYCLES", "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", "Unit": "PCU" }, { - "BriefDescription": "This is an occupancy event that tracks the nu= mber of cores that are in C6. It can be used by itself to get the average = number of cores in C0, with threshholding to generate histograms, or with o= ther PCU events ", + "BriefDescription": "Core C State Transition Cycles", "Counter": "0,1,2,3", - "EventCode": "0x80", - "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", - "Filter": "occ_sel=3D3", - "MetricExpr": "(UNC_P_POWER_STATE_OCCUPANCY.CORES_C6 / UNC_P_CLOCK= TICKS) * 100.", - "MetricName": "power_state_occupancy.cores_c6 %", + "EventCode": "0x6B", + "EventName": "UNC_P_CORE11_TRANSITION_CYCLES", "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles that we are in ex= ternal PROCHOT mode. This mode is triggered when a sensor off the die dete= rmines that something off-die (like DRAM) is too hot and must throttle to a= void damaging the chip", + "BriefDescription": "Core C State Transition Cycles", "Counter": "0,1,2,3", - "EventCode": "0xA", - "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES", - "MetricExpr": "(UNC_P_PROCHOT_EXTERNAL_CYCLES / UNC_P_CLOCKTICKS) = * 100.", - "MetricName": "prochot_external_cycles %", + "EventCode": "0x6C", + "EventName": "UNC_P_CORE12_TRANSITION_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x6D", + "EventName": "UNC_P_CORE13_TRANSITION_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x6E", + "EventName": "UNC_P_CORE14_TRANSITION_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x6F", + "EventName": "UNC_P_CORE15_TRANSITION_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x70", + "EventName": "UNC_P_CORE16_TRANSITION_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "UNC_P_CORE17_TRANSITION_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x61", + "EventName": "UNC_P_CORE1_TRANSITION_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x62", + "EventName": "UNC_P_CORE2_TRANSITION_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x63", + "EventName": "UNC_P_CORE3_TRANSITION_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x64", + "EventName": "UNC_P_CORE4_TRANSITION_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x65", + "EventName": "UNC_P_CORE5_TRANSITION_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x66", + "EventName": "UNC_P_CORE6_TRANSITION_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x67", + "EventName": "UNC_P_CORE7_TRANSITION_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x68", + "EventName": "UNC_P_CORE8_TRANSITION_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x69", + "EventName": "UNC_P_CORE9_TRANSITION_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x30", + "EventName": "UNC_P_DEMOTIONS_CORE0", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x31", + "EventName": "UNC_P_DEMOTIONS_CORE1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x3A", + "EventName": "UNC_P_DEMOTIONS_CORE10", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x3B", + "EventName": "UNC_P_DEMOTIONS_CORE11", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x3C", + "EventName": "UNC_P_DEMOTIONS_CORE12", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x3D", + "EventName": "UNC_P_DEMOTIONS_CORE13", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x3E", + "EventName": "UNC_P_DEMOTIONS_CORE14", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x3F", + "EventName": "UNC_P_DEMOTIONS_CORE15", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_P_DEMOTIONS_CORE16", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_P_DEMOTIONS_CORE17", "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles when temperature = is the upper limit on frequency", + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_P_DEMOTIONS_CORE2", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_P_DEMOTIONS_CORE3", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_P_DEMOTIONS_CORE4", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_P_DEMOTIONS_CORE5", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x36", + "EventName": "UNC_P_DEMOTIONS_CORE6", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_P_DEMOTIONS_CORE7", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_P_DEMOTIONS_CORE8", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_P_DEMOTIONS_CORE9", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Thermal Strongest Upper Limit Cycles", "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES", - "MetricExpr": "(UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES / UNC_P_CLOCKT= ICKS) * 100.", - "MetricName": "freq_max_limit_thermal_cycles %", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when thermal con= ditions are the upper limit on frequency. This is related to the THERMAL_T= HROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are abo= ve the thermal temperature. This event (STRONGEST_UPPER_LIMIT) is sampled = at the output of the algorithm that determines the actual frequency, while = THERMAL_THROTTLE looks at the input.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles when the OS is th= e upper limit on frequency", + "BriefDescription": "OS Strongest Upper Limit Cycles", "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_P_FREQ_MAX_OS_CYCLES", - "MetricExpr": "(UNC_P_FREQ_MAX_OS_CYCLES / UNC_P_CLOCKTICKS) * 100= .", - "MetricName": "freq_max_os_cycles %", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the OS is t= he upper limit on frequency.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles when power is the= upper limit on frequency", + "BriefDescription": "Power Strongest Upper Limit Cycles", "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES", - "MetricExpr": "(UNC_P_FREQ_MAX_POWER_CYCLES / UNC_P_CLOCKTICKS) * = 100.", - "MetricName": "freq_max_power_cycles %", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when power is th= e upper limit on frequency.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles when current is t= he upper limit on frequency", + "BriefDescription": "IO P Limit Strongest Lower Limit Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x73", + "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when IO P Limit = is preventing us from dropping the frequency lower. This algorithm monitor= s the needs to the IO subsystem on both local and remote sockets and will m= aintain a frequency high enough to maintain good IO BW. This is necessary = for when all the IA cores on a socket are idle but a user still would like = to maintain high IO Bandwidth.", + "Unit": "PCU" + }, + { + "BriefDescription": "Cycles spent changing Frequency", "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "UNC_P_FREQ_TRANS_CYCLES", - "MetricExpr": "(UNC_P_FREQ_TRANS_CYCLES / UNC_P_CLOCKTICKS) * 100.= ", - "MetricName": "freq_trans_cycles %", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the system = is changing frequency. This can not be filtered by thread ID. One can als= o use it with the occupancy counter that monitors number of threads in C0 t= o estimate the performance impact that frequency transitions had on the sys= tem.", + "Unit": "PCU" + }, + { + "BriefDescription": "Memory Phase Shedding Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x2F", + "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the PCU has= triggered memory phase shedding. This is a mode that can be run in the iM= C physicals that saves power at the expense of additional latency.", + "Unit": "PCU" + }, + { + "BriefDescription": "Package C State Residency - C0", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the package= was in C0. This event can be used in conjunction with edge detect to coun= t C0 entrances (or exits using invert). Residency events do not include tr= ansition times.", + "Unit": "PCU" + }, + { + "BriefDescription": "Package C State Residency - C1E", + "Counter": "0,1,2,3", + "EventCode": "0x4E", + "EventName": "UNC_P_PKG_RESIDENCY_C1E_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the package= was in C1E. This event can be used in conjunction with edge detect to cou= nt C1E entrances (or exits using invert). Residency events do not include = transition times.", + "Unit": "PCU" + }, + { + "BriefDescription": "Package C State Residency - C2E", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the package= was in C2E. This event can be used in conjunction with edge detect to cou= nt C2E entrances (or exits using invert). Residency events do not include = transition times.", + "Unit": "PCU" + }, + { + "BriefDescription": "Package C State Residency - C3", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the package= was in C3. This event can be used in conjunction with edge detect to coun= t C3 entrances (or exits using invert). Residency events do not include tr= ansition times.", + "Unit": "PCU" + }, + { + "BriefDescription": "Package C State Residency - C6", + "Counter": "0,1,2,3", + "EventCode": "0x2D", + "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the package= was in C6. This event can be used in conjunction with edge detect to coun= t C6 entrances (or exits using invert). Residency events do not include tr= ansition times.", + "Unit": "PCU" + }, + { + "BriefDescription": "Package C7 State Residency", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_P_PKG_RESIDENCY_C7_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the package= was in C7. This event can be used in conjunction with edge detect to coun= t C7 entrances (or exits using invert). Residency events do not include tr= ansition times.", + "Unit": "PCU" + }, + { + "BriefDescription": "Number of cores in C-State; C0 and C1", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", + "PerPkg": "1", + "PublicDescription": "This is an occupancy event that tracks the n= umber of cores that are in the chosen C-State. It can be used by itself to= get the average number of cores in that C-state with threshholding to gene= rate histograms, or with other PCU events and occupancy triggering to captu= re other details.", + "Unit": "PCU" + }, + { + "BriefDescription": "Number of cores in C-State; C3", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", + "PerPkg": "1", + "PublicDescription": "This is an occupancy event that tracks the n= umber of cores that are in the chosen C-State. It can be used by itself to= get the average number of cores in that C-state with threshholding to gene= rate histograms, or with other PCU events and occupancy triggering to captu= re other details.", + "Unit": "PCU" + }, + { + "BriefDescription": "Number of cores in C-State; C6 and C7", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", + "PerPkg": "1", + "PublicDescription": "This is an occupancy event that tracks the n= umber of cores that are in the chosen C-State. It can be used by itself to= get the average number of cores in that C-state with threshholding to gene= rate histograms, or with other PCU events and occupancy triggering to captu= re other details.", + "Unit": "PCU" + }, + { + "BriefDescription": "External Prochot", + "Counter": "0,1,2,3", + "EventCode": "0xA", + "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that we are in e= xternal PROCHOT mode. This mode is triggered when a sensor off the die det= ermines that something off-die (like DRAM) is too hot and must throttle to = avoid damaging the chip.", + "Unit": "PCU" + }, + { + "BriefDescription": "Internal Prochot", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that we are in I= nteral PROCHOT mode. This mode is triggered when a sensor on the die deter= mines that we are too hot and must throttle to avoid damaging the chip.", + "Unit": "PCU" + }, + { + "BriefDescription": "Total Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x72", + "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions across all cores.", + "Unit": "PCU" + }, + { + "Counter": "0,1,2,3", + "EventCode": "0x79", + "EventName": "UNC_P_UFS_TRANSITIONS_RING_GV", + "PerPkg": "1", + "PublicDescription": "Ring GV with same final and initial frequenc= y", + "Unit": "PCU" + }, + { + "BriefDescription": "VR Hot", + "Counter": "0,1,2,3", + "EventCode": "0x42", + "EventName": "UNC_P_VR_HOT_CYCLES", "PerPkg": "1", "Unit": "PCU" } diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/virtual-memory.json= b/tools/perf/pmu-events/arch/x86/broadwellde/virtual-memory.json index 818a8b132c08..6a6de8790f25 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/virtual-memory.json @@ -385,4 +385,4 @@ "SampleAfterValue": "100007", "UMask": "0x20" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 94ef16f0207a..dd1d24d3cb65 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -1,6 +1,6 @@ Family-model,Version,Filename,EventType -GenuineIntel-6-56,v5,broadwellde,core GenuineIntel-6-(3D|47),v26,broadwell,core +GenuineIntel-6-56,v23,broadwellde,core GenuineIntel-6-4F,v19,broadwellx,core GenuineIntel-6-1C,v4,bonnell,core GenuineIntel-6-26,v4,bonnell,core --=20 2.37.1.359.gd136c6c3e2-goog From nobody Wed Apr 15 05:45:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC2BFC3F6B0 for ; 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Wed, 27 Jul 2022 15:08:54 -0700 (PDT) Date: Wed, 27 Jul 2022 15:08:06 -0700 In-Reply-To: <20220727220832.2865794-1-irogers@google.com> Message-Id: <20220727220832.2865794-5-irogers@google.com> Mime-Version: 1.0 References: <20220727220832.2865794-1-irogers@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH v3 04/30] perf vendor events: Update Intel alderlake From: Ian Rogers To: perry.taylor@intel.com, caleb.biggers@intel.com, kshipra.bopardikar@intel.com, Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Sedat Dilek Cc: Stephane Eranian , Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update to v1.13, the metrics are based on TMA 4.4 full. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/downloa= d_and_gen.py to download and generate the latest events and metrics. Manually copy the alderlake files into perf and update mapfile.csv. Tested on a non-alderlake with 'perf test': 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok Signed-off-by: Ian Rogers --- .../arch/x86/alderlake/adl-metrics.json | 4 +- .../pmu-events/arch/x86/alderlake/cache.json | 33 +- .../pmu-events/arch/x86/alderlake/other.json | 54 ++++ .../arch/x86/alderlake/pipeline.json | 285 +++++++++++++++++- .../arch/x86/alderlake/uncore-other.json | 2 +- .../arch/x86/alderlake/virtual-memory.json | 36 +++ tools/perf/pmu-events/arch/x86/mapfile.csv | 3 +- 7 files changed, 398 insertions(+), 19 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json b/to= ols/perf/pmu-events/arch/x86/alderlake/adl-metrics.json index f8bdf7812b51..095dd8c7f161 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json @@ -592,13 +592,13 @@ "Unit": "cpu_atom" }, { - "BriefDescription": "Instructions per Branch (lower number means h= igher occurrence rate)", + "BriefDescription": "Instructions per Branch (lower number means h= igher occurance rate)", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", "MetricName": "IpBranch", "Unit": "cpu_atom" }, { - "BriefDescription": "Instruction per (near) call (lower number mea= ns higher occurrence rate)", + "BriefDescription": "Instruction per (near) call (lower number mea= ns higher occurance rate)", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.CALL", "MetricName": "IpCall", "Unit": "cpu_atom" diff --git a/tools/perf/pmu-events/arch/x86/alderlake/cache.json b/tools/pe= rf/pmu-events/arch/x86/alderlake/cache.json index c6062c44ca75..887dce4dfeba 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/cache.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/cache.json @@ -505,6 +505,18 @@ "UMask": "0x1f", "Unit": "cpu_core" }, + { + "BriefDescription": "Cache lines that have been L2 hardware prefet= ched but not used by demand accesses", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x26", + "EventName": "L2_LINES_OUT.USELESS_HWPF", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x4", + "Unit": "cpu_core" + }, { "BriefDescription": "All accesses to L2 cache[This event is alias = to L2_RQSTS.REFERENCES]", "CollectPEBSRecord": "2", @@ -722,7 +734,7 @@ "Unit": "cpu_core" }, { - "BriefDescription": "LONGEST_LAT_CACHE.MISS", + "BriefDescription": "Core-originated cacheable requests that misse= d L3 (Except hardware prefetches to the L3)", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x2e", @@ -734,7 +746,19 @@ "Unit": "cpu_core" }, { - "BriefDescription": "All retired load instructions.", + "BriefDescription": "Core-originated cacheable requests that refer= to L3 (Except hardware prefetches to the L3)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x2e", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x4f", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired load instructions.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", @@ -747,7 +771,7 @@ "Unit": "cpu_core" }, { - "BriefDescription": "All retired store instructions.", + "BriefDescription": "Retired store instructions.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", @@ -1140,6 +1164,7 @@ "BriefDescription": "This event is deprecated. Refer to new event = OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", + "Errata": "ADL038", "EventCode": "0x20", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", "PEBScounters": "0,1,2,3", @@ -1153,6 +1178,7 @@ "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "CounterMask": "1", + "Errata": "ADL038", "EventCode": "0x20", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", "PEBScounters": "0,1,2,3", @@ -1178,6 +1204,7 @@ "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", + "Errata": "ADL038", "EventCode": "0x20", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", "PEBScounters": "0,1,2,3", diff --git a/tools/perf/pmu-events/arch/x86/alderlake/other.json b/tools/pe= rf/pmu-events/arch/x86/alderlake/other.json index b575275654a2..67a9c13cc71d 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/other.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/other.json @@ -125,6 +125,60 @@ "UMask": "0x1", "Unit": "cpu_core" }, + { + "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa5", + "EventName": "RS.EMPTY", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x7", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xa5", + "EventName": "RS.EMPTY_COUNT", + "Invert": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x7", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = RS.EMPTY_COUNT", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xa5", + "EventName": "RS_EMPTY.COUNT", + "Invert": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x7", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = RS.EMPTY", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa5", + "EventName": "RS_EMPTY.CYCLES", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x7", + "Unit": "cpu_core" + }, { "BriefDescription": "XQ.FULL_CYCLES", "CollectPEBSRecord": "2", diff --git a/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json b/tools= /perf/pmu-events/arch/x86/alderlake/pipeline.json index e0d1495202af..d02e078a90c9 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json @@ -22,6 +22,30 @@ "UMask": "0xf9", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of retired JCC (Jump on Con= ditional Code) branch instructions retired, includes both taken and not tak= en branches.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.COND", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0x7e", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of taken JCC (Jump on Condi= tional Code) branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.COND_TAKEN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xfe", + "Unit": "cpu_atom" + }, { "BriefDescription": "Counts the number of far branch instructions = retired, includes far jump, far call and return, and interrupt call and ret= urn.", "CollectPEBSRecord": "2", @@ -34,6 +58,54 @@ "UMask": "0xbf", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of near indirect JMP and ne= ar indirect CALL branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.INDIRECT", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xeb", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of near indirect CALL branc= h instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.INDIRECT_CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xfb", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = BR_INST_RETIRED.INDIRECT_CALL", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.IND_CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xfb", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = BR_INST_RETIRED.COND", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.JCC", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0x7e", + "Unit": "cpu_atom" + }, { "BriefDescription": "Counts the number of near CALL branch instruc= tions retired.", "CollectPEBSRecord": "2", @@ -46,6 +118,66 @@ "UMask": "0xf9", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of near RET branch instruct= ions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xf7", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = BR_INST_RETIRED.INDIRECT", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.NON_RETURN_IND", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xeb", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of near relative CALL branc= h instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.REL_CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xfd", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = BR_INST_RETIRED.NEAR_RETURN", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.RETURN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xf7", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = BR_INST_RETIRED.COND_TAKEN", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.TAKEN_JCC", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xfe", + "Unit": "cpu_atom" + }, { "BriefDescription": "Counts the total number of mispredicted branc= h instructions retired for all branch types.", "CollectPEBSRecord": "2", @@ -57,10 +189,118 @@ "SampleAfterValue": "200003", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of mispredicted JCC (Jump o= n Conditional Code) branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.COND", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0x7e", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of mispredicted taken JCC (= Jump on Conditional Code) branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.COND_TAKEN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xfe", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of mispredicted near indire= ct JMP and near indirect CALL branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.INDIRECT", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xeb", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of mispredicted near indire= ct CALL branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xfb", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = BR_MISP_RETIRED.INDIRECT_CALL", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.IND_CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xfb", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = BR_MISP_RETIRED.COND", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.JCC", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0x7e", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = BR_MISP_RETIRED.INDIRECT", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xeb", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of mispredicted near RET br= anch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.RETURN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xf7", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = BR_MISP_RETIRED.COND_TAKEN", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.TAKEN_JCC", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xfe", + "Unit": "cpu_atom" + }, { "BriefDescription": "Counts the number of unhalted core clock cycl= es. (Fixed event)", "CollectPEBSRecord": "2", - "Counter": "33", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.CORE", "PEBScounters": "33", "SampleAfterValue": "2000003", @@ -82,7 +322,7 @@ { "BriefDescription": "Counts the number of unhalted reference clock= cycles at TSC frequency. (Fixed event)", "CollectPEBSRecord": "2", - "Counter": "34", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PEBScounters": "34", "SampleAfterValue": "2000003", @@ -93,7 +333,7 @@ { "BriefDescription": "Counts the number of unhalted core clock cycl= es. (Fixed event)", "CollectPEBSRecord": "2", - "Counter": "33", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "PEBScounters": "33", "SampleAfterValue": "2000003", @@ -115,7 +355,7 @@ { "BriefDescription": "Counts the total number of instructions retir= ed. (Fixed event)", "CollectPEBSRecord": "2", - "Counter": "32", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PEBS": "1", "PEBScounters": "32", @@ -123,6 +363,17 @@ "UMask": "0x1", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the total number of instructions retir= ed.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc0", + "EventName": "INST_RETIRED.ANY_P", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "2000003", + "Unit": "cpu_atom" + }, { "BriefDescription": "This event is deprecated. Refer to new event = LD_BLOCKS.ADDRESS_ALIAS", "CollectPEBSRecord": "2", @@ -769,7 +1020,7 @@ "Unit": "cpu_core" }, { - "BriefDescription": "number of branch instructions retired that we= re mispredicted and taken. Non PEBS", + "BriefDescription": "number of branch instructions retired that we= re mispredicted and taken.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", @@ -915,7 +1166,7 @@ { "BriefDescription": "Reference cycles when the core is not in halt= state.", "CollectPEBSRecord": "2", - "Counter": "34", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PEBScounters": "34", "SampleAfterValue": "2000003", @@ -923,10 +1174,22 @@ "UMask": "0x3", "Unit": "cpu_core" }, + { + "BriefDescription": "Reference cycles when the core is not in halt= state.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x3c", + "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, { "BriefDescription": "Core cycles when the thread is not in halt st= ate", "CollectPEBSRecord": "2", - "Counter": "33", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "PEBScounters": "33", "SampleAfterValue": "2000003", @@ -1124,7 +1387,7 @@ { "BriefDescription": "Number of instructions retired. Fixed Counter= - architectural event", "CollectPEBSRecord": "2", - "Counter": "32", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PEBS": "1", "PEBScounters": "32", @@ -1155,7 +1418,7 @@ "Unit": "cpu_core" }, { - "BriefDescription": "Number of all retired NOP instructions.", + "BriefDescription": "Retired NOP instructions.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", @@ -1168,7 +1431,7 @@ { "BriefDescription": "Precise instruction retired with PEBS precise= -distribution", "CollectPEBSRecord": "2", - "Counter": "32", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.PREC_DIST", "PEBS": "1", "PEBScounters": "32", @@ -1532,7 +1795,7 @@ { "BriefDescription": "TMA slots available for an unhalted logical p= rocessor. Fixed counter - architectural event", "CollectPEBSRecord": "2", - "Counter": "35", + "Counter": "Fixed counter 3", "EventName": "TOPDOWN.SLOTS", "PEBScounters": "35", "SampleAfterValue": "10000003", diff --git a/tools/perf/pmu-events/arch/x86/alderlake/uncore-other.json b/t= ools/perf/pmu-events/arch/x86/alderlake/uncore-other.json index 50de82c29944..b1ae349f5f21 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/uncore-other.json @@ -3,7 +3,7 @@ "BriefDescription": "This 48-bit fixed counter counts the UCLK cyc= les", "Counter": "Fixed", "CounterType": "PGMABLE", - "EventCode": "0xff", + "EventCode": "0xff", "EventName": "UNC_CLOCK.SOCKET", "PerPkg": "1", "Unit": "CLOCK" diff --git a/tools/perf/pmu-events/arch/x86/alderlake/virtual-memory.json b= /tools/perf/pmu-events/arch/x86/alderlake/virtual-memory.json index c5676f11d863..12baf768ad8d 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/virtual-memory.json @@ -23,6 +23,42 @@ "UMask": "0xe", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of page walks initiated by = a instruction fetch that missed the first and second level TLBs.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.MISS_CAUSED_WALK", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x1", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of page walks due to an ins= truction fetch that miss the PDE (Page Directory Entry) cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.PDE_CACHE_MISS", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x80", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to any page size.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0xe", + "Unit": "cpu_atom" + }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer and retirement are both stalled due to a DTLB= miss.", "CollectPEBSRecord": "2", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index dd1d24d3cb65..2842f23db82a 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -1,4 +1,5 @@ Family-model,Version,Filename,EventType +GenuineIntel-6-9[7A],v1.13,alderlake,core GenuineIntel-6-(3D|47),v26,broadwell,core GenuineIntel-6-56,v23,broadwellde,core GenuineIntel-6-4F,v19,broadwellx,core @@ -41,8 +42,6 @@ GenuineIntel-6-6A,v1,icelakex,core GenuineIntel-6-6C,v1,icelakex,core GenuineIntel-6-86,v1,snowridgex,core GenuineIntel-6-96,v1,elkhartlake,core -GenuineIntel-6-97,v1,alderlake,core -GenuineIntel-6-9A,v1,alderlake,core GenuineIntel-6-8F,v1,sapphirerapids,core AuthenticAMD-23-([12][0-9A-F]|[0-9A-F]),v2,amdzen1,core AuthenticAMD-23-[[:xdigit:]]+,v1,amdzen2,core --=20 2.37.1.359.gd136c6c3e2-goog From nobody Wed Apr 15 05:45:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2065FC19F2B for ; Wed, 27 Jul 2022 22:09:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234199AbiG0WJ1 (ORCPT ); Wed, 27 Jul 2022 18:09:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233961AbiG0WJB (ORCPT ); Wed, 27 Jul 2022 18:09:01 -0400 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 28C08558CB for ; Wed, 27 Jul 2022 15:08:57 -0700 (PDT) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-31dfe25bd47so846867b3.18 for ; Wed, 27 Jul 2022 15:08:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=8F+fz6+0/gUalMupUoM3UlVut6MQCtx2E2VfaCYyCYs=; b=SVrzjdA/29nNMvxtMEUOAmZjsomAqykdTmkEngLitpMomnZZwE06XS4fPMaoa1387w 9MYE+Eu5EE80/Ys86P/8OIvtCSXzZKJt2PmnabnqXvdkKB2nVSpGibW9O4i2bv9XZKlK Sd3/A7fn5Yi45H8hr9ZWe9nVMceuwvDVWBrk2BZPyP1fSktKr2dSLiY2i8s77QqB2SKh X5iItT/To9rea2fQ21xTcpDJCg9aoST9nMpTL+fMVCdy8EEcZTTlAa/gwteLEHscYjRm TssFkFv+wF9vvz3irksGb5nDZ9Uh83fjRFCPKpkuzoLeHkBRErJsi7U+C+JgOGed5m2K 58Ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=8F+fz6+0/gUalMupUoM3UlVut6MQCtx2E2VfaCYyCYs=; b=Nsas9oQa/UPsntemIPzaCIQU15N2YL93c3Ez43bDsPXNyjldn6Kg10hLMwjsd3Aoar Mj/bGr8+BXdaSl+vUjUr/mm0xzyQ8UlK2d1ZWUBVZ3pAPTQsDVIMYl/ax2+ap2hwLDj9 iZ88DTUkzePqLcqU6CW+RfLez7vmqY5u0xlU/PXQJVo6ZFoeh2wv7esLve0APWP1YSi5 aLPirSMG+Df3QmnMTi4nMLR3zuiUysAJW04fuCTGesVFbKF2Glmu6BYocUosxz6P6S9X I369oBXQDn3T1LhV8pj9XGkWIP6OxGjA4QP/8SdenIQMNZcI7ENZRytxSLtVZQsIORiO bQnQ== X-Gm-Message-State: AJIora+1nzOY0vcHFYAW368rY/iKJmzcBodtJ4BbKDgtbjOVn3XMGYVC J3vsHxo/MBMclg39ndvBfyI20DjuK+34 X-Google-Smtp-Source: AGRyM1vcNms7CX+IV4N8vvNYD0KM3NFfqflu7Gp/S+6+PQ53h+1Kq1xz56/htqhh8ihmrG7gqa22U7iGFz6u X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:882a:af57:8cb6:6f9e]) (user=irogers job=sendgmr) by 2002:a81:5748:0:b0:31f:6587:b25 with SMTP id l69-20020a815748000000b0031f65870b25mr3836694ywb.517.1658959736916; Wed, 27 Jul 2022 15:08:56 -0700 (PDT) Date: Wed, 27 Jul 2022 15:08:07 -0700 In-Reply-To: <20220727220832.2865794-1-irogers@google.com> Message-Id: <20220727220832.2865794-6-irogers@google.com> Mime-Version: 1.0 References: <20220727220832.2865794-1-irogers@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH v3 05/30] perf vendor events: Update bonnell mapfile.csv From: Ian Rogers To: perry.taylor@intel.com, caleb.biggers@intel.com, kshipra.bopardikar@intel.com, Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Sedat Dilek Cc: Stephane Eranian , Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Align end of file whitespace with what is generated by: https://github.com/intel/event-converter-for-linux-perf/blob/master/downloa= d_and_gen.py Fold the mapfile.csv entries together with a more complex regular expression. This will reduce the pmu-events.c table size. The files following this change are still at v4. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/arch/x86/bonnell/cache.json | 2 +- tools/perf/pmu-events/arch/x86/bonnell/floating-point.json | 2 +- tools/perf/pmu-events/arch/x86/bonnell/frontend.json | 2 +- tools/perf/pmu-events/arch/x86/bonnell/memory.json | 2 +- tools/perf/pmu-events/arch/x86/bonnell/other.json | 2 +- tools/perf/pmu-events/arch/x86/bonnell/pipeline.json | 2 +- tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json | 2 +- tools/perf/pmu-events/arch/x86/mapfile.csv | 6 +----- 8 files changed, 8 insertions(+), 12 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/bonnell/cache.json b/tools/perf= /pmu-events/arch/x86/bonnell/cache.json index 71653bfe7093..86582bb8aa39 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/cache.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/cache.json @@ -743,4 +743,4 @@ "SampleAfterValue": "10000", "UMask": "0x2" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json b/t= ools/perf/pmu-events/arch/x86/bonnell/floating-point.json index f8055ff47f19..1fa347d07c98 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json @@ -258,4 +258,4 @@ "SampleAfterValue": "2000000", "UMask": "0x2" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/bonnell/frontend.json b/tools/p= erf/pmu-events/arch/x86/bonnell/frontend.json index e852eb2cc878..21fe5fe229aa 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/frontend.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/frontend.json @@ -88,4 +88,4 @@ "SampleAfterValue": "2000000", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/bonnell/memory.json b/tools/per= f/pmu-events/arch/x86/bonnell/memory.json index 2aa4c41f528e..f8b45b6fb4d3 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/memory.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/memory.json @@ -151,4 +151,4 @@ "SampleAfterValue": "200000", "UMask": "0x86" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/bonnell/other.json b/tools/perf= /pmu-events/arch/x86/bonnell/other.json index 114c062e7e96..e0bdcfbfa9dc 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/other.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/other.json @@ -447,4 +447,4 @@ "SampleAfterValue": "200000", "UMask": "0xc0" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json b/tools/p= erf/pmu-events/arch/x86/bonnell/pipeline.json index 896b738e59b6..f5123c99a7ba 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json @@ -353,4 +353,4 @@ "SampleAfterValue": "2000000", "UMask": "0x10" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json b/t= ools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json index c2363b8e61b4..e8512c585572 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json @@ -121,4 +121,4 @@ "SampleAfterValue": "200000", "UMask": "0x3" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 2842f23db82a..dbd6bcbbca8b 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -1,13 +1,9 @@ Family-model,Version,Filename,EventType GenuineIntel-6-9[7A],v1.13,alderlake,core +GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core GenuineIntel-6-(3D|47),v26,broadwell,core GenuineIntel-6-56,v23,broadwellde,core GenuineIntel-6-4F,v19,broadwellx,core -GenuineIntel-6-1C,v4,bonnell,core -GenuineIntel-6-26,v4,bonnell,core -GenuineIntel-6-27,v4,bonnell,core -GenuineIntel-6-36,v4,bonnell,core -GenuineIntel-6-35,v4,bonnell,core GenuineIntel-6-5C,v8,goldmont,core GenuineIntel-6-7A,v1,goldmontplus,core GenuineIntel-6-3C,v24,haswell,core --=20 2.37.1.359.gd136c6c3e2-goog From nobody Wed Apr 15 05:45:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0B362C04A68 for ; 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Wed, 27 Jul 2022 15:08:59 -0700 (PDT) Date: Wed, 27 Jul 2022 15:08:08 -0700 In-Reply-To: <20220727220832.2865794-1-irogers@google.com> Message-Id: <20220727220832.2865794-7-irogers@google.com> Mime-Version: 1.0 References: <20220727220832.2865794-1-irogers@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH v3 06/30] perf vendor events: Update Intel cascadelakex From: Ian Rogers To: perry.taylor@intel.com, caleb.biggers@intel.com, kshipra.bopardikar@intel.com, Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Sedat Dilek Cc: Stephane Eranian , Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Update to v1.16, the metrics are based on TMA 4.4 full. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/downloa= d_and_gen.py to download and generate the latest events and metrics. Manually copy the cascadelakex files into perf and update mapfile.csv. Tested with 'perf test': 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok 90: perf all metricgroups test : Ok 91: perf all metrics test : Skip 93: perf all PMU test : Ok Signed-off-by: Ian Rogers --- .../arch/x86/cascadelakex/cache.json | 8 +- .../arch/x86/cascadelakex/clx-metrics.json | 724 ++++++++++++++++-- .../arch/x86/cascadelakex/floating-point.json | 2 +- .../arch/x86/cascadelakex/frontend.json | 2 +- .../arch/x86/cascadelakex/other.json | 63 ++ .../arch/x86/cascadelakex/pipeline.json | 11 + .../arch/x86/cascadelakex/uncore-memory.json | 9 + .../arch/x86/cascadelakex/uncore-other.json | 697 ++++++++++++++++- .../arch/x86/cascadelakex/virtual-memory.json | 2 +- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 10 files changed, 1439 insertions(+), 81 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json b/tools= /perf/pmu-events/arch/x86/cascadelakex/cache.json index fcaa487b8737..716c1b507496 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json @@ -482,7 +482,7 @@ "UMask": "0x4" }, { - "BriefDescription": "Retired load instructions with remote Intel O= ptane DC persistent memory as the data source where the data request missed= all caches. Precise event.", + "BriefDescription": "Retired load instructions with remote Intel(R= ) Optane(TM) DC persistent memory as the data source where the data request= missed all caches. Precise event.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "Data_LA": "1", @@ -490,7 +490,7 @@ "EventCode": "0xD3", "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM", "PEBS": "1", - "PublicDescription": "Counts retired load instructions with remote= Intel Optane DC persistent memory as the data source and the data request = missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode). Precise e= vent", + "PublicDescription": "Counts retired load instructions with remote= Intel(R) Optane(TM) DC persistent memory as the data source and the data r= equest missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode). Pr= ecise event", "SampleAfterValue": "100007", "UMask": "0x10" }, @@ -590,7 +590,7 @@ "UMask": "0x20" }, { - "BriefDescription": "Retired load instructions with local Intel Op= tane DC persistent memory as the data source where the data request missed = all caches. Precise event.", + "BriefDescription": "Retired load instructions with local Intel(R)= Optane(TM) DC persistent memory as the data source where the data request = missed all caches. Precise event.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "Data_LA": "1", @@ -598,7 +598,7 @@ "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.LOCAL_PMM", "PEBS": "1", - "PublicDescription": "Counts retired load instructions with local = Intel Optane DC persistent memory as the data source and the data request m= issed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode). Precise ev= ent", + "PublicDescription": "Counts retired load instructions with local = Intel(R) Optane(TM) DC persistent memory as the data source and the data re= quest missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode). Pre= cise event", "SampleAfterValue": "100003", "UMask": "0x80" }, diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json b= /tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json index 5a1631448b46..ba5863a80d43 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json @@ -95,13 +95,13 @@ { "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIV= ITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORT= S_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_= ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NO= T_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 *= INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) * ( ( (max( (= CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK= _UNHALTED.THREAD , 0 )) / ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.= BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UT= IL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTI= VITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DE= LIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT= _MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (min( 9 * c= pu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=3D1@ + DTLB_LOAD_MISSES.WALK_ACTIVE = , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 )= ) / CPU_CLK_UNHALTED.THREAD) / (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYC= LE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) + ( (EXE_A= CTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.ST= ALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTA= L + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_= UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STOR= ES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) -= ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED= .THREAD))) ) * ( (( 9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=3D1@ + DTL= B_STORE_MISSES.WALK_ACTIVE ) / CPU_CLK_UNHALTED.THREAD) / #(EXE_ACTIVITY.BO= UND_ON_STORES / CPU_CLK_UNHALTED.THREAD) ) ) ", - "MetricGroup": "Mem;MemoryTLB", + "MetricGroup": "Mem;MemoryTLB;Offcore", "MetricName": "Memory_Data_TLBs" }, { "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIV= ITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORT= S_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 = ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) = ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (I= DQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 += CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( U= OPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) )))) * ( ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - = CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / ((( CYC= LE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVI= TY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS /= (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD= _ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EX= E_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( (= CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE /= CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOV= ERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU= _CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (m= in( 9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=3D1@ + DTLB_LOAD_MISSES.WAL= K_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_M= ISS , 0 ) ) / CPU_CLK_UNHALTED.THREAD) / (max( ( CYCLE_ACTIVITY.STALLS_MEM_= ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) += ( (EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_AC= TIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.ST= ALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 *= ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTI= VE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACT= IVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_C= YCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_= UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (( 9 * = cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=3D1@ + DTLB_STORE_MISSES.WALK_ACTI= VE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREA= D_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / #(EXE_ACTIVITY.BOUND_ON_STORES = / CPU_CLK_UNHALTED.THREAD) ) ) ", - "MetricGroup": "Mem;MemoryTLB;_SMT", + "MetricGroup": "Mem;MemoryTLB;Offcore_SMT", "MetricName": "Memory_Data_TLBs_SMT" }, { @@ -158,12 +158,6 @@ "MetricGroup": "Branches;Fed;FetchBW", "MetricName": "UpTB" }, - { - "BriefDescription": "Cycles Per Instruction (per Logical Processor= )", - "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", - "MetricGroup": "Pipeline;Mem", - "MetricName": "CPI" - }, { "BriefDescription": "Per-Logical Processor actual clocks when the = Logical Processor is active.", "MetricExpr": "CPU_CLK_UNHALTED.THREAD", @@ -214,42 +208,36 @@ "MetricName": "FLOPc_SMT" }, { - "BriefDescription": "Actual per-core usage of the Floating Point e= xecution units (regardless of the vector width)", + "BriefDescription": "Actual per-core usage of the Floating Point n= on-X87 execution units (regardless of precision or vector-width)", "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_I= NST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP= _ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_= DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.5= 12B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) ) / ( 2 * CPU= _CLK_UNHALTED.THREAD )", "MetricGroup": "Cor;Flops;HPC", "MetricName": "FP_Arith_Utilization", - "PublicDescription": "Actual per-core usage of the Floating Point = execution units (regardless of the vector width). Values > 1 are possible d= ue to Fused-Multiply Add (FMA) counting." + "PublicDescription": "Actual per-core usage of the Floating Point = non-X87 execution units (regardless of precision or vector-width). Values >= 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; = [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less commo= n)." }, { - "BriefDescription": "Actual per-core usage of the Floating Point e= xecution units (regardless of the vector width). SMT version; use when SMT = is enabled and measuring per logical CPU.", + "BriefDescription": "Actual per-core usage of the Floating Point n= on-X87 execution units (regardless of precision or vector-width). SMT versi= on; use when SMT is enabled and measuring per logical CPU.", "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_I= NST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP= _ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_= DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.5= 12B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) ) / ( 2 * ( (= CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE /= CPU_CLK_UNHALTED.REF_XCLK ) ) )", "MetricGroup": "Cor;Flops;HPC_SMT", "MetricName": "FP_Arith_Utilization_SMT", - "PublicDescription": "Actual per-core usage of the Floating Point = execution units (regardless of the vector width). Values > 1 are possible d= ue to Fused-Multiply Add (FMA) counting. SMT version; use when SMT is enabl= ed and measuring per logical CPU." + "PublicDescription": "Actual per-core usage of the Floating Point = non-X87 execution units (regardless of precision or vector-width). Values >= 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; = [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less commo= n). SMT version; use when SMT is enabled and measuring per logical CPU." }, { - "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is at least 1 uop executed)", + "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per-core", "MetricExpr": "UOPS_EXECUTED.THREAD / (( UOPS_EXECUTED.CORE_CYCLES= _GE_1 / 2 ) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, { - "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIR= ED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.TH= READ))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_C= LK_UNHALTED.THREAD)) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.A= LL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU= _CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CO= RE / (4 * CPU_CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_= MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BrMispredicts", - "MetricName": "Branch_Misprediction_Cost" - }, - { - "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIR= ED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU= _CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU= _CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_D= ELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED= .ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ((BR_MISP_RETIRED.AL= L_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT= _MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_= DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 )= * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )= )) ) * (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_= THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCH= ES", - "MetricGroup": "Bad;BrMispredicts_SMT", - "MetricName": "Branch_Misprediction_Cost_SMT" + "BriefDescription": "Probability of Core Bound bottleneck hidden b= y SMT-profiling artifacts", + "MetricExpr": "( 1 - ((1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU= _CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES )= / (4 * CPU_CLK_UNHALTED.THREAD)) - ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE= _ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.= 1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) = * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_U= OPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY= + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)))) / ((EX= E_ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.R= ETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL)) = / CPU_CLK_UNHALTED.THREAD if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STAL= LS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else (EXE_ACTIVITY.1_PORTS_UTI= L + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIV= ITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD) if ((1 - (IDQ_UOPS_NOT_DELIVER= ED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC= .RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)) - ((( CYCLE_ACTIVITY.ST= ALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTA= L + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_= UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STOR= ES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) -= ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED= .THREAD)))) < ((EXE_ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACTIVITY.1_PORTS_UTIL= + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVI= TY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD if ( ARITH.DIVIDER_ACTIVE < ( C= YCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else (EXE_AC= TIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.TH= READ)) * EXE_ACTIVITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD) else 1 ) if = 0 > 0.5 else 0", + "MetricGroup": "Cor;SMT", + "MetricName": "Core_Bound_Likely" }, { - "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear)", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "IpMispredict" + "BriefDescription": "Probability of Core Bound bottleneck hidden b= y SMT-profiling artifacts", + "MetricExpr": "( 1 - ((1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( (= CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE /= CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOV= ERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU= _CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ((( CYC= LE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVI= TY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS /= (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD= _ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EX= E_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( (= CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE /= CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOV= ERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU= _CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))))) / ((EXE= _ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RE= TIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTE= D.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORT= S_UTIL)) / CPU_CLK_UNHALTED.THREAD if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTI= VITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else (EXE_ACTIVITY.1_= PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD = / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCL= K ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD) if ((1 - (I= DQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 += CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( U= OPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) ))) - ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIV= ITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORT= S_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 = ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) = ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (I= DQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 += CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( U= OPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) ))))) < ((EXE_ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACT= IVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED= .THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED= .REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD if = ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STA= LLS_MEM_ANY ) ) else (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOT= S / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THR= EAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) /= CPU_CLK_UNHALTED.THREAD) else 1 ) if (1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTI= VE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 )) > 0.5 else 0", + "MetricGroup": "Cor;SMT_SMT", + "MetricName": "Core_Bound_Likely_SMT" }, { "BriefDescription": "Core actual clocks when any Logical Processor= is active on the Physical Core", @@ -341,48 +329,84 @@ "MetricName": "IpArith_AVX512", "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit i= nstruction (lower number means higher occurrence rate). May undercount due = to FMA double counting." }, + { + "BriefDescription": "Instructions per Software prefetch instructio= n (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrenc= e rate)", + "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umas= k\\=3D0xF@", + "MetricGroup": "Prefetches", + "MetricName": "IpSWPF" + }, { "BriefDescription": "Total number of retired Instructions, Sample = with: INST_RETIRED.PREC_DIST", "MetricExpr": "INST_RETIRED.ANY", "MetricGroup": "Summary;TmaL1", "MetricName": "Instructions" }, + { + "BriefDescription": "Average number of Uops retired in cycles wher= e at least one uop has retired.", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE= _SLOTS\\,cmask\\=3D1@", + "MetricGroup": "Pipeline;Ret", + "MetricName": "Retire" + }, + { + "BriefDescription": "", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,c= mask\\=3D1@", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", + "MetricName": "Execute" + }, { "BriefDescription": "Average number of Uops issued by front-end wh= en it issued something", "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=3D1= @", "MetricGroup": "Fed;FetchBW", "MetricName": "Fetch_UpC" }, - { - "BriefDescription": "Fraction of Uops delivered by the LSD (Loop S= tream Detector; aka Loop Cache)", - "MetricExpr": "LSD.UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS= + IDQ.MS_UOPS)", - "MetricGroup": "Fed;LSD", - "MetricName": "LSD_Coverage" - }, { "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_= UOPS + IDQ.MS_UOPS)", + "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.= MS_UOPS)", "MetricGroup": "DSB;Fed;FetchBW", "MetricName": "DSB_Coverage" }, { - "BriefDescription": "Total penalty related to DSB (uop cache) miss= es - subset/see of/the Instruction_Fetch_BW Bottleneck.", - "MetricExpr": "(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.COR= E / (4 * CPU_CLK_UNHALTED.THREAD)) * (DSB2MITE_SWITCHES.PENALTY_CYCLES / CP= U_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.C= ORE / (4 * CPU_CLK_UNHALTED.THREAD)) + ((IDQ_UOPS_NOT_DELIVERED.CORE / (4 *= CPU_CLK_UNHALTED.THREAD)) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELI= V.CORE / (4 * CPU_CLK_UNHALTED.THREAD))) * (( IDQ.ALL_MITE_CYCLES_ANY_UOPS = - IDQ.ALL_MITE_CYCLES_4_UOPS ) / CPU_CLK_UNHALTED.THREAD / 2) / #((IDQ_UOPS= _NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - (4 * IDQ_UOPS_NOT_DE= LIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)))", + "BriefDescription": "Average number of cycles of a switch from the= DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details= .", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / DSB2MITE_SWITCHE= S.COUNT", + "MetricGroup": "DSBmiss", + "MetricName": "DSB_Switch_Cost" + }, + { + "BriefDescription": "Total penalty related to DSB (uop cache) miss= es - subset of the Instruction_Fetch_BW Bottleneck.", + "MetricExpr": "100 * ( (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_D= ELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * (DSB2MITE_SWITCHES.PENALTY_CYC= LES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS= _DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) + ((IDQ_UOPS_NOT_DELIVERED.COR= E / (4 * CPU_CLK_UNHALTED.THREAD)) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_U= OPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD))) * (( IDQ.ALL_MITE_CYCLES_A= NY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS ) / CPU_CLK_UNHALTED.THREAD / 2) / #((= IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - (4 * IDQ_UOP= S_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD))) = )", "MetricGroup": "DSBmiss;Fed", - "MetricName": "DSB_Misses_Cost" + "MetricName": "DSB_Misses" }, { - "BriefDescription": "Total penalty related to DSB (uop cache) miss= es - subset/see of/the Instruction_Fetch_BW Bottleneck.", - "MetricExpr": "(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.COR= E / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THR= EAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (DSB2MITE_SWITCHES.PENALTY_C= YCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UO= PS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHA= LTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + ((IDQ_UOPS_NOT_D= ELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHA= LTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ_UOPS_NO= T_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2= ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK )= )))) * (( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS ) / ( = ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE = / CPU_CLK_UNHALTED.REF_XCLK ) ) / 2) / #((IDQ_UOPS_NOT_DELIVERED.CORE / (4 = * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACT= IVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_= 0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_= UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))))", + "BriefDescription": "Total penalty related to DSB (uop cache) miss= es - subset of the Instruction_Fetch_BW Bottleneck.", + "MetricExpr": "100 * ( (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_D= ELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED= .ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (DSB2MITE_SWITCHES.P= ENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYC= LES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_= CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + ((IDQ_UO= PS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_= CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ= _UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.TH= READ / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.RE= F_XCLK ) )))) * (( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOP= S ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD= _ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) / 2) / #((IDQ_UOPS_NOT_DELIVERED.CO= RE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_TH= READ_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ_UOPS_NOT_DELIVERED= .CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + = CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) )", "MetricGroup": "DSBmiss;Fed_SMT", - "MetricName": "DSB_Misses_Cost_SMT" + "MetricName": "DSB_Misses_SMT" }, { - "BriefDescription": "Number of Instructions per non-speculative DS= B miss", + "BriefDescription": "Number of Instructions per non-speculative DS= B miss (lower number means higher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", "MetricGroup": "DSBmiss;Fed", "MetricName": "IpDSB_Miss_Ret" }, + { + "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "IpMispredict" + }, + { + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIR= ED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.TH= READ))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_C= LK_UNHALTED.THREAD)) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.A= LL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU= _CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CO= RE / (4 * CPU_CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_= MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "Branch_Misprediction_Cost" + }, + { + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIR= ED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU= _CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU= _CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_D= ELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED= .ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ((BR_MISP_RETIRED.AL= L_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT= _MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_= DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 )= * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )= )) ) * (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_= THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCH= ES", + "MetricGroup": "Bad;BrMispredicts_SMT", + "MetricName": "Branch_Misprediction_Cost_SMT" + }, { "BriefDescription": "Fraction of branches that are non-taken condi= tionals", "MetricExpr": "BR_INST_RETIRED.NOT_TAKEN / BR_INST_RETIRED.ALL_BRA= NCHES", @@ -408,11 +432,10 @@ "MetricName": "Jump" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load instructions (in core cycles)", + "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load operations (in core cycles)", "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS = + MEM_LOAD_RETIRED.FB_HIT )", "MetricGroup": "Mem;MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency", - "PublicDescription": "Actual Average Latency for L1 data-cache mis= s demand load instructions (in core cycles). Latency may be overestimated f= or multi-load instructions - e.g. repeat strings." + "MetricName": "Load_Miss_Real_Latency" }, { "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", @@ -420,30 +443,6 @@ "MetricGroup": "Mem;MemoryBound;MemoryBW", "MetricName": "MLP" }, - { - "BriefDescription": "Average data fill bandwidth to the L1 data ca= che [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW" - }, - { - "BriefDescription": "Average data fill bandwidth to the L2 cache [= GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW" - }, - { - "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW" - }, - { - "BriefDescription": "Average per-core data access bandwidth to the= L3 cache [GB / sec]", - "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / d= uration_time", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "L3_Cache_Access_BW" - }, { "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", @@ -463,13 +462,13 @@ "MetricName": "L2MPKI" }, { - "BriefDescription": "L2 cache misses per kilo instruction for all = request types (including speculative)", + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instru= ction for all request types (including speculative)", "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", "MetricGroup": "Mem;CacheMisses;Offcore", "MetricName": "L2MPKI_All" }, { - "BriefDescription": "L2 cache misses per kilo instruction for all = demand loads (including speculative)", + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instru= ction for all demand loads (including speculative)", "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.= ANY", "MetricGroup": "Mem;CacheMisses", "MetricName": "L2MPKI_Load" @@ -493,7 +492,7 @@ "MetricName": "L3MPKI" }, { - "BriefDescription": "Fill Buffer (FB) true hits per kilo instructi= ons for retired demand loads", + "BriefDescription": "Fill Buffer (FB) hits per kilo instructions f= or retired demand loads (L1D misses that merge into ongoing miss-handling e= ntries)", "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", "MetricGroup": "Mem;CacheMisses", "MetricName": "FB_HPKI" @@ -511,6 +510,30 @@ "MetricGroup": "Mem;MemoryTLB_SMT", "MetricName": "Page_Walks_Utilization_SMT" }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", + "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L1D_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 2 cache [GB / sec]", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L2_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L3_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-core data access bandwidth to the= L3 cache [GB / sec]", + "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / d= uration_time", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "L3_Cache_Access_BW" + }, { "BriefDescription": "Rate of silent evictions from the L2 cache pe= r Kilo instruction where the evicted lines are dropped (no writeback to L3 = or memory)", "MetricExpr": "1000 * L2_LINES_OUT.SILENT / INST_RETIRED.ANY", @@ -523,6 +546,30 @@ "MetricGroup": "L2Evicts;Mem;Server", "MetricName": "L2_Evictions_NonSilent_PKI" }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L1 data cache [GB / sec]", + "MetricExpr": "(64 * L1D.REPLACEMENT / 1000000000 / duration_time)= ", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L1D_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L2 cache [GB / sec]", + "MetricExpr": "(64 * L2_LINES_IN.ALL / 1000000000 / duration_time)= ", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L2_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L3 cache [GB / sec]", + "MetricExpr": "(64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duratio= n_time)", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L3_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data access bandwidth to t= he L3 cache [GB / sec]", + "MetricExpr": "(64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / = duration_time)", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "L3_Cache_Access_BW_1T" + }, { "BriefDescription": "Average CPU Utilization", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", @@ -539,7 +586,8 @@ "BriefDescription": "Giga Floating Point Operations Per Second", "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_= ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_= DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RET= IRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE = + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.5= 12B_PACKED_SINGLE ) / 1000000000 ) / duration_time", "MetricGroup": "Cor;Flops;HPC", - "MetricName": "GFLOPs" + "MetricName": "GFLOPs", + "PublicDescription": "Giga Floating Point Operations Per Second. A= ggregate across all supported options of: FP precisions, scalar and vector = instructions, vector-width and AMX engine." }, { "BriefDescription": "Average Frequency Utilization relative nomina= l frequency", @@ -714,5 +762,537 @@ "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C7_Pkg_Residency" + }, + { + "BriefDescription": "Percentage of time spent in the active CPU po= wer state C0", + "MetricExpr": "100 * CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricGroup": "", + "MetricName": "cpu_utilization_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "CPU operating frequency (in GHz)", + "MetricExpr": "( CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TS= C * #SYSTEM_TSC_FREQ ) / 1000000000", + "MetricGroup": "", + "MetricName": "cpu_operating_frequency", + "ScaleUnit": "1GHz" + }, + { + "BriefDescription": "Cycles per instruction retired; indicating ho= w much time each executed instruction took; in units of cycles.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "cpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "The ratio of number of completed memory load = instructions to the total number completed instructions", + "MetricExpr": "MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "loads_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "The ratio of number of completed memory store= instructions to the total number completed instructions", + "MetricExpr": "MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "stores_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of requests missing L1 data c= ache (includes data+rfo w/ prefetches) to the total number of completed ins= tructions", + "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l1d_mpi_includes_data_plus_rfo_with_prefetches", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of demand load requests hitti= ng in L1 data cache to the total number of completed instructions ", + "MetricExpr": "MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l1d_demand_data_read_hits_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read requests missing= in L1 instruction cache (includes prefetches) to the total number of compl= eted instructions", + "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed demand load requ= ests hitting in L2 cache to the total number of completed instructions ", + "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l2_demand_data_read_hits_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of requests missing L2 cache = (includes code+data+rfo w/ prefetches) to the total number of completed ins= tructions", + "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l2_mpi_includes_code_plus_data_plus_rfo_with_prefet= ches", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed data read reques= t missing L2 cache to the total number of completed instructions", + "MetricExpr": "MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l2_demand_data_read_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read request missing = L2 cache to the total number of completed instructions", + "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l2_demand_code_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of data read requests missing= last level core cache (includes demand w/ prefetches) to the total number = of completed instructions", + "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=3D0x12D= 4043300000000@ / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "llc_data_read_mpi_demand_plus_prefetch", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read requests missing= last level core cache (includes demand w/ prefetches) to the total number = of completed instructions", + "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=3D0x12C= C023300000000@ / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "llc_code_read_mpi_demand_plus_prefetch", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) d= emand and prefetch data read miss (read memory access) in nano seconds", + "MetricExpr": "( ( 1000000000 * ( cha@unc_cha_tor_occupancy.ia_mis= s\\,config1\\=3D0x4043300000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config= 1\\=3D0x4043300000000@ ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_CL= OCKTICKS) * #num_packages ) ) ) * duration_time )", + "MetricGroup": "", + "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) d= emand and prefetch data read miss (read memory access) addressed to local m= emory in nano seconds", + "MetricExpr": "( ( 1000000000 * ( cha@unc_cha_tor_occupancy.ia_mis= s\\,config1\\=3D0x4043200000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config= 1\\=3D0x4043200000000@ ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_CL= OCKTICKS) * #num_packages ) ) ) * duration_time )", + "MetricGroup": "", + "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for= _local_requests", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) d= emand and prefetch data read miss (read memory access) addressed to remote = memory in nano seconds", + "MetricExpr": "( ( 1000000000 * ( cha@unc_cha_tor_occupancy.ia_mis= s\\,config1\\=3D0x4043100000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config= 1\\=3D0x4043100000000@ ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_CL= OCKTICKS) * #num_packages ) ) ) * duration_time )", + "MetricGroup": "", + "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for= _remote_requests", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = all page sizes) caused by a code fetch to the total number of completed ins= tructions. This implies it missed in the ITLB (Instruction TLB) and further= levels of TLB.", + "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "itlb_2nd_level_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total n= umber of completed instructions. This implies it missed in the Instruction = Translation Lookaside Buffer (ITLB) and further levels of TLB.", + "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY= ", + "MetricGroup": "", + "MetricName": "itlb_2nd_level_large_page_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = all page sizes) caused by demand data loads to the total number of complete= d instructions. This implies it missed in the DTLB and further levels of TL= B.", + "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "dtlb_2nd_level_load_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = 2 megabyte page sizes) caused by demand data loads to the total number of c= ompleted instructions. This implies it missed in the Data Translation Looka= side Buffer (DTLB) and further levels of TLB.", + "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRE= D.ANY", + "MetricGroup": "", + "MetricName": "dtlb_2nd_level_2mb_large_page_load_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = all page sizes) caused by demand data stores to the total number of complet= ed instructions. This implies it missed in the DTLB and further levels of T= LB.", + "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY= ", + "MetricGroup": "", + "MetricName": "dtlb_2nd_level_store_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Memory read that miss the last level cache (L= LC) addressed to local DRAM as a percentage of total memory read accesses, = does not include LLC prefetches.", + "MetricExpr": "100 * cha@unc_cha_tor_inserts.ia_miss\\,config1\\= =3D0x4043200000000@ / ( cha@unc_cha_tor_inserts.ia_miss\\,config1\\=3D0x404= 3200000000@ + cha@unc_cha_tor_inserts.ia_miss\\,config1\\=3D0x4043100000000= @ )", + "MetricGroup": "", + "MetricName": "numa_percent_reads_addressed_to_local_dram", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Memory reads that miss the last level cache (= LLC) addressed to remote DRAM as a percentage of total memory read accesses= , does not include LLC prefetches.", + "MetricExpr": "100 * cha@unc_cha_tor_inserts.ia_miss\\,config1\\= =3D0x4043100000000@ / ( cha@unc_cha_tor_inserts.ia_miss\\,config1\\=3D0x404= 3200000000@ + cha@unc_cha_tor_inserts.ia_miss\\,config1\\=3D0x4043100000000= @ )", + "MetricGroup": "", + "MetricName": "numa_percent_reads_addressed_to_remote_dram", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Uncore operating frequency in GHz", + "MetricExpr": "UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_CLOCKTI= CKS) * #num_packages ) / 1000000000", + "MetricGroup": "", + "MetricName": "uncore_frequency", + "ScaleUnit": "1GHz" + }, + { + "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data t= ransmit bandwidth (MB/sec)", + "MetricExpr": "( UNC_UPI_TxL_FLITS.ALL_DATA * (64 / 9.0) / 1000000= ) / duration_time", + "MetricGroup": "", + "MetricName": "upi_data_transmit_bw_only_data", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "DDR memory read bandwidth (MB/sec)", + "MetricExpr": "( UNC_M_CAS_COUNT.RD * 64 / 1000000) / duration_tim= e", + "MetricGroup": "", + "MetricName": "memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "DDR memory write bandwidth (MB/sec)", + "MetricExpr": "( UNC_M_CAS_COUNT.WR * 64 / 1000000) / duration_tim= e", + "MetricGroup": "", + "MetricName": "memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "DDR memory bandwidth (MB/sec)", + "MetricExpr": "(( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) * 64 /= 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "memory_bandwidth_total", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) m= emory read bandwidth (MB/sec)", + "MetricExpr": "( UNC_M_PMM_RPQ_INSERTS * 64 / 1000000) / duration_= time", + "MetricGroup": "", + "MetricName": "pmem_memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) m= emory write bandwidth (MB/sec)", + "MetricExpr": "( UNC_M_PMM_WPQ_INSERTS * 64 / 1000000) / duration_= time", + "MetricGroup": "", + "MetricName": "pmem_memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) m= emory bandwidth (MB/sec)", + "MetricExpr": "(( UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS ) = * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "pmem_memory_bandwidth_total", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO reads that are initiated by e= nd device controllers that are requesting memory from the CPU.", + "MetricExpr": "(( UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO= _DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 ) * 4 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "io_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO writes that are initiated by = end device controllers that are writing memory to the CPU.", + "MetricExpr": "(( UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0 + UNC_I= IO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PA= RT2 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3 ) * 4 / 1000000) / duration_= time", + "MetricGroup": "", + "MetricName": "io_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Uops delivered from decoded instruction cache= (decoded stream buffer or DSB) as a percent of total uops delivered to Ins= truction Decode Queue", + "MetricExpr": "100 * ( IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UO= PS + IDQ.MS_UOPS + LSD.UOPS ) )", + "MetricGroup": "", + "MetricName": "percent_uops_delivered_from_decoded_icache_dsb", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Uops delivered from legacy decode pipeline (M= icro-instruction Translation Engine or MITE) as a percent of total uops del= ivered to Instruction Decode Queue", + "MetricExpr": "100 * ( IDQ.MITE_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_U= OPS + IDQ.MS_UOPS + LSD.UOPS ) )", + "MetricGroup": "", + "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline_= mite", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Uops delivered from microcode sequencer (MS) = as a percent of total uops delivered to Instruction Decode Queue", + "MetricExpr": "100 * ( IDQ.MS_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOP= S + IDQ.MS_UOPS + LSD.UOPS ) )", + "MetricGroup": "", + "MetricName": "percent_uops_delivered_from_microcode_sequencer_ms", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Bandwidth (MB/sec) of read requests that miss= the last level cache (LLC) and go to local memory.", + "MetricExpr": "( UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1000000) / du= ration_time", + "MetricGroup": "", + "MetricName": "llc_miss_local_memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth (MB/sec) of write requests that mis= s the last level cache (LLC) and go to local memory.", + "MetricExpr": "( UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1000000) / d= uration_time", + "MetricGroup": "", + "MetricName": "llc_miss_local_memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth (MB/sec) of read requests that miss= the last level cache (LLC) and go to remote memory.", + "MetricExpr": "( UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1000000) / d= uration_time", + "MetricGroup": "", + "MetricName": "llc_miss_remote_memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend. Frontend denotes th= e first part of the processor core responsible to fetch operations that are= executed later on by the Backend part. Within the Frontend; a branch predi= ctor predicts the next address to fetch; cache-lines are fetched from the m= emory subsystem; parsed into instructions; and lastly decoded into micro-op= erations (uops). Ideally the Frontend can issue Machine_Width uops every cy= cle to the Backend. Frontend Bound denotes unutilized issue-slots when ther= e is no Backend stall; i.e. bubbles where Frontend delivered no uops while = Backend could have accepted them. For example; stalls due to instruction-ca= che misses would be categorized under Frontend Bound.", + "MetricExpr": "100 * ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( (= CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREA= D ) ) ) )", + "MetricGroup": "TmaL1;PGO", + "MetricName": "tma_frontend_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = CPU was stalled due to Frontend latency issues. For example; instruction-c= ache misses; iTLB misses or fetch stalls after a branch misprediction are c= ategorized under Frontend Latency. In such cases; the Frontend eventually d= elivers no uops for some period.", + "MetricExpr": "100 * ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOP= S_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on e= lse ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricGroup": "Frontend;TmaL2;m_tma_frontend_bound_percent", + "MetricName": "tma_fetch_latency_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to instruction cache misses.", + "MetricExpr": "100 * ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_= 16B.IFDATA_STALL\\,cmask\\=3D0x1\\,edge\\=3D0x1@ ) / ( CPU_CLK_UNHALTED.THR= EAD ) )", + "MetricGroup": "BigFoot;FetchLat;IcMiss;TmaL3;m_tma_fetch_latency_= percent", + "MetricName": "tma_icache_misses_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Instruction TLB (ITLB) misses.", + "MetricExpr": "100 * ( ICACHE_64B.IFTAG_STALL / ( CPU_CLK_UNHALTED= .THREAD ) )", + "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TmaL3;m_tma_fetch_laten= cy_percent", + "MetricName": "tma_itlb_misses_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Branch Resteers. Branch Resteers estimates the Fron= tend delay in fetching operations from corrected path; following all sorts = of miss-predicted branches. For example; branchy code with lots of miss-pre= dictions might get categorized under Branch Resteers. Note the value of thi= s node may overlap with its siblings.", + "MetricExpr": "100 * ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_U= NHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) )= ", + "MetricGroup": "FetchLat;TmaL3;m_tma_fetch_latency_percent", + "MetricName": "tma_branch_resteers_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decod= ed i-cache) is a Uop Cache where the front-end directly delivers Uops (micr= o operations) avoiding heavy x86 decoding. The DSB pipeline has shorter lat= ency and delivered higher bandwidth than the MITE (legacy instruction decod= e pipeline). Switching between the two pipelines can cause penalties hence = this metric measures the exposed penalty.", + "MetricExpr": "100 * ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CL= K_UNHALTED.THREAD ) )", + "MetricGroup": "DSBmiss;FetchLat;TmaL3;m_tma_fetch_latency_percent= ", + "MetricName": "tma_dsb_switches_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU= was stalled due to Length Changing Prefixes (LCPs). Using proper compiler = flags or Intel Compiler by default will certainly avoid this. #Link: Optimi= zation Guide about LCP BKMs.", + "MetricExpr": "100 * ( ILD_STALL.LCP / ( CPU_CLK_UNHALTED.THREAD )= )", + "MetricGroup": "FetchLat;TmaL3;m_tma_fetch_latency_percent", + "MetricName": "tma_lcp_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates the fraction of cycles = when the CPU was stalled due to switches of uop delivery to the Microcode S= equencer (MS). Commonly used instructions are optimized for delivery by the= DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certa= in operations cannot be handled natively by the execution pipeline; and mus= t be performed by microcode (small programs injected into the execution str= eam). Switching to the MS too often can negatively impact performance. The = MS is designated to deliver long uop flows required by CISC instructions li= ke CPUID; or uncommon conditions like Floating Point Assists when dealing w= ith Denormals.", + "MetricExpr": "100 * ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTE= D.THREAD ) )", + "MetricGroup": "FetchLat;MicroSeq;TmaL3;m_tma_fetch_latency_percen= t", + "MetricName": "tma_ms_switches_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = CPU was stalled due to Frontend bandwidth issues. For example; inefficienc= ies at the instruction decoders; or restrictions for caching in the DSB (de= coded uops cache) are categorized under Fetch Bandwidth. In such cases; the= Frontend typically delivers suboptimal amount of uops to the Backend.", + "MetricExpr": "100 * ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * (= ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THR= EAD ) ) ) ) - ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (= ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UN= HALTED.THREAD ) ) ) ) )", + "MetricGroup": "FetchBW;Frontend;TmaL2;m_tma_frontend_bound_percen= t", + "MetricName": "tma_fetch_bandwidth_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycle= s in which CPU was likely limited due to the MITE pipeline (the legacy deco= de pipeline). This pipeline is used for code that was not pre-cached in the= DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of= long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", + "MetricExpr": "100 * ( ( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MI= TE_CYCLES_4_UOPS ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else = ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", + "MetricGroup": "DSBmiss;FetchBW;TmaL3;m_tma_fetch_bandwidth_percen= t", + "MetricName": "tma_mite_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycle= s in which CPU was likely limited due to DSB (decoded uop cache) fetch pipe= line. For example; inefficient utilization of the DSB cache structure or b= ank conflict when reading from it; are categorized here.", + "MetricExpr": "100 * ( ( IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB= _CYCLES_4_UOPS ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( = CPU_CLK_UNHALTED.THREAD ) ) / 2 )", + "MetricGroup": "DSB;FetchBW;TmaL3;m_tma_fetch_bandwidth_percent", + "MetricName": "tma_dsb_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This category represents fraction of slots wa= sted due to incorrect speculations. This include slots used to issue uops t= hat do not eventually get retired and slots for which the issue-pipeline wa= s blocked due to recovery from earlier incorrect speculation. For example; = wasted work due to miss-predicted branches are categorized under Bad Specul= ation category. Incorrect data speculation followed by Memory Ordering Nuke= s is another example.", + "MetricExpr": "100 * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_S= LOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT= _MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 )= if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricGroup": "TmaL1", + "MetricName": "tma_bad_speculation_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Branch Misprediction. These slots are either wasted = by uops fetched from an incorrectly speculated program path; or stalls when= the out-of-order part of the machine needs to recover its state from a spe= culative path.", + "MetricExpr": "100 * ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_= RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( U= OPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 )= if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHAL= TED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricGroup": "BadSpec;BrMispredicts;TmaL2;m_tma_bad_speculation_= percent", + "MetricName": "tma_branch_mispredicts_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Machine Clears. These slots are either wasted by uop= s fetched prior to the clear; or stalls the out-of-order portion of the mac= hine needs to recover its state after the clear. For example; this can happ= en due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modify= ing-Code (SMC) nukes.", + "MetricExpr": "100 * ( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE= _SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else I= NT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2= ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.= ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * = ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.= RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( = ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNH= ALTED.THREAD ) ) ) ) ) )", + "MetricGroup": "BadSpec;MachineClears;TmaL2;m_tma_bad_speculation_= percent", + "MetricName": "tma_machine_clears_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend. Backend is the portion of the processor cor= e where the out-of-order scheduler dispatches ready uops into their respect= ive execution units; and once completed these uops get retired according to= program order. For example; stalls due to data-cache misses or stalls due = to the divider unit being overloaded are both categorized under Backend Bou= nd. Backend Bound is further divided into two main categories: Memory Bound= and Core Bound.", + "MetricExpr": "100 * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 )= * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED= .THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_= ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_= CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) )= ) )", + "MetricGroup": "TmaL1", + "MetricName": "tma_backend_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = Memory subsystem within the Backend was a bottleneck. Memory Bound estimat= es fraction of slots where pipeline is likely stalled due to demand load or= store instructions. This accounts mainly for (1) non-completed in-flight m= emory demand loads which coincides with execution units starvation; in addi= tion to (2) cases where stores could impose backpressure on the pipeline wh= en many of them get buffered at the same time (less common out of the two).= ", + "MetricExpr": "100 * ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACT= IVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_= PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALT= ED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE= _ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_U= OPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if= #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 )= * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY= _CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on el= se ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricGroup": "Backend;TmaL2;m_tma_backend_bound_percent", + "MetricName": "tma_memory_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was s= talled without loads missing the L1 data cache. The L1 data cache typicall= y has the shortest latency. However; in certain cases like loads blocked o= n older stores; a load might suffer due to high latency even though it is b= eing satisfied by the L1. Another example is loads who miss in the TLB. The= se cases are characterized by execution unit stalls; while some non-complet= ed demand load lives in the machine without having that demand load missing= the L1 cache.", + "MetricExpr": "100 * ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCL= E_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) )", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TmaL3;m_tma_memor= y_bound_percent", + "MetricName": "tma_l1_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was s= talled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 m= isses/L2 hits) can improve the latency and increase performance.", + "MetricExpr": "100 * ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_L= OAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) / ( ( MEM_LOAD_RETI= RED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS )= ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=3D0x1@ ) ) * ( ( CYCLE_ACTIVIT= Y.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.TH= READ ) ) )", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TmaL3;m_tma_memor= y_bound_percent", + "MetricName": "tma_l2_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was s= talled due to loads accesses to L3 cache or contended with a sibling Core. = Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and= increase performance.", + "MetricExpr": "100 * ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACT= IVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TmaL3;m_tma_memor= y_bound_percent", + "MetricName": "tma_l3_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was s= talled on accesses to external memory (DRAM) by loads. Better caching can i= mprove the latency and increase performance.", + "MetricExpr": "100 * ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / = ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_AC= TIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RE= TIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS= ) ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / = ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=3D= 0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MI= SS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( ( 19 * ( = MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( = MEM_LOAD_RETIRED.L1_MISS ) ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_= DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) )= + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT = / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HI= TM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) )= ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RET= IRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) + 10 * ( ( MEM_LOAD_L3_MIS= S_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED= .L1_MISS ) ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD= _RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) + ( MEM_LOAD_L3_MISS_R= ETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L= 1_MISS ) ) ) ) ) ) + ( 25 * ( ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LO= AD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + 33 * ( ( MEM_LOA= D_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD= _RETIRED.L1_MISS ) ) ) ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( = CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTI= VITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETI= RED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS )= ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( = MEM_LOAD_RETIRED.L1_MISS ) ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=3D0x= 1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS= ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_M= ISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1= _MISS ) else 0 ) ) , ( 1 ) ) ) ) ) , ( 1 ) ) )", + "MetricGroup": "MemoryBound;TmaL3mem;TmaL3;m_tma_memory_bound_perc= ent", + "MetricName": "tma_dram_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric roughly estimates (based on idle = latencies) how often the CPU was stalled on accesses to external 3D-Xpoint = (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memo= ry Module. ", + "MetricExpr": "100 * ( min( ( ( ( ( 1 - ( ( ( 19 * ( MEM_LOAD_L3_M= ISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETI= RED.L1_MISS ) ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + = ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) + ( MEM_LOAD= _L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_= RETIRED.L1_MISS ) ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( = MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) / ( ( 19 *= ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT /= ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOC= AL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) = ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_H= IT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE= _HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) = ) ) ) + ( 25 * ( ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB= _HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + 33 * ( ( MEM_LOAD_L3_MISS_RET= IRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_M= ISS ) ) ) ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHAL= TED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L= 2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * = ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) / ( ( = MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETI= RED.L1_MISS ) ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=3D0x1@ ) ) * ( ( = CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CL= K_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.R= EMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else = 0 ) ) , ( 1 ) ) )", + "MetricGroup": "MemoryBound;Server;TmaL3mem;TmaL3;m_tma_memory_bou= nd_percent", + "MetricName": "tma_pmm_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates how often CPU was stall= ed due to RFO store memory accesses; RFO store issue a read-for-ownership = request before the write. Even though store accesses do not typically stall= out-of-order CPUs; there are few cases where stores can lead to actual sta= lls. This metric will be flagged should RFO stores be a bottleneck.", + "MetricExpr": "100 * ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UN= HALTED.THREAD ) )", + "MetricGroup": "MemoryBound;TmaL3mem;TmaL3;m_tma_memory_bound_perc= ent", + "MetricName": "tma_store_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e Core non-memory issues were of a bottleneck. Shortage in hardware comput= e resources; or dependencies in software's instructions are both categorize= d under Core Bound. Hence it may indicate the machine ran out of an out-of-= order resource; certain execution units are overloaded or dependencies in p= rogram's data- or instruction-flow are limiting the performance (e.g. FP-ch= ained long-latency arithmetic operations).", + "MetricExpr": "100 * ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4= ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALT= ED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLE= S_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CP= U_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD )= ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES= ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS= _RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) i= f #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTI= L ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.COR= E / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_C= LK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOV= ERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 )= * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED= .THREAD ) ) ) ) ) )", + "MetricGroup": "Backend;TmaL2;Compute;m_tma_backend_bound_percent", + "MetricName": "tma_core_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles whe= re the Divider unit was active. Divide and square root instructions are per= formed by the Divider unit and can take considerably longer latency than in= teger or Floating Point addition; subtraction; or multiplication.", + "MetricExpr": "100 * ( ARITH.DIVIDER_ACTIVE / ( CPU_CLK_UNHALTED.T= HREAD ) )", + "MetricGroup": "TmaL3;m_tma_core_bound_percent", + "MetricName": "tma_divider_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles the = CPU performance was potentially limited due to Core computation issues (non= divider-related). Two distinct categories can be attributed into this met= ric: (1) heavy data-dependency among contiguous instructions would manifest= in this metric - such cases are often referred to as low Instruction Level= Parallelism (ILP). (2) Contention on some hardware execution unit other th= an Divider. For example; when there are too many multiply operations.", + "MetricExpr": "100 * ( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( EXE_AC= TIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_C= LK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) = ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARIT= H.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_ME= M_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS = ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_C= LK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALT= ED.THREAD ) )", + "MetricGroup": "PortsUtil;TmaL3;m_tma_core_bound_percent", + "MetricName": "tma_ports_utilization_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired. Ideally= ; all pipeline slots would be attributed to the Retiring category. Retirin= g of 100% would indicate the maximum Pipeline_Width throughput was achieved= . Maximizing Retiring typically increases the Instructions-per-cycle (see = IPC metric). Note that a high Retiring value does not necessary mean there = is no room for more performance. For example; Heavy-operations or Microcod= e Assists are categorized under Retiring. They often indicate suboptimal pe= rformance and can often be optimized or avoided. ", + "MetricExpr": "100 * ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * (= ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THR= EAD ) ) ) )", + "MetricGroup": "TmaL1", + "MetricName": "tma_retiring_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring light-weight operations -- instructions that require= no more than one uop (micro-operation). This correlates with total number = of instructions used by the program. A uops-per-instruction (see UPI metric= ) ratio of 1 or less should be expected for decently optimized software run= ning on Intel Core/Xeon products. While this often indicates efficient X86 = instructions were executed; high value does not necessarily mean better per= formance cannot be achieved.", + "MetricExpr": "100 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) *= ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.T= HREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSE= D - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if= #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricGroup": "Retire;TmaL2;m_tma_retiring_percent", + "MetricName": "tma_light_operations_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents overall arithmetic flo= ating-point (FP) operations fraction the CPU has executed (retired). Note t= his metric's value may exceed its parent due to use of \"Uops\" CountDomain= and FMA double-counting.", + "MetricExpr": "100 * ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 )= * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED= .THREAD ) ) ) ) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD ) + ( ( FP_ARITH= _INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) / ( UOP= S_RETIRED.RETIRE_SLOTS ) ) + ( min( ( ( FP_ARITH_INST_RETIRED.128B_PACKED_D= OUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.25= 6B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST= _RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / = ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1 ) ) ) )", + "MetricGroup": "HPC;TmaL3;m_tma_light_operations_percent", + "MetricName": "tma_fp_arith_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring memory operations -- uops for memory load or store a= ccesses.", + "MetricExpr": "100 * ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 )= * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED= .THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FU= SED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) = if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * MEM_INST_RETIRED.ANY = / INST_RETIRED.ANY )", + "MetricGroup": "Pipeline;TmaL3;m_tma_light_operations_percent", + "MetricName": "tma_memory_operations_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring fused instructions -- where one uop can represent mu= ltiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC= are commonly used examples.", + "MetricExpr": "100 * ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 )= * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED= .THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FU= SED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) = if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * UOPS_RETIRED.MACRO_FU= SED / ( UOPS_RETIRED.RETIRE_SLOTS ) )", + "MetricGroup": "Pipeline;TmaL3;m_tma_light_operations_percent", + "MetricName": "tma_fused_instructions_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring branch instructions that were not fused. Non-conditi= onal branches like direct JMP or CALL would count here. Can be used to exam= ine fusible conditional jumps that were not fused.", + "MetricExpr": "100 * ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 )= * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED= .THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FU= SED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) = if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( BR_INST_RETIRED.ALL= _BRANCHES - UOPS_RETIRED.MACRO_FUSED ) / ( UOPS_RETIRED.RETIRE_SLOTS ) )", + "MetricGroup": "Pipeline;TmaL3;m_tma_light_operations_percent", + "MetricName": "tma_non_fused_branches_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring NOP (no op) instructions. Compilers often use NOPs f= or certain address alignments - e.g. start address of a function or loop bo= dy.", + "MetricExpr": "100 * ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 )= * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED= .THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FU= SED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) = if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * INST_RETIRED.NOP / ( = UOPS_RETIRED.RETIRE_SLOTS ) )", + "MetricGroup": "Pipeline;TmaL3;m_tma_light_operations_percent", + "MetricName": "tma_nop_instructions_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents the remaining light uo= ps fraction the CPU has executed - remaining means not covered by other sib= ling nodes. May undercount due to FMA double counting", + "MetricExpr": "100 * ( max( 0 , ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) = / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK= _UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED= .MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_A= NY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) - ( ( ( ( ( UO= PS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 )= if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * UOPS_EXECUTED.X87 / UO= PS_EXECUTED.THREAD ) + ( ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_I= NST_RETIRED.SCALAR_DOUBLE ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) + ( min( ( ( = FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKE= D_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED= .256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_I= NST_RETIRED.512B_PACKED_SINGLE ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1 ) = ) ) ) + ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTE= D.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( = ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY= ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_= CLK_UNHALTED.THREAD ) ) ) ) ) * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY ) += ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREA= D_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_= RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( = ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNH= ALTED.THREAD ) ) ) ) ) * UOPS_RETIRED.MACRO_FUSED / ( UOPS_RETIRED.RETIRE_S= LOTS ) ) + ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHA= LTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - (= ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.= ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( C= PU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( BR_INST_RETIRED.ALL_BRANCHES - UOPS_RE= TIRED.MACRO_FUSED ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) + ( ( ( ( UOPS_RETIRE= D.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_= on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS= ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_= UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )= ) * INST_RETIRED.NOP / ( UOPS_RETIRED.RETIRE_SLOTS ) ) ) ) )", + "MetricGroup": "Pipeline;TmaL3;m_tma_light_operations_percent", + "MetricName": "tma_other_light_ops_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring heavy-weight operations -- instructions that require= two or more uops or microcoded sequences. This highly-correlates with the = uop length of these instructions/sequences.", + "MetricExpr": "100 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETI= RED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREA= D_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricGroup": "Retire;TmaL2;m_tma_retiring_percent", + "MetricName": "tma_heavy_operations_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring instructions that that are decoder into two or up to= ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of= uops in such instructions.", + "MetricExpr": "100 * ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RE= TIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THR= EAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOP= S_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( = CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD= ) ) ) ) )", + "MetricGroup": "TmaL3;m_tma_heavy_operations_percent", + "MetricName": "tma_few_uops_instructions_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS= is used for CISC instructions not supported by the default decoders (like = repeat move strings; or CPUID); or by microcode assists used to address som= e operation modes (like in Floating Point assists). These cases can often b= e avoided.", + "MetricExpr": "100 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSU= ED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if= #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricGroup": "MicroSeq;TmaL3;m_tma_heavy_operations_percent", + "MetricName": "tma_microcode_sequencer_percent", + "ScaleUnit": "1%" } ] diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/floating-point.jso= n b/tools/perf/pmu-events/arch/x86/cascadelakex/floating-point.json index 41a3d13fc4b2..48bb1b38dde6 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/floating-point.json @@ -120,4 +120,4 @@ "SampleAfterValue": "100003", "UMask": "0x1e" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/frontend.json b/to= ols/perf/pmu-events/arch/x86/cascadelakex/frontend.json index ecce4273ae52..8633ee406813 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/frontend.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/frontend.json @@ -527,4 +527,4 @@ "SampleAfterValue": "2000003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/other.json b/tools= /perf/pmu-events/arch/x86/cascadelakex/other.json index 60d8a99813b9..6baa338e72f1 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/other.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/other.json @@ -39,6 +39,69 @@ "SampleAfterValue": "200003", "UMask": "0x40" }, + { + "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDFE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xEF", + "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDFE", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDM", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xEF", + "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDM", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITFSE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xEF", + "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITFSE", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITI", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xEF", + "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITI", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDFE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xEF", + "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDFE", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDM", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xEF", + "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDM", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SHITFSE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xEF", + "EventName": "CORE_SNOOP_RESPONSE.RSP_SHITFSE", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, { "BriefDescription": "Number of hardware interrupts received by the= processor.", "Counter": "0,1,2,3", diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/pipeline.json b/to= ols/perf/pmu-events/arch/x86/cascadelakex/pipeline.json index 79fda10ec4bb..f085b9145952 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/pipeline.json @@ -165,6 +165,17 @@ "SampleAfterValue": "400009", "UMask": "0x20" }, + { + "BriefDescription": "This event counts the number of mispredicted = ret instructions retired. Non PEBS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.RET", + "PEBS": "1", + "PublicDescription": "This is a non-precise version (that is, does= not use PEBS) of the event that counts mispredicted return instructions re= tired.", + "SampleAfterValue": "100007", + "UMask": "0x8" + }, { "BriefDescription": "Core crystal clock cycles when this thread is= unhalted and the other thread is halted.", "Counter": "0,1,2,3", diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json= b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json index a416515d41da..e82c6fa053a1 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json @@ -84,6 +84,15 @@ "UMask": "0x4", "Unit": "iMC" }, + { + "BriefDescription": "Pre-charge for writes", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_M_PRE_COUNT.WR", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, { "BriefDescription": "Write requests allocated in the PMM Write Pen= ding Queue for Intel Optane DC persistent memory", "Counter": "0,1,2,3", diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json = b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json index aa460d0c4851..f301385845a4 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json @@ -155,6 +155,15 @@ "UMask": "0x04", "Unit": "CHA" }, + { + "BriefDescription": "write requests from remote home agent", + "Counter": "0,1,2,3", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, { "BriefDescription": "UPI interconnect send bandwidth for payload. = Derived from unc_upi_txl_flits.all_data", "Counter": "0,1,2,3", @@ -620,6 +629,83 @@ "UMask": "0x10", "Unit": "CHA" }, + { + "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hi= t the LLC", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", + "Filter": "config1=3D0x40233", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRds issued by iA Cores that H= it the LLC : Counts the number of entries successfully inserted into the TO= R that match qualifications specified by the subevent. Does not include a= ddressless requests such as locks and interrupts.", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hi= t the LLC", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD", + "Filter": "config1=3D0x40433", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores that H= it the LLC : Counts the number of entries successfully inserted into the TO= R that match qualifications specified by the subevent. Does not include a= ddressless requests such as locks and interrupts.", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD", + "Filter": "config1=3D0x4b233", + "PerPkg": "1", + "PublicDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD", + "Filter": "config1=3D0x4b433", + "PerPkg": "1", + "PublicDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores t= hat hit the LLC", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefRFO", + "Filter": "config1=3D0x4b033", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores = that hit the LLC : Counts the number of entries successfully inserted into = the TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hi= t the LLC", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", + "Filter": "config1=3D0x40033", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that H= it the LLC : Counts the number of entries successfully inserted into the TO= R that match qualifications specified by the subevent. Does not include a= ddressless requests such as locks and interrupts.", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Mi= ssed the LLC", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", + "Filter": "config1=3D0x40233", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRds issued by iA Cores that M= issed the LLC : Counts the number of entries successfully inserted into the= TOR that match qualifications specified by the subevent. Does not includ= e addressless requests such as locks and interrupts.", + "UMask": "0x21", + "Unit": "CHA" + }, { "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Mi= ssed the LLC", "Counter": "0,1,2,3", @@ -631,6 +717,132 @@ "UMask": "0x21", "Unit": "CHA" }, + { + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD", + "Filter": "config1=3D0x4b233", + "PerPkg": "1", + "PublicDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD", + "Filter": "config1=3D0x4b433", + "PerPkg": "1", + "PublicDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores t= hat missed the LLC", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefRFO", + "Filter": "config1=3D0x4b033", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores = that missed the LLC : Counts the number of entries successfully inserted in= to the TOR that match qualifications specified by the subevent. Does not = include addressless requests such as locks and interrupts.", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Mi= ssed the LLC", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", + "Filter": "config1=3D0x40033", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that M= issed the LLC : Counts the number of entries successfully inserted into the= TOR that match qualifications specified by the subevent. Does not includ= e addressless requests such as locks and interrupts.", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.REM_ALL", + "Filter": "CHAfilter1", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. ", + "UMask": "0x30", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", + "Filter": "config1=3D0x40233", + "PerPkg": "1", + "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", + "Filter": "config1=3D0x40433", + "PerPkg": "1", + "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD", + "Filter": "config1=3D0x4b233", + "PerPkg": "1", + "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD", + "Filter": "config1=3D0x4b433", + "PerPkg": "1", + "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO", + "Filter": "config1=3D0x4b033", + "PerPkg": "1", + "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", + "Filter": "config1=3D0x40033", + "PerPkg": "1", + "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", + "Filter": "config1=3D0x40233", + "PerPkg": "1", + "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", + "UMask": "0x21", + "Unit": "CHA" + }, { "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that = Missed the LLC", "EventCode": "0x36", @@ -641,13 +853,359 @@ "UMask": "0x21", "Unit": "CHA" }, + { + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD", + "Filter": "config1=3D0x4b233", + "PerPkg": "1", + "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD", + "Filter": "config1=3D0x4b433", + "PerPkg": "1", + "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO", + "Filter": "config1=3D0x4b033", + "PerPkg": "1", + "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", + "Filter": "config1=3D0x40033", + "PerPkg": "1", + "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CLOCKTICKS", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventName": "UNC_C_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_CLOCKTICKS", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_FAST_ASSERTED.HORZ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xA5", + "EventName": "UNC_C_FAST_ASSERTED", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_FAST_ASSERTED.HORZ", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_E", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.E_STATE", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_LLC_VICTIMS.TOTAL_E", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_F", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.F_STATE", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_LLC_VICTIMS.TOTAL_F", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_M", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.M_STATE", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_LLC_VICTIMS.TOTAL_M", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_S", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.S_STATE", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_LLC_VICTIMS.TOTAL_S", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.REM_ALL", + "Filter": "CHAfilter1", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. ", + "UMask": "0x30", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.CORE_GTONE", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.CORE_GTONE", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_CORE_SNP.CORE_GTONE", + "UMask": "0x42", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.EVICT_GTONE", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.EVICT_GTONE", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_CORE_SNP.EVICT_GTONE", + "UMask": "0x82", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_DIR_LOOKUP.NO_SNP", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x53", + "EventName": "UNC_H_DIR_LOOKUP.NO_SNP", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_DIR_LOOKUP.NO_SNP", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_DIR_LOOKUP.SNP", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x53", + "EventName": "UNC_H_DIR_LOOKUP.SNP", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_DIR_LOOKUP.SNP", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_DIR_UPDATE.HA", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x54", + "EventName": "UNC_H_DIR_UPDATE.HA", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_DIR_UPDATE.HA", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_DIR_UPDATE.TOR", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x54", + "EventName": "UNC_H_DIR_UPDATE.TOR", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_DIR_UPDATE.TOR", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_HIT.EX_RDS", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5F", + "EventName": "UNC_H_HITME_HIT.EX_RDS", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_HITME_HIT.EX_RDS", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_MISC.RFO_HIT_S", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x39", + "EventName": "UNC_H_MISC.RFO_HIT_S", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_MISC.RFO_HIT_S", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_REQUESTS.INVITOE_LOCAL", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_REQUESTS.INVITOE_LOCAL", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_REQUESTS.INVITOE_REMOTE", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_REQUESTS.INVITOE_REMOTE", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_REQUESTS.READS", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.READS", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_REQUESTS.READS", + "UMask": "0x3", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_REQUESTS.READS_LOCAL", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.READS_LOCAL", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_REQUESTS.READS_LOCAL", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_REQUESTS.WRITES", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.WRITES", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_REQUESTS.WRITES", + "UMask": "0xC", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_REQUESTS.WRITES_LOCAL", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.WRITES_LOCAL", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_REQUESTS.WRITES_LOCAL", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_INSERTS.IRQ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x13", + "EventName": "UNC_H_RxC_INSERTS.IRQ", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_RxC_INSERTS.IRQ", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x19", + "EventName": "UNC_H_RxC_IRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OCCUPANCY.IRQ", + "Deprecated": "1", + "EventCode": "0x11", + "EventName": "UNC_H_RxC_OCCUPANCY.IRQ", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_RxC_OCCUPANCY.IRQ", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSPCNFLCTS", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_SNOOP_RESP.RSPCNFLCTS", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSPIFWD", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSPIFWD", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_SNOOP_RESP.RSPIFWD", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSPSFWD", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSPSFWD", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_SNOOP_RESP.RSPSFWD", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSP_FWD_WB", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_SNOOP_RESP.RSP_FWD_WB", + "UMask": "0x20", + "Unit": "CHA" + }, { "BriefDescription": "Clockticks of the IIO Traffic Controller", "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_IIO_CLOCKTICKS", "PerPkg": "1", - "PublicDescription": "Counts clockticks of the 1GHz trafiic contro= ller clock in the IIO unit.", + "PublicDescription": "Counts clockticks of the 1GHz traffic contro= ller clock in the IIO unit.", "Unit": "IIO" }, { @@ -1053,6 +1611,110 @@ "UMask": "0x02", "Unit": "IIO" }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "UMask": "0x1", + "Unit": "IIO" + }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by the CPU to IIO Part0", "Counter": "0,1,2,3", @@ -1898,6 +2560,17 @@ "UMask": "0x1", "Unit": "UPI LL" }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_DIRECT_ATTEMPTS.D2U", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x12", + "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_UPI_DIRECT_ATTEMPTS.D2U", + "UMask": "0x2", + "Unit": "UPI LL" + }, { "BriefDescription": "Data Response packets that go direct to Intel= UPI", "Counter": "0,1,2,3", @@ -1986,6 +2659,17 @@ "UMask": "0x97", "Unit": "UPI LL" }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_FLITS.ALL_NULL", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.NULL", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_UPI_RxL_FLITS.ALL_NULL", + "UMask": "0x20", + "Unit": "UPI LL" + }, { "BriefDescription": "Cycles in which the Tx of the Intel Ultra Pat= h Interconnect (UPI) is in L0p power mode", "Counter": "0,1,2,3", @@ -2043,5 +2727,16 @@ "PublicDescription": "Counts protocol header and credit FLITs (80 = bit FLow control unITs) transmitted across any of the 3 UPI (Ultra Path Int= erconnect) slots on this UPI unit.", "UMask": "0x97", "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_FLITS.ALL_NULL", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.NULL", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_UPI_TxL_FLITS.ALL_NULL", + "UMask": "0x20", + "Unit": "UPI LL" } ] diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/virtual-memory.jso= n b/tools/perf/pmu-events/arch/x86/cascadelakex/virtual-memory.json index 792ca39f013a..dd334b416c57 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/virtual-memory.json @@ -281,4 +281,4 @@ "SampleAfterValue": "100007", "UMask": "0x20" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index dbd6bcbbca8b..dcaa68b09717 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -4,6 +4,7 @@ GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core GenuineIntel-6-(3D|47),v26,broadwell,core GenuineIntel-6-56,v23,broadwellde,core GenuineIntel-6-4F,v19,broadwellx,core +GenuineIntel-6-55-[56789ABCDEF],v1.16,cascadelakex,core GenuineIntel-6-5C,v8,goldmont,core GenuineIntel-6-7A,v1,goldmontplus,core GenuineIntel-6-3C,v24,haswell,core @@ -29,7 +30,6 @@ GenuineIntel-6-2C,v2,westmereep-dp,core GenuineIntel-6-25,v2,westmereep-sp,core GenuineIntel-6-2F,v2,westmereex,core GenuineIntel-6-55-[01234],v1,skylakex,core -GenuineIntel-6-55-[56789ABCDEF],v1,cascadelakex,core GenuineIntel-6-7D,v1,icelake,core GenuineIntel-6-7E,v1,icelake,core GenuineIntel-6-8[CD],v1,tigerlake,core --=20 2.37.1.359.gd136c6c3e2-goog From nobody Wed Apr 15 05:45:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D6DDC19F29 for ; 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Wed, 27 Jul 2022 15:09:02 -0700 (PDT) Date: Wed, 27 Jul 2022 15:08:09 -0700 In-Reply-To: <20220727220832.2865794-1-irogers@google.com> Message-Id: <20220727220832.2865794-8-irogers@google.com> Mime-Version: 1.0 References: <20220727220832.2865794-1-irogers@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH v3 07/30] perf vendor events: Update Intel elkhartlake From: Ian Rogers To: perry.taylor@intel.com, caleb.biggers@intel.com, kshipra.bopardikar@intel.com, Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Sedat Dilek Cc: Stephane Eranian , Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Update to v1.03. Elkhartlake metrics aren't in TMA but basic metrics are left unchanged. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/downloa= d_and_gen.py to download and generate the latest events and metrics. Manually copy the elkhartlake files into perf and update mapfile.csv. Tested on a non-elkhartlake with 'perf test': 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok Signed-off-by: Ian Rogers --- .../arch/x86/elkhartlake/cache.json | 956 +++++++++++++++++- .../arch/x86/elkhartlake/floating-point.json | 19 +- .../arch/x86/elkhartlake/frontend.json | 34 +- .../arch/x86/elkhartlake/memory.json | 388 ++++++- .../arch/x86/elkhartlake/other.json | 527 +++++++++- .../arch/x86/elkhartlake/pipeline.json | 203 +++- .../arch/x86/elkhartlake/virtual-memory.json | 151 ++- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 8 files changed, 2150 insertions(+), 130 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/cache.json b/tools/= perf/pmu-events/arch/x86/elkhartlake/cache.json index 734be4ea095f..d674ee88c3a5 100644 --- a/tools/perf/pmu-events/arch/x86/elkhartlake/cache.json +++ b/tools/perf/pmu-events/arch/x86/elkhartlake/cache.json @@ -1,25 +1,94 @@ [ { - "BriefDescription": "Counts the number of first level data cacheli= ne (dirty) evictions caused by misses, stores, and prefetches.", + "BriefDescription": "Counts the number of core requests (demand an= d L1 prefetchers) rejected by the L2 queue (L2Q) due to a full condition.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x31", + "EventName": "CORE_REJECT_L2Q.ANY", + "PDIR_COUNTER": "NA", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of (demand and L1 prefetch= ers) core requests rejected by the L2 queue (L2Q) due to a full or nearly f= ull condition, which likely indicates back pressure from L2Q. It also coun= ts requests that would have gone directly to the External Queue (XQ), but a= re rejected due to a full or nearly full condition, indicating back pressur= e from the IDI link. The L2Q may also reject transactions from a core to = ensure fairness between cores, or to delay a cores dirty eviction when the = address conflicts incoming external snoops. (Note that L2 prefetcher reque= sts that are dropped are not counted by this event). Counts on a per core = basis.", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Counts the number of L1D cacheline (dirty) ev= ictions caused by load misses, stores, and prefetches.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "DL1.DIRTY_EVICTION", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of L1D cacheline (dirty) e= victions caused by load misses, stores, and prefetches. Does not count evi= ctions or dirty writebacks caused by snoops. Does not count a replacement = unless a (dirty) line was written back.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of demand and prefetch tran= sactions that the External Queue (XQ) rejects due to a full or near full co= ndition.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x30", + "EventName": "L2_REJECT_XQ.ANY", + "PDIR_COUNTER": "NA", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of demand and prefetch tra= nsactions that the External Queue (XQ) rejects due to a full or near full c= ondition which likely indicates back pressure from the IDI link. The XQ ma= y reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses= ) and WOB (L2 write-back victims).", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Counts the total number of L2 Cache accesses.= Counts on a per core basis.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_REQUEST.ALL", + "PDIR_COUNTER": "NA", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the total number of L2 Cache Accesses= , includes hits, misses, rejects front door requests for CRd/DRd/RFO/ItoM/= L2 Prefetches only. Counts on a per core basis.", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Counts the number of L2 Cache accesses that r= esulted in a hit. Counts on a per core basis.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_REQUEST.HIT", + "PDIR_COUNTER": "NA", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of L2 Cache accesses that = resulted in a hit from a front door request only (does not include rejects = or recycles), Counts on a per core basis.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of L2 Cache accesses that r= esulted in a miss. Counts on a per core basis.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_REQUEST.MISS", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of first level data cachel= ine (dirty) evictions caused by misses, stores, and prefetches. Does not c= ount evictions or dirty writebacks caused by snoops. Does not count a repl= acement unless a (dirty) line was written back.", + "PublicDescription": "Counts the number of L2 Cache accesses that = resulted in a miss from a front door request only (does not include rejects= or recycles). Counts on a per core basis.", "SampleAfterValue": "200003", "UMask": "0x1" }, + { + "BriefDescription": "Counts the number of L2 Cache accesses that m= iss the L2 and get rejected. Counts on a per core basis.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_REQUEST.REJECTS", + "PDIR_COUNTER": "NA", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of L2 Cache accesses that = miss the L2 and get BBL reject short and long rejects (includes those coun= ted in L2_reject_XQ.any). Counts on a per core basis.", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, { "BriefDescription": "Counts the number of cacheable memory request= s that miss in the LLC. Counts on a per core basis.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.MISS", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of cacheable memory reques= ts that miss in the Last Level Cache (LLC). If the platform has an L3 cache= , the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per co= re basis.", + "PublicDescription": "Counts the number of cacheable memory reques= ts that miss in the Last Level Cache (LLC). Requests include demand loads, = reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the= platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 = cache. Counts on a per core basis.", "SampleAfterValue": "200003", "UMask": "0x41" }, @@ -29,21 +98,31 @@ "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.REFERENCE", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of cacheable memory reques= ts that access the Last Level Cache (LLC). Requests include demand loads, r= eads for ownership (RFO), instruction fetches and L1 HW prefetches. If the = platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 c= ache. Counts on a per core basis.", "SampleAfterValue": "200003", "UMask": "0x4f" }, + { + "BriefDescription": "Counts the number of cycles the core is stall= ed due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM o= r MMIO (Non-DRAM).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.IFETCH", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x38" + }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-D= RAM).", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of cycles a core is stalle= d due to an instruction cache or translation lookaside buffer (TLB) access = which hit in DRAM or MMIO (non-DRAM).", + "PublicDescription": "Counts the number of cycles the core is stal= led due to an instruction cache or translation lookaside buffer (TLB) miss = which hit in DRAM or MMIO (non-DRAM).", "SampleAfterValue": "200003", "UMask": "0x20" }, @@ -53,9 +132,9 @@ "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of cycles a core is stalle= d due to an instruction cache or Translation Lookaside Buffer (TLB) access = which hit in the L2 cache.", + "PublicDescription": "Counts the number of cycles the core is stal= led due to an instruction cache or Translation Lookaside Buffer (TLB) miss = which hit in the L2 cache.", "SampleAfterValue": "200003", "UMask": "0x8" }, @@ -65,19 +144,29 @@ "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of cycles a core is stalle= d due to an instruction cache or Translation Lookaside Buffer (TLB) access = which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", + "PublicDescription": "Counts the number of cycles the core is stal= led due to an instruction cache or Translation Lookaside Buffer (TLB) miss = which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", "SampleAfterValue": "200003", "UMask": "0x10" }, + { + "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DR= AM).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.LOAD", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x7" + }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.LOAD_DRAM_HIT", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x4" @@ -88,9 +177,8 @@ "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of cycles a core is stalle= d due to a demand load which hit in the L2 cache.", "SampleAfterValue": "200003", "UMask": "0x1" }, @@ -100,33 +188,47 @@ "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of cycles a core is stalle= d due to a demand load which hit in the Last Level Cache (LLC) or other cor= e with HITE/F/M.", + "PublicDescription": "Counts the number of cycles the core is stal= led due to a demand load which hit in the Last Level Cache (LLC) or other c= ore with HITE/F/M.", "SampleAfterValue": "200003", "UMask": "0x2" }, { - "BriefDescription": "Counts the number of cycles a core is stalled= due to a store buffer being full.", + "BriefDescription": "Counts the number of cycles the core is stall= ed due to a store buffer being full.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.STORE_BUFFER_FULL", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x40" }, { - "BriefDescription": "Counts the number of load ops retired that hi= t in DRAM.", + "BriefDescription": "Counts the number of load uops retired that h= it in DRAM.", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", + "PEBS": "1", "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x80" }, + { + "BriefDescription": "Counts the number of load uops retired that h= it in the L3 cache, in which a snoop was required and modified data was for= warded from another core or module.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_UOPS_RETIRED.HITM", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x20" + }, { "BriefDescription": "Counts the number of load uops retired that h= it in the L1 data cache.", "CollectPEBSRecord": "2", @@ -179,6 +281,7 @@ "BriefDescription": "Counts the number of load uops retired that h= it in the L3 cache.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", + "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", "PEBS": "1", @@ -186,6 +289,19 @@ "SampleAfterValue": "200003", "UMask": "0x4" }, + { + "BriefDescription": "Counts the number of memory uops retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.ALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of memory uops retired. A= single uop that performs both a load AND a store will be counted as 1, not= 2 (e.g. ADD [mem], CONST)", + "SampleAfterValue": "200003", + "UMask": "0x83" + }, { "BriefDescription": "Counts the number of load uops retired.", "CollectPEBSRecord": "2", @@ -212,15 +328,811 @@ "SampleAfterValue": "200003", "UMask": "0x82" }, + { + "BriefDescription": "Counts the number of load uops retired that p= erformed one or more locks.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x21" + }, + { + "BriefDescription": "Counts the number of memory uops retired that= were splits.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.SPLIT", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x43" + }, + { + "BriefDescription": "Counts the number of retired split load uops.= ", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x41" + }, + { + "BriefDescription": "Counts the number of retired split store uops= .", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x42" + }, + { + "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0044", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache where a snoop was sent, the snoop hit, and modified data was fo= rwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0044", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache where a snoop was sent, the snoop hit, but no data was forwarde= d.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0044", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache where a snoop was sent, the snoop hit, and non-modified data wa= s forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0044", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0044", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache where no snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0044", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.COREWB_M.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3001F803C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache where a snoop w= as sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache where no snoop = was needed to satisfy the request.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache where a snoop was sent, the snoop hit, and modi= fied data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache where a snoop was sent, the snoop hit, but no d= ata was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache where a snoop was sent, the snoop hit, and non-= modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FW= D", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache where no snoop was needed to satisfy the reques= t.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, and modified data was= forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, but no data was forwa= rded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, and non-modified data= was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where no snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores which modify a full 6= 4 byte cacheline that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.FULL_STREAMING_WR.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x801F803C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetches and = software prefetches (except PREFETCHW and PFRFO) that were supplied by the = L3 cache where a snoop was sent, the snoop hit, and modified data was forwa= rded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0400", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache where no = snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache where no = snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache where a snoop w= as sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache where no snoop = was needed to satisfy the request.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writebacks from L1 cache that= miss the L2 cache that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.L1WB_M.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1001F803C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writeBacks from L2 cache that= miss the L3 cache that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.L2WB_M.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2001F803C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores which modify only par= t of a 64 byte cacheline that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.PARTIAL_STREAMING_WR.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x401F803C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0477", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache where a snoop was sent, the snoop hit, and modif= ied data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0477", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache where a snoop was sent, the snoop hit, but no da= ta was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0477", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache where a snoop was sent, the snoop hit, and non-m= odified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0477", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0477", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache where no snoop was needed to satisfy the request= .", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0477", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores that were supplied by= the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.STREAMING_WR.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0800", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x101F803C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache where a snoop was sent, the snoop hit, and modified data= was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1010003C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache where a snoop was sent, the snoop hit, but no data was f= orwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1004003C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache where a snoop was sent, the snoop hit, and non-modified = data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1008003C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1002003C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache where no snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1001003C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory writes that were suppl= ied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_WR.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x201F803C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to instruction cache misses.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ICACHE", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x20" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/floating-point.json= b/tools/perf/pmu-events/arch/x86/elkhartlake/floating-point.json index 2515b9aa6e66..2e1b80c714fd 100644 --- a/tools/perf/pmu-events/arch/x86/elkhartlake/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/elkhartlake/floating-point.json @@ -1,15 +1,28 @@ [ { - "BriefDescription": "Counts the number of cycles the floating poin= t divider is busy. Does not imply a stall waiting for the divider.", + "BriefDescription": "Counts the number of cycles the floating poin= t divider is busy.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xcd", "EventName": "CYCLES_DIV_BUSY.FPDIV", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of cycles the floating poi= nt divider is busy. Does not imply a stall waiting for the divider.", "SampleAfterValue": "200003", "UMask": "0x2" }, + { + "BriefDescription": "Counts the number of floating point operation= s retired that required microcode assist.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.FP_ASSIST", + "PDIR_COUNTER": "NA", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of floating point operatio= ns retired that required microcode assist, which is not a reflection of the= number of FP operations, instructions or uops.", + "SampleAfterValue": "20003", + "UMask": "0x4" + }, { "BriefDescription": "Counts the number of floating point divide uo= ps retired (x87 and SSE, including x87 sqrt).", "CollectPEBSRecord": "2", @@ -21,4 +34,4 @@ "SampleAfterValue": "2000003", "UMask": "0x8" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/frontend.json b/too= ls/perf/pmu-events/arch/x86/elkhartlake/frontend.json index b7b8cb7bd868..5d938a5dafcf 100644 --- a/tools/perf/pmu-events/arch/x86/elkhartlake/frontend.json +++ b/tools/perf/pmu-events/arch/x86/elkhartlake/frontend.json @@ -1,11 +1,11 @@ [ { - "BriefDescription": "Counts the total number of BACLEARS.", + "BriefDescription": "Counts the total number of BACLEARS due to al= l branch types including conditional and unconditional jumps, returns, and = indirect branches.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.ANY", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the total number of BACLEARS, which o= ccur when the Branch Target Buffer (BTB) prediction or lack thereof, was co= rrected by a later branch predictor in the frontend. Includes BACLEARS due= to all branch types including conditional and unconditional jumps, returns= , and indirect branches.", "SampleAfterValue": "200003", @@ -17,7 +17,7 @@ "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.COND", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x10" @@ -28,7 +28,7 @@ "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.INDIRECT", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x2" @@ -39,18 +39,18 @@ "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.RETURN", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x8" }, { - "BriefDescription": "Counts the number of BACLEARS due to a non-in= direct, non-conditional jump.", + "BriefDescription": "Counts the number of BACLEARS due to a direct= , unconditional jump.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.UNCOND", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x4" @@ -61,7 +61,7 @@ "Counter": "0,1,2,3", "EventCode": "0xe9", "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x1" @@ -72,22 +72,34 @@ "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.ACCESSES", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the total number of requests to the i= nstruction cache. The event only counts new cache line accesses, so that m= ultiple back to back fetches to the exact same cache line or byte chunk cou= nt as one. Specifically, the event counts when accesses from sequential co= de crosses the cache line boundary, or when a branch target is moved to a n= ew line or to a non-sequential byte chunk of the same line.", "SampleAfterValue": "200003", "UMask": "0x3" }, + { + "BriefDescription": "Counts the number of instruction cache hits.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "ICACHE.HIT", + "PDIR_COUNTER": "NA", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of requests that hit in th= e instruction cache. The event only counts new cache line accesses, so tha= t multiple back to back fetches to the exact same cache line and byte chunk= count as one. Specifically, the event counts when accesses from sequentia= l code crosses the cache line boundary, or when a branch target is moved to= a new line or to a non-sequential byte chunk of the same line.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, { "BriefDescription": "Counts the number of instruction cache misses= .", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.MISSES", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of missed requests to the = instruction cache. The event only counts new cache line accesses, so that = multiple back to back fetches to the exact same cache line and byte chunk c= ount as one. Specifically, the event counts when accesses from sequential = code crosses the cache line boundary, or when a branch target is moved to a= new line or to a non-sequential byte chunk of the same line.", "SampleAfterValue": "200003", "UMask": "0x2" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/memory.json b/tools= /perf/pmu-events/arch/x86/elkhartlake/memory.json index 4e4eab23a300..15eba23796e4 100644 --- a/tools/perf/pmu-events/arch/x86/elkhartlake/memory.json +++ b/tools/perf/pmu-events/arch/x86/elkhartlake/memory.json @@ -1,25 +1,111 @@ [ { - "BriefDescription": "Counts the number of memory ordering machine = clears triggered by a snoop from an external agent.", + "BriefDescription": "Counts the number of machine clears due to me= mory ordering caused by a snoop from an external agent. Does not count inte= rnally generated machine clears such as those due to memory disambiguation.= ", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of memory ordering machine= clears triggered by a snoop from an external agent. Does not count interna= lly generated machine clears such as those due to disambiguations.", "SampleAfterValue": "20003", "UMask": "0x2" }, + { + "BriefDescription": "Counts the number of misaligned load uops tha= t are 4K page splits.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of misaligned store uops th= at are 4K page splits.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts all code reads that were not supplied = by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000044", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that were not supplied = by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000044", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.COREWB_M.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3002184000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.COREWB_M.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3002184000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re not supplied by the L3 cache.", "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2104000001", + "MSRValue": "0x2184000001", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -29,9 +115,8 @@ "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2104000001", + "MSRValue": "0x2184000001", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -41,9 +126,8 @@ "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2104000001", + "MSRValue": "0x2184000001", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -53,9 +137,8 @@ "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2104000001", + "MSRValue": "0x2184000001", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -65,9 +148,8 @@ "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2104000002", + "MSRValue": "0x2184000002", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -77,10 +159,284 @@ "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2104000002", + "MSRValue": "0x2184000002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores which modify a full 6= 4 byte cacheline that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.FULL_STREAMING_WR.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x802184000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores which modify a full 6= 4 byte cacheline that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.FULL_STREAMING_WR.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x802184000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writebacks from L1 cache that= miss the L2 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.L1WB_M.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1002184000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writebacks from L1 cache that= miss the L2 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.L1WB_M.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1002184000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writeBacks from L2 cache that= miss the L3 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.L2WB_M.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2002184000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writeBacks from L2 cache that= miss the L3 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.L2WB_M.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2002184000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts miscellaneous requests, such as I/O ac= cesses, that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.OTHER.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184008000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts miscellaneous requests, such as I/O ac= cesses, that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.OTHER.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184008000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores which modify only par= t of a 64 byte cacheline that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x402184000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores which modify only par= t of a 64 byte cacheline that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x402184000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all hardware and software prefetches t= hat were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.PREFETCHES.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000470", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000477", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000477", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores that were not supplie= d by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.STREAMING_WR.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000800", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores that were not supplie= d by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000800", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were not su= pplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x102184000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were not su= pplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x102184000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory writes that were not s= upplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_WR.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x202184000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory writes that were not s= upplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_WR.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x202184000000", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/other.json b/tools/= perf/pmu-events/arch/x86/elkhartlake/other.json index 8692d4847476..4a1b7cc5aa23 100644 --- a/tools/perf/pmu-events/arch/x86/elkhartlake/other.json +++ b/tools/perf/pmu-events/arch/x86/elkhartlake/other.json @@ -6,7 +6,7 @@ "EdgeDetect": "1", "EventCode": "0x63", "EventName": "BUS_LOCK.ALL", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003" }, @@ -27,7 +27,7 @@ "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "BUS_LOCK.CYCLES_OTHER_BLOCK", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x2" @@ -38,7 +38,7 @@ "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "BUS_LOCK.CYCLES_SELF_BLOCK", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x1" @@ -71,7 +71,7 @@ "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "C0_STALLS.LOAD_DRAM_HIT", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x4" @@ -82,7 +82,7 @@ "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "C0_STALLS.LOAD_L2_HIT", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x1" @@ -93,7 +93,7 @@ "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "C0_STALLS.LOAD_LLC_HIT", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x2" @@ -104,7 +104,7 @@ "Counter": "0,1,2,3", "EventCode": "0xcb", "EventName": "HW_INTERRUPTS.MASKED", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of core cycles during whic= h interrupts are masked (disabled). Increments by 1 each core cycle that EF= LAGS.IF is 0, regardless of whether interrupts are pending or not.", "SampleAfterValue": "200003", @@ -116,7 +116,7 @@ "Counter": "0,1,2,3", "EventCode": "0xcb", "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of core cycles during whic= h there are pending interrupts while interrupts are masked (disabled). Incr= ements by 1 each core cycle that both EFLAGS.IF is 0 and an INTR is pending= (which means the APIC is telling the ROB to cause an INTR). This event doe= s not increment if EFLAGS.IF is 0 but all interrupt in the APICs Interrupt = Request Register (IRR) are inhibited by the PPR (thus either by ISRV or TPR= ) because in these cases the interrupts would be held up in the APIC and w= ould not be pended to the ROB. This event does count when an interrupt is o= nly inhibited by MOV/POP SS state machines or the STI state machine. These = extra inhibits only last for a single instructions and would not be importa= nt.", "SampleAfterValue": "200003", @@ -128,11 +128,110 @@ "Counter": "0,1,2,3", "EventCode": "0xcb", "EventName": "HW_INTERRUPTS.RECEIVED", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "203", "UMask": "0x1" }, + { + "BriefDescription": "Counts all code reads that have any type of r= esponse.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10044", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that were supplied by D= RAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000044", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that were supplied by D= RAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000044", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that have an outstandin= g request. Returns the number of cycles until the response is received (i.e= . XQ to XQ latency).", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000000000000044", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.COREWB_M.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3000000010000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that have an outstanding request. Returns the number of cycles unt= il the response is received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.COREWB_M.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8003000000000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that ha= ve any type of response.", "Counter": "0,1,2,3", @@ -141,7 +240,39 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10001", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that ha= ve an outstanding request. Returns the number of cycles until the response = is received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000000000000001", + "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -153,7 +284,39 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10001", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.DRAM", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000000000000001", + "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -165,7 +328,347 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10002", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that have an outstan= ding request. Returns the number of cycles until the response is received (= i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000000000000002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores which modify a full 6= 4 byte cacheline that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.FULL_STREAMING_WR.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800000010000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetches and = software prefetches (except PREFETCHW and PFRFO) that have any type of resp= onse.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10400", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that have an outstanding request. Returns th= e number of cycles until the response is received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000000000000040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that have an outstanding request. Returns the numb= er of cycles until the response is received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000000000000020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writebacks from L1 cache that= miss the L2 cache that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.L1WB_M.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000000010000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writeBacks from L2 cache that= miss the L3 cache that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.L2WB_M.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000000010000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts miscellaneous requests, such as I/O ac= cesses, that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.OTHER.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x18000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores which modify only par= t of a 64 byte cacheline that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.PARTIAL_STREAMING_WR.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400000010000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all hardware and software prefetches t= hat have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.PREFETCHES.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10470", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that hav= e any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10477", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000477", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000477", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that hav= e an outstanding request. Returns the number of cycles until the response i= s received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000000000000477", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores that have any type of= response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10800", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that have any ty= pe of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100000010000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were suppli= ed by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100184000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were suppli= ed by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100184000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that have an out= standing request. Returns the number of cycles until the response is receiv= ed (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000100000000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory writes that have any t= ype of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_WR.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200000010000", + "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" } diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json b/too= ls/perf/pmu-events/arch/x86/elkhartlake/pipeline.json index c18acb422145..09919fdb9a38 100644 --- a/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json @@ -131,6 +131,17 @@ "SampleAfterValue": "200003", "UMask": "0x7e" }, + { + "BriefDescription": "Counts the number of mispredicted near indire= ct JMP and near indirect CALL branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xeb" + }, { "BriefDescription": "Counts the number of mispredicted near RET br= anch instructions retired.", "CollectPEBSRecord": "2", @@ -159,7 +170,7 @@ "Counter": "0,1,2,3", "EventCode": "0xe8", "EventName": "BTCLEAR.ANY", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the total number of BTCLEARS which oc= curs when the Branch Target Buffer (BTB) predicts a taken branch.", "SampleAfterValue": "200003" @@ -169,9 +180,9 @@ "CollectPEBSRecord": "2", "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.CORE", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "33", - "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runn= ing the HLT instruction. The core frequency may change from time to time. F= or this reason this event may have a changing ratio with regards to time. T= his event uses fixed counter 1.", + "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runni= ng the HLT instruction. The core frequency may change from time to time. Fo= r this reason this event may have a changing ratio with regards to time. Th= is event uses fixed counter 1.", "SampleAfterValue": "2000003", "UMask": "0x2" }, @@ -181,9 +192,9 @@ "Counter": "0,1,2,3", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.CORE_P", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runn= ing the HLT instruction. The core frequency may change from time to time. F= or this reason this event may have a changing ratio with regards to time. T= his event uses a programmable general purpose performance counter.", + "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runni= ng the HLT instruction. The core frequency may change from time to time. Fo= r this reason this event may have a changing ratio with regards to time. Th= is event uses a programmable general purpose performance counter.", "SampleAfterValue": "2000003" }, { @@ -192,7 +203,7 @@ "Counter": "0,1,2,3", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. This event is not affected by core frequency ch= anges and increments at a fixed frequency that is also used for the Time St= amp Counter (TSC). This event uses fixed counter 2.", "SampleAfterValue": "2000003", @@ -203,7 +214,7 @@ "CollectPEBSRecord": "2", "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "34", "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. This event is not affected by core frequency ch= anges and increments at a fixed frequency that is also used for the Time St= amp Counter (TSC). This event uses fixed counter 2.", "SampleAfterValue": "2000003", @@ -216,7 +227,7 @@ "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. This event is not affected by core frequency c= hanges and increments at a fixed frequency that is also used for the Time S= tamp Counter (TSC). This event uses a programmable general purpose performa= nce counter.", + "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. This event is not affected by core frequency ch= anges and increments at a fixed frequency that is also used for the Time St= amp Counter (TSC). This event uses a programmable general purpose performan= ce counter.", "SampleAfterValue": "2000003", "UMask": "0x1" }, @@ -226,18 +237,19 @@ "Counter": "0,1,2,3", "EventCode": "0xcd", "EventName": "CYCLES_DIV_BUSY.ANY", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "2000003" }, { - "BriefDescription": "Counts the number of cycles the integer divid= er is busy. Does not imply a stall waiting for the divider.", + "BriefDescription": "Counts the number of cycles the integer divid= er is busy.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xcd", "EventName": "CYCLES_DIV_BUSY.IDIV", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of cycles the integer divi= der is busy. Does not imply a stall waiting for the divider.", "SampleAfterValue": "200003", "UMask": "0x1" }, @@ -264,29 +276,107 @@ "SampleAfterValue": "2000003" }, { - "BriefDescription": "Counts the total number of machine clears inc= luding memory ordering, memory disambiguation, self-modifying code, page fa= ults and floating point assist.", + "BriefDescription": "Counts the number of retired loads that are b= locked because it initially appears to be store forward blocked, but subseq= uently is shown not to be blocked based on 4K alias check.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.4K_ALIAS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of retired loads that are b= locked for any of the following reasons: DTLB miss, address alias, store f= orward or data unknown (includes memory disambiguation blocks and ESP consu= ming load blocks).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.ALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts the number of retired loads that are b= locked because its address exactly matches an older store whose data is not= ready.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.DATA_UNKNOWN", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of retired loads that are b= locked because its address partially overlapped with an older store.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the total number of machine clears for= any reason including, but not limited to, memory ordering, memory disambig= uation, SMC, and FP assist.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.ANY", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "20003" }, + { + "BriefDescription": "Counts the number of machine clears due to me= mory ordering in which an internal load passes an older store within the sa= me CPU.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.DISAMBIGUATION", + "PDIR_COUNTER": "NA", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of machine clears due to a = page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A p= age fault occurs when either the page is not present, or an access violatio= n occurs.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.PAGE_FAULT", + "PDIR_COUNTER": "NA", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20003", + "UMask": "0x20" + }, + { + "BriefDescription": "Counts the number of machine clears due to pr= ogram modifying data (self modifying code) within 1K of a recently fetched = code page.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.SMC", + "PDIR_COUNTER": "NA", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20003", + "UMask": "0x1" + }, { "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend because allocation is stalled due to a misp= redicted jump or a machine clear.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.ALL", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the total number of issue slots that = were not consumed by the backend because allocation is stalled due to a mis= predicted jump or a machine clear. Only issue slots wasted due to fast nuke= s such as memory ordering nukes are counted. Other nukes are not accounted = for. Counts all issue slots blocked during this recovery window including r= elevant microcode flows and while uops are not yet available in the instruc= tion queue (IQ). Also includes the issue slots that were consumed by the ba= ckend but were thrown away because they were younger than the mispredict or= machine clear.", + "PublicDescription": "Counts the total number of issue slots that = were not consumed by the backend because allocation is stalled due to a mis= predicted jump or a machine clear. Only issue slots wasted due to fast nuke= s such as memory ordering nukes are counted. Other nukes are not accounted = for. Counts all issue slots blocked during this recovery window including r= elevant microcode flows and while uops are not yet available in the instruc= tion queue (IQ) even if an FE_bound event occurs during this period. Also i= ncludes the issue slots that were consumed by the backend but were thrown a= way because they were younger than the mispredict or machine clear.", "SampleAfterValue": "1000003", "UMask": "0x6" }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to fast nukes such as memory orde= ring and memory disambiguation machine clears.", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE", @@ -297,6 +387,7 @@ }, { "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend because allocation is stalled due to a mach= ine clear (nuke) of any kind including memory ordering and memory disambigu= ation.", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", @@ -311,7 +402,7 @@ "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x4" @@ -322,7 +413,7 @@ "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.MONUKE", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x2" @@ -333,7 +424,7 @@ "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.ALL", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003" }, @@ -343,7 +434,7 @@ "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x1" @@ -354,7 +445,7 @@ "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x2" @@ -365,7 +456,7 @@ "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x8" @@ -376,7 +467,7 @@ "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.REGISTER", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x20" @@ -387,7 +478,7 @@ "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x40" @@ -398,7 +489,7 @@ "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x10" @@ -409,18 +500,18 @@ "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.STORE_BUFFER", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x4" }, { - "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to frontend stalls.", + "BriefDescription": "Counts the total number of issue slots every = cycle that were not consumed by the backend due to frontend stalls.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ALL", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003" }, @@ -430,7 +521,7 @@ "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of issue slots every cycle= that were not delivered by the frontend due to BACLEARS, which occurs when= the Branch Target Buffer (BTB) prediction or lack thereof, was corrected b= y a later branch predictor in the frontend. Includes BACLEARS due to all br= anch types including conditional and unconditional jumps, returns, and indi= rect branches.", "SampleAfterValue": "1000003", @@ -442,7 +533,7 @@ "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of issue slots every cycle= that were not delivered by the frontend due to BTCLEARS, which occurs when= the Branch Target Buffer (BTB) predicts a taken branch.", "SampleAfterValue": "1000003", @@ -454,7 +545,7 @@ "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.CISC", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x1" @@ -465,7 +556,7 @@ "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.DECODE", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x8" @@ -476,7 +567,7 @@ "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ITLB", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of issue slots every cycle= that were not delivered by the frontend due to Instruction Table Lookaside= Buffer (ITLB) misses.", "SampleAfterValue": "1000003", @@ -488,7 +579,7 @@ "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.OTHER", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x80" @@ -499,7 +590,7 @@ "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.PREDECODE", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x4" @@ -514,17 +605,59 @@ "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003" }, + { + "BriefDescription": "Counts the number of uops issued by the front= end every cycle.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x0e", + "EventName": "UOPS_ISSUED.ANY", + "PDIR_COUNTER": "NA", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of uops issued by the fron= t end every cycle. When 4-uops are requested and only 2-uops are delivered,= the event counts 2. Uops_issued correlates to the number of ROB entries. = If uop takes 2 ROB slots it counts as 2 uops_issued.", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Counts the total number of uops retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.ALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Counts the number of integer divide uops reti= red.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.IDIV", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, { "BriefDescription": "Counts the number of uops that are from compl= ex flows issued by the micro-sequencer (MS).", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.MS", - "PDIR_COUNTER": "na", "PEBS": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of uops that are from comp= lex flows issued by the Microcode Sequencer (MS). This includes uops from f= lows due to complex instructions, faults, assists, and inserted flows.", "SampleAfterValue": "2000003", "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of x87 uops retired, includ= es those in MS flows.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.X87", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "UMask": "0x2" } ] diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/virtual-memory.json= b/tools/perf/pmu-events/arch/x86/elkhartlake/virtual-memory.json index c58b589ff80f..b82f11591f13 100644 --- a/tools/perf/pmu-events/arch/x86/elkhartlake/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/elkhartlake/virtual-memory.json @@ -5,18 +5,18 @@ "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x80" }, { - "BriefDescription": "Counts the number of first level TLB misses b= ut second level hits due to loads that did not start a page walk. Account f= or all pages sizes. Will result in a DTLB write from STLB.", + "BriefDescription": "Counts the number of first level TLB misses b= ut second level hits due to a demand load that did not start a page walk. A= ccount for all page sizes. Will result in a DTLB write from STLB.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x20" @@ -32,13 +32,25 @@ "SampleAfterValue": "200003", "UMask": "0xe" }, + { + "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses to a 1G page.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "PDIR_COUNTER": "NA", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks completed du= e to loads (including SW prefetches) whose address translations missed in a= ll Translation Lookaside Buffer (TLB) levels and were mapped to 1GB pages. = Includes page walks that page fault.", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, { "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses to a 2M or 4M page.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of page walks completed du= e to loads (including SW prefetches) whose address translations missed in a= ll Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pa= ges. Includes page walks that page fault.", "SampleAfterValue": "200003", @@ -50,21 +62,21 @@ "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of page walks completed du= e to loads (including SW prefetches) whose address translations missed in a= ll Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. I= ncludes page walks that page fault.", "SampleAfterValue": "200003", "UMask": "0x2" }, { - "BriefDescription": "Counts the number of page walks outstanding i= n the page miss handler (PMH) for loads every cycle.", + "BriefDescription": "Counts the number of page walks outstanding i= n the page miss handler (PMH) for demand loads every cycle.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of page walks outstanding = in the page miss handler (PMH) for loads every cycle. A page walk is outst= anding from start till PMH becomes idle again (ready to serve next walk). I= ncludes EPT-walk intervals.", + "PublicDescription": "Counts the number of page walks outstanding = in the page miss handler (PMH) for demand loads every cycle. A page walk i= s outstanding from start till PMH becomes idle again (ready to serve next w= alk). Includes EPT-walk intervals.", "SampleAfterValue": "200003", "UMask": "0x10" }, @@ -74,19 +86,52 @@ "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of page walks due to stors= e that miss the PDE (Page Directory Entry) cache.", "SampleAfterValue": "2000003", "UMask": "0x80" }, + { + "BriefDescription": "Counts the number of first level TLB misses b= ut second level hits due to stores that did not start a page walk. Account = for all pages sizes. Will result in a DTLB write from STLB.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "PDIR_COUNTER": "NA", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to any page size.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks completed du= e to stores whose address translations missed in all Translation Lookaside = Buffer (TLB) levels and were mapped to any page size. Includes page walks = that page fault.", + "SampleAfterValue": "200003", + "UMask": "0xe" + }, + { + "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to a 1G page.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "PDIR_COUNTER": "NA", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks completed du= e to stores whose address translations missed in all Translation Lookaside = Buffer (TLB) levels and were mapped to 1G pages. Includes page walks that = page fault.", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, { "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to a 2M or 4M page.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of page walks completed du= e to stores whose address translations missed in all Translation Lookaside = Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks= that page fault.", "SampleAfterValue": "2000003", @@ -98,7 +143,7 @@ "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of page walks completed du= e to stores whose address translations missed in all Translation Lookaside = Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that = page fault.", "SampleAfterValue": "2000003", @@ -110,7 +155,7 @@ "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_PENDING", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of page walks outstanding = in the page miss handler (PMH) for stores every cycle. A page walk is outs= tanding from start till PMH becomes idle again (ready to serve next walk). = Includes EPT-walk intervals.", "SampleAfterValue": "200003", @@ -122,11 +167,11 @@ "Counter": "0,1,2,3", "EventCode": "0x4f", "EventName": "EPT.EPDE_HIT", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of Extended Page Directory= Entry hits. The Extended Page Directory cache is used by Virtual Machine = operating systems while the guest operating systems use the standard TLB ca= ches.", "SampleAfterValue": "2000003", - "UMask": "0x2" + "UMask": "0x1" }, { "BriefDescription": "Counts the number of Extended Page Directory = Entry misses.", @@ -134,11 +179,11 @@ "Counter": "0,1,2,3", "EventCode": "0x4f", "EventName": "EPT.EPDE_MISS", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number Extended Page Directory En= try misses. The Extended Page Directory cache is used by Virtual Machine o= perating systems while the guest operating systems use the standard TLB cac= hes.", "SampleAfterValue": "2000003", - "UMask": "0x1" + "UMask": "0x2" }, { "BriefDescription": "Counts the number of Extended Page Directory = Pointer Entry hits.", @@ -146,7 +191,7 @@ "Counter": "0,1,2,3", "EventCode": "0x4f", "EventName": "EPT.EPDPE_HIT", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number Extended Page Directory Po= inter Entry hits. The Extended Page Directory cache is used by Virtual Mac= hine operating systems while the guest operating systems use the standard T= LB caches.", "SampleAfterValue": "2000003", @@ -158,19 +203,31 @@ "Counter": "0,1,2,3", "EventCode": "0x4f", "EventName": "EPT.EPDPE_MISS", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number Extended Page Directory Po= inter Entry misses. The Extended Page Directory cache is used by Virtual M= achine operating systems while the guest operating systems use the standard= TLB caches.", "SampleAfterValue": "2000003", "UMask": "0x8" }, + { + "BriefDescription": "Counts the number of page walks outstanding f= or an Extended Page table walk including GTLB hits per cycle.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x4f", + "EventName": "EPT.WALK_PENDING", + "PDIR_COUNTER": "NA", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks outstanding = for an Extended Page table walk including GTLB hits per cycle. The Extende= d Page Directory cache is used by Virtual Machine operating systems while t= he guest operating systems use the standard TLB caches.", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, { "BriefDescription": "Counts the number of times there was an ITLB = miss and a new translation was filled into the ITLB.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "ITLB.FILLS", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of times the machine was u= nable to find a translation in the Instruction Translation Lookaside Buffer= (ITLB) and a new translation was filled into the ITLB. The event is specul= ative in nature, but will not count translations (page walks) that are begu= n and not finished, or translations that are finished but not filled into t= he ITLB.", "SampleAfterValue": "200003", @@ -182,29 +239,52 @@ "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.PDE_CACHE_MISS", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "2000003", "UMask": "0x80" }, { - "BriefDescription": "Counts the number of first level TLB misses b= ut second level hits due to an instruction fetch that did not start a page = walk. Account for all pages sizes. Will results in a DTLB write from STLB.", + "BriefDescription": "Counts the number of first level TLB misses b= ut second level hits due to an instruction fetch that did not start a page = walk. Account for all pages sizes. Will result in an ITLB write from STLB.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "SampleAfterValue": "2000003", "UMask": "0x20" }, + { + "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to any page size.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to any page size. Include= s page walks that page fault.", + "SampleAfterValue": "200003", + "UMask": "0xe" + }, + { + "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to a 1G page.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", + "PDIR_COUNTER": "NA", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to 1G pages. Includes pag= e walks that page fault.", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, { "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to a 2M or 4M page.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includ= es page walks that page fault.", "SampleAfterValue": "2000003", @@ -216,7 +296,7 @@ "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes pag= e walks that page fault.", "SampleAfterValue": "2000003", @@ -228,14 +308,25 @@ "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_PENDING", - "PDIR_COUNTER": "na", + "PDIR_COUNTER": "NA", "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of page walks outstanding = in the page miss handler (PMH) for instruction fetches every cycle. A page= walk is outstanding from start till PMH becomes idle again (ready to serve= next walk).", "SampleAfterValue": "200003", "UMask": "0x10" }, { - "BriefDescription": "Counts the number of memory retired ops that = missed in the second level TLB.", + "BriefDescription": "Counts the number of retired loads that are b= locked due to a first level TLB miss.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.DTLB_MISS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of memory uops retired that= missed in the second level TLB.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", @@ -247,7 +338,7 @@ "UMask": "0x13" }, { - "BriefDescription": "Counts the number of load ops retired that mi= ss in the second Level TLB.", + "BriefDescription": "Counts the number of load uops retired that m= iss in the second Level TLB.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", @@ -259,7 +350,7 @@ "UMask": "0x11" }, { - "BriefDescription": "Counts the number of store ops retired that m= iss in the second level TLB.", + "BriefDescription": "Counts the number of store uops retired that = miss in the second level TLB.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", @@ -270,4 +361,4 @@ "SampleAfterValue": "200003", "UMask": "0x12" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index dcaa68b09717..195c61157da7 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -5,6 +5,7 @@ GenuineIntel-6-(3D|47),v26,broadwell,core GenuineIntel-6-56,v23,broadwellde,core GenuineIntel-6-4F,v19,broadwellx,core GenuineIntel-6-55-[56789ABCDEF],v1.16,cascadelakex,core +GenuineIntel-6-96,v1.03,elkhartlake,core GenuineIntel-6-5C,v8,goldmont,core GenuineIntel-6-7A,v1,goldmontplus,core GenuineIntel-6-3C,v24,haswell,core @@ -37,7 +38,6 @@ GenuineIntel-6-A7,v1,icelake,core GenuineIntel-6-6A,v1,icelakex,core GenuineIntel-6-6C,v1,icelakex,core GenuineIntel-6-86,v1,snowridgex,core -GenuineIntel-6-96,v1,elkhartlake,core GenuineIntel-6-8F,v1,sapphirerapids,core AuthenticAMD-23-([12][0-9A-F]|[0-9A-F]),v2,amdzen1,core AuthenticAMD-23-[[:xdigit:]]+,v1,amdzen2,core --=20 2.37.1.359.gd136c6c3e2-goog From nobody Wed Apr 15 05:45:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 439DDC19F21 for ; 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Wed, 27 Jul 2022 15:09:04 -0700 (PDT) Date: Wed, 27 Jul 2022 15:08:10 -0700 In-Reply-To: <20220727220832.2865794-1-irogers@google.com> Message-Id: <20220727220832.2865794-9-irogers@google.com> Mime-Version: 1.0 References: <20220727220832.2865794-1-irogers@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH v3 08/30] perf vendor events: Update goldmont mapfile.csv From: Ian Rogers To: perry.taylor@intel.com, caleb.biggers@intel.com, kshipra.bopardikar@intel.com, Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Sedat Dilek Cc: Stephane Eranian , Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Align end of file whitespace with what is generated by: https://github.com/intel/event-converter-for-linux-perf/blob/master/downloa= d_and_gen.py Modify mapfile.csv to have a missing goldmont cpuid. Event json remains at v13, there are no goldmont metrics. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/arch/x86/goldmont/cache.json | 2 +- tools/perf/pmu-events/arch/x86/goldmont/floating-point.json | 2 +- tools/perf/pmu-events/arch/x86/goldmont/frontend.json | 2 +- tools/perf/pmu-events/arch/x86/goldmont/memory.json | 2 +- tools/perf/pmu-events/arch/x86/goldmont/pipeline.json | 2 +- tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json | 2 +- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/goldmont/cache.json b/tools/per= f/pmu-events/arch/x86/goldmont/cache.json index 0b887d73b7f3..ed957d4f9c6d 100644 --- a/tools/perf/pmu-events/arch/x86/goldmont/cache.json +++ b/tools/perf/pmu-events/arch/x86/goldmont/cache.json @@ -1300,4 +1300,4 @@ "SampleAfterValue": "100007", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/goldmont/floating-point.json b/= tools/perf/pmu-events/arch/x86/goldmont/floating-point.json index bb364a04a75f..37174392a510 100644 --- a/tools/perf/pmu-events/arch/x86/goldmont/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/goldmont/floating-point.json @@ -30,4 +30,4 @@ "SampleAfterValue": "2000003", "UMask": "0x8" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/goldmont/frontend.json b/tools/= perf/pmu-events/arch/x86/goldmont/frontend.json index 120ff65897c0..216da6e121c8 100644 --- a/tools/perf/pmu-events/arch/x86/goldmont/frontend.json +++ b/tools/perf/pmu-events/arch/x86/goldmont/frontend.json @@ -79,4 +79,4 @@ "SampleAfterValue": "200003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/goldmont/memory.json b/tools/pe= rf/pmu-events/arch/x86/goldmont/memory.json index 6252503f68a1..9f6f0328249e 100644 --- a/tools/perf/pmu-events/arch/x86/goldmont/memory.json +++ b/tools/perf/pmu-events/arch/x86/goldmont/memory.json @@ -31,4 +31,4 @@ "SampleAfterValue": "200003", "UMask": "0x4" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json b/tools/= perf/pmu-events/arch/x86/goldmont/pipeline.json index 5dba4313013f..42ff0b134aeb 100644 --- a/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json @@ -354,7 +354,7 @@ "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", - "PublicDescription": "Counts the number of times that the processo= r detects that a program is writing to a code section and has to perform a = machine clear because of that modification. Self-modifying code (SMC) caus= es a severe penalty in all Intel architecture processors.", + "PublicDescription": "Counts the number of times that the processo= r detects that a program is writing to a code section and has to perform a = machine clear because of that modification. Self-modifying code (SMC) caus= es a severe penalty in all Intel(R) architecture processors.", "SampleAfterValue": "200003", "UMask": "0x1" }, diff --git a/tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json b/= tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json index d5e89c74a9be..2e17e02e1463 100644 --- a/tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json @@ -75,4 +75,4 @@ "SampleAfterValue": "200003", "UMask": "0x2" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 195c61157da7..17047a972c16 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -6,7 +6,7 @@ GenuineIntel-6-56,v23,broadwellde,core GenuineIntel-6-4F,v19,broadwellx,core GenuineIntel-6-55-[56789ABCDEF],v1.16,cascadelakex,core GenuineIntel-6-96,v1.03,elkhartlake,core -GenuineIntel-6-5C,v8,goldmont,core +GenuineIntel-6-5[CF],v13,goldmont,core GenuineIntel-6-7A,v1,goldmontplus,core GenuineIntel-6-3C,v24,haswell,core GenuineIntel-6-45,v24,haswell,core --=20 2.37.1.359.gd136c6c3e2-goog From nobody Wed Apr 15 05:45:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9735FC04A68 for ; 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Wed, 27 Jul 2022 15:09:07 -0700 (PDT) Date: Wed, 27 Jul 2022 15:08:11 -0700 In-Reply-To: <20220727220832.2865794-1-irogers@google.com> Message-Id: <20220727220832.2865794-10-irogers@google.com> Mime-Version: 1.0 References: <20220727220832.2865794-1-irogers@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH v3 09/30] perf vendor events: Update goldmontplus mapfile.csv From: Ian Rogers To: perry.taylor@intel.com, caleb.biggers@intel.com, kshipra.bopardikar@intel.com, Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Sedat Dilek Cc: Stephane Eranian , Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Align end of file whitespace with what is generated by: https://github.com/intel/event-converter-for-linux-perf/blob/master/downloa= d_and_gen.py Correct the version in mapfile.csv. Event json remains at v1.01, there are no goldmontplus metrics. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/arch/x86/goldmontplus/cache.json | 2 +- tools/perf/pmu-events/arch/x86/goldmontplus/floating-point.json | 2 +- tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json | 2 +- tools/perf/pmu-events/arch/x86/goldmontplus/memory.json | 2 +- tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json | 2 +- tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json | 2 +- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json b/tools= /perf/pmu-events/arch/x86/goldmontplus/cache.json index 59c039169eb8..16e8913c0434 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json @@ -1462,4 +1462,4 @@ "SampleAfterValue": "100007", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/floating-point.jso= n b/tools/perf/pmu-events/arch/x86/goldmontplus/floating-point.json index c1f00c9470f4..9c3d22439530 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/floating-point.json @@ -35,4 +35,4 @@ "SampleAfterValue": "2000003", "UMask": "0x8" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json b/to= ols/perf/pmu-events/arch/x86/goldmontplus/frontend.json index 3fdc788a2b20..4c2abfbac8f8 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json @@ -95,4 +95,4 @@ "SampleAfterValue": "200003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json b/tool= s/perf/pmu-events/arch/x86/goldmontplus/memory.json index e26763d16d52..ae0cb3451866 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json @@ -35,4 +35,4 @@ "SampleAfterValue": "200003", "UMask": "0x4" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json b/to= ols/perf/pmu-events/arch/x86/goldmontplus/pipeline.json index 4d7e3129e5ac..2b712b12cc1f 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json @@ -428,7 +428,7 @@ "EventName": "MACHINE_CLEARS.SMC", "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times that the processo= r detects that a program is writing to a code section and has to perform a = machine clear because of that modification. Self-modifying code (SMC) caus= es a severe penalty in all Intel architecture processors.", + "PublicDescription": "Counts the number of times that the processo= r detects that a program is writing to a code section and has to perform a = machine clear because of that modification. Self-modifying code (SMC) caus= es a severe penalty in all Intel(R) architecture processors.", "SampleAfterValue": "20003", "UMask": "0x1" }, diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.jso= n b/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json index 36eaec87eead..1f7db22c15e6 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json @@ -218,4 +218,4 @@ "SampleAfterValue": "20003", "UMask": "0x20" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 17047a972c16..9a69ecc95d66 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -7,7 +7,7 @@ GenuineIntel-6-4F,v19,broadwellx,core GenuineIntel-6-55-[56789ABCDEF],v1.16,cascadelakex,core GenuineIntel-6-96,v1.03,elkhartlake,core GenuineIntel-6-5[CF],v13,goldmont,core -GenuineIntel-6-7A,v1,goldmontplus,core +GenuineIntel-6-7A,v1.01,goldmontplus,core GenuineIntel-6-3C,v24,haswell,core GenuineIntel-6-45,v24,haswell,core GenuineIntel-6-46,v24,haswell,core --=20 2.37.1.359.gd136c6c3e2-goog From nobody Wed Apr 15 05:45:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5157FC19F21 for ; Wed, 27 Jul 2022 22:10:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237000AbiG0WKC (ORCPT ); Wed, 27 Jul 2022 18:10:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51146 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236193AbiG0WJT (ORCPT ); Wed, 27 Jul 2022 18:09:19 -0400 Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB9435C9C6 for ; Wed, 27 Jul 2022 15:09:10 -0700 (PDT) Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-31edbd801b5so1268367b3.3 for ; Wed, 27 Jul 2022 15:09:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc:content-transfer-encoding; bh=z+3QILxOrvOjFC8m3UEVHbWt47VsBHDF0JrBSjSC4oY=; b=aOn/7Yz3LP21+pJRDXWrZbLPiGC3WAY8clWkj2mzZWXpMi/qxgmax6cxBuTGVxKcWp VAf0R+ZT9WONhfYQ7ycOXZF3AxHHPEce6LWkFT5wvE5HR6+okKHl2RjkpxCQ3I4zB8iW OiQkZGsh5jhLrSxWVTjcUkvj0YdAIZYR8wAwXEKufA4ci4dy/to0KXJafhrZJHuplb4d eRgGi5oOdFL5JLpbOHZcQMVRh+9kdL/KxznLpwnZ8b0PmKs0cx2THyHdNbhXhViHtuG9 r4O+hQwdbuCWLiRAhDVBOgZWuGN6PIeFuDB1gJNiYMPbKcFgl9T14jw5C9qBmhyvk/JD 1ycg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc:content-transfer-encoding; bh=z+3QILxOrvOjFC8m3UEVHbWt47VsBHDF0JrBSjSC4oY=; b=Tkztfiw5a5muSPD3j6yaX8UHCCQ49oTY2QznF1NpzH0DwfbbYMmsINOEM8Nc8UPhQb Dvr7a7VhIL26HYSi2WVZ4w1EBepNCelqqSBmg8PMtbGA3QtzG70jvM4uF9QOVYr0gD5f AxXQEwqJMwwb1BX4ZUgEAZtsW2+HeaMZGxD9IfLWdRJlnevHHvIXBBlPsKQ11ZME457a 0o/oFm2bRkc1ipOaXJUINS9p4leXxxgl5ZKQUuQErVY2ygHTokzvITRaE/79qc9pwR/t oFex1r9LhW5Dp3yTKVZgrevDPagueCIDDkCVbBVPko6ow1qVqtxlrTZnyyfZjl2RQE23 RGrw== X-Gm-Message-State: AJIora94EnK86/TjQNd5eXdNEatbqgM3mZeVRyFskwkBjFAk7k1C7a18 k+V7Ncl8ql3mzdpzqyeePvKuEsoIn68y X-Google-Smtp-Source: AGRyM1uUjGLdNUdMutWxgXcz6nKqsgxDkCSaDwxhBjlnVvoKEnuE8nbRqlc1KVLQWIwaYq6MC8jN9+D6A90Q X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:882a:af57:8cb6:6f9e]) (user=irogers job=sendgmr) by 2002:a5b:74e:0:b0:66f:4c3a:2141 with SMTP id s14-20020a5b074e000000b0066f4c3a2141mr19895756ybq.203.1658959750160; Wed, 27 Jul 2022 15:09:10 -0700 (PDT) Date: Wed, 27 Jul 2022 15:08:12 -0700 In-Reply-To: <20220727220832.2865794-1-irogers@google.com> Message-Id: <20220727220832.2865794-11-irogers@google.com> Mime-Version: 1.0 References: <20220727220832.2865794-1-irogers@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH v3 10/30] perf vendor events: Update Intel haswell From: Ian Rogers To: perry.taylor@intel.com, caleb.biggers@intel.com, kshipra.bopardikar@intel.com, Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Sedat Dilek Cc: Stephane Eranian , Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Update to v31, the metrics are based on TMA 4.4 full. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/downloa= d_and_gen.py to download and generate the latest events and metrics. Manually copy the haswell files into perf and update mapfile.csv. Tested on a non-haswell with 'perf test': 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/haswell/cache.json | 78 +++++++---------- .../arch/x86/haswell/floating-point.json | 2 +- .../pmu-events/arch/x86/haswell/frontend.json | 2 +- .../arch/x86/haswell/hsw-metrics.json | 85 +++++++++++++------ .../pmu-events/arch/x86/haswell/memory.json | 75 ++++++---------- .../pmu-events/arch/x86/haswell/other.json | 2 +- .../pmu-events/arch/x86/haswell/pipeline.json | 9 +- .../arch/x86/haswell/uncore-other.json | 7 +- .../arch/x86/haswell/virtual-memory.json | 2 +- tools/perf/pmu-events/arch/x86/mapfile.csv | 4 +- 10 files changed, 125 insertions(+), 141 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/haswell/cache.json b/tools/perf= /pmu-events/arch/x86/haswell/cache.json index 91464cfb9615..3b0f3a264246 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/cache.json +++ b/tools/perf/pmu-events/arch/x86/haswell/cache.json @@ -556,7 +556,7 @@ "UMask": "0x20" }, { - "BriefDescription": "All retired load uops.", + "BriefDescription": "Retired load uops.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "Data_LA": "1", @@ -564,11 +564,12 @@ "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", "PEBS": "1", + "PublicDescription": "Counts all retired load uops. This event acc= ounts for SW prefetch uops of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.", "SampleAfterValue": "2000003", "UMask": "0x81" }, { - "BriefDescription": "All retired store uops.", + "BriefDescription": "Retired store uops.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "Data_LA": "1", @@ -577,6 +578,7 @@ "EventName": "MEM_UOPS_RETIRED.ALL_STORES", "L1_Hit_Indication": "1", "PEBS": "1", + "PublicDescription": "Counts all retired store uops.", "SampleAfterValue": "2000003", "UMask": "0x82" }, @@ -790,20 +792,19 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand & prefetch code reads hit i= n the L3 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded", + "BriefDescription": "Counts all demand & prefetch code readshit in= the L3 and the snoops to sibling cores hit in either E/S state and the lin= e is not forwarded", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_HIT.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0244", + "MSRValue": "0x4003C0244", "Offcore": "1", - "PublicDescription": "Counts all demand & prefetch code reads hit = in the L3 and the snoops to sibling cores hit in either E/S state and the l= ine is not forwarded", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand & prefetch data reads hit i= n the L3 and the snoop to one of the sibling cores hits the line in M state= and the line is forwarded", + "BriefDescription": "Counts all demand & prefetch data readshit in= the L3 and the snoop to one of the sibling cores hits the line in M state = and the line is forwarded", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", @@ -811,20 +812,18 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0091", "Offcore": "1", - "PublicDescription": "Counts all demand & prefetch data reads hit = in the L3 and the snoop to one of the sibling cores hits the line in M stat= e and the line is forwarded", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand & prefetch data reads hit i= n the L3 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded", + "BriefDescription": "Counts all demand & prefetch data readshit in= the L3 and the snoops to sibling cores hit in either E/S state and the lin= e is not forwarded", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0091", + "MSRValue": "0x4003C0091", "Offcore": "1", - "PublicDescription": "Counts all demand & prefetch data reads hit = in the L3 and the snoops to sibling cores hit in either E/S state and the l= ine is not forwarded", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -837,7 +836,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C07F7", "Offcore": "1", - "PublicDescription": "hit in the L3 and the snoop to one of the si= bling cores hits the line in M state and the line is forwarded", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -848,14 +846,13 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C07F7", + "MSRValue": "0x4003C07F7", "Offcore": "1", - "PublicDescription": "hit in the L3 and the snoops to sibling core= s hit in either E/S state and the line is not forwarded", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all requests hit in the L3", + "BriefDescription": "Counts all requestshit in the L3", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", @@ -863,12 +860,11 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C8FFF", "Offcore": "1", - "PublicDescription": "Counts all requests hit in the L3", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand & prefetch RFOs hit in the = L3 and the snoop to one of the sibling cores hits the line in M state and t= he line is forwarded", + "BriefDescription": "Counts all demand & prefetch RFOshit in the L= 3 and the snoop to one of the sibling cores hits the line in M state and th= e line is forwarded", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", @@ -876,25 +872,23 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0122", "Offcore": "1", - "PublicDescription": "Counts all demand & prefetch RFOs hit in the= L3 and the snoop to one of the sibling cores hits the line in M state and = the line is forwarded", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand & prefetch RFOs hit in the = L3 and the snoops to sibling cores hit in either E/S state and the line is = not forwarded", + "BriefDescription": "Counts all demand & prefetch RFOshit in the L= 3 and the snoops to sibling cores hit in either E/S state and the line is n= ot forwarded", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0122", + "MSRValue": "0x4003C0122", "Offcore": "1", - "PublicDescription": "Counts all demand & prefetch RFOs hit in the= L3 and the snoops to sibling cores hit in either E/S state and the line is= not forwarded", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads hit in the L3 an= d the snoop to one of the sibling cores hits the line in M state and the li= ne is forwarded", + "BriefDescription": "Counts all demand code readshit in the L3 and= the snoop to one of the sibling cores hits the line in M state and the lin= e is forwarded", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", @@ -902,25 +896,23 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0004", "Offcore": "1", - "PublicDescription": "Counts all demand code reads hit in the L3 a= nd the snoop to one of the sibling cores hits the line in M state and the l= ine is forwarded", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads hit in the L3 an= d the snoops to sibling cores hit in either E/S state and the line is not f= orwarded", + "BriefDescription": "Counts all demand code readshit in the L3 and= the snoops to sibling cores hit in either E/S state and the line is not fo= rwarded", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0004", + "MSRValue": "0x4003C0004", "Offcore": "1", - "PublicDescription": "Counts all demand code reads hit in the L3 a= nd the snoops to sibling cores hit in either E/S state and the line is not = forwarded", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads hit in the L3 and th= e snoop to one of the sibling cores hits the line in M state and the line i= s forwarded", + "BriefDescription": "Counts demand data readshit in the L3 and the= snoop to one of the sibling cores hits the line in M state and the line is= forwarded", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", @@ -928,25 +920,23 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0001", "Offcore": "1", - "PublicDescription": "Counts demand data reads hit in the L3 and t= he snoop to one of the sibling cores hits the line in M state and the line = is forwarded", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads hit in the L3 and th= e snoops to sibling cores hit in either E/S state and the line is not forwa= rded", + "BriefDescription": "Counts demand data readshit in the L3 and the= snoops to sibling cores hit in either E/S state and the line is not forwar= ded", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0001", + "MSRValue": "0x4003C0001", "Offcore": "1", - "PublicDescription": "Counts demand data reads hit in the L3 and t= he snoops to sibling cores hit in either E/S state and the line is not forw= arded", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs) hit in t= he L3 and the snoop to one of the sibling cores hits the line in M state an= d the line is forwarded", + "BriefDescription": "Counts all demand data writes (RFOs)hit in th= e L3 and the snoop to one of the sibling cores hits the line in M state and= the line is forwarded", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", @@ -954,25 +944,23 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0002", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs) hit in = the L3 and the snoop to one of the sibling cores hits the line in M state a= nd the line is forwarded", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs) hit in t= he L3 and the snoops to sibling cores hit in either E/S state and the line = is not forwarded", + "BriefDescription": "Counts all demand data writes (RFOs)hit in th= e L3 and the snoops to sibling cores hit in either E/S state and the line i= s not forwarded", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0002", + "MSRValue": "0x4003C0002", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs) hit in = the L3 and the snoops to sibling cores hit in either E/S state and the line= is not forwarded", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads hit in the L3", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code readshit in the L3", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", @@ -980,12 +968,11 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0040", "Offcore": "1", - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) code reads hit in the L3", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads hit in the L3", + "BriefDescription": "Counts prefetch (that bring data to L2) data = readshit in the L3", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", @@ -993,12 +980,11 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0010", "Offcore": "1", - "PublicDescription": "Counts prefetch (that bring data to L2) data= reads hit in the L3", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs hit in the L3", + "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOshit in the L3", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", @@ -1006,12 +992,11 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0020", "Offcore": "1", - "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs hit in the L3", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads hit in the L3", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= code readshit in the L3", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", @@ -1019,12 +1004,11 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0200", "Offcore": "1", - "PublicDescription": "Counts prefetch (that bring data to LLC only= ) code reads hit in the L3", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads hit in the L3", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data readshit in the L3", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", @@ -1032,12 +1016,11 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0080", "Offcore": "1", - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) data reads hit in the L3", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs hit in the L3", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOshit in the L3", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", @@ -1045,7 +1028,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0100", "Offcore": "1", - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs hit in the L3", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1058,4 +1040,4 @@ "SampleAfterValue": "100003", "UMask": "0x10" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/haswell/floating-point.json b/t= ools/perf/pmu-events/arch/x86/haswell/floating-point.json index 55cf5b96464e..7cf203a90a74 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/haswell/floating-point.json @@ -100,4 +100,4 @@ "SampleAfterValue": "100003", "UMask": "0x10" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/haswell/frontend.json b/tools/p= erf/pmu-events/arch/x86/haswell/frontend.json index 0c8d5ccf1276..c45a09abe5d3 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/frontend.json +++ b/tools/perf/pmu-events/arch/x86/haswell/frontend.json @@ -301,4 +301,4 @@ "SampleAfterValue": "2000003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json b/tool= s/perf/pmu-events/arch/x86/haswell/hsw-metrics.json index 3ade2c19533e..75dc6dd9a7bc 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json +++ b/tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json @@ -111,17 +111,11 @@ "MetricName": "CoreIPC_SMT" }, { - "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is at least 1 uop executed)", + "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per-core", "MetricExpr": "( UOPS_EXECUTED.CORE / 2 / (( cpu@UOPS_EXECUTED.COR= E\\,cmask\\=3D1@ / 2 ) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=3D1= @) ) if #SMT_on else UOPS_EXECUTED.CORE / (( cpu@UOPS_EXECUTED.CORE\\,cmask= \\=3D1@ / 2 ) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=3D1@)", "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, - { - "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear)", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "IpMispredict" - }, { "BriefDescription": "Core actual clocks when any Logical Processor= is active on the Physical Core", "MetricExpr": "( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_U= NHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", @@ -170,6 +164,12 @@ "MetricGroup": "Summary;TmaL1", "MetricName": "Instructions" }, + { + "BriefDescription": "Average number of Uops retired in cycles wher= e at least one uop has retired.", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE= _SLOTS\\,cmask\\=3D1@", + "MetricGroup": "Pipeline;Ret", + "MetricName": "Retire" + }, { "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MIT= E_UOPS + IDQ.MS_UOPS ) )", @@ -177,11 +177,16 @@ "MetricName": "DSB_Coverage" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load instructions (in core cycles)", + "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "IpMispredict" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load operations (in core cycles)", "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_= MISS + mem_load_uops_retired.hit_lfb )", "MetricGroup": "Mem;MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency", - "PublicDescription": "Actual Average Latency for L1 data-cache mis= s demand load instructions (in core cycles). Latency may be overestimated f= or multi-load instructions - e.g. repeat strings." + "MetricName": "Load_Miss_Real_Latency" }, { "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", @@ -189,24 +194,6 @@ "MetricGroup": "Mem;MemoryBound;MemoryBW", "MetricName": "MLP" }, - { - "BriefDescription": "Average data fill bandwidth to the L1 data ca= che [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW" - }, - { - "BriefDescription": "Average data fill bandwidth to the L2 cache [= GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW" - }, - { - "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW" - }, { "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED= .ANY", @@ -238,6 +225,48 @@ "MetricGroup": "Mem;MemoryTLB_SMT", "MetricName": "Page_Walks_Utilization_SMT" }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", + "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L1D_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 2 cache [GB / sec]", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L2_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L3_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L1 data cache [GB / sec]", + "MetricExpr": "(64 * L1D.REPLACEMENT / 1000000000 / duration_time)= ", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L1D_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L2 cache [GB / sec]", + "MetricExpr": "(64 * L2_LINES_IN.ALL / 1000000000 / duration_time)= ", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L2_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L3 cache [GB / sec]", + "MetricExpr": "(64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duratio= n_time)", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L3_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data access bandwidth to t= he L3 cache [GB / sec]", + "MetricExpr": "0", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "L3_Cache_Access_BW_1T" + }, { "BriefDescription": "Average CPU Utilization", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", diff --git a/tools/perf/pmu-events/arch/x86/haswell/memory.json b/tools/per= f/pmu-events/arch/x86/haswell/memory.json index 8b69493e3726..9e5a1e0966d9 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/memory.json +++ b/tools/perf/pmu-events/arch/x86/haswell/memory.json @@ -225,7 +225,7 @@ "UMask": "0x2" }, { - "BriefDescription": "Counts all demand & prefetch code reads miss = in the L3", + "BriefDescription": "Counts all demand & prefetch code readsmiss i= n the L3", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", @@ -233,25 +233,23 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFFC00244", "Offcore": "1", - "PublicDescription": "Counts all demand & prefetch code reads miss= in the L3", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand & prefetch code reads miss = the L3 and the data is returned from local dram", + "BriefDescription": "Counts all demand & prefetch code readsmiss t= he L3 and the data is returned from local dram", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400244", + "MSRValue": "0x100400244", "Offcore": "1", - "PublicDescription": "Counts all demand & prefetch code reads miss= the L3 and the data is returned from local dram", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand & prefetch data reads miss = in the L3", + "BriefDescription": "Counts all demand & prefetch data readsmiss i= n the L3", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", @@ -259,20 +257,18 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFFC00091", "Offcore": "1", - "PublicDescription": "Counts all demand & prefetch data reads miss= in the L3", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand & prefetch data reads miss = the L3 and the data is returned from local dram", + "BriefDescription": "Counts all demand & prefetch data readsmiss t= he L3 and the data is returned from local dram", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400091", + "MSRValue": "0x100400091", "Offcore": "1", - "PublicDescription": "Counts all demand & prefetch data reads miss= the L3 and the data is returned from local dram", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -285,7 +281,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFFC007F7", "Offcore": "1", - "PublicDescription": "miss in the L3", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -296,14 +291,13 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01004007F7", + "MSRValue": "0x1004007F7", "Offcore": "1", - "PublicDescription": "miss the L3 and the data is returned from lo= cal dram", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all requests miss in the L3", + "BriefDescription": "Counts all requestsmiss in the L3", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", @@ -311,12 +305,11 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFFC08FFF", "Offcore": "1", - "PublicDescription": "Counts all requests miss in the L3", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand & prefetch RFOs miss in the= L3", + "BriefDescription": "Counts all demand & prefetch RFOsmiss in the = L3", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", @@ -324,25 +317,23 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFFC00122", "Offcore": "1", - "PublicDescription": "Counts all demand & prefetch RFOs miss in th= e L3", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand & prefetch RFOs miss the L3= and the data is returned from local dram", + "BriefDescription": "Counts all demand & prefetch RFOsmiss the L3 = and the data is returned from local dram", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400122", + "MSRValue": "0x100400122", "Offcore": "1", - "PublicDescription": "Counts all demand & prefetch RFOs miss the L= 3 and the data is returned from local dram", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads miss in the L3", + "BriefDescription": "Counts all demand code readsmiss in the L3", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", @@ -350,25 +341,23 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFFC00004", "Offcore": "1", - "PublicDescription": "Counts all demand code reads miss in the L3", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads miss the L3 and = the data is returned from local dram", + "BriefDescription": "Counts all demand code readsmiss the L3 and t= he data is returned from local dram", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400004", + "MSRValue": "0x100400004", "Offcore": "1", - "PublicDescription": "Counts all demand code reads miss the L3 and= the data is returned from local dram", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads miss in the L3", + "BriefDescription": "Counts demand data readsmiss in the L3", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", @@ -376,25 +365,23 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFFC00001", "Offcore": "1", - "PublicDescription": "Counts demand data reads miss in the L3", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads miss the L3 and the = data is returned from local dram", + "BriefDescription": "Counts demand data readsmiss the L3 and the d= ata is returned from local dram", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400001", + "MSRValue": "0x100400001", "Offcore": "1", - "PublicDescription": "Counts demand data reads miss the L3 and the= data is returned from local dram", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs) miss in = the L3", + "BriefDescription": "Counts all demand data writes (RFOs)miss in t= he L3", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", @@ -402,25 +389,23 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFFC00002", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs) miss in= the L3", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs) miss the= L3 and the data is returned from local dram", + "BriefDescription": "Counts all demand data writes (RFOs)miss the = L3 and the data is returned from local dram", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400002", + "MSRValue": "0x100400002", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs) miss th= e L3 and the data is returned from local dram", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads miss in the L3", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code readsmiss in the L3", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", @@ -428,12 +413,11 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFFC00040", "Offcore": "1", - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) code reads miss in the L3", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts prefetch (that bring data to L2) data = reads miss in the L3", + "BriefDescription": "Counts prefetch (that bring data to L2) data = readsmiss in the L3", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", @@ -441,12 +425,11 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFFC00010", "Offcore": "1", - "PublicDescription": "Counts prefetch (that bring data to L2) data= reads miss in the L3", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs miss in the L3", + "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOsmiss in the L3", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", @@ -454,12 +437,11 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFFC00020", "Offcore": "1", - "PublicDescription": "Counts all prefetch (that bring data to L2) = RFOs miss in the L3", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads miss in the L3", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= code readsmiss in the L3", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", @@ -467,12 +449,11 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFFC00200", "Offcore": "1", - "PublicDescription": "Counts prefetch (that bring data to LLC only= ) code reads miss in the L3", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads miss in the L3", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data readsmiss in the L3", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", @@ -480,12 +461,11 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFFC00080", "Offcore": "1", - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) data reads miss in the L3", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs miss in the L3", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOsmiss in the L3", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", @@ -493,7 +473,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFFC00100", "Offcore": "1", - "PublicDescription": "Counts all prefetch (that bring data to LLC = only) RFOs miss in the L3", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -681,4 +660,4 @@ "SampleAfterValue": "2000003", "UMask": "0x40" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/haswell/other.json b/tools/perf= /pmu-events/arch/x86/haswell/other.json index 4c6b9d34325a..7ca34f09b185 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/other.json +++ b/tools/perf/pmu-events/arch/x86/haswell/other.json @@ -40,4 +40,4 @@ "SampleAfterValue": "2000003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/haswell/pipeline.json b/tools/p= erf/pmu-events/arch/x86/haswell/pipeline.json index a53f28ec9270..42f6a8100661 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/haswell/pipeline.json @@ -1035,7 +1035,6 @@ "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", - "PublicDescription": "Cycles per core when uops are exectuted in p= ort 0.", "SampleAfterValue": "2000003", "UMask": "0x1" }, @@ -1056,7 +1055,6 @@ "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", - "PublicDescription": "Cycles per core when uops are exectuted in p= ort 1.", "SampleAfterValue": "2000003", "UMask": "0x2" }, @@ -1117,7 +1115,6 @@ "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", - "PublicDescription": "Cycles per core when uops are exectuted in p= ort 4.", "SampleAfterValue": "2000003", "UMask": "0x10" }, @@ -1138,7 +1135,6 @@ "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", - "PublicDescription": "Cycles per core when uops are exectuted in p= ort 5.", "SampleAfterValue": "2000003", "UMask": "0x20" }, @@ -1159,7 +1155,6 @@ "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", - "PublicDescription": "Cycles per core when uops are exectuted in p= ort 6.", "SampleAfterValue": "2000003", "UMask": "0x40" }, @@ -1295,11 +1290,11 @@ "BriefDescription": "Cycles with less than 10 actually retired uop= s.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "CounterMask": "10", + "CounterMask": "16", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", "Invert": "1", "SampleAfterValue": "2000003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/haswell/uncore-other.json b/too= ls/perf/pmu-events/arch/x86/haswell/uncore-other.json index 8f2ae2891042..56c4b380dc95 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/haswell/uncore-other.json @@ -19,11 +19,11 @@ "Unit": "ARB" }, { - "BriefDescription": "Each cycle count number of all Core outgoing = valid entries. Such entry is defined as valid from it's allocation till fir= st of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-cohe= rent traffic.", + "BriefDescription": "Each cycle counts number of all Core outgoing= valid entries. Such entry is defined as valid from its allocation till fir= st of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-cohe= rent traffic.", "EventCode": "0x80", "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", "PerPkg": "1", - "PublicDescription": "Each cycle count number of all Core outgoing= valid entries. Such entry is defined as valid from it's allocation till fi= rst of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coh= erent traffic.", + "PublicDescription": "Each cycle counts number of all Core outgoin= g valid entries. Such entry is defined as valid from its allocation till fi= rst of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coh= erent traffic.", "UMask": "0x01", "Unit": "ARB" }, @@ -34,6 +34,7 @@ "EventCode": "0x80", "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", "PerPkg": "1", + "PublicDescription": "Cycles with at least one request outstanding= is waiting for data return from memory controller. Account for coherent an= d non-coherent requests initiated by IA Cores, Processor Graphics Unit, or = LLC.\n", "UMask": "0x01", "Unit": "ARB" }, @@ -64,6 +65,6 @@ "EventName": "UNC_CLOCK.SOCKET", "PerPkg": "1", "PublicDescription": "This 48-bit fixed counter counts the UCLK cy= cles.", - "Unit": "NCU" + "Unit": "CLOCK" } ] diff --git a/tools/perf/pmu-events/arch/x86/haswell/virtual-memory.json b/t= ools/perf/pmu-events/arch/x86/haswell/virtual-memory.json index ba3e77a9f9a0..57d2a6452fec 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/haswell/virtual-memory.json @@ -481,4 +481,4 @@ "SampleAfterValue": "100003", "UMask": "0x20" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 9a69ecc95d66..39741e24f733 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -8,9 +8,7 @@ GenuineIntel-6-55-[56789ABCDEF],v1.16,cascadelakex,core GenuineIntel-6-96,v1.03,elkhartlake,core GenuineIntel-6-5[CF],v13,goldmont,core GenuineIntel-6-7A,v1.01,goldmontplus,core -GenuineIntel-6-3C,v24,haswell,core -GenuineIntel-6-45,v24,haswell,core -GenuineIntel-6-46,v24,haswell,core +GenuineIntel-6-(3C|45|46),v31,haswell,core GenuineIntel-6-3F,v17,haswellx,core GenuineIntel-6-3A,v18,ivybridge,core GenuineIntel-6-3E,v19,ivytown,core --=20 2.37.1.359.gd136c6c3e2-goog From nobody Wed Apr 15 05:45:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 710E2C04A68 for ; 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Wed, 27 Jul 2022 15:09:12 -0700 (PDT) Date: Wed, 27 Jul 2022 15:08:13 -0700 In-Reply-To: <20220727220832.2865794-1-irogers@google.com> Message-Id: <20220727220832.2865794-12-irogers@google.com> Mime-Version: 1.0 References: <20220727220832.2865794-1-irogers@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH v3 11/30] perf vendor events: Update Intel haswellx From: Ian Rogers To: perry.taylor@intel.com, caleb.biggers@intel.com, kshipra.bopardikar@intel.com, Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Sedat Dilek Cc: Stephane Eranian , Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Update to v25, the metrics are based on TMA 4.4 full. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/downloa= d_and_gen.py to download and generate the latest events and metrics. Manually copy the haswellx files into perf and update mapfile.csv. Tested with 'perf test': 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok 90: perf all metricgroups test : Ok 91: perf all metrics test : Fail= ed 93: perf all PMU test : Ok The test 91 failure is a pre-existing failure on the test system with the metric Load_Miss_Real_Latency which is fixed by prefixing it with --metric-no-group. Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/haswellx/cache.json | 9 +- .../arch/x86/haswellx/hsx-metrics.json | 85 +++++++++++++------ .../arch/x86/haswellx/pipeline.json | 5 -- .../arch/x86/haswellx/uncore-cache.json | 8 +- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 5 files changed, 67 insertions(+), 42 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/haswellx/cache.json b/tools/per= f/pmu-events/arch/x86/haswellx/cache.json index 5760ffb1eaf4..7557a203a1b6 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/cache.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/cache.json @@ -20,7 +20,7 @@ "UMask": "0x2" }, { - "BriefDescription": "L1D miss oustandings duration in cycles", + "BriefDescription": "L1D miss outstanding duration in cycles", "Counter": "2", "CounterHTOff": "2", "EventCode": "0x48", @@ -592,7 +592,7 @@ "UMask": "0x20" }, { - "BriefDescription": "All retired load uops.", + "BriefDescription": "Retired load uops.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "Data_LA": "1", @@ -600,11 +600,12 @@ "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", "PEBS": "1", + "PublicDescription": "Counts all retired load uops. This event acc= ounts for SW prefetch uops of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.", "SampleAfterValue": "2000003", "UMask": "0x81" }, { - "BriefDescription": "All retired store uops.", + "BriefDescription": "Retired store uops.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "Data_LA": "1", @@ -613,6 +614,7 @@ "EventName": "MEM_UOPS_RETIRED.ALL_STORES", "L1_Hit_Indication": "1", "PEBS": "1", + "PublicDescription": "Counts all retired store uops.", "SampleAfterValue": "2000003", "UMask": "0x82" }, @@ -1071,7 +1073,6 @@ "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xf4", "EventName": "SQ_MISC.SPLIT_LOCK", - "PublicDescription": "SQ_MISC.SPLIT_LOCK", "SampleAfterValue": "100003", "UMask": "0x10" } diff --git a/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json b/too= ls/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json index c99734fd907d..5c9e008ca995 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json @@ -111,17 +111,11 @@ "MetricName": "CoreIPC_SMT" }, { - "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is at least 1 uop executed)", + "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per-core", "MetricExpr": "( UOPS_EXECUTED.CORE / 2 / (( cpu@UOPS_EXECUTED.COR= E\\,cmask\\=3D1@ / 2 ) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=3D1= @) ) if #SMT_on else UOPS_EXECUTED.CORE / (( cpu@UOPS_EXECUTED.CORE\\,cmask= \\=3D1@ / 2 ) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=3D1@)", "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, - { - "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear)", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "IpMispredict" - }, { "BriefDescription": "Core actual clocks when any Logical Processor= is active on the Physical Core", "MetricExpr": "( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_U= NHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", @@ -170,6 +164,12 @@ "MetricGroup": "Summary;TmaL1", "MetricName": "Instructions" }, + { + "BriefDescription": "Average number of Uops retired in cycles wher= e at least one uop has retired.", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE= _SLOTS\\,cmask\\=3D1@", + "MetricGroup": "Pipeline;Ret", + "MetricName": "Retire" + }, { "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MIT= E_UOPS + IDQ.MS_UOPS ) )", @@ -177,11 +177,16 @@ "MetricName": "DSB_Coverage" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load instructions (in core cycles)", + "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "IpMispredict" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load operations (in core cycles)", "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_= MISS + mem_load_uops_retired.hit_lfb )", "MetricGroup": "Mem;MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency", - "PublicDescription": "Actual Average Latency for L1 data-cache mis= s demand load instructions (in core cycles). Latency may be overestimated f= or multi-load instructions - e.g. repeat strings." + "MetricName": "Load_Miss_Real_Latency" }, { "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", @@ -189,24 +194,6 @@ "MetricGroup": "Mem;MemoryBound;MemoryBW", "MetricName": "MLP" }, - { - "BriefDescription": "Average data fill bandwidth to the L1 data ca= che [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW" - }, - { - "BriefDescription": "Average data fill bandwidth to the L2 cache [= GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW" - }, - { - "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW" - }, { "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED= .ANY", @@ -238,6 +225,48 @@ "MetricGroup": "Mem;MemoryTLB_SMT", "MetricName": "Page_Walks_Utilization_SMT" }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", + "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L1D_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 2 cache [GB / sec]", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L2_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L3_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L1 data cache [GB / sec]", + "MetricExpr": "(64 * L1D.REPLACEMENT / 1000000000 / duration_time)= ", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L1D_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L2 cache [GB / sec]", + "MetricExpr": "(64 * L2_LINES_IN.ALL / 1000000000 / duration_time)= ", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L2_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L3 cache [GB / sec]", + "MetricExpr": "(64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duratio= n_time)", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L3_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data access bandwidth to t= he L3 cache [GB / sec]", + "MetricExpr": "0", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "L3_Cache_Access_BW_1T" + }, { "BriefDescription": "Average CPU Utilization", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", diff --git a/tools/perf/pmu-events/arch/x86/haswellx/pipeline.json b/tools/= perf/pmu-events/arch/x86/haswellx/pipeline.json index 6165933ee1a4..42f6a8100661 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/pipeline.json @@ -1035,7 +1035,6 @@ "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", - "PublicDescription": "Cycles per core when uops are exectuted in p= ort 0.", "SampleAfterValue": "2000003", "UMask": "0x1" }, @@ -1056,7 +1055,6 @@ "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", - "PublicDescription": "Cycles per core when uops are exectuted in p= ort 1.", "SampleAfterValue": "2000003", "UMask": "0x2" }, @@ -1117,7 +1115,6 @@ "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", - "PublicDescription": "Cycles per core when uops are exectuted in p= ort 4.", "SampleAfterValue": "2000003", "UMask": "0x10" }, @@ -1138,7 +1135,6 @@ "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", - "PublicDescription": "Cycles per core when uops are exectuted in p= ort 5.", "SampleAfterValue": "2000003", "UMask": "0x20" }, @@ -1159,7 +1155,6 @@ "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", - "PublicDescription": "Cycles per core when uops are exectuted in p= ort 6.", "SampleAfterValue": "2000003", "UMask": "0x40" }, diff --git a/tools/perf/pmu-events/arch/x86/haswellx/uncore-cache.json b/to= ols/perf/pmu-events/arch/x86/haswellx/uncore-cache.json index b48833d1c170..03598904d746 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/uncore-cache.json @@ -511,7 +511,7 @@ "Unit": "CBO" }, { - "BriefDescription": "AD", + "BriefDescription": "UNC_C_RING_SINK_STARVED.AD", "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.AD", @@ -520,7 +520,7 @@ "Unit": "CBO" }, { - "BriefDescription": "AK", + "BriefDescription": "UNC_C_RING_SINK_STARVED.AK", "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.AK", @@ -529,7 +529,7 @@ "Unit": "CBO" }, { - "BriefDescription": "IV", + "BriefDescription": "UNC_C_RING_SINK_STARVED.IV", "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.IV", @@ -538,7 +538,7 @@ "Unit": "CBO" }, { - "BriefDescription": "BL", + "BriefDescription": "UNC_C_RING_SINK_STARVED.BL", "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.BL", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 39741e24f733..b602d2da1b89 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -9,7 +9,7 @@ GenuineIntel-6-96,v1.03,elkhartlake,core GenuineIntel-6-5[CF],v13,goldmont,core GenuineIntel-6-7A,v1.01,goldmontplus,core GenuineIntel-6-(3C|45|46),v31,haswell,core -GenuineIntel-6-3F,v17,haswellx,core +GenuineIntel-6-3F,v25,haswellx,core GenuineIntel-6-3A,v18,ivybridge,core GenuineIntel-6-3E,v19,ivytown,core GenuineIntel-6-2D,v20,jaketown,core --=20 2.37.1.359.gd136c6c3e2-goog From nobody Wed Apr 15 05:45:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBCA9C04A68 for ; Wed, 27 Jul 2022 22:10:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232026AbiG0WKY (ORCPT ); Wed, 27 Jul 2022 18:10:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51340 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236467AbiG0WJY (ORCPT ); Wed, 27 Jul 2022 18:09:24 -0400 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2839C57270 for ; Wed, 27 Jul 2022 15:09:16 -0700 (PDT) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-31f99336d8dso871597b3.17 for ; Wed, 27 Jul 2022 15:09:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc:content-transfer-encoding; bh=6o0EQD4JQngkIEeYiGc7/XAki5aA8ETmOlcVBv+uqVk=; b=d7kLx736TrBKe4g4SMk8VwPb/Dmi4PX32rpEC9IhkCL2SX7gzbMREEaSb8//rYw1es 3WXWjfFWaQC8mJCFrXmugMD5Bt2HTn45IYi76U5yDj/nv09k/EbfhZkdPhe+2P8uurkN 87o6TmygvFcFvFxt616lg3iHzqbiqVMsalTN0oO2RyvB774XsnbtrWU7TD3CCYhMOtIc C31qWCifbgMJqRhJJtnbWaGXKlPx3aXvu07miFlRmTUQZvL4H1NG4VmfvnnkscguR9YD ZbMMg6zzfY8EXLV998woui57ehf0MRraEDPoa262QnlrAYt4PNihbImfFMYlfPxoihbv xftw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc:content-transfer-encoding; bh=6o0EQD4JQngkIEeYiGc7/XAki5aA8ETmOlcVBv+uqVk=; b=A8+N5XZiXlX3HLhp7KCN+FiriuC16dgTv/d5X62Vk0ttZjO1tUAhBKYFxWOcdbS3YG 5X8KvYC8NAZri57P5nda9/gDQ0aurba2x36q9c0O5VHl5ErRLMaWMf0gEkjBctvEwLFQ GaxN+EMiLEuZxk8b/5AcJTt72E9GIJSkfB/3q3l0XkSPCTt8iittg7b9ARei8ffkvpo4 Js+putv3JgGYBcUgUNX9e7gqsL+6proxUxNMLh74RzIawVjJY3NEJGt4o94wl8VZo1ML 5Ud/o4dDc6bJBUpcX0n1aX/QqrpczQ0ciT4G5wuHdlKqHD/DQLWZRCnLOFHpnynS9ZE9 os3A== X-Gm-Message-State: AJIora8Isgplpwd7udDm83Iu5oA/ZxchL65BO48AA+9DLHnl5H/tPDQ5 0f2AcJzbhAWYOpG8kRUqextMeyR3c/cs X-Google-Smtp-Source: AGRyM1vkUSd+RHWCBe2tX/SUwF1oljHIze8MnN9dE6VaHb22rUX1kehxIaE4GqvzIIsbadq8I7OezCg9qn37 X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:882a:af57:8cb6:6f9e]) (user=irogers job=sendgmr) by 2002:a25:69d3:0:b0:671:7336:eab6 with SMTP id e202-20020a2569d3000000b006717336eab6mr7401221ybc.387.1658959755415; Wed, 27 Jul 2022 15:09:15 -0700 (PDT) Date: Wed, 27 Jul 2022 15:08:14 -0700 In-Reply-To: <20220727220832.2865794-1-irogers@google.com> Message-Id: <20220727220832.2865794-13-irogers@google.com> Mime-Version: 1.0 References: <20220727220832.2865794-1-irogers@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH v3 12/30] perf vendor events: Update Intel icelake From: Ian Rogers To: perry.taylor@intel.com, caleb.biggers@intel.com, kshipra.bopardikar@intel.com, Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Sedat Dilek Cc: Stephane Eranian , Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Update to v1.14, the metrics are based on TMA 4.4 full. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/downloa= d_and_gen.py to download and generate the latest events and metrics. Manually copy the icelake files into perf and update mapfile.csv. Tested on a non-icelake with 'perf test': 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/icelake/cache.json | 8 +- .../arch/x86/icelake/floating-point.json | 2 +- .../pmu-events/arch/x86/icelake/frontend.json | 2 +- .../arch/x86/icelake/icl-metrics.json | 126 ++++++++++++------ .../arch/x86/icelake/uncore-other.json | 31 +++++ .../arch/x86/icelake/virtual-memory.json | 2 +- tools/perf/pmu-events/arch/x86/mapfile.csv | 4 +- 7 files changed, 123 insertions(+), 52 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/icelake/uncore-other.json diff --git a/tools/perf/pmu-events/arch/x86/icelake/cache.json b/tools/perf= /pmu-events/arch/x86/icelake/cache.json index 9989f3338f0a..b4f28f24ee63 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/cache.json +++ b/tools/perf/pmu-events/arch/x86/icelake/cache.json @@ -303,7 +303,7 @@ "UMask": "0x41" }, { - "BriefDescription": "All retired load instructions.", + "BriefDescription": "Retired load instructions.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", @@ -311,12 +311,12 @@ "EventName": "MEM_INST_RETIRED.ALL_LOADS", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts all retired load instructions. This e= vent accounts for SW prefetch instructions for loads.", + "PublicDescription": "Counts all retired load instructions. This e= vent accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2= or PREFETCHW.", "SampleAfterValue": "1000003", "UMask": "0x81" }, { - "BriefDescription": "All retired store instructions.", + "BriefDescription": "Retired store instructions.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", @@ -325,7 +325,7 @@ "L1_Hit_Indication": "1", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts all retired store instructions. This = event account for SW prefetch instructions and PREFETCHW instruction for st= ores.", + "PublicDescription": "Counts all retired store instructions.", "SampleAfterValue": "1000003", "UMask": "0x82" }, diff --git a/tools/perf/pmu-events/arch/x86/icelake/floating-point.json b/t= ools/perf/pmu-events/arch/x86/icelake/floating-point.json index 4347e2d0d090..1925388969bb 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/icelake/floating-point.json @@ -99,4 +99,4 @@ "SampleAfterValue": "100003", "UMask": "0x2" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/icelake/frontend.json b/tools/p= erf/pmu-events/arch/x86/icelake/frontend.json index b510dd5d80da..739361d3f52f 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/frontend.json +++ b/tools/perf/pmu-events/arch/x86/icelake/frontend.json @@ -494,4 +494,4 @@ "Speculative": "1", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json b/tool= s/perf/pmu-events/arch/x86/icelake/icl-metrics.json index 622c392f59be..f0356d66a927 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json @@ -38,7 +38,7 @@ { "BriefDescription": "Fraction of Physical Core issue-slots utilize= d by this Logical Processor", "MetricExpr": "TOPDOWN.SLOTS / ( TOPDOWN.SLOTS / 2 ) if #SMT_on el= se 1", - "MetricGroup": "SMT", + "MetricGroup": "SMT;TmaL1", "MetricName": "Slots_Utilization" }, { @@ -61,24 +61,18 @@ "MetricName": "FLOPc" }, { - "BriefDescription": "Actual per-core usage of the Floating Point e= xecution units (regardless of the vector width)", + "BriefDescription": "Actual per-core usage of the Floating Point n= on-X87 execution units (regardless of precision or vector-width)", "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_I= NST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP= _ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_= DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.5= 12B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) ) / ( 2 * CPU= _CLK_UNHALTED.DISTRIBUTED )", "MetricGroup": "Cor;Flops;HPC", "MetricName": "FP_Arith_Utilization", - "PublicDescription": "Actual per-core usage of the Floating Point = execution units (regardless of the vector width). Values > 1 are possible d= ue to Fused-Multiply Add (FMA) counting." + "PublicDescription": "Actual per-core usage of the Floating Point = non-X87 execution units (regardless of precision or vector-width). Values >= 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; = [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less commo= n)." }, { - "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is at least 1 uop executed)", + "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per-core", "MetricExpr": "UOPS_EXECUTED.THREAD / (( UOPS_EXECUTED.CORE_CYCLES= _GE_1 / 2 ) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, - { - "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear)", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "IpMispredict" - }, { "BriefDescription": "Core actual clocks when any Logical Processor= is active on the Physical Core", "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED", @@ -169,12 +163,24 @@ "MetricName": "IpArith_AVX512", "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit i= nstruction (lower number means higher occurrence rate). May undercount due = to FMA double counting." }, + { + "BriefDescription": "Instructions per Software prefetch instructio= n (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrenc= e rate)", + "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umas= k\\=3D0xF@", + "MetricGroup": "Prefetches", + "MetricName": "IpSWPF" + }, { "BriefDescription": "Total number of retired Instructions, Sample = with: INST_RETIRED.PREC_DIST", "MetricExpr": "INST_RETIRED.ANY", "MetricGroup": "Summary;TmaL1", "MetricName": "Instructions" }, + { + "BriefDescription": "", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,c= mask\\=3D1@", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", + "MetricName": "Execute" + }, { "BriefDescription": "Average number of Uops issued by front-end wh= en it issued something", "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=3D1= @", @@ -194,11 +200,23 @@ "MetricName": "DSB_Coverage" }, { - "BriefDescription": "Number of Instructions per non-speculative DS= B miss", + "BriefDescription": "Average number of cycles of a switch from the= DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details= .", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu@DSB2MITE_SWI= TCHES.PENALTY_CYCLES\\,cmask\\=3D1\\,edge@", + "MetricGroup": "DSBmiss", + "MetricName": "DSB_Switch_Cost" + }, + { + "BriefDescription": "Number of Instructions per non-speculative DS= B miss (lower number means higher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", "MetricGroup": "DSBmiss;Fed", "MetricName": "IpDSB_Miss_Ret" }, + { + "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "IpMispredict" + }, { "BriefDescription": "Fraction of branches that are non-taken condi= tionals", "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_B= RANCHES", @@ -230,11 +248,10 @@ "MetricName": "Other_Branches" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load instructions (in core cycles)", + "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load operations (in core cycles)", "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS = + MEM_LOAD_RETIRED.FB_HIT )", "MetricGroup": "Mem;MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency", - "PublicDescription": "Actual Average Latency for L1 data-cache mis= s demand load instructions (in core cycles). Latency may be overestimated f= or multi-load instructions - e.g. repeat strings." + "MetricName": "Load_Miss_Real_Latency" }, { "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", @@ -242,30 +259,6 @@ "MetricGroup": "Mem;MemoryBound;MemoryBW", "MetricName": "MLP" }, - { - "BriefDescription": "Average data fill bandwidth to the L1 data ca= che [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW" - }, - { - "BriefDescription": "Average data fill bandwidth to the L2 cache [= GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW" - }, - { - "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW" - }, - { - "BriefDescription": "Average per-core data access bandwidth to the= L3 cache [GB / sec]", - "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / d= uration_time", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "L3_Cache_Access_BW" - }, { "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", @@ -285,13 +278,13 @@ "MetricName": "L2MPKI" }, { - "BriefDescription": "L2 cache misses per kilo instruction for all = request types (including speculative)", + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instru= ction for all request types (including speculative)", "MetricExpr": "1000 * ( ( OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_R= EQUESTS.DEMAND_DATA_RD ) + L2_RQSTS.ALL_DEMAND_MISS + L2_RQSTS.SWPF_MISS ) = / INST_RETIRED.ANY", "MetricGroup": "Mem;CacheMisses;Offcore", "MetricName": "L2MPKI_All" }, { - "BriefDescription": "L2 cache misses per kilo instruction for all = demand loads (including speculative)", + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instru= ction for all demand loads (including speculative)", "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.= ANY", "MetricGroup": "Mem;CacheMisses", "MetricName": "L2MPKI_Load" @@ -309,7 +302,7 @@ "MetricName": "L3MPKI" }, { - "BriefDescription": "Fill Buffer (FB) true hits per kilo instructi= ons for retired demand loads", + "BriefDescription": "Fill Buffer (FB) hits per kilo instructions f= or retired demand loads (L1D misses that merge into ongoing miss-handling e= ntries)", "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", "MetricGroup": "Mem;CacheMisses", "MetricName": "FB_HPKI" @@ -321,6 +314,54 @@ "MetricGroup": "Mem;MemoryTLB", "MetricName": "Page_Walks_Utilization" }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", + "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L1D_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 2 cache [GB / sec]", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L2_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L3_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-core data access bandwidth to the= L3 cache [GB / sec]", + "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / d= uration_time", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "L3_Cache_Access_BW" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L1 data cache [GB / sec]", + "MetricExpr": "(64 * L1D.REPLACEMENT / 1000000000 / duration_time)= ", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L1D_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L2 cache [GB / sec]", + "MetricExpr": "(64 * L2_LINES_IN.ALL / 1000000000 / duration_time)= ", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L2_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L3 cache [GB / sec]", + "MetricExpr": "(64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duratio= n_time)", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L3_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data access bandwidth to t= he L3 cache [GB / sec]", + "MetricExpr": "(64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / = duration_time)", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "L3_Cache_Access_BW_1T" + }, { "BriefDescription": "Average CPU Utilization", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", @@ -337,7 +378,8 @@ "BriefDescription": "Giga Floating Point Operations Per Second", "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_= ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_= DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RET= IRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE = + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.5= 12B_PACKED_SINGLE ) / 1000000000 ) / duration_time", "MetricGroup": "Cor;Flops;HPC", - "MetricName": "GFLOPs" + "MetricName": "GFLOPs", + "PublicDescription": "Giga Floating Point Operations Per Second. A= ggregate across all supported options of: FP precisions, scalar and vector = instructions, vector-width and AMX engine." }, { "BriefDescription": "Average Frequency Utilization relative nomina= l frequency", diff --git a/tools/perf/pmu-events/arch/x86/icelake/uncore-other.json b/too= ls/perf/pmu-events/arch/x86/icelake/uncore-other.json new file mode 100644 index 000000000000..e007b976547d --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/icelake/uncore-other.json @@ -0,0 +1,31 @@ +[ + { + "BriefDescription": "Number of entries allocated. Account for Any = type: e.g. Snoop, etc.", + "Counter": "1", + "EventCode": "0x84", + "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", + "PerPkg": "1", + "PublicDescription": "Number of entries allocated. Account for Any= type: e.g. Snoop, etc.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Total number of all outgoing entries allocate= d. Accounts for Coherent and non-coherent traffic.", + "Counter": "1", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.ALL", + "PerPkg": "1", + "PublicDescription": "Total number of all outgoing entries allocat= ed. Accounts for Coherent and non-coherent traffic.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "UNC_CLOCK.SOCKET", + "Counter": "FIXED", + "EventCode": "0xff", + "EventName": "UNC_CLOCK.SOCKET", + "PerPkg": "1", + "PublicDescription": "UNC_CLOCK.SOCKET", + "Unit": "CLOCK" + } +] diff --git a/tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json b/t= ools/perf/pmu-events/arch/x86/icelake/virtual-memory.json index a006fd7f7b18..58809e16bf98 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json @@ -242,4 +242,4 @@ "Speculative": "1", "UMask": "0x20" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index b602d2da1b89..898e507288a2 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -10,6 +10,7 @@ GenuineIntel-6-5[CF],v13,goldmont,core GenuineIntel-6-7A,v1.01,goldmontplus,core GenuineIntel-6-(3C|45|46),v31,haswell,core GenuineIntel-6-3F,v25,haswellx,core +GenuineIntel-6-(7D|7E|A7),v1.14,icelake,core GenuineIntel-6-3A,v18,ivybridge,core GenuineIntel-6-3E,v19,ivytown,core GenuineIntel-6-2D,v20,jaketown,core @@ -29,10 +30,7 @@ GenuineIntel-6-2C,v2,westmereep-dp,core GenuineIntel-6-25,v2,westmereep-sp,core GenuineIntel-6-2F,v2,westmereex,core GenuineIntel-6-55-[01234],v1,skylakex,core -GenuineIntel-6-7D,v1,icelake,core -GenuineIntel-6-7E,v1,icelake,core GenuineIntel-6-8[CD],v1,tigerlake,core -GenuineIntel-6-A7,v1,icelake,core GenuineIntel-6-6A,v1,icelakex,core GenuineIntel-6-6C,v1,icelakex,core GenuineIntel-6-86,v1,snowridgex,core --=20 2.37.1.359.gd136c6c3e2-goog From nobody Wed Apr 15 05:45:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36E2BC04A68 for ; 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Wed, 27 Jul 2022 15:09:18 -0700 (PDT) Date: Wed, 27 Jul 2022 15:08:15 -0700 In-Reply-To: <20220727220832.2865794-1-irogers@google.com> Message-Id: <20220727220832.2865794-14-irogers@google.com> Mime-Version: 1.0 References: <20220727220832.2865794-1-irogers@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH v3 13/30] perf vendor events: Update Intel icelakex From: Ian Rogers To: perry.taylor@intel.com, caleb.biggers@intel.com, kshipra.bopardikar@intel.com, Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Sedat Dilek Cc: Stephane Eranian , Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Update to v1.15, the metrics are based on TMA 4.4 full. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/downloa= d_and_gen.py to download and generate the latest events and metrics. Manually copy the icelakex files into perf and update mapfile.csv. Tested with 'perf test': 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok 90: perf all metricgroups test : Ok 91: perf all metrics test : Skip 93: perf all PMU test : Ok Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/icelakex/cache.json | 28 +- .../arch/x86/icelakex/floating-point.json | 2 +- .../arch/x86/icelakex/frontend.json | 2 +- .../arch/x86/icelakex/icx-metrics.json | 691 ++++++++++++++++-- .../pmu-events/arch/x86/icelakex/memory.json | 6 +- .../pmu-events/arch/x86/icelakex/other.json | 51 +- .../arch/x86/icelakex/pipeline.json | 12 + .../arch/x86/icelakex/virtual-memory.json | 2 +- tools/perf/pmu-events/arch/x86/mapfile.csv | 3 +- 9 files changed, 689 insertions(+), 108 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/icelakex/cache.json b/tools/per= f/pmu-events/arch/x86/icelakex/cache.json index 95fcbec188f8..775190bdd063 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/cache.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/cache.json @@ -291,7 +291,7 @@ "UMask": "0x4f" }, { - "BriefDescription": "All retired load instructions.", + "BriefDescription": "Retired load instructions.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", @@ -299,12 +299,12 @@ "EventName": "MEM_INST_RETIRED.ALL_LOADS", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts all retired load instructions. This e= vent accounts for SW prefetch instructions for loads.", + "PublicDescription": "Counts all retired load instructions. This e= vent accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2= or PREFETCHW.", "SampleAfterValue": "1000003", "UMask": "0x81" }, { - "BriefDescription": "All retired store instructions.", + "BriefDescription": "Retired store instructions.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", @@ -313,7 +313,7 @@ "L1_Hit_Indication": "1", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts all retired store instructions. This = event account for SW prefetch instructions and PREFETCHW instruction for st= ores.", + "PublicDescription": "Counts all retired store instructions.", "SampleAfterValue": "1000003", "UMask": "0x82" }, @@ -409,7 +409,6 @@ "PEBScounters": "0,1,2,3", "PublicDescription": "Counts retired load instructions whose data = sources were HitM responses from shared L3.", "SampleAfterValue": "20011", - "Speculative": "1", "UMask": "0x4" }, { @@ -473,7 +472,6 @@ "PEBScounters": "0,1,2,3", "PublicDescription": "Counts retired load instructions whose data = sources were L3 and cross-core snoop hits in on-pkg core cache.", "SampleAfterValue": "20011", - "Speculative": "1", "UMask": "0x2" }, { @@ -867,7 +865,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that hit= in the L3 or were snooped from another core's caches on the same socket.", + "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that hit in the L3 or were snooped from another core's caches on the sa= me socket.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.L3_HIT", @@ -878,7 +876,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that res= ulted in a snoop hit a modified line in another core's caches which forward= ed the data.", + "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that resulted in a snoop hit a modified line in another core's caches w= hich forwarded the data.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM", @@ -889,7 +887,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that res= ulted in a snoop that hit in another core, which did not forward the data.", + "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that resulted in a snoop that hit in another core, which did not forwar= d the data.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD", @@ -900,7 +898,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that res= ulted in a snoop hit in another core's caches which forwarded the unmodifie= d data to the requesting core.", + "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that resulted in a snoop hit in another core's caches which forwarded t= he unmodified data to the requesting core.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD", @@ -911,7 +909,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by a cache on a remote socket where a snoop was sent and data wa= s returned (Modified or Not Modified).", + "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by a cache on a remote socket where a snoop was sent= and data was returned (Modified or Not Modified).", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_FWD", @@ -922,7 +920,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by a cache on a remote socket where a snoop hit a modified line = in another core's caches which forwarded the data.", + "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by a cache on a remote socket where a snoop hit a mo= dified line in another core's caches which forwarded the data.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM", @@ -933,7 +931,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by a cache on a remote socket where a snoop hit in another core'= s caches which forwarded the unmodified data to the requesting core.", + "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by a cache on a remote socket where a snoop hit in a= nother core's caches which forwarded the unmodified data to the requesting = core.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD", @@ -944,7 +942,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that hit= a modified line in a distant L3 Cache or were snooped from a distant core'= s L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) = mode.", + "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that hit a modified line in a distant L3 Cache or were snooped from a d= istant core's L1/L2 caches on this socket when the system is in SNC (sub-NU= MA cluster) mode.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.SNC_CACHE.HITM", @@ -955,7 +953,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that eit= her hit a non-modified line in a distant L3 Cache or were snooped from a di= stant core's L1/L2 caches on this socket when the system is in SNC (sub-NUM= A cluster) mode.", + "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that either hit a non-modified line in a distant L3 Cache or were snoop= ed from a distant core's L1/L2 caches on this socket when the system is in = SNC (sub-NUMA cluster) mode.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.SNC_CACHE.HIT_WITH_FWD", diff --git a/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json b/= tools/perf/pmu-events/arch/x86/icelakex/floating-point.json index 4347e2d0d090..1925388969bb 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json @@ -99,4 +99,4 @@ "SampleAfterValue": "100003", "UMask": "0x2" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/icelakex/frontend.json b/tools/= perf/pmu-events/arch/x86/icelakex/frontend.json index f217c3211ba2..eb27d9d9c8be 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/frontend.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/frontend.json @@ -481,4 +481,4 @@ "Speculative": "1", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json b/too= ls/perf/pmu-events/arch/x86/icelakex/icx-metrics.json index be70672bfdb0..0abdfe433a2c 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json @@ -17,24 +17,6 @@ "MetricGroup": "Ret;Summary", "MetricName": "IPC" }, - { - "BriefDescription": "Uops Per Instruction", - "MetricExpr": "UOPS_RETIRED.SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Ret;Retire", - "MetricName": "UPI" - }, - { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "UOPS_RETIRED.SLOTS / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;FetchBW", - "MetricName": "UpTB" - }, - { - "BriefDescription": "Cycles Per Instruction (per Logical Processor= )", - "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", - "MetricGroup": "Pipeline;Mem", - "MetricName": "CPI" - }, { "BriefDescription": "Per-Logical Processor actual clocks when the = Logical Processor is active.", "MetricExpr": "CPU_CLK_UNHALTED.THREAD", @@ -50,7 +32,7 @@ { "BriefDescription": "Fraction of Physical Core issue-slots utilize= d by this Logical Processor", "MetricExpr": "TOPDOWN.SLOTS / ( TOPDOWN.SLOTS / 2 ) if #SMT_on el= se 1", - "MetricGroup": "SMT", + "MetricGroup": "SMT;TmaL1", "MetricName": "Slots_Utilization" }, { @@ -73,24 +55,18 @@ "MetricName": "FLOPc" }, { - "BriefDescription": "Actual per-core usage of the Floating Point e= xecution units (regardless of the vector width)", + "BriefDescription": "Actual per-core usage of the Floating Point n= on-X87 execution units (regardless of precision or vector-width)", "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_I= NST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP= _ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_= DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.5= 12B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) ) / ( 2 * CPU= _CLK_UNHALTED.DISTRIBUTED )", "MetricGroup": "Cor;Flops;HPC", "MetricName": "FP_Arith_Utilization", - "PublicDescription": "Actual per-core usage of the Floating Point = execution units (regardless of the vector width). Values > 1 are possible d= ue to Fused-Multiply Add (FMA) counting." + "PublicDescription": "Actual per-core usage of the Floating Point = non-X87 execution units (regardless of precision or vector-width). Values >= 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; = [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less commo= n)." }, { - "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is at least 1 uop executed)", + "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per-core", "MetricExpr": "UOPS_EXECUTED.THREAD / (( UOPS_EXECUTED.CORE_CYCLES= _GE_1 / 2 ) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, - { - "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear)", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "IpMispredict" - }, { "BriefDescription": "Core actual clocks when any Logical Processor= is active on the Physical Core", "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED", @@ -181,36 +157,54 @@ "MetricName": "IpArith_AVX512", "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit i= nstruction (lower number means higher occurrence rate). May undercount due = to FMA double counting." }, + { + "BriefDescription": "Instructions per Software prefetch instructio= n (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrenc= e rate)", + "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umas= k\\=3D0xF@", + "MetricGroup": "Prefetches", + "MetricName": "IpSWPF" + }, { "BriefDescription": "Total number of retired Instructions, Sample = with: INST_RETIRED.PREC_DIST", "MetricExpr": "INST_RETIRED.ANY", "MetricGroup": "Summary;TmaL1", "MetricName": "Instructions" }, + { + "BriefDescription": "", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,c= mask\\=3D1@", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", + "MetricName": "Execute" + }, { "BriefDescription": "Average number of Uops issued by front-end wh= en it issued something", "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=3D1= @", "MetricGroup": "Fed;FetchBW", "MetricName": "Fetch_UpC" }, - { - "BriefDescription": "Fraction of Uops delivered by the LSD (Loop S= tream Detector; aka Loop Cache)", - "MetricExpr": "LSD.UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS= + IDQ.MS_UOPS)", - "MetricGroup": "Fed;LSD", - "MetricName": "LSD_Coverage" - }, { "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_= UOPS + IDQ.MS_UOPS)", + "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.= MS_UOPS)", "MetricGroup": "DSB;Fed;FetchBW", "MetricName": "DSB_Coverage" }, { - "BriefDescription": "Number of Instructions per non-speculative DS= B miss", + "BriefDescription": "Average number of cycles of a switch from the= DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details= .", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu@DSB2MITE_SWI= TCHES.PENALTY_CYCLES\\,cmask\\=3D1\\,edge@", + "MetricGroup": "DSBmiss", + "MetricName": "DSB_Switch_Cost" + }, + { + "BriefDescription": "Number of Instructions per non-speculative DS= B miss (lower number means higher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", "MetricGroup": "DSBmiss;Fed", "MetricName": "IpDSB_Miss_Ret" }, + { + "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "IpMispredict" + }, { "BriefDescription": "Fraction of branches that are non-taken condi= tionals", "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_B= RANCHES", @@ -242,11 +236,10 @@ "MetricName": "Other_Branches" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load instructions (in core cycles)", + "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load operations (in core cycles)", "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS = + MEM_LOAD_RETIRED.FB_HIT )", "MetricGroup": "Mem;MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency", - "PublicDescription": "Actual Average Latency for L1 data-cache mis= s demand load instructions (in core cycles). Latency may be overestimated f= or multi-load instructions - e.g. repeat strings." + "MetricName": "Load_Miss_Real_Latency" }, { "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", @@ -254,30 +247,6 @@ "MetricGroup": "Mem;MemoryBound;MemoryBW", "MetricName": "MLP" }, - { - "BriefDescription": "Average data fill bandwidth to the L1 data ca= che [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW" - }, - { - "BriefDescription": "Average data fill bandwidth to the L2 cache [= GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW" - }, - { - "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW" - }, - { - "BriefDescription": "Average per-core data access bandwidth to the= L3 cache [GB / sec]", - "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / d= uration_time", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "L3_Cache_Access_BW" - }, { "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", @@ -297,13 +266,13 @@ "MetricName": "L2MPKI" }, { - "BriefDescription": "L2 cache misses per kilo instruction for all = request types (including speculative)", + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instru= ction for all request types (including speculative)", "MetricExpr": "1000 * ( ( OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_R= EQUESTS.DEMAND_DATA_RD ) + L2_RQSTS.ALL_DEMAND_MISS + L2_RQSTS.SWPF_MISS ) = / INST_RETIRED.ANY", "MetricGroup": "Mem;CacheMisses;Offcore", "MetricName": "L2MPKI_All" }, { - "BriefDescription": "L2 cache misses per kilo instruction for all = demand loads (including speculative)", + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instru= ction for all demand loads (including speculative)", "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.= ANY", "MetricGroup": "Mem;CacheMisses", "MetricName": "L2MPKI_Load" @@ -321,7 +290,7 @@ "MetricName": "L3MPKI" }, { - "BriefDescription": "Fill Buffer (FB) true hits per kilo instructi= ons for retired demand loads", + "BriefDescription": "Fill Buffer (FB) hits per kilo instructions f= or retired demand loads (L1D misses that merge into ongoing miss-handling e= ntries)", "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", "MetricGroup": "Mem;CacheMisses", "MetricName": "FB_HPKI" @@ -333,6 +302,30 @@ "MetricGroup": "Mem;MemoryTLB", "MetricName": "Page_Walks_Utilization" }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", + "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L1D_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 2 cache [GB / sec]", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L2_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L3_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-core data access bandwidth to the= L3 cache [GB / sec]", + "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / d= uration_time", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "L3_Cache_Access_BW" + }, { "BriefDescription": "Rate of silent evictions from the L2 cache pe= r Kilo instruction where the evicted lines are dropped (no writeback to L3 = or memory)", "MetricExpr": "1000 * L2_LINES_OUT.SILENT / INST_RETIRED.ANY", @@ -345,6 +338,30 @@ "MetricGroup": "L2Evicts;Mem;Server", "MetricName": "L2_Evictions_NonSilent_PKI" }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L1 data cache [GB / sec]", + "MetricExpr": "(64 * L1D.REPLACEMENT / 1000000000 / duration_time)= ", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L1D_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L2 cache [GB / sec]", + "MetricExpr": "(64 * L2_LINES_IN.ALL / 1000000000 / duration_time)= ", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L2_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L3 cache [GB / sec]", + "MetricExpr": "(64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duratio= n_time)", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L3_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data access bandwidth to t= he L3 cache [GB / sec]", + "MetricExpr": "(64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / = duration_time)", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "L3_Cache_Access_BW_1T" + }, { "BriefDescription": "Average CPU Utilization", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", @@ -361,7 +378,8 @@ "BriefDescription": "Giga Floating Point Operations Per Second", "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_= ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_= DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RET= IRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE = + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.5= 12B_PACKED_SINGLE ) / 1000000000 ) / duration_time", "MetricGroup": "Cor;Flops;HPC", - "MetricName": "GFLOPs" + "MetricName": "GFLOPs", + "PublicDescription": "Giga Floating Point Operations Per Second. A= ggregate across all supported options of: FP precisions, scalar and vector = instructions, vector-width and AMX engine." }, { "BriefDescription": "Average Frequency Utilization relative nomina= l frequency", @@ -497,5 +515,544 @@ "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C6_Pkg_Residency" + }, + { + "BriefDescription": "Percentage of time spent in the active CPU po= wer state C0", + "MetricExpr": "100 * CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricGroup": "", + "MetricName": "cpu_utilization_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "CPU operating frequency (in GHz)", + "MetricExpr": "(( CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_T= SC * #SYSTEM_TSC_FREQ ) / 1000000000) / duration_time", + "MetricGroup": "", + "MetricName": "cpu_operating_frequency", + "ScaleUnit": "1GHz" + }, + { + "BriefDescription": "Cycles per instruction retired; indicating ho= w much time each executed instruction took; in units of cycles.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "cpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "The ratio of number of completed memory load = instructions to the total number completed instructions", + "MetricExpr": "MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "loads_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "The ratio of number of completed memory store= instructions to the total number completed instructions", + "MetricExpr": "MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "stores_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of requests missing L1 data c= ache (includes data+rfo w/ prefetches) to the total number of completed ins= tructions", + "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l1d_mpi_includes_data_plus_rfo_with_prefetches", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of demand load requests hitti= ng in L1 data cache to the total number of completed instructions ", + "MetricExpr": "MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l1d_demand_data_read_hits_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read requests missing= in L1 instruction cache (includes prefetches) to the total number of compl= eted instructions", + "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed demand load requ= ests hitting in L2 cache to the total number of completed instructions ", + "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l2_demand_data_read_hits_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of requests missing L2 cache = (includes code+data+rfo w/ prefetches) to the total number of completed ins= tructions", + "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l2_mpi_includes_code_plus_data_plus_rfo_with_prefet= ches", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed data read reques= t missing L2 cache to the total number of completed instructions", + "MetricExpr": "MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l2_demand_data_read_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read request missing = L2 cache to the total number of completed instructions", + "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l2_demand_code_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of data read requests missing= last level core cache (includes demand w/ prefetches) to the total number = of completed instructions", + "MetricExpr": "( UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA + UNC_CHA= _TOR_INSERTS.IA_MISS_DRD + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF ) / INST_RE= TIRED.ANY", + "MetricGroup": "", + "MetricName": "llc_data_read_mpi_demand_plus_prefetch", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read requests missing= last level core cache (includes demand w/ prefetches) to the total number = of completed instructions", + "MetricExpr": "( UNC_CHA_TOR_INSERTS.IA_MISS_CRD ) / INST_RETIRED.= ANY", + "MetricGroup": "", + "MetricName": "llc_code_read_mpi_demand_plus_prefetch", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) d= emand data read miss (read memory access) in nano seconds", + "MetricExpr": "( ( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DR= D / UNC_CHA_TOR_INSERTS.IA_MISS_DRD ) / ( UNC_CHA_CLOCKTICKS / ( source_cou= nt(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD) * #num_packages ) ) ) * duration_time= )", + "MetricGroup": "", + "MetricName": "llc_demand_data_read_miss_latency", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) d= emand data read miss (read memory access) addressed to local memory in nano= seconds", + "MetricExpr": "( ( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DR= D_LOCAL / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL ) / ( UNC_CHA_CLOCKTICKS / = ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL) * #num_packages ) )= ) * duration_time )", + "MetricGroup": "", + "MetricName": "llc_demand_data_read_miss_latency_for_local_request= s", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) d= emand data read miss (read memory access) addressed to remote memory in nan= o seconds", + "MetricExpr": "( ( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DR= D_REMOTE / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE ) / ( UNC_CHA_CLOCKTICKS = / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE) * #num_packages = ) ) ) * duration_time )", + "MetricGroup": "", + "MetricName": "llc_demand_data_read_miss_latency_for_remote_reques= ts", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) d= emand data read miss (read memory access) addressed to Intel(R) Optane(TM) = Persistent Memory(PMEM) in nano seconds", + "MetricExpr": "( ( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DR= D_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM ) / ( UNC_CHA_CLOCKTICKS / ( so= urce_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM) * #num_packages ) ) ) * d= uration_time )", + "MetricGroup": "", + "MetricName": "llc_demand_data_read_miss_to_pmem_latency", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) d= emand data read miss (read memory access) addressed to DRAM in nano seconds= ", + "MetricExpr": "( ( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DR= D_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR ) / ( UNC_CHA_CLOCKTICKS / ( so= urce_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR) * #num_packages ) ) ) * d= uration_time )", + "MetricGroup": "", + "MetricName": "llc_demand_data_read_miss_to_dram_latency", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = all page sizes) caused by a code fetch to the total number of completed ins= tructions. This implies it missed in the ITLB (Instruction TLB) and further= levels of TLB.", + "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "itlb_2nd_level_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total n= umber of completed instructions. This implies it missed in the Instruction = Translation Lookaside Buffer (ITLB) and further levels of TLB.", + "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY= ", + "MetricGroup": "", + "MetricName": "itlb_2nd_level_large_page_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = all page sizes) caused by demand data loads to the total number of complete= d instructions. This implies it missed in the DTLB and further levels of TL= B.", + "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "dtlb_2nd_level_load_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = 2 megabyte page sizes) caused by demand data loads to the total number of c= ompleted instructions. This implies it missed in the Data Translation Looka= side Buffer (DTLB) and further levels of TLB.", + "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRE= D.ANY", + "MetricGroup": "", + "MetricName": "dtlb_2nd_level_2mb_large_page_load_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = all page sizes) caused by demand data stores to the total number of complet= ed instructions. This implies it missed in the DTLB and further levels of T= LB.", + "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY= ", + "MetricGroup": "", + "MetricName": "dtlb_2nd_level_store_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Memory read that miss the last level cache (L= LC) addressed to local DRAM as a percentage of total memory read accesses, = does not include LLC prefetches.", + "MetricExpr": "100 * ( UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC= _CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL ) / ( UNC_CHA_TOR_INSERTS.IA_MISS_D= RD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS= .IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE )", + "MetricGroup": "", + "MetricName": "numa_percent_reads_addressed_to_local_dram", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Memory reads that miss the last level cache (= LLC) addressed to remote DRAM as a percentage of total memory read accesses= , does not include LLC prefetches.", + "MetricExpr": "100 * ( UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UN= C_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE ) / ( UNC_CHA_TOR_INSERTS.IA_MISS= _DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSER= TS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE )", + "MetricGroup": "", + "MetricName": "numa_percent_reads_addressed_to_remote_dram", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Uncore operating frequency in GHz", + "MetricExpr": "( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_CLOCK= TICKS) * #num_packages ) / 1000000000) / duration_time", + "MetricGroup": "", + "MetricName": "uncore_frequency", + "ScaleUnit": "1GHz" + }, + { + "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data t= ransmit bandwidth (MB/sec)", + "MetricExpr": "( UNC_UPI_TxL_FLITS.ALL_DATA * (64 / 9.0) / 1000000= ) / duration_time", + "MetricGroup": "", + "MetricName": "upi_data_transmit_bw_only_data", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "DDR memory read bandwidth (MB/sec)", + "MetricExpr": "( UNC_M_CAS_COUNT.RD * 64 / 1000000) / duration_tim= e", + "MetricGroup": "", + "MetricName": "memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "DDR memory write bandwidth (MB/sec)", + "MetricExpr": "( UNC_M_CAS_COUNT.WR * 64 / 1000000) / duration_tim= e", + "MetricGroup": "", + "MetricName": "memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "DDR memory bandwidth (MB/sec)", + "MetricExpr": "(( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) * 64 /= 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "memory_bandwidth_total", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) m= emory read bandwidth (MB/sec)", + "MetricExpr": "( UNC_M_PMM_RPQ_INSERTS * 64 / 1000000) / duration_= time", + "MetricGroup": "", + "MetricName": "pmem_memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) m= emory write bandwidth (MB/sec)", + "MetricExpr": "( UNC_M_PMM_WPQ_INSERTS * 64 / 1000000) / duration_= time", + "MetricGroup": "", + "MetricName": "pmem_memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) m= emory bandwidth (MB/sec)", + "MetricExpr": "(( UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS ) = * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "pmem_memory_bandwidth_total", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO reads that are initiated by e= nd device controllers that are requesting memory from the CPU.", + "MetricExpr": "(( UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR + UNC_CHA_TO= R_INSERTS.IO_MISS_PCIRDCUR ) * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "io_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO writes that are initiated by = end device controllers that are writing memory to the CPU.", + "MetricExpr": "(( UNC_CHA_TOR_INSERTS.IO_HIT_ITOM + UNC_CHA_TOR_IN= SERTS.IO_MISS_ITOM + UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR + UNC_CHA_TOR= _INSERTS.IO_MISS_ITOMCACHENEAR ) * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "io_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Uops delivered from decoded instruction cache= (decoded stream buffer or DSB) as a percent of total uops delivered to Ins= truction Decode Queue", + "MetricExpr": "100 * ( IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UO= PS + IDQ.MS_UOPS + LSD.UOPS ) )", + "MetricGroup": "", + "MetricName": "percent_uops_delivered_from_decoded_icache_dsb", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Uops delivered from legacy decode pipeline (M= icro-instruction Translation Engine or MITE) as a percent of total uops del= ivered to Instruction Decode Queue", + "MetricExpr": "100 * ( IDQ.MITE_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_U= OPS + IDQ.MS_UOPS + LSD.UOPS ) )", + "MetricGroup": "", + "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline_= mite", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Uops delivered from microcode sequencer (MS) = as a percent of total uops delivered to Instruction Decode Queue", + "MetricExpr": "100 * ( IDQ.MS_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOP= S + IDQ.MS_UOPS + LSD.UOPS ) )", + "MetricGroup": "", + "MetricName": "percent_uops_delivered_from_microcode_sequencer_ms", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Bandwidth (MB/sec) of read requests that miss= the last level cache (LLC) and go to local memory.", + "MetricExpr": "( UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1000000) / du= ration_time", + "MetricGroup": "", + "MetricName": "llc_miss_local_memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth (MB/sec) of write requests that mis= s the last level cache (LLC) and go to local memory.", + "MetricExpr": "( UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1000000) / d= uration_time", + "MetricGroup": "", + "MetricName": "llc_miss_local_memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth (MB/sec) of read requests that miss= the last level cache (LLC) and go to remote memory.", + "MetricExpr": "( UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1000000) / d= uration_time", + "MetricGroup": "", + "MetricName": "llc_miss_remote_memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth (MB/sec) of write requests that mis= s the last level cache (LLC) and go to remote memory.", + "MetricExpr": "( UNC_CHA_REQUESTS.WRITES_REMOTE * 64 / 1000000) / = duration_time", + "MetricGroup": "", + "MetricName": "llc_miss_remote_memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend. Frontend denotes th= e first part of the processor core responsible to fetch operations that are= executed later on by the Backend part. Within the Frontend; a branch predi= ctor predicts the next address to fetch; cache-lines are fetched from the m= emory subsystem; parsed into instructions; and lastly decoded into micro-op= erations (uops). Ideally the Frontend can issue Machine_Width uops every cy= cle to the Backend. Frontend Bound denotes unutilized issue-slots when ther= e is no Backend stall; i.e. bubbles where Frontend delivered no uops while = Backend could have accepted them. For example; stalls due to instruction-ca= che misses would be categorized under Frontend Bound.", + "MetricExpr": "100 * ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bou= nd + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - I= NT_MISC.UOP_DROPPING / ( slots ) )", + "MetricGroup": "TmaL1;PGO", + "MetricName": "tma_frontend_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = CPU was stalled due to Frontend latency issues. For example; instruction-c= ache misses; iTLB misses or fetch stalls after a branch misprediction are c= ategorized under Frontend Latency. In such cases; the Frontend eventually d= elivers no uops for some period.", + "MetricExpr": "100 * ( ( ( 5 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_U= OPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / ( slots ) )", + "MetricGroup": "Frontend;TmaL2;m_tma_frontend_bound_percent", + "MetricName": "tma_fetch_latency_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to instruction cache misses.", + "MetricExpr": "100 * ( ICACHE_16B.IFDATA_STALL / ( CPU_CLK_UNHALTE= D.THREAD ) )", + "MetricGroup": "BigFoot;FetchLat;IcMiss;TmaL3;m_tma_fetch_latency_= percent", + "MetricName": "tma_icache_misses_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Instruction TLB (ITLB) misses.", + "MetricExpr": "100 * ( ICACHE_64B.IFTAG_STALL / ( CPU_CLK_UNHALTED= .THREAD ) )", + "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TmaL3;m_tma_fetch_laten= cy_percent", + "MetricName": "tma_itlb_misses_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Branch Resteers. Branch Resteers estimates the Fron= tend delay in fetching operations from corrected path; following all sorts = of miss-predicted branches. For example; branchy code with lots of miss-pre= dictions might get categorized under Branch Resteers. Note the value of thi= s node may overlap with its siblings.", + "MetricExpr": "100 * ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_U= NHALTED.THREAD ) + ( ( 10 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) = )", + "MetricGroup": "FetchLat;TmaL3;m_tma_fetch_latency_percent", + "MetricName": "tma_branch_resteers_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decod= ed i-cache) is a Uop Cache where the front-end directly delivers Uops (micr= o operations) avoiding heavy x86 decoding. The DSB pipeline has shorter lat= ency and delivered higher bandwidth than the MITE (legacy instruction decod= e pipeline). Switching between the two pipelines can cause penalties hence = this metric measures the exposed penalty.", + "MetricExpr": "100 * ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CL= K_UNHALTED.THREAD ) )", + "MetricGroup": "DSBmiss;FetchLat;TmaL3;m_tma_fetch_latency_percent= ", + "MetricName": "tma_dsb_switches_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU= was stalled due to Length Changing Prefixes (LCPs). Using proper compiler = flags or Intel Compiler by default will certainly avoid this. #Link: Optimi= zation Guide about LCP BKMs.", + "MetricExpr": "100 * ( ILD_STALL.LCP / ( CPU_CLK_UNHALTED.THREAD )= )", + "MetricGroup": "FetchLat;TmaL3;m_tma_fetch_latency_percent", + "MetricName": "tma_lcp_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates the fraction of cycles = when the CPU was stalled due to switches of uop delivery to the Microcode S= equencer (MS). Commonly used instructions are optimized for delivery by the= DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certa= in operations cannot be handled natively by the execution pipeline; and mus= t be performed by microcode (small programs injected into the execution str= eam). Switching to the MS too often can negatively impact performance. The = MS is designated to deliver long uop flows required by CISC instructions li= ke CPUID; or uncommon conditions like Floating Point Assists when dealing w= ith Denormals.", + "MetricExpr": "100 * ( ( 3 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTE= D.THREAD ) )", + "MetricGroup": "FetchLat;MicroSeq;TmaL3;m_tma_fetch_latency_percen= t", + "MetricName": "tma_ms_switches_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = CPU was stalled due to Frontend bandwidth issues. For example; inefficienc= ies at the instruction decoders; or restrictions for caching in the DSB (de= coded uops cache) are categorized under Fetch Bandwidth. In such cases; the= Frontend typically delivers suboptimal amount of uops to the Backend.", + "MetricExpr": "100 * ( max( 0 , ( topdown\\-fe\\-bound / ( topdown= \\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-= bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) - ( ( ( 5 ) * IDQ_UOPS_NOT_DE= LIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / ( slots ) ) ) = )", + "MetricGroup": "FetchBW;Frontend;TmaL2;m_tma_frontend_bound_percen= t", + "MetricName": "tma_fetch_bandwidth_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycle= s in which CPU was likely limited due to the MITE pipeline (the legacy deco= de pipeline). This pipeline is used for code that was not pre-cached in the= DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of= long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", + "MetricExpr": "100 * ( ( IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK = ) / ( CPU_CLK_UNHALTED.DISTRIBUTED ) / 2 )", + "MetricGroup": "DSBmiss;FetchBW;TmaL3;m_tma_fetch_bandwidth_percen= t", + "MetricName": "tma_mite_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycle= s in which CPU was likely limited due to DSB (decoded uop cache) fetch pipe= line. For example; inefficient utilization of the DSB cache structure or b= ank conflict when reading from it; are categorized here.", + "MetricExpr": "100 * ( ( IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK ) = / ( CPU_CLK_UNHALTED.DISTRIBUTED ) / 2 )", + "MetricGroup": "DSB;FetchBW;TmaL3;m_tma_fetch_bandwidth_percent", + "MetricName": "tma_dsb_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This category represents fraction of slots wa= sted due to incorrect speculations. This include slots used to issue uops t= hat do not eventually get retired and slots for which the issue-pipeline wa= s blocked due to recovery from earlier incorrect speculation. For example; = wasted work due to miss-predicted branches are categorized under Bad Specul= ation category. Incorrect data speculation followed by Memory Ordering Nuke= s is another example.", + "MetricExpr": "100 * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdo= wn\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\= \-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / = ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdow= n\\-be\\-bound ) + ( ( 5 ) * cpu@INT_MISC.RECOVERY_CYCLES\\,cmask\\=3D0x1\\= ,edge\\=3D0x1@ ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bo= und + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) = ) , 0 ) )", + "MetricGroup": "TmaL1", + "MetricName": "tma_bad_speculation_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Branch Misprediction. These slots are either wasted = by uops fetched from an incorrectly speculated program path; or stalls when= the out-of-order part of the machine needs to recover its state from a spe= culative path.", + "MetricExpr": "100 * ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_= RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-= fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-reti= ring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( top= down\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown= \\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * cpu@INT_MISC.RECOVERY_CYCL= ES\\,cmask\\=3D0x1\\,edge\\=3D0x1@ ) / ( slots ) ) + ( topdown\\-retiring /= ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdo= wn\\-be\\-bound ) ) ) , 0 ) ) )", + "MetricGroup": "BadSpec;BrMispredicts;TmaL2;m_tma_bad_speculation_= percent", + "MetricName": "tma_branch_mispredicts_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Machine Clears. These slots are either wasted by uop= s fetched prior to the clear; or stalls the out-of-order portion of the mac= hine needs to recover its state after the clear. For example; this can happ= en due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modify= ing-Code (SMC) nukes.", + "MetricExpr": "100 * ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-boun= d / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + to= pdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be= \\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiri= ng + topdown\\-be\\-bound ) + ( ( 5 ) * cpu@INT_MISC.RECOVERY_CYCLES\\,cmas= k\\=3D0x1\\,edge\\=3D0x1@ ) / ( slots ) ) + ( topdown\\-retiring / ( topdow= n\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\= -bound ) ) ) , 0 ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED= .ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bo= und / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + = topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-= be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-reti= ring + topdown\\-be\\-bound ) + ( ( 5 ) * cpu@INT_MISC.RECOVERY_CYCLES\\,cm= ask\\=3D0x1\\,edge\\=3D0x1@ ) / ( slots ) ) + ( topdown\\-retiring / ( topd= own\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be= \\-bound ) ) ) , 0 ) ) ) ) )", + "MetricGroup": "BadSpec;MachineClears;TmaL2;m_tma_bad_speculation_= percent", + "MetricName": "tma_machine_clears_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend. Backend is the portion of the processor cor= e where the out-of-order scheduler dispatches ready uops into their respect= ive execution units; and once completed these uops get retired according to= program order. For example; stalls due to data-cache misses or stalls due = to the divider unit being overloaded are both categorized under Backend Bou= nd. Backend Bound is further divided into two main categories: Memory Bound= and Core Bound.", + "MetricExpr": "100 * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bou= nd + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + (= ( 5 ) * cpu@INT_MISC.RECOVERY_CYCLES\\,cmask\\=3D0x1\\,edge\\=3D0x1@ ) / (= slots ) )", + "MetricGroup": "TmaL1", + "MetricName": "tma_backend_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = Memory subsystem within the Backend was a bottleneck. Memory Bound estimat= es fraction of slots where pipeline is likely stalled due to demand load or= store instructions. This accounts mainly for (1) non-completed in-flight m= emory demand loads which coincides with execution units starvation; in addi= tion to (2) cases where stores could impose backpressure on the pipeline wh= en many of them get buffered at the same time (less common out of the two).= ", + "MetricExpr": "100 * ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACT= IVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_= PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\= \-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_POR= TS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( t= opdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\= -be\\-bound ) + ( ( 5 ) * cpu@INT_MISC.RECOVERY_CYCLES\\,cmask\\=3D0x1\\,ed= ge\\=3D0x1@ ) / ( slots ) ) )", + "MetricGroup": "Backend;TmaL2;m_tma_backend_bound_percent", + "MetricName": "tma_memory_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was s= talled without loads missing the L1 data cache. The L1 data cache typicall= y has the shortest latency. However; in certain cases like loads blocked o= n older stores; a load might suffer due to high latency even though it is b= eing satisfied by the L1. Another example is loads who miss in the TLB. The= se cases are characterized by execution unit stalls; while some non-complet= ed demand load lives in the machine without having that demand load missing= the L1 cache.", + "MetricExpr": "100 * ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCL= E_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) )", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TmaL3;m_tma_memor= y_bound_percent", + "MetricName": "tma_l1_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was s= talled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 m= isses/L2 hits) can improve the latency and increase performance.", + "MetricExpr": "100 * ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_L= OAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) / ( ( MEM_LOAD_RETI= RED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS )= ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_= MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TmaL3;m_tma_memor= y_bound_percent", + "MetricName": "tma_l2_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was s= talled due to loads accesses to L3 cache or contended with a sibling Core. = Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and= increase performance.", + "MetricExpr": "100 * ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACT= IVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TmaL3;m_tma_memor= y_bound_percent", + "MetricName": "tma_l3_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was s= talled on accesses to external memory (DRAM) by loads. Better caching can i= mprove the latency and increase performance.", + "MetricExpr": "100 * ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / = ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_AC= TIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RE= TIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS= ) ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / = ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( = ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_= CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( ( 19 * ( MEM_LOAD_L3_M= ISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETI= RED.L1_MISS ) ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + = ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) + ( MEM_LOAD= _L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_= RETIRED.L1_MISS ) ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( = MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) / ( ( 19 *= ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT /= ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOC= AL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) = ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_H= IT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE= _HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) = ) ) ) + ( 25 * ( ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB= _HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + 33 * ( ( MEM_LOAD_L3_MISS_RET= IRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_M= ISS ) ) ) ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHAL= TED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L= 2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * = ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) / ( ( = MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETI= RED.L1_MISS ) ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVIT= Y.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.TH= READ ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + M= EM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1 )= ) ) ) ) , ( 1 ) ) )", + "MetricGroup": "MemoryBound;TmaL3mem;TmaL3;m_tma_memory_bound_perc= ent", + "MetricName": "tma_dram_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric roughly estimates (based on idle = latencies) how often the CPU was stalled on accesses to external 3D-Xpoint = (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memo= ry Module. ", + "MetricExpr": "100 * ( min( ( ( ( ( 1 - ( ( ( 19 * ( MEM_LOAD_L3_M= ISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETI= RED.L1_MISS ) ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + = ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) + ( MEM_LOAD= _L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_= RETIRED.L1_MISS ) ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( = MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) / ( ( 19 *= ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT /= ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOC= AL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) = ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_H= IT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE= _HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) = ) ) ) + ( 25 * ( ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB= _HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + 33 * ( ( MEM_LOAD_L3_MISS_RET= IRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_M= ISS ) ) ) ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHAL= TED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L= 2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * = ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) / ( ( = MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETI= RED.L1_MISS ) ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVIT= Y.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.TH= READ ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + M= EM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1 )= ) )", + "MetricGroup": "MemoryBound;Server;TmaL3mem;TmaL3;m_tma_memory_bou= nd_percent", + "MetricName": "tma_pmm_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates how often CPU was stall= ed due to RFO store memory accesses; RFO store issue a read-for-ownership = request before the write. Even though store accesses do not typically stall= out-of-order CPUs; there are few cases where stores can lead to actual sta= lls. This metric will be flagged should RFO stores be a bottleneck.", + "MetricExpr": "100 * ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UN= HALTED.THREAD ) )", + "MetricGroup": "MemoryBound;TmaL3mem;TmaL3;m_tma_memory_bound_perc= ent", + "MetricName": "tma_store_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e Core non-memory issues were of a bottleneck. Shortage in hardware comput= e resources; or dependencies in software's instructions are both categorize= d under Core Bound. Hence it may indicate the machine ran out of an out-of-= order resource; certain execution units are overloaded or dependencies in p= rogram's data- or instruction-flow are limiting the performance (e.g. FP-ch= ained long-latency arithmetic operations).", + "MetricExpr": "100 * ( max( 0 , ( topdown\\-be\\-bound / ( topdown= \\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-= bound ) + ( ( 5 ) * cpu@INT_MISC.RECOVERY_CYCLES\\,cmask\\=3D0x1\\,edge\\= =3D0x1@ ) / ( slots ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVIT= Y.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORT= S_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-sp= ec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_U= TIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdo= wn\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\= \-bound ) + ( ( 5 ) * cpu@INT_MISC.RECOVERY_CYCLES\\,cmask\\=3D0x1\\,edge\\= =3D0x1@ ) / ( slots ) ) ) ) )", + "MetricGroup": "Backend;TmaL2;Compute;m_tma_backend_bound_percent", + "MetricName": "tma_core_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles whe= re the Divider unit was active. Divide and square root instructions are per= formed by the Divider unit and can take considerably longer latency than in= teger or Floating Point addition; subtraction; or multiplication.", + "MetricExpr": "100 * ( ARITH.DIVIDER_ACTIVE / ( CPU_CLK_UNHALTED.T= HREAD ) )", + "MetricGroup": "TmaL3;m_tma_core_bound_percent", + "MetricName": "tma_divider_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired. Ideally= ; all pipeline slots would be attributed to the Retiring category. Retirin= g of 100% would indicate the maximum Pipeline_Width throughput was achieved= . Maximizing Retiring typically increases the Instructions-per-cycle (see = IPC metric). Note that a high Retiring value does not necessary mean there = is no room for more performance. For example; Heavy-operations or Microcod= e Assists are categorized under Retiring. They often indicate suboptimal pe= rformance and can often be optimized or avoided. ", + "MetricExpr": "( 100 * ( topdown\\-retiring / ( topdown\\-fe\\-bou= nd + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) )= + ( 0 * slots )", + "MetricGroup": "TmaL1", + "MetricName": "tma_retiring_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring light-weight operations -- instructions that require= no more than one uop (micro-operation). This correlates with total number = of instructions used by the program. A uops-per-instruction (see UPI metric= ) ratio of 1 or less should be expected for decently optimized software run= ning on Intel Core/Xeon products. While this often indicates efficient X86 = instructions were executed; high value does not necessarily mean better per= formance cannot be achieved.", + "MetricExpr": "100 * ( max( 0 , ( topdown\\-retiring / ( topdown\\= -fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bo= und ) ) - ( ( ( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\= -bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) /= UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( t= opdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\= -be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=3D0= x1@ ) / IDQ.MITE_UOPS ) ) )", + "MetricGroup": "Retire;TmaL2;m_tma_retiring_percent", + "MetricName": "tma_light_operations_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents overall arithmetic flo= ating-point (FP) operations fraction the CPU has executed (retired). Note t= his metric's value may exceed its parent due to use of \"Uops\" CountDomain= and FMA double-counting.", + "MetricExpr": "100 * ( ( ( topdown\\-retiring / ( topdown\\-fe\\-b= ound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) )= * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD ) + ( ( FP_ARITH_INST_RETIRED.S= CALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) / ( ( topdown\\-retiri= ng / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + t= opdown\\-be\\-bound ) ) * ( slots ) ) ) + ( min( ( ( FP_ARITH_INST_RETIRED.= 128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_IN= ST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + = FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKE= D_SINGLE ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-ba= d\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , = ( 1 ) ) ) )", + "MetricGroup": "HPC;TmaL3;m_tma_light_operations_percent", + "MetricName": "tma_fp_arith_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring memory operations -- uops for memory load or store a= ccesses.", + "MetricExpr": "100 * ( ( max( 0 , ( topdown\\-retiring / ( topdown= \\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-= bound ) ) - ( ( ( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown= \\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) )= / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / (= topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown= \\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\= =3D0x1@ ) / IDQ.MITE_UOPS ) ) ) * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY )= ", + "MetricGroup": "Pipeline;TmaL3;m_tma_light_operations_percent", + "MetricName": "tma_memory_operations_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring branch instructions.", + "MetricExpr": "100 * ( ( max( 0 , ( topdown\\-retiring / ( topdown= \\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-= bound ) ) - ( ( ( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown= \\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) )= / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / (= topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown= \\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\= =3D0x1@ ) / IDQ.MITE_UOPS ) ) ) * BR_INST_RETIRED.ALL_BRANCHES / ( ( topdow= n\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-re= tiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", + "MetricGroup": "Pipeline;TmaL3;m_tma_light_operations_percent", + "MetricName": "tma_branch_instructions_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring NOP (no op) instructions. Compilers often use NOPs f= or certain address alignments - e.g. start address of a function or loop bo= dy.", + "MetricExpr": "100 * ( ( max( 0 , ( topdown\\-retiring / ( topdown= \\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-= bound ) ) - ( ( ( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown= \\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) )= / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / (= topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown= \\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\= =3D0x1@ ) / IDQ.MITE_UOPS ) ) ) * INST_RETIRED.NOP / ( ( topdown\\-retiring= / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + top= down\\-be\\-bound ) ) * ( slots ) ) )", + "MetricGroup": "Pipeline;TmaL3;m_tma_light_operations_percent", + "MetricName": "tma_nop_instructions_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents the remaining light uo= ps fraction the CPU has executed - remaining means not covered by other sib= ling nodes. May undercount due to FMA double counting", + "MetricExpr": "100 * ( max( 0 , ( max( 0 , ( topdown\\-retiring / = ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdow= n\\-be\\-bound ) ) - ( ( ( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound = + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( = slots ) ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-ret= iring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring = + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,= cmask\\=3D0x1@ ) / IDQ.MITE_UOPS ) ) ) - ( ( ( ( topdown\\-retiring / ( top= down\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-b= e\\-bound ) ) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD ) + ( ( FP_ARITH_I= NST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) / ( ( top= down\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\= -retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( min( ( ( FP_ARITH_= INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE = + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PAC= KED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIR= ED.512B_PACKED_SINGLE ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound += topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( s= lots ) ) ) , ( 1 ) ) ) ) + ( ( max( 0 , ( topdown\\-retiring / ( topdown\\-= fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bou= nd ) ) - ( ( ( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-= bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) / = UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( to= pdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-= be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=3D0x= 1@ ) / IDQ.MITE_UOPS ) ) ) * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY ) + ( = ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-= spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( ( ( ( ( topdown\\-= retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiri= ng + topdown\\-be\\-bound ) ) * ( slots ) ) / UOPS_ISSUED.ANY ) * IDQ.MS_UO= PS / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\= \-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECOD= ED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=3D0x1@ ) / IDQ.MITE_UOPS ) ) ) * = BR_INST_RETIRED.ALL_BRANCHES / ( ( topdown\\-retiring / ( topdown\\-fe\\-bo= und + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) = * ( slots ) ) ) + ( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-boun= d + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - = ( ( ( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spe= c + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) / UOPS_ISSU= ED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-f= e\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-boun= d ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=3D0x1@ ) / ID= Q.MITE_UOPS ) ) ) * INST_RETIRED.NOP / ( ( topdown\\-retiring / ( topdown\\= -fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bo= und ) ) * ( slots ) ) ) ) ) )", + "MetricGroup": "Pipeline;TmaL3;m_tma_light_operations_percent", + "MetricName": "tma_other_light_ops_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring heavy-weight operations -- instructions that require= two or more uops or microcoded sequences. This highly-correlates with the = uop length of these instructions/sequences.", + "MetricExpr": "100 * ( ( ( ( ( topdown\\-retiring / ( topdown\\-fe= \\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound= ) ) * ( slots ) ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topd= own\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-= retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODE= D.DEC0\\,cmask\\=3D0x1@ ) / IDQ.MITE_UOPS )", + "MetricGroup": "Retire;TmaL2;m_tma_retiring_percent", + "MetricName": "tma_heavy_operations_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring instructions that that are decoder into two or up to= ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of= uops in such instructions.", + "MetricExpr": "100 * ( ( ( ( ( ( topdown\\-retiring / ( topdown\\-= fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bou= nd ) ) * ( slots ) ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( to= pdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\= \-retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECO= DED.DEC0\\,cmask\\=3D0x1@ ) / IDQ.MITE_UOPS ) - ( ( ( ( topdown\\-retiring = / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topd= own\\-be\\-bound ) ) * ( slots ) ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( sl= ots ) ) )", + "MetricGroup": "TmaL3;m_tma_heavy_operations_percent", + "MetricName": "tma_few_uops_instructions_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS= is used for CISC instructions not supported by the default decoders (like = repeat move strings; or CPUID); or by microcode assists used to address som= e operation modes (like in Floating Point assists). These cases can often b= e avoided.", + "MetricExpr": "100 * ( ( ( ( topdown\\-retiring / ( topdown\\-fe\\= -bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound )= ) * ( slots ) ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) )", + "MetricGroup": "MicroSeq;TmaL3;m_tma_heavy_operations_percent", + "MetricName": "tma_microcode_sequencer_percent", + "ScaleUnit": "1%" } ] diff --git a/tools/perf/pmu-events/arch/x86/icelakex/memory.json b/tools/pe= rf/pmu-events/arch/x86/icelakex/memory.json index 58b03a8a1b95..48e8d1102b9d 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/memory.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/memory.json @@ -306,7 +306,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e not supplied by the local socket's L1, L2, or L3 caches.", + "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were not supplied by the local socket's L1, L2, or L3 caches.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.L3_MISS", @@ -317,7 +317,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e not supplied by the local socket's L1, L2, or L3 caches and were supplied= by the local socket.", + "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were not supplied by the local socket's L1, L2, or L3 caches and w= ere supplied by the local socket.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL", @@ -328,7 +328,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that mis= sed the L3 Cache and were supplied by the local socket (DRAM or PMM), wheth= er or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM ac= cesses that are controlled by the close or distant SNC Cluster.", + "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that missed the L3 Cache and were supplied by the local socket (DRAM or= PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PM= M or DRAM accesses that are controlled by the close or distant SNC Cluster.= ", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL_SOCKET", diff --git a/tools/perf/pmu-events/arch/x86/icelakex/other.json b/tools/per= f/pmu-events/arch/x86/icelakex/other.json index c9bf6808ead7..919e620e7db8 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/other.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/other.json @@ -44,7 +44,6 @@ "PEBScounters": "0,1,2,3", "PublicDescription": "Counts responses to snoops indicating the li= ne will now be (I)nvalidated: removed from this core's cache, after the dat= a is forwarded back to the requestor and indicating the data was found unmo= dified in the (FE) Forward or Exclusive State in this cores caches cache. = A single snoop response from the core counts on all hyperthreads of the cor= e.", "SampleAfterValue": "1000003", - "Speculative": "1", "UMask": "0x20" }, { @@ -56,7 +55,6 @@ "PEBScounters": "0,1,2,3", "PublicDescription": "Counts responses to snoops indicating the li= ne will now be (I)nvalidated: removed from this core's caches, after the da= ta is forwarded back to the requestor, and indicating the data was found mo= dified(M) in this cores caches cache (aka HitM response). A single snoop r= esponse from the core counts on all hyperthreads of the core.", "SampleAfterValue": "1000003", - "Speculative": "1", "UMask": "0x10" }, { @@ -68,7 +66,6 @@ "PEBScounters": "0,1,2,3", "PublicDescription": "Counts responses to snoops indicating the li= ne will now be (I)nvalidated in this core's caches without being forwarded = back to the requestor. The line was in Forward, Shared or Exclusive (FSE) s= tate in this cores caches. A single snoop response from the core counts on= all hyperthreads of the core.", "SampleAfterValue": "1000003", - "Speculative": "1", "UMask": "0x2" }, { @@ -80,7 +77,6 @@ "PEBScounters": "0,1,2,3", "PublicDescription": "Counts responses to snoops indicating that t= he data was not found (IHitI) in this core's caches. A single snoop respons= e from the core counts on all hyperthreads of the Core.", "SampleAfterValue": "1000003", - "Speculative": "1", "UMask": "0x1" }, { @@ -92,7 +88,6 @@ "PEBScounters": "0,1,2,3", "PublicDescription": "Counts responses to snoops indicating the li= ne may be kept on this core in the (S)hared state, after the data is forwar= ded back to the requestor, initially the data was found in the cache in the= (FS) Forward or Shared state. A single snoop response from the core count= s on all hyperthreads of the core.", "SampleAfterValue": "1000003", - "Speculative": "1", "UMask": "0x40" }, { @@ -104,7 +99,6 @@ "PEBScounters": "0,1,2,3", "PublicDescription": "Counts responses to snoops indicating the li= ne may be kept on this core in the (S)hared state, after the data is forwar= ded back to the requestor, initially the data was found in the cache in the= (M)odified state. A single snoop response from the core counts on all hyp= erthreads of the core.", "SampleAfterValue": "1000003", - "Speculative": "1", "UMask": "0x8" }, { @@ -116,7 +110,6 @@ "PEBScounters": "0,1,2,3", "PublicDescription": "Counts responses to snoops indicating the li= ne was kept on this core in the (S)hared state, and that the data was found= unmodified but not forwarded back to the requestor, initially the data was= found in the cache in the (FSE) Forward, Shared state or Exclusive state. = A single snoop response from the core counts on all hyperthreads of the co= re.", "SampleAfterValue": "1000003", - "Speculative": "1", "UMask": "0x4" }, { @@ -428,7 +421,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that hav= e any type of response.", + "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that have any type of response.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.ANY_RESPONSE", @@ -439,7 +432,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by DRAM.", + "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by DRAM.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.DRAM", @@ -450,7 +443,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC)= Mode. In SNC Mode counts only those DRAM accesses that are controlled by = the close SNC Cluster.", + "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA = Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are co= ntrolled by the close SNC Cluster.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM", @@ -461,7 +454,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) = Mode. In SNC Mode counts only those PMM accesses that are controlled by th= e close SNC Cluster.", + "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by PMM attached to this socket, unless in Sub NUMA C= luster(SNC) Mode. In SNC Mode counts only those PMM accesses that are cont= rolled by the close SNC Cluster.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.LOCAL_PMM", @@ -472,7 +465,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by DRAM attached to this socket, whether or not in Sub NUMA Clus= ter(SNC) Mode. In SNC Mode counts DRAM accesses that are controlled by the= close or distant SNC Cluster.", + "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by DRAM attached to this socket, whether or not in S= ub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are contr= olled by the close or distant SNC Cluster.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_DRAM", @@ -483,7 +476,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by PMM attached to this socket, whether or not in Sub NUMA Clust= er(SNC) Mode. In SNC Mode counts PMM accesses that are controlled by the c= lose or distant SNC Cluster.", + "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by PMM attached to this socket, whether or not in Su= b NUMA Cluster(SNC) Mode. In SNC Mode counts PMM accesses that are control= led by the close or distant SNC Cluster.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_PMM", @@ -494,7 +487,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e not supplied by the local socket's L1, L2, or L3 caches and were supplied= by a remote socket.", + "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were not supplied by the local socket's L1, L2, or L3 caches and w= ere supplied by a remote socket.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.REMOTE", @@ -505,7 +498,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by DRAM attached to another socket.", + "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by DRAM attached to another socket.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.REMOTE_DRAM", @@ -516,7 +509,18 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by PMM attached to another socket.", + "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by DRAM or PMM attached to another socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.REMOTE_MEMORY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x731800477", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by PMM attached to another socket.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.REMOTE_PMM", @@ -527,7 +531,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by DRAM on a distant memory controller of this socket when the s= ystem is in SNC (sub-NUMA cluster) mode.", + "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by DRAM on a distant memory controller of this socke= t when the system is in SNC (sub-NUMA cluster) mode.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.SNC_DRAM", @@ -538,7 +542,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by PMM on a distant memory controller of this socket when the sy= stem is in SNC (sub-NUMA cluster) mode.", + "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by PMM on a distant memory controller of this socket= when the system is in SNC (sub-NUMA cluster) mode.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.SNC_PMM", @@ -558,5 +562,16 @@ "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand RFOs, ItoM's, PREFECTHW's, Hard= ware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted = in a store to Memory (DRAM or PMM)", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.WRITE_ESTIMATE.MEMORY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFBFF80822", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" } ] diff --git a/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json b/tools/= perf/pmu-events/arch/x86/icelakex/pipeline.json index 95c1008ef057..396868f70004 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json @@ -214,6 +214,18 @@ "SampleAfterValue": "50021", "UMask": "0x20" }, + { + "BriefDescription": "This event counts the number of mispredicted = ret instructions retired. Non PEBS", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.RET", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "This is a non-precise version (that is, does= not use PEBS) of the event that counts mispredicted return instructions re= tired.", + "SampleAfterValue": "50021", + "UMask": "0x8" + }, { "BriefDescription": "Cycle counts are evenly distributed between a= ctive threads in the Core.", "CollectPEBSRecord": "2", diff --git a/tools/perf/pmu-events/arch/x86/icelakex/virtual-memory.json b/= tools/perf/pmu-events/arch/x86/icelakex/virtual-memory.json index bc43ea855840..d70864da5c67 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/virtual-memory.json @@ -266,4 +266,4 @@ "Speculative": "1", "UMask": "0x20" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 898e507288a2..9a9593abd274 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -11,6 +11,7 @@ GenuineIntel-6-7A,v1.01,goldmontplus,core GenuineIntel-6-(3C|45|46),v31,haswell,core GenuineIntel-6-3F,v25,haswellx,core GenuineIntel-6-(7D|7E|A7),v1.14,icelake,core +GenuineIntel-6-6[AC],v1.15,icelakex,core GenuineIntel-6-3A,v18,ivybridge,core GenuineIntel-6-3E,v19,ivytown,core GenuineIntel-6-2D,v20,jaketown,core @@ -31,8 +32,6 @@ GenuineIntel-6-25,v2,westmereep-sp,core GenuineIntel-6-2F,v2,westmereex,core GenuineIntel-6-55-[01234],v1,skylakex,core GenuineIntel-6-8[CD],v1,tigerlake,core -GenuineIntel-6-6A,v1,icelakex,core -GenuineIntel-6-6C,v1,icelakex,core GenuineIntel-6-86,v1,snowridgex,core GenuineIntel-6-8F,v1,sapphirerapids,core AuthenticAMD-23-([12][0-9A-F]|[0-9A-F]),v2,amdzen1,core --=20 2.37.1.359.gd136c6c3e2-goog From nobody Wed Apr 15 05:45:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13EFEC04A68 for ; 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Wed, 27 Jul 2022 15:09:20 -0700 (PDT) Date: Wed, 27 Jul 2022 15:08:16 -0700 In-Reply-To: <20220727220832.2865794-1-irogers@google.com> Message-Id: <20220727220832.2865794-15-irogers@google.com> Mime-Version: 1.0 References: <20220727220832.2865794-1-irogers@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH v3 14/30] perf vendor events: Update Intel ivybridge From: Ian Rogers To: perry.taylor@intel.com, caleb.biggers@intel.com, kshipra.bopardikar@intel.com, Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Sedat Dilek Cc: Stephane Eranian , Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Update to v22, the metrics are based on TMA 4.4 full. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/downloa= d_and_gen.py to download and generate the latest events and metrics. Manually copy the ivybridge files into perf and update mapfile.csv. Tested on a non-ivybridge with 'perf test': 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/ivybridge/cache.json | 2 +- .../arch/x86/ivybridge/floating-point.json | 2 +- .../arch/x86/ivybridge/frontend.json | 2 +- .../arch/x86/ivybridge/ivb-metrics.json | 94 +++++++++++++------ .../pmu-events/arch/x86/ivybridge/memory.json | 2 +- .../pmu-events/arch/x86/ivybridge/other.json | 2 +- .../arch/x86/ivybridge/pipeline.json | 4 +- .../arch/x86/ivybridge/uncore-other.json | 2 +- .../arch/x86/ivybridge/virtual-memory.json | 2 +- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 10 files changed, 75 insertions(+), 39 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/cache.json b/tools/pe= rf/pmu-events/arch/x86/ivybridge/cache.json index 62e9705daa19..8adb2e45e23d 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/cache.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/cache.json @@ -1099,4 +1099,4 @@ "SampleAfterValue": "100003", "UMask": "0x10" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json b= /tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json index db8b1c4fceb0..4c2ac010cf55 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json @@ -166,4 +166,4 @@ "SampleAfterValue": "2000003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/frontend.json b/tools= /perf/pmu-events/arch/x86/ivybridge/frontend.json index c956a0a51312..2b1a82dd86ab 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/frontend.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/frontend.json @@ -312,4 +312,4 @@ "SampleAfterValue": "2000003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json b/to= ols/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json index 87670226f52d..3f48e75f8a86 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json @@ -130,17 +130,11 @@ "MetricName": "FLOPc_SMT" }, { - "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is at least 1 uop executed)", + "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per-core", "MetricExpr": "UOPS_EXECUTED.THREAD / (( cpu@UOPS_EXECUTED.CORE\\,= cmask\\=3D1@ / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, - { - "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear)", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "IpMispredict" - }, { "BriefDescription": "Core actual clocks when any Logical Processor= is active on the Physical Core", "MetricExpr": "( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_U= NHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", @@ -196,6 +190,18 @@ "MetricGroup": "Summary;TmaL1", "MetricName": "Instructions" }, + { + "BriefDescription": "Average number of Uops retired in cycles wher= e at least one uop has retired.", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE= _SLOTS\\,cmask\\=3D1@", + "MetricGroup": "Pipeline;Ret", + "MetricName": "Retire" + }, + { + "BriefDescription": "", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,c= mask\\=3D1@", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", + "MetricName": "Execute" + }, { "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MIT= E_UOPS + IDQ.MS_UOPS ) )", @@ -203,11 +209,16 @@ "MetricName": "DSB_Coverage" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load instructions (in core cycles)", + "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "IpMispredict" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load operations (in core cycles)", "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_= MISS + mem_load_uops_retired.hit_lfb )", "MetricGroup": "Mem;MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency", - "PublicDescription": "Actual Average Latency for L1 data-cache mis= s demand load instructions (in core cycles). Latency may be overestimated f= or multi-load instructions - e.g. repeat strings." + "MetricName": "Load_Miss_Real_Latency" }, { "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", @@ -215,24 +226,6 @@ "MetricGroup": "Mem;MemoryBound;MemoryBW", "MetricName": "MLP" }, - { - "BriefDescription": "Average data fill bandwidth to the L1 data ca= che [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW" - }, - { - "BriefDescription": "Average data fill bandwidth to the L2 cache [= GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW" - }, - { - "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW" - }, { "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED= .ANY", @@ -264,6 +257,48 @@ "MetricGroup": "Mem;MemoryTLB_SMT", "MetricName": "Page_Walks_Utilization_SMT" }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", + "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L1D_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 2 cache [GB / sec]", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L2_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L3_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L1 data cache [GB / sec]", + "MetricExpr": "(64 * L1D.REPLACEMENT / 1000000000 / duration_time)= ", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L1D_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L2 cache [GB / sec]", + "MetricExpr": "(64 * L2_LINES_IN.ALL / 1000000000 / duration_time)= ", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L2_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L3 cache [GB / sec]", + "MetricExpr": "(64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duratio= n_time)", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L3_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data access bandwidth to t= he L3 cache [GB / sec]", + "MetricExpr": "0", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "L3_Cache_Access_BW_1T" + }, { "BriefDescription": "Average CPU Utilization", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", @@ -280,7 +315,8 @@ "BriefDescription": "Giga Floating Point Operations Per Second", "MetricExpr": "( ( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_CO= MP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 = * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * S= IMD_FP_256.PACKED_SINGLE ) / 1000000000 ) / duration_time", "MetricGroup": "Cor;Flops;HPC", - "MetricName": "GFLOPs" + "MetricName": "GFLOPs", + "PublicDescription": "Giga Floating Point Operations Per Second. A= ggregate across all supported options of: FP precisions, scalar and vector = instructions, vector-width and AMX engine." }, { "BriefDescription": "Average Frequency Utilization relative nomina= l frequency", diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/memory.json b/tools/p= erf/pmu-events/arch/x86/ivybridge/memory.json index 5f98f7746cf7..30fc0af61eb3 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/memory.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/memory.json @@ -233,4 +233,4 @@ "SampleAfterValue": "100003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/other.json b/tools/pe= rf/pmu-events/arch/x86/ivybridge/other.json index 83fe8f79adc6..2d62521791d8 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/other.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/other.json @@ -41,4 +41,4 @@ "SampleAfterValue": "2000003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json b/tools= /perf/pmu-events/arch/x86/ivybridge/pipeline.json index 2de31c56c2a5..d89d3f8db190 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json @@ -676,7 +676,7 @@ "UMask": "0x3" }, { - "BriefDescription": "Number of occurences waiting for the checkpoi= nts in Resource Allocation Table (RAT) to be recovered after Nuke due to al= l other cases except JEClear (e.g. whenever a ucode assist is needed like S= SE exception, memory disambiguation, etc.)", + "BriefDescription": "Number of occurrences waiting for the checkpo= ints in Resource Allocation Table (RAT) to be recovered after Nuke due to a= ll other cases except JEClear (e.g. whenever a ucode assist is needed like = SSE exception, memory disambiguation, etc.)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", @@ -1269,4 +1269,4 @@ "SampleAfterValue": "2000003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/uncore-other.json b/t= ools/perf/pmu-events/arch/x86/ivybridge/uncore-other.json index 6278068908cf..88f1e326205f 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/uncore-other.json @@ -82,10 +82,10 @@ { "BriefDescription": "This 48-bit fixed counter counts the UCLK cyc= les.", "Counter": "Fixed", + "EventCode": "0xff", "EventName": "UNC_CLOCK.SOCKET", "PerPkg": "1", "PublicDescription": "This 48-bit fixed counter counts the UCLK cy= cles.", - "UMask": "0x01", "Unit": "ARB" } ] diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json b= /tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json index 8cf1549797b0..a5e387bbb134 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json @@ -177,4 +177,4 @@ "SampleAfterValue": "100007", "UMask": "0x20" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 9a9593abd274..dbb1197805d3 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -12,7 +12,7 @@ GenuineIntel-6-(3C|45|46),v31,haswell,core GenuineIntel-6-3F,v25,haswellx,core GenuineIntel-6-(7D|7E|A7),v1.14,icelake,core GenuineIntel-6-6[AC],v1.15,icelakex,core -GenuineIntel-6-3A,v18,ivybridge,core +GenuineIntel-6-3A,v22,ivybridge,core GenuineIntel-6-3E,v19,ivytown,core GenuineIntel-6-2D,v20,jaketown,core GenuineIntel-6-57,v9,knightslanding,core --=20 2.37.1.359.gd136c6c3e2-goog From nobody Wed Apr 15 05:45:07 2026 Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5D49C04A68 for ; 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Wed, 27 Jul 2022 15:09:23 -0700 (PDT) Date: Wed, 27 Jul 2022 15:08:17 -0700 In-Reply-To: <20220727220832.2865794-1-irogers@google.com> Message-Id: <20220727220832.2865794-16-irogers@google.com> Mime-Version: 1.0 References: <20220727220832.2865794-1-irogers@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH v3 15/30] perf vendor events: Update Intel ivytown From: Ian Rogers To: perry.taylor@intel.com, caleb.biggers@intel.com, kshipra.bopardikar@intel.com, Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Sedat Dilek Cc: Stephane Eranian , Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Update to v21, the metrics are based on TMA 4.4 full. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/downloa= d_and_gen.py to download and generate the latest events and metrics. Manually copy the ivytown files into perf and update mapfile.csv. Tested on a non-ivytown with 'perf test': 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/ivytown/cache.json | 2 +- .../arch/x86/ivytown/floating-point.json | 2 +- .../pmu-events/arch/x86/ivytown/frontend.json | 2 +- .../arch/x86/ivytown/ivt-metrics.json | 94 +- .../pmu-events/arch/x86/ivytown/memory.json | 2 +- .../pmu-events/arch/x86/ivytown/other.json | 2 +- .../arch/x86/ivytown/uncore-cache.json | 3495 ++++++++++++++++- .../arch/x86/ivytown/uncore-interconnect.json | 1750 ++++++++- .../arch/x86/ivytown/uncore-memory.json | 1775 ++++++++- .../arch/x86/ivytown/uncore-other.json | 2411 ++++++++++++ .../arch/x86/ivytown/uncore-power.json | 696 +++- .../arch/x86/ivytown/virtual-memory.json | 2 +- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 13 files changed, 9864 insertions(+), 371 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/ivytown/uncore-other.json diff --git a/tools/perf/pmu-events/arch/x86/ivytown/cache.json b/tools/perf= /pmu-events/arch/x86/ivytown/cache.json index 9bbf2bc59859..27576d53b347 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/cache.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/cache.json @@ -1257,4 +1257,4 @@ "SampleAfterValue": "100003", "UMask": "0x10" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/ivytown/floating-point.json b/t= ools/perf/pmu-events/arch/x86/ivytown/floating-point.json index db8b1c4fceb0..4c2ac010cf55 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/floating-point.json @@ -166,4 +166,4 @@ "SampleAfterValue": "2000003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/ivytown/frontend.json b/tools/p= erf/pmu-events/arch/x86/ivytown/frontend.json index c956a0a51312..2b1a82dd86ab 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/frontend.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/frontend.json @@ -312,4 +312,4 @@ "SampleAfterValue": "2000003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json b/tool= s/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json index 8d0ddcbd6c7c..782d68e1cd0d 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json @@ -130,17 +130,11 @@ "MetricName": "FLOPc_SMT" }, { - "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is at least 1 uop executed)", + "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per-core", "MetricExpr": "UOPS_EXECUTED.THREAD / (( cpu@UOPS_EXECUTED.CORE\\,= cmask\\=3D1@ / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, - { - "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear)", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "IpMispredict" - }, { "BriefDescription": "Core actual clocks when any Logical Processor= is active on the Physical Core", "MetricExpr": "( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_U= NHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", @@ -196,6 +190,18 @@ "MetricGroup": "Summary;TmaL1", "MetricName": "Instructions" }, + { + "BriefDescription": "Average number of Uops retired in cycles wher= e at least one uop has retired.", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE= _SLOTS\\,cmask\\=3D1@", + "MetricGroup": "Pipeline;Ret", + "MetricName": "Retire" + }, + { + "BriefDescription": "", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,c= mask\\=3D1@", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", + "MetricName": "Execute" + }, { "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MIT= E_UOPS + IDQ.MS_UOPS ) )", @@ -203,11 +209,16 @@ "MetricName": "DSB_Coverage" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load instructions (in core cycles)", + "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "IpMispredict" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load operations (in core cycles)", "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_= MISS + mem_load_uops_retired.hit_lfb )", "MetricGroup": "Mem;MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency", - "PublicDescription": "Actual Average Latency for L1 data-cache mis= s demand load instructions (in core cycles). Latency may be overestimated f= or multi-load instructions - e.g. repeat strings." + "MetricName": "Load_Miss_Real_Latency" }, { "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", @@ -215,24 +226,6 @@ "MetricGroup": "Mem;MemoryBound;MemoryBW", "MetricName": "MLP" }, - { - "BriefDescription": "Average data fill bandwidth to the L1 data ca= che [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW" - }, - { - "BriefDescription": "Average data fill bandwidth to the L2 cache [= GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW" - }, - { - "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW" - }, { "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED= .ANY", @@ -264,6 +257,48 @@ "MetricGroup": "Mem;MemoryTLB_SMT", "MetricName": "Page_Walks_Utilization_SMT" }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", + "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L1D_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 2 cache [GB / sec]", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L2_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L3_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L1 data cache [GB / sec]", + "MetricExpr": "(64 * L1D.REPLACEMENT / 1000000000 / duration_time)= ", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L1D_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L2 cache [GB / sec]", + "MetricExpr": "(64 * L2_LINES_IN.ALL / 1000000000 / duration_time)= ", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L2_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L3 cache [GB / sec]", + "MetricExpr": "(64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duratio= n_time)", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L3_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data access bandwidth to t= he L3 cache [GB / sec]", + "MetricExpr": "0", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "L3_Cache_Access_BW_1T" + }, { "BriefDescription": "Average CPU Utilization", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", @@ -280,7 +315,8 @@ "BriefDescription": "Giga Floating Point Operations Per Second", "MetricExpr": "( ( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_CO= MP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 = * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * S= IMD_FP_256.PACKED_SINGLE ) / 1000000000 ) / duration_time", "MetricGroup": "Cor;Flops;HPC", - "MetricName": "GFLOPs" + "MetricName": "GFLOPs", + "PublicDescription": "Giga Floating Point Operations Per Second. A= ggregate across all supported options of: FP precisions, scalar and vector = instructions, vector-width and AMX engine." }, { "BriefDescription": "Average Frequency Utilization relative nomina= l frequency", diff --git a/tools/perf/pmu-events/arch/x86/ivytown/memory.json b/tools/per= f/pmu-events/arch/x86/ivytown/memory.json index f904140203fe..99b71e43acad 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/memory.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/memory.json @@ -500,4 +500,4 @@ "SampleAfterValue": "100003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/ivytown/other.json b/tools/perf= /pmu-events/arch/x86/ivytown/other.json index 83fe8f79adc6..2d62521791d8 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/other.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/other.json @@ -41,4 +41,4 @@ "SampleAfterValue": "2000003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/ivytown/uncore-cache.json b/too= ls/perf/pmu-events/arch/x86/ivytown/uncore-cache.json index 267410594833..1e53bee8af5c 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/uncore-cache.json @@ -1,321 +1,3480 @@ [ { - "BriefDescription": "Uncore cache clock ticks", + "BriefDescription": "Uncore Clocks", "Counter": "0,1,2,3", "EventName": "UNC_C_CLOCKTICKS", "PerPkg": "1", "Unit": "CBO" }, { - "BriefDescription": "All LLC Misses (code+ data rd + data wr - inc= luding demand and prefetch)", + "BriefDescription": "Counter 0 Occupancy", + "Counter": "1,2,3", + "EventCode": "0x1f", + "EventName": "UNC_C_COUNTER0_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Since occupancy counts can only be captured = in the Cbo's 0 counter, this event allows a user to capture occupancy relat= ed information by filtering the Cb0 occupancy count captured in Counter 0. = The filtering available is found in the control register - threshold, inv= ert and edge detect. E.g. setting threshold to 1 can effectively monitor = how many cycles the monitored queue has an entry.", + "Unit": "CBO" + }, + { + "BriefDescription": "Cache Lookups; Any Request", "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.ANY", - "Filter": "filter_state=3D0x1", + "Filter": "CBoFilter0[23:17]", "PerPkg": "1", - "ScaleUnit": "64Bytes", + "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set filter mask bit 0 and select a sta= te or states to match. Otherwise, the event will count nothing. CBoGlCtr= l[22:17] bits correspond to [M'FMESI] state.; Filters for any transaction o= riginating from the IPQ or IRQ. This does not include lookups originating = from the ISMQ.", "UMask": "0x11", "Unit": "CBO" }, { - "BriefDescription": "M line evictions from LLC (writebacks to memo= ry)", + "BriefDescription": "Cache Lookups; Data Read Request", "Counter": "0,1", - "EventCode": "0x37", - "EventName": "UNC_C_LLC_VICTIMS.M_STATE", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.DATA_READ", + "Filter": "CBoFilter0[23:17]", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x1", + "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set filter mask bit 0 and select a sta= te or states to match. Otherwise, the event will count nothing. CBoGlCtr= l[22:17] bits correspond to [M'FMESI] state.; Read transactions", + "UMask": "0x3", "Unit": "CBO" }, { - "BriefDescription": "LLC misses - demand and prefetch data reads -= excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode.demand= ", + "BriefDescription": "Cache Lookups; Lookups that Match NID", "Counter": "0,1", - "EventCode": "0x35", - "EventName": "LLC_MISSES.DATA_READ", - "Filter": "filter_opc=3D0x182", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.NID", + "Filter": "CBoFilter0[23:17]", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", + "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set filter mask bit 0 and select a sta= te or states to match. Otherwise, the event will count nothing. CBoGlCtr= l[22:17] bits correspond to [M'FMESI] state.; Qualify one of the other sube= vents by the Target NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.n= id. In conjunction with STATE =3D I, it is possible to monitor misses to = specific NIDs in the system.", + "UMask": "0x41", "Unit": "CBO" }, { - "BriefDescription": "LLC misses - Uncacheable reads. Derived from = unc_c_tor_inserts.miss_opcode.uncacheable", + "BriefDescription": "Cache Lookups; External Snoop Request", "Counter": "0,1", - "EventCode": "0x35", - "EventName": "LLC_MISSES.UNCACHEABLE", - "Filter": "filter_opc=3D0x187", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP", + "Filter": "CBoFilter0[23:17]", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", + "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set filter mask bit 0 and select a sta= te or states to match. Otherwise, the event will count nothing. CBoGlCtr= l[22:17] bits correspond to [M'FMESI] state.; Filters for only snoop reques= ts coming from the remote socket(s) through the IPQ.", + "UMask": "0x9", "Unit": "CBO" }, { - "BriefDescription": "LLC prefetch misses for RFO. Derived from unc= _c_tor_inserts.miss_opcode.rfo_prefetch", + "BriefDescription": "Cache Lookups; Write Requests", "Counter": "0,1", - "EventCode": "0x35", - "EventName": "LLC_MISSES.RFO_LLC_PREFETCH", - "Filter": "filter_opc=3D0x190", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.WRITE", + "Filter": "CBoFilter0[23:17]", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", + "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set filter mask bit 0 and select a sta= te or states to match. Otherwise, the event will count nothing. CBoGlCtr= l[22:17] bits correspond to [M'FMESI] state.; Writeback transactions from L= 2 to the LLC This includes all write transactions -- both Cachable and UC.= ", + "UMask": "0x5", "Unit": "CBO" }, { - "BriefDescription": "LLC prefetch misses for code reads. Derived f= rom unc_c_tor_inserts.miss_opcode.code", + "BriefDescription": "Lines Victimized; Lines in E state", "Counter": "0,1", - "EventCode": "0x35", - "EventName": "LLC_MISSES.CODE_LLC_PREFETCH", - "Filter": "filter_opc=3D0x191", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.E_STATE", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", + "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x2", "Unit": "CBO" }, { - "BriefDescription": "LLC prefetch misses for data reads. Derived f= rom unc_c_tor_inserts.miss_opcode.data_read", + "BriefDescription": "Lines Victimized", "Counter": "0,1", - "EventCode": "0x35", - "EventName": "LLC_MISSES.DATA_LLC_PREFETCH", - "Filter": "filter_opc=3D0x192", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.MISS", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", + "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x8", "Unit": "CBO" }, { - "BriefDescription": "PCIe allocating writes that miss LLC - DDIO m= isses. Derived from unc_c_tor_inserts.miss_opcode.ddio_miss", + "BriefDescription": "Lines Victimized; Lines in M state", "Counter": "0,1", - "EventCode": "0x35", - "EventName": "LLC_MISSES.PCIE_WRITE", - "Filter": "filter_opc=3D0x19c", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.M_STATE", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", + "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x1", "Unit": "CBO" }, { - "BriefDescription": "LLC misses for PCIe read current. Derived fro= m unc_c_tor_inserts.miss_opcode.pcie_read", + "BriefDescription": "Lines Victimized; Victimized Lines that Match= NID", "Counter": "0,1", - "EventCode": "0x35", - "EventName": "LLC_MISSES.PCIE_READ", - "Filter": "filter_opc=3D0x19e", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.NID", + "Filter": "CBoFilter1[15:0]", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", + "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.; Qu= alify one of the other subevents by the Target NID. The NID is programmed = in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE =3D I, it is pos= sible to monitor misses to specific NIDs in the system.", + "UMask": "0x40", "Unit": "CBO" }, { - "BriefDescription": "LLC misses for ItoM writes (as part of fast s= tring memcpy stores). Derived from unc_c_tor_inserts.miss_opcode.itom_write= ", + "BriefDescription": "Lines Victimized; Lines in S State", "Counter": "0,1", - "EventCode": "0x35", - "EventName": "LLC_MISSES.ITOM_WRITE", - "Filter": "filter_opc=3D0x1c8", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.S_STATE", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", + "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x4", "Unit": "CBO" }, { - "BriefDescription": "LLC misses for PCIe non-snoop reads. Derived = from unc_c_tor_inserts.miss_opcode.pcie_read", + "BriefDescription": "Cbo Misc; RFO HitS", "Counter": "0,1", - "EventCode": "0x35", - "EventName": "LLC_MISSES.PCIE_NON_SNOOP_READ", - "Filter": "filter_opc=3D0x1e4", + "EventCode": "0x39", + "EventName": "UNC_C_MISC.RFO_HIT_S", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", + "PublicDescription": "Miscellaneous events in the Cbo.; Number of = times that an RFO hit in S state. This is useful for determining if it mig= ht be good for a workload to use RspIWB instead of RspSWB.", + "UMask": "0x8", "Unit": "CBO" }, { - "BriefDescription": "LLC misses for PCIe non-snoop writes (full li= ne). Derived from unc_c_tor_inserts.miss_opcode.pcie_write", + "BriefDescription": "Cbo Misc; Silent Snoop Eviction", "Counter": "0,1", - "EventCode": "0x35", - "EventName": "LLC_MISSES.PCIE_NON_SNOOP_WRITE", - "Filter": "filter_opc=3D0x1e6", + "EventCode": "0x39", + "EventName": "UNC_C_MISC.RSPI_WAS_FSE", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", + "PublicDescription": "Miscellaneous events in the Cbo.; Counts the= number of times when a Snoop hit in FSE states and triggered a silent evic= tion. This is useful because this information is lost in the PRE encodings= .", + "UMask": "0x1", "Unit": "CBO" }, { - "BriefDescription": "Streaming stores (full cache line). Derived f= rom unc_c_tor_inserts.opcode.streaming_full", + "BriefDescription": "Cbo Misc", "Counter": "0,1", - "EventCode": "0x35", - "EventName": "LLC_REFERENCES.STREAMING_FULL", - "Filter": "filter_opc=3D0x18c", + "EventCode": "0x39", + "EventName": "UNC_C_MISC.STARTED", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x1", + "PublicDescription": "Miscellaneous events in the Cbo.", + "UMask": "0x4", "Unit": "CBO" }, { - "BriefDescription": "Streaming stores (partial cache line). Derive= d from unc_c_tor_inserts.opcode.streaming_partial", + "BriefDescription": "Cbo Misc; Write Combining Aliasing", "Counter": "0,1", - "EventCode": "0x35", - "EventName": "LLC_REFERENCES.STREAMING_PARTIAL", - "Filter": "filter_opc=3D0x18d", + "EventCode": "0x39", + "EventName": "UNC_C_MISC.WC_ALIASING", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x1", + "PublicDescription": "Miscellaneous events in the Cbo.; Counts the= number of times that a USWC write (WCIL(F)) transaction hit in the LLC in = M state, triggering a WBMtoI followed by the USWC write. This occurs when = there is WC aliasing.", + "UMask": "0x2", "Unit": "CBO" }, { - "BriefDescription": "Partial PCIe reads. Derived from unc_c_tor_in= serts.opcode.pcie_partial", + "BriefDescription": "LRU Queue; LRU Age 0", "Counter": "0,1", - "EventCode": "0x35", - "EventName": "LLC_REFERENCES.PCIE_PARTIAL_READ", - "Filter": "filter_opc=3D0x195", + "EventCode": "0x3c", + "EventName": "UNC_C_QLRU.AGE0", "PerPkg": "1", - "ScaleUnit": "64Bytes", + "PublicDescription": "How often age was set to 0", "UMask": "0x1", "Unit": "CBO" }, { - "BriefDescription": "PCIe allocating writes that hit in LLC (DDIO = hits). Derived from unc_c_tor_inserts.opcode.ddio_hit", + "BriefDescription": "LRU Queue; LRU Age 1", "Counter": "0,1", - "EventCode": "0x35", - "EventName": "LLC_REFERENCES.PCIE_WRITE", - "Filter": "filter_opc=3D0x19c", + "EventCode": "0x3c", + "EventName": "UNC_C_QLRU.AGE1", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x1", + "PublicDescription": "How often age was set to 1", + "UMask": "0x2", "Unit": "CBO" }, { - "BriefDescription": "PCIe read current. Derived from unc_c_tor_ins= erts.opcode.pcie_read_current", + "BriefDescription": "LRU Queue; LRU Age 2", "Counter": "0,1", - "EventCode": "0x35", - "EventName": "LLC_REFERENCES.PCIE_READ", - "Filter": "filter_opc=3D0x19e", + "EventCode": "0x3c", + "EventName": "UNC_C_QLRU.AGE2", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x1", + "PublicDescription": "How often age was set to 2", + "UMask": "0x4", "Unit": "CBO" }, { - "BriefDescription": "ItoM write hits (as part of fast string memcp= y stores). Derived from unc_c_tor_inserts.opcode.itom_write_hit", + "BriefDescription": "LRU Queue; LRU Age 3", "Counter": "0,1", - "EventCode": "0x35", - "EventName": "LLC_REFERENCES.ITOM_WRITE", - "Filter": "filter_opc=3D0x1c8", + "EventCode": "0x3c", + "EventName": "UNC_C_QLRU.AGE3", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x1", + "PublicDescription": "How often age was set to 3", + "UMask": "0x8", "Unit": "CBO" }, { - "BriefDescription": "PCIe non-snoop reads. Derived from unc_c_tor_= inserts.opcode.pcie_read", + "BriefDescription": "LRU Queue; LRU Bits Decremented", "Counter": "0,1", - "EventCode": "0x35", - "EventName": "LLC_REFERENCES.PCIE_NS_READ", - "Filter": "filter_opc=3D0x1e4", + "EventCode": "0x3c", + "EventName": "UNC_C_QLRU.LRU_DECREMENT", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x1", + "PublicDescription": "How often all LRU bits were decremented by 1= ", + "UMask": "0x10", "Unit": "CBO" }, { - "BriefDescription": "PCIe non-snoop writes (partial). Derived from= unc_c_tor_inserts.opcode.pcie_partial_write", + "BriefDescription": "LRU Queue; Non-0 Aged Victim", "Counter": "0,1", - "EventCode": "0x35", - "EventName": "LLC_REFERENCES.PCIE_NS_PARTIAL_WRITE", - "Filter": "filter_opc=3D0x1e5", + "EventCode": "0x3c", + "EventName": "UNC_C_QLRU.VICTIM_NON_ZERO", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x1", + "PublicDescription": "How often we picked a victim that had a non-= zero age", + "UMask": "0x20", "Unit": "CBO" }, { - "BriefDescription": "PCIe non-snoop writes (full line). Derived fr= om unc_c_tor_inserts.opcode.pcie_full_write", - "Counter": "0,1", - "EventCode": "0x35", - "EventName": "LLC_REFERENCES.PCIE_NS_WRITE", - "Filter": "filter_opc=3D0x1e6", + "BriefDescription": "AD Ring In Use; Counterclockwise", + "Counter": "2,3", + "EventCode": "0x1B", + "EventName": "UNC_C_RING_AD_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop. We really have two rings in JKT -- a clockwis= e ring and a counter-clockwise ring. On the left side of the ring, the UP = direction is on the clockwise ring and DN is on the counter-clockwise ring.= On the right side of the ring, this is reversed. The first half of the C= Bos are on the left side of the ring, and the 2nd half are on the right sid= e of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is = NOT the same ring as CBo 2 UP AD because they are on opposite sides of the = ring.", + "UMask": "0xC", + "Unit": "CBO" + }, + { + "BriefDescription": "AD Ring In Use; Clockwise", + "Counter": "2,3", + "EventCode": "0x1B", + "EventName": "UNC_C_RING_AD_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop. We really have two rings in JKT -- a clockwis= e ring and a counter-clockwise ring. On the left side of the ring, the UP = direction is on the clockwise ring and DN is on the counter-clockwise ring.= On the right side of the ring, this is reversed. The first half of the C= Bos are on the left side of the ring, and the 2nd half are on the right sid= e of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is = NOT the same ring as CBo 2 UP AD because they are on opposite sides of the = ring.", + "UMask": "0x3", + "Unit": "CBO" + }, + { + "BriefDescription": "AD Ring In Use; Down", + "Counter": "2,3", + "EventCode": "0x1B", + "EventName": "UNC_C_RING_AD_USED.DOWN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop. We really have two rings in JKT -- a clockwis= e ring and a counter-clockwise ring. On the left side of the ring, the UP = direction is on the clockwise ring and DN is on the counter-clockwise ring.= On the right side of the ring, this is reversed. The first half of the C= Bos are on the left side of the ring, and the 2nd half are on the right sid= e of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is = NOT the same ring as CBo 2 UP AD because they are on opposite sides of the = ring.", + "UMask": "0xCC", + "Unit": "CBO" + }, + { + "BriefDescription": "AD Ring In Use; Down and Even on Vring 0", + "Counter": "2,3", + "EventCode": "0x1b", + "EventName": "UNC_C_RING_AD_USED.DOWN_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop. We really have two rings in JKT -- a clockwis= e ring and a counter-clockwise ring. On the left side of the ring, the UP = direction is on the clockwise ring and DN is on the counter-clockwise ring.= On the right side of the ring, this is reversed. The first half of the C= Bos are on the left side of the ring, and the 2nd half are on the right sid= e of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is = NOT the same ring as CBo 2 UP AD because they are on opposite sides of the = ring.; Filters for the Down and Even ring polarity on Virtual Ring 0.", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "AD Ring In Use; Down and Odd on Vring 0", + "Counter": "2,3", + "EventCode": "0x1b", + "EventName": "UNC_C_RING_AD_USED.DOWN_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop. We really have two rings in JKT -- a clockwis= e ring and a counter-clockwise ring. On the left side of the ring, the UP = direction is on the clockwise ring and DN is on the counter-clockwise ring.= On the right side of the ring, this is reversed. The first half of the C= Bos are on the left side of the ring, and the 2nd half are on the right sid= e of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is = NOT the same ring as CBo 2 UP AD because they are on opposite sides of the = ring.; Filters for the Down and Odd ring polarity on Virtual Ring 0.", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "AD Ring In Use; Down and Even on VRing 1", + "Counter": "2,3", + "EventCode": "0x1b", + "EventName": "UNC_C_RING_AD_USED.DOWN_VR1_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop. We really have two rings in JKT -- a clockwis= e ring and a counter-clockwise ring. On the left side of the ring, the UP = direction is on the clockwise ring and DN is on the counter-clockwise ring.= On the right side of the ring, this is reversed. The first half of the C= Bos are on the left side of the ring, and the 2nd half are on the right sid= e of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is = NOT the same ring as CBo 2 UP AD because they are on opposite sides of the = ring.; Filters for the Down and Even ring polarity on Virtual Ring 1.", + "UMask": "0x40", + "Unit": "CBO" + }, + { + "BriefDescription": "AD Ring In Use; Down and Odd on VRing 1", + "Counter": "2,3", + "EventCode": "0x1b", + "EventName": "UNC_C_RING_AD_USED.DOWN_VR1_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop. We really have two rings in JKT -- a clockwis= e ring and a counter-clockwise ring. On the left side of the ring, the UP = direction is on the clockwise ring and DN is on the counter-clockwise ring.= On the right side of the ring, this is reversed. The first half of the C= Bos are on the left side of the ring, and the 2nd half are on the right sid= e of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is = NOT the same ring as CBo 2 UP AD because they are on opposite sides of the = ring.; Filters for the Down and Odd ring polarity on Virtual Ring 1.", + "UMask": "0x80", + "Unit": "CBO" + }, + { + "BriefDescription": "AD Ring In Use; Up", + "Counter": "2,3", + "EventCode": "0x1B", + "EventName": "UNC_C_RING_AD_USED.UP", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop. We really have two rings in JKT -- a clockwis= e ring and a counter-clockwise ring. On the left side of the ring, the UP = direction is on the clockwise ring and DN is on the counter-clockwise ring.= On the right side of the ring, this is reversed. The first half of the C= Bos are on the left side of the ring, and the 2nd half are on the right sid= e of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is = NOT the same ring as CBo 2 UP AD because they are on opposite sides of the = ring.", + "UMask": "0x33", + "Unit": "CBO" + }, + { + "BriefDescription": "AD Ring In Use; Up and Even on Vring 0", + "Counter": "2,3", + "EventCode": "0x1b", + "EventName": "UNC_C_RING_AD_USED.UP_VR0_EVEN", "PerPkg": "1", - "ScaleUnit": "64Bytes", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop. We really have two rings in JKT -- a clockwis= e ring and a counter-clockwise ring. On the left side of the ring, the UP = direction is on the clockwise ring and DN is on the counter-clockwise ring.= On the right side of the ring, this is reversed. The first half of the C= Bos are on the left side of the ring, and the 2nd half are on the right sid= e of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is = NOT the same ring as CBo 2 UP AD because they are on opposite sides of the = ring.; Filters for the Up and Even ring polarity on Virtual Ring 0.", "UMask": "0x1", "Unit": "CBO" }, { - "BriefDescription": "Occupancy for all LLC misses that are address= ed to local memory", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL", + "BriefDescription": "AD Ring In Use; Up and Odd on Vring 0", + "Counter": "2,3", + "EventCode": "0x1b", + "EventName": "UNC_C_RING_AD_USED.UP_VR0_ODD", "PerPkg": "1", - "UMask": "0x2A", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop. We really have two rings in JKT -- a clockwis= e ring and a counter-clockwise ring. On the left side of the ring, the UP = direction is on the clockwise ring and DN is on the counter-clockwise ring.= On the right side of the ring, this is reversed. The first half of the C= Bos are on the left side of the ring, and the 2nd half are on the right sid= e of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is = NOT the same ring as CBo 2 UP AD because they are on opposite sides of the = ring.; Filters for the Up and Odd ring polarity on Virtual Ring 0.", + "UMask": "0x2", "Unit": "CBO" }, { - "BriefDescription": "Occupancy counter for LLC data reads (demand = and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode.llc_data_rea= d", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.LLC_DATA_READ", - "Filter": "filter_opc=3D0x182", + "BriefDescription": "AD Ring In Use; Up and Even on VRing 1", + "Counter": "2,3", + "EventCode": "0x1b", + "EventName": "UNC_C_RING_AD_USED.UP_VR1_EVEN", "PerPkg": "1", - "UMask": "0x3", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop. We really have two rings in JKT -- a clockwis= e ring and a counter-clockwise ring. On the left side of the ring, the UP = direction is on the clockwise ring and DN is on the counter-clockwise ring.= On the right side of the ring, this is reversed. The first half of the C= Bos are on the left side of the ring, and the 2nd half are on the right sid= e of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is = NOT the same ring as CBo 2 UP AD because they are on opposite sides of the = ring.; Filters for the Up and Even ring polarity on Virtual Ring 1.", + "UMask": "0x10", "Unit": "CBO" }, { - "BriefDescription": "Occupancy for all LLC misses that are address= ed to remote memory", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE", + "BriefDescription": "AD Ring In Use; Up and Odd on VRing 1", + "Counter": "2,3", + "EventCode": "0x1b", + "EventName": "UNC_C_RING_AD_USED.UP_VR1_ODD", "PerPkg": "1", - "UMask": "0x8A", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop. We really have two rings in JKT -- a clockwis= e ring and a counter-clockwise ring. On the left side of the ring, the UP = direction is on the clockwise ring and DN is on the counter-clockwise ring.= On the right side of the ring, this is reversed. The first half of the C= Bos are on the left side of the ring, and the 2nd half are on the right sid= e of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is = NOT the same ring as CBo 2 UP AD because they are on opposite sides of the = ring.; Filters for the Up and Odd ring polarity on Virtual Ring 1.", + "UMask": "0x20", "Unit": "CBO" }, { - "BriefDescription": "Read requests to home agent", - "Counter": "0,1,2,3", - "EventCode": "0x1", - "EventName": "UNC_H_REQUESTS.READS", + "BriefDescription": "AK Ring In Use; Counterclockwise", + "Counter": "2,3", + "EventCode": "0x1C", + "EventName": "UNC_C_RING_AK_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in JKT -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.", + "UMask": "0xC", + "Unit": "CBO" + }, + { + "BriefDescription": "AK Ring In Use; Clockwise", + "Counter": "2,3", + "EventCode": "0x1C", + "EventName": "UNC_C_RING_AK_USED.CW", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in JKT -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.", "UMask": "0x3", - "Unit": "HA" + "Unit": "CBO" }, { - "BriefDescription": "Write requests to home agent", - "Counter": "0,1,2,3", - "EventCode": "0x1", - "EventName": "UNC_H_REQUESTS.WRITES", + "BriefDescription": "AK Ring In Use; Down", + "Counter": "2,3", + "EventCode": "0x1C", + "EventName": "UNC_C_RING_AK_USED.DOWN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in JKT -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.", + "UMask": "0xCC", + "Unit": "CBO" + }, + { + "BriefDescription": "AK Ring In Use; Down and Even on Vring 0", + "Counter": "2,3", + "EventCode": "0x1c", + "EventName": "UNC_C_RING_AK_USED.DOWN_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in JKT -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.; Filters for the Down and Even ring polarity on Virtual Ring 0.", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "AK Ring In Use; Down and Odd on Vring 0", + "Counter": "2,3", + "EventCode": "0x1c", + "EventName": "UNC_C_RING_AK_USED.DOWN_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in JKT -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.; Filters for the Down and Odd ring polarity on Virtual Ring 0.", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "AK Ring In Use; Down and Even on VRing 1", + "Counter": "2,3", + "EventCode": "0x1c", + "EventName": "UNC_C_RING_AK_USED.DOWN_VR1_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in JKT -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.; Filters for the Down and Even ring polarity on Virtual Ring 1.", + "UMask": "0x40", + "Unit": "CBO" + }, + { + "BriefDescription": "AK Ring In Use; Down and Odd on VRing 1", + "Counter": "2,3", + "EventCode": "0x1c", + "EventName": "UNC_C_RING_AK_USED.DOWN_VR1_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in JKT -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.; Filters for the Down and Odd ring polarity on Virtual Ring 1.", + "UMask": "0x80", + "Unit": "CBO" + }, + { + "BriefDescription": "AK Ring In Use; Up", + "Counter": "2,3", + "EventCode": "0x1C", + "EventName": "UNC_C_RING_AK_USED.UP", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in JKT -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.", + "UMask": "0x33", + "Unit": "CBO" + }, + { + "BriefDescription": "AK Ring In Use; Up and Even on Vring 0", + "Counter": "2,3", + "EventCode": "0x1c", + "EventName": "UNC_C_RING_AK_USED.UP_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in JKT -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.; Filters for the Up and Even ring polarity on Virtual Ring 0.", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "AK Ring In Use; Up and Odd on Vring 0", + "Counter": "2,3", + "EventCode": "0x1c", + "EventName": "UNC_C_RING_AK_USED.UP_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in JKT -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.; Filters for the Up and Odd ring polarity on Virtual Ring 0.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "AK Ring In Use; Up and Even on VRing 1", + "Counter": "2,3", + "EventCode": "0x1c", + "EventName": "UNC_C_RING_AK_USED.UP_VR1_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in JKT -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.; Filters for the Up and Even ring polarity on Virtual Ring 1.", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "AK Ring In Use; Up and Odd on VRing 1", + "Counter": "2,3", + "EventCode": "0x1c", + "EventName": "UNC_C_RING_AK_USED.UP_VR1_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in JKT -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.; Filters for the Up and Odd ring polarity on Virtual Ring 1.", + "UMask": "0x20", + "Unit": "CBO" + }, + { + "BriefDescription": "BL Ring in Use; Counterclockwise", + "Counter": "2,3", + "EventCode": "0x1D", + "EventName": "UNC_C_RING_BL_USED.CCW", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in JKT -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.", "UMask": "0xC", - "Unit": "HA" + "Unit": "CBO" }, { - "BriefDescription": "M line forwarded from remote cache along with= writeback to memory", - "Counter": "0,1,2,3", - "EventCode": "0x21", - "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB", + "BriefDescription": "BL Ring in Use; Clockwise", + "Counter": "2,3", + "EventCode": "0x1D", + "EventName": "UNC_C_RING_BL_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in JKT -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.", + "UMask": "0x3", + "Unit": "CBO" + }, + { + "BriefDescription": "BL Ring in Use; Down", + "Counter": "2,3", + "EventCode": "0x1D", + "EventName": "UNC_C_RING_BL_USED.DOWN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in JKT -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.", + "UMask": "0xCC", + "Unit": "CBO" + }, + { + "BriefDescription": "BL Ring in Use; Down and Even on Vring 0", + "Counter": "2,3", + "EventCode": "0x1d", + "EventName": "UNC_C_RING_BL_USED.DOWN_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in JKT -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.; Filters for the Down and Even ring polarity on Virtual Ring 0.", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "BL Ring in Use; Down and Odd on Vring 0", + "Counter": "2,3", + "EventCode": "0x1d", + "EventName": "UNC_C_RING_BL_USED.DOWN_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in JKT -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.; Filters for the Down and Odd ring polarity on Virtual Ring 0.", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "BL Ring in Use; Down and Even on VRing 1", + "Counter": "2,3", + "EventCode": "0x1d", + "EventName": "UNC_C_RING_BL_USED.DOWN_VR1_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in JKT -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.; Filters for the Down and Even ring polarity on Virtual Ring 1.", + "UMask": "0x40", + "Unit": "CBO" + }, + { + "BriefDescription": "BL Ring in Use; Down and Odd on VRing 1", + "Counter": "2,3", + "EventCode": "0x1d", + "EventName": "UNC_C_RING_BL_USED.DOWN_VR1_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in JKT -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.; Filters for the Down and Odd ring polarity on Virtual Ring 1.", + "UMask": "0x80", + "Unit": "CBO" + }, + { + "BriefDescription": "BL Ring in Use; Up", + "Counter": "2,3", + "EventCode": "0x1D", + "EventName": "UNC_C_RING_BL_USED.UP", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in JKT -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.", + "UMask": "0x33", + "Unit": "CBO" + }, + { + "BriefDescription": "BL Ring in Use; Up and Even on Vring 0", + "Counter": "2,3", + "EventCode": "0x1d", + "EventName": "UNC_C_RING_BL_USED.UP_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in JKT -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.; Filters for the Up and Even ring polarity on Virtual Ring 0.", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "BL Ring in Use; Up and Odd on Vring 0", + "Counter": "2,3", + "EventCode": "0x1d", + "EventName": "UNC_C_RING_BL_USED.UP_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in JKT -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.; Filters for the Up and Odd ring polarity on Virtual Ring 0.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "BL Ring in Use; Up and Even on VRing 1", + "Counter": "2,3", + "EventCode": "0x1d", + "EventName": "UNC_C_RING_BL_USED.UP_VR1_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in JKT -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.; Filters for the Up and Even ring polarity on Virtual Ring 1.", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "BL Ring in Use; Up and Odd on VRing 1", + "Counter": "2,3", + "EventCode": "0x1d", + "EventName": "UNC_C_RING_BL_USED.UP_VR1_ODD", "PerPkg": "1", - "ScaleUnit": "64Bytes", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in JKT -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the UP di= rection is on the clockwise ring and DN is on the counter-clockwise ring. = On the right side of the ring, this is reversed. The first half of the CBo= s are on the left side of the ring, and the 2nd half are on the right side = of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NO= T the same ring as CBo 2 UP AD because they are on opposite sides of the ri= ng.; Filters for the Up and Odd ring polarity on Virtual Ring 1.", "UMask": "0x20", - "Unit": "HA" + "Unit": "CBO" }, { - "BriefDescription": "M line forwarded from remote cache with no wr= iteback to memory", - "Counter": "0,1,2,3", - "EventCode": "0x21", - "EventName": "UNC_H_SNOOP_RESP.RSPIFWD", + "BriefDescription": "Number of LLC responses that bounced on the R= ing.", + "Counter": "0,1", + "EventCode": "0x5", + "EventName": "UNC_C_RING_BOUNCES.AD_IRQ", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Number of LLC responses that bounced on the R= ing.; Acknowledgements to core", + "Counter": "0,1", + "EventCode": "0x5", + "EventName": "UNC_C_RING_BOUNCES.AK", "PerPkg": "1", - "ScaleUnit": "64Bytes", "UMask": "0x4", - "Unit": "HA" + "Unit": "CBO" }, { - "BriefDescription": "Shared line response from remote cache", - "Counter": "0,1,2,3", - "EventCode": "0x21", - "EventName": "UNC_H_SNOOP_RESP.RSPS", + "BriefDescription": "Number of LLC responses that bounced on the R= ing.: Acknowledgements to core", + "Counter": "0,1", + "EventCode": "0x5", + "EventName": "UNC_C_RING_BOUNCES.AK_CORE", "PerPkg": "1", - "ScaleUnit": "64Bytes", "UMask": "0x2", - "Unit": "HA" + "Unit": "CBO" }, { - "BriefDescription": "Shared line forwarded from remote cache", - "Counter": "0,1,2,3", - "EventCode": "0x21", - "EventName": "UNC_H_SNOOP_RESP.RSPSFWD", + "BriefDescription": "Number of LLC responses that bounced on the R= ing.; Data Responses to core", + "Counter": "0,1", + "EventCode": "0x5", + "EventName": "UNC_C_RING_BOUNCES.BL", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "Number of LLC responses that bounced on the R= ing.: Data Responses to core", + "Counter": "0,1", + "EventCode": "0x5", + "EventName": "UNC_C_RING_BOUNCES.BL_CORE", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Number of LLC responses that bounced on the R= ing.; Snoops of processor's cache.", + "Counter": "0,1", + "EventCode": "0x5", + "EventName": "UNC_C_RING_BOUNCES.IV", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "Number of LLC responses that bounced on the R= ing.: Snoops of processor's cache.", + "Counter": "0,1", + "EventCode": "0x5", + "EventName": "UNC_C_RING_BOUNCES.IV_CORE", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "IV Ring in Use; Any", + "Counter": "2,3", + "EventCode": "0x1e", + "EventName": "UNC_C_RING_IV_USED.ANY", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters any polarity", + "UMask": "0xF", + "Unit": "CBO" + }, + { + "BriefDescription": "IV Ring in Use; Down", + "Counter": "2,3", + "EventCode": "0x1e", + "EventName": "UNC_C_RING_IV_USED.DOWN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for Down polarity", + "UMask": "0xCC", + "Unit": "CBO" + }, + { + "BriefDescription": "IV Ring in Use; Up", + "Counter": "2,3", + "EventCode": "0x1e", + "EventName": "UNC_C_RING_IV_USED.UP", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for Up polarity", + "UMask": "0x33", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_C_RxR_EXT_STARVED.IPQ", + "PerPkg": "1", + "PublicDescription": "Counts cycles in external starvation. This = occurs when one of the ingress queues is being starved by the other queues.= ; IPQ is externally startved and therefore we are blocking the IRQ.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_C_RxR_EXT_STARVED.IRQ", + "PerPkg": "1", + "PublicDescription": "Counts cycles in external starvation. This = occurs when one of the ingress queues is being starved by the other queues.= ; IRQ is externally starved and therefore we are blocking the IPQ.", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_C_RxR_EXT_STARVED.ISMQ_BIDS", + "PerPkg": "1", + "PublicDescription": "Counts cycles in external starvation. This = occurs when one of the ingress queues is being starved by the other queues.= ; Number of times that the ISMQ Bid.", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Arbiter Blocking Cycles", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_C_RxR_EXT_STARVED.PRQ", + "PerPkg": "1", + "PublicDescription": "IRQ is blocking the ingress queue and causin= g the starvation.", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Allocations; IPQ", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_C_RxR_INSERTS.IPQ", + "PerPkg": "1", + "PublicDescription": "Counts number of allocations per cycle into = the specified Ingress queue.", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Allocations; IRQ", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_C_RxR_INSERTS.IRQ", + "PerPkg": "1", + "PublicDescription": "Counts number of allocations per cycle into = the specified Ingress queue.", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Allocations; IRQ Rejected", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_C_RxR_INSERTS.IRQ_REJ", + "PerPkg": "1", + "PublicDescription": "Counts number of allocations per cycle into = the specified Ingress queue.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Allocations: IRQ Rejected", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_C_RxR_INSERTS.IRQ_REJECTED", + "PerPkg": "1", + "PublicDescription": "Counts number of allocations per cycle into = the specified Ingress queue.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Allocations; VFIFO", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_C_RxR_INSERTS.VFIFO", + "PerPkg": "1", + "PublicDescription": "Counts number of allocations per cycle into = the specified Ingress queue.; Counts the number of allocations into the IRQ= Ordering FIFO. In JKT, it is necessary to keep IO requests in order. The= refore, they are allocated into an ordering FIFO that sits next to the IRQ,= and must be satisfied from the FIFO in order (with respect to each other).= This event, in conjunction with the Occupancy Accumulator event, can be u= sed to calculate average lifetime in the FIFO. Transactions are allocated = into the FIFO as soon as they enter the Cachebo (and the IRQ) and are deall= ocated from the FIFO as soon as they are deallocated from the IRQ.", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Internal Starvation Cycles; IPQ", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "UNC_C_RxR_INT_STARVED.IPQ", + "PerPkg": "1", + "PublicDescription": "Counts cycles in internal starvation. This = occurs when one (or more) of the entries in the ingress queue are being sta= rved out by other entries in that queue.; Cycles with the IPQ in Internal S= tarvation.", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Internal Starvation Cycles; IRQ", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "UNC_C_RxR_INT_STARVED.IRQ", + "PerPkg": "1", + "PublicDescription": "Counts cycles in internal starvation. This = occurs when one (or more) of the entries in the ingress queue are being sta= rved out by other entries in that queue.; Cycles with the IRQ in Internal S= tarvation.", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Internal Starvation Cycles; ISMQ", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "UNC_C_RxR_INT_STARVED.ISMQ", + "PerPkg": "1", + "PublicDescription": "Counts cycles in internal starvation. This = occurs when one (or more) of the entries in the ingress queue are being sta= rved out by other entries in that queue.; Cycles with the ISMQ in Internal = Starvation.", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "Probe Queue Retries; Address Conflict", + "Counter": "0,1", + "EventCode": "0x31", + "EventName": "UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT", + "PerPkg": "1", + "PublicDescription": "Number of times a snoop (probe) request had = to retry. Filters exist to cover some of the common cases retries.; Counts= the number of times that a request form the IPQ was retried because of a T= OR reject from an address conflicts. Address conflicts out of the IPQ shou= ld be rare. They will generally only occur if two different sockets are se= nding requests to the same address at the same time. This is a true confli= ct case, unlike the IPQ Address Conflict which is commonly caused by prefet= ching characteristics.", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Probe Queue Retries; Any Reject", + "Counter": "0,1", + "EventCode": "0x31", + "EventName": "UNC_C_RxR_IPQ_RETRY.ANY", + "PerPkg": "1", + "PublicDescription": "Number of times a snoop (probe) request had = to retry. Filters exist to cover some of the common cases retries.; Counts= the number of times that a request form the IPQ was retried because of a T= OR reject. TOR rejects from the IPQ can be caused by the Egress being full= or Address Conflicts.", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Probe Queue Retries; No Egress Credits", + "Counter": "0,1", + "EventCode": "0x31", + "EventName": "UNC_C_RxR_IPQ_RETRY.FULL", + "PerPkg": "1", + "PublicDescription": "Number of times a snoop (probe) request had = to retry. Filters exist to cover some of the common cases retries.; Counts= the number of times that a request form the IPQ was retried because of a T= OR reject from the Egress being full. IPQ requests make use of the AD Egre= ss for regular responses, the BL egress to forward data, and the AK egress = to return credits.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Probe Queue Retries; No QPI Credits", + "Counter": "0,1", + "EventCode": "0x31", + "EventName": "UNC_C_RxR_IPQ_RETRY.QPI_CREDITS", + "PerPkg": "1", + "PublicDescription": "Number of times a snoop (probe) request had = to retry. Filters exist to cover some of the common cases retries.", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Request Queue Rejects; Address Confli= ct", + "Counter": "0,1", + "EventCode": "0x32", + "EventName": "UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that a request fr= om the IRQ was retried because of an address match in the TOR. In order to= maintain coherency, requests to the same address are not allowed to pass e= ach other up in the Cbo. Therefore, if there is an outstanding request to = a given address, one cannot issue another request to that address until it = is complete. This comes up most commonly with prefetches. Outstanding pre= fetches occasionally will not complete their memory fetch and a demand requ= est to the same address will then sit in the IRQ and get retried until the = prefetch fills the data into the LLC. Therefore, it will not be uncommon t= o see this case in high bandwidth streaming workloads when the LLC Prefetch= er in the core is enabled.", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Request Queue Rejects; Any Reject", + "Counter": "0,1", + "EventCode": "0x32", + "EventName": "UNC_C_RxR_IRQ_RETRY.ANY", + "PerPkg": "1", + "PublicDescription": "Counts the number of IRQ retries that occur.= Requests from the IRQ are retried if they are rejected from the TOR pipel= ine for a variety of reasons. Some of the most common reasons include if t= he Egress is full, there are no RTIDs, or there is a Physical Address match= to another outstanding request.", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Request Queue Rejects; No Egress Cred= its", + "Counter": "0,1", + "EventCode": "0x32", + "EventName": "UNC_C_RxR_IRQ_RETRY.FULL", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that a request fr= om the IRQ was retried because it failed to acquire an entry in the Egress.= The egress is the buffer that queues up for allocating onto the ring. IR= Q requests can make use of all four rings and all four Egresses. If any of= the queues that a given request needs to make use of are full, the request= will be retried.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Request Queue Rejects; No IIO Credits= ", + "Counter": "0,1", + "EventCode": "0x32", + "EventName": "UNC_C_RxR_IRQ_RETRY.IIO_CREDITS", + "PerPkg": "1", + "PublicDescription": "Number of times a request attempted to acqui= re the NCS/NCB credit for sending messages on BL to the IIO. There is a si= ngle credit in each CBo that is shared between the NCS and NCB message clas= ses for sending transactions on the BL ring (such as read data) to the IIO.= ", + "UMask": "0x20", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Request Queue Rejects; No QPI Credits= ", + "Counter": "0,1", + "EventCode": "0x32", + "EventName": "UNC_C_RxR_IRQ_RETRY.QPI_CREDITS", + "PerPkg": "1", + "PublicDescription": "Number of requests rejects because of lack o= f QPI Ingress credits. These credits are required in order to send transac= tions to the QPI agent. Please see the QPI_IGR_CREDITS events for more inf= ormation.", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Request Queue Rejects; No RTIDs", + "Counter": "0,1", + "EventCode": "0x32", + "EventName": "UNC_C_RxR_IRQ_RETRY.RTID", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that requests fro= m the IRQ were retried because there were no RTIDs available. RTIDs are re= quired after a request misses the LLC and needs to send snoops and/or reque= sts to memory. If there are no RTIDs available, requests will queue up in = the IRQ and retry until one becomes available. Note that there are multipl= e RTID pools for the different sockets. There may be cases where the local= RTIDs are all used, but requests destined for remote memory can still acqu= ire an RTID because there are remote RTIDs available. This event does not = provide any filtering for this case.", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "ISMQ Retries; Any Reject", + "Counter": "0,1", + "EventCode": "0x33", + "EventName": "UNC_C_RxR_ISMQ_RETRY.ANY", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.; Counts the = total number of times that a request from the ISMQ retried because of a TOR= reject. ISMQ requests generally will not need to retry (or at least ISMQ = retries are less common than IRQ retries). ISMQ requests will retry if the= y are not able to acquire a needed Egress credit to get onto the ring, or f= or cache evictions that need to acquire an RTID. Most ISMQ requests alread= y have an RTID, so eviction retries will be less common here.", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "ISMQ Retries; No Egress Credits", + "Counter": "0,1", + "EventCode": "0x33", + "EventName": "UNC_C_RxR_ISMQ_RETRY.FULL", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.; Counts the = number of times that a request from the ISMQ retried because of a TOR rejec= t caused by a lack of Egress credits. The egress is the buffer that queues = up for allocating onto the ring. If any of the Egress queues that a given = request needs to make use of are full, the request will be retried.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "ISMQ Retries; No IIO Credits", + "Counter": "0,1", + "EventCode": "0x33", + "EventName": "UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.; Number of t= imes a request attempted to acquire the NCS/NCB credit for sending messages= on BL to the IIO. There is a single credit in each CBo that is shared bet= ween the NCS and NCB message classes for sending transactions on the BL rin= g (such as read data) to the IIO.", + "UMask": "0x20", + "Unit": "CBO" + }, + { + "BriefDescription": "ISMQ Retries; No QPI Credits", + "Counter": "0,1", + "EventCode": "0x33", + "EventName": "UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "ISMQ Retries; No RTIDs", + "Counter": "0,1", + "EventCode": "0x33", + "EventName": "UNC_C_RxR_ISMQ_RETRY.RTID", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.; Counts the = number of times that a request from the ISMQ retried because of a TOR rejec= t caused by no RTIDs. M-state cache evictions are serviced through the ISM= Q, and must acquire an RTID in order to write back to memory. If no RTIDs = are available, they will be retried.", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "ISMQ Retries; No WB Credits", + "Counter": "0,1", + "EventCode": "0x33", + "EventName": "UNC_C_RxR_ISMQ_RETRY.WB_CREDITS", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.; Retries of = writes to local memory due to lack of HT WB credits", + "UMask": "0x80", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Occupancy; IPQ", + "EventCode": "0x11", + "EventName": "UNC_C_RxR_OCCUPANCY.IPQ", + "PerPkg": "1", + "PublicDescription": "Counts number of entries in the specified In= gress queue in each cycle.", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Occupancy; IRQ", + "EventCode": "0x11", + "EventName": "UNC_C_RxR_OCCUPANCY.IRQ", + "PerPkg": "1", + "PublicDescription": "Counts number of entries in the specified In= gress queue in each cycle.", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Occupancy; IRQ Rejected", + "EventCode": "0x11", + "EventName": "UNC_C_RxR_OCCUPANCY.IRQ_REJ", + "PerPkg": "1", + "PublicDescription": "Counts number of entries in the specified In= gress queue in each cycle.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "IRQ Rejected", + "EventCode": "0x11", + "EventName": "UNC_C_RxR_OCCUPANCY.IRQ_REJECTED", + "PerPkg": "1", + "PublicDescription": "Counts number of entries in the specified In= gress queue in each cycle.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Occupancy; VFIFO", + "EventCode": "0x11", + "EventName": "UNC_C_RxR_OCCUPANCY.VFIFO", + "PerPkg": "1", + "PublicDescription": "Counts number of entries in the specified In= gress queue in each cycle.; Accumulates the number of used entries in the I= RQ Ordering FIFO in each cycle. In JKT, it is necessary to keep IO request= s in order. Therefore, they are allocated into an ordering FIFO that sits = next to the IRQ, and must be satisfied from the FIFO in order (with respect= to each other). This event, in conjunction with the Allocations event, ca= n be used to calculate average lifetime in the FIFO. This event can be use= d in conjunction with the Not Empty event to calculate average queue occupa= ncy. Transactions are allocated into the FIFO as soon as they enter the Cac= hebo (and the IRQ) and are deallocated from the FIFO as soon as they are de= allocated from the IRQ.", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; All", + "Counter": "0,1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted= into the TOR. This includes requests that reside in the TOR for a short= time, such as LLC Hits that do not need to snoop cores or requests that ge= t rejected and have to be retried through one of the ingress queues. The T= OR is more commonly a bottleneck in skews with smaller core counts, where t= he ratio of RTIDs to TOR entries is larger. Note that there are reserved T= OR entries for various request types, so it is possible that a given reques= t type be blocked with an occupancy that is less than 20. Also note that g= enerally requests will not be able to arbitrate into the TOR pipeline if th= ere are no available TOR slots.", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Evictions", + "Counter": "0,1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.EVICTION", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Eviction transactions ins= erted into the TOR. Evictions can be quick, such as when the line is in th= e F, S, or E states and no core valid bits are set. They can also be longe= r if either CV bits are set (so the cores need to be snooped) and/or if the= re is a HitM (in which case it is necessary to write the request out to mem= ory).", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Local Memory", + "Counter": "0,1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted= into the TOR that are satisifed by locally HOMed memory.", + "UMask": "0x28", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Local Memory - Opcode Matched", + "Counter": "0,1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.LOCAL_OPCODE", + "Filter": "CBoFilter1[28:20]", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisif= ed by an opcode, inserted into the TOR that are satisifed by locally HOMed= memory.", + "UMask": "0x21", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Misses to Local Memory", + "Counter": "0,1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserte= d into the TOR that are satisifed by locally HOMed memory.", + "UMask": "0x2A", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Misses to Local Memory - Opcode = Matched", + "Counter": "0,1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE", + "Filter": "CBoFilter1[28:20]", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisi= fed by an opcode, inserted into the TOR that are satisifed by locally HOMed= memory.", + "UMask": "0x23", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Miss Opcode Match", + "Counter": "0,1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", + "Filter": "CBoFilter1[28:20]", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserte= d into the TOR that match an opcode.", + "UMask": "0x3", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Misses to Remote Memory", + "Counter": "0,1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserte= d into the TOR that are satisifed by remote caches or remote memory.", + "UMask": "0x8A", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Misses to Remote Memory - Opcode= Matched", + "Counter": "0,1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE", + "Filter": "CBoFilter1[28:20]", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisi= fed by an opcode, inserted into the TOR that are satisifed by remote cache= s or remote memory.", + "UMask": "0x83", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; NID Matched", + "Counter": "0,1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.NID_ALL", + "Filter": "CBoFilter1[15:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched (matches = an RTID destination) transactions inserted into the TOR. The NID is progra= mmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE =3D I, it is= possible to monitor misses to specific NIDs in the system.", + "UMask": "0x48", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; NID Matched Evictions", + "Counter": "0,1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION", + "Filter": "CBoFilter1[15:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched eviction tran= sactions inserted into the TOR.", + "UMask": "0x44", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; NID Matched Miss All", + "Counter": "0,1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL", + "Filter": "CBoFilter1[15:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched miss requ= ests that were inserted into the TOR.", + "UMask": "0x4A", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; NID and Opcode Matched Miss", + "Counter": "0,1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE", + "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserte= d into the TOR that match a NID and an opcode.", + "UMask": "0x43", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; NID and Opcode Matched", + "Counter": "0,1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.NID_OPCODE", + "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted int= o the TOR that match a NID and an opcode.", + "UMask": "0x41", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; NID Matched Writebacks", + "Counter": "0,1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.NID_WB", + "Filter": "CBoFilter1[15:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched write transac= tions inserted into the TOR.", + "UMask": "0x50", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Opcode Match", + "Counter": "0,1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.OPCODE", + "Filter": "CBoFilter1[28:20]", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted int= o the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Remote Memory", + "Counter": "0,1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted= into the TOR that are satisifed by remote caches or remote memory.", + "UMask": "0x88", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Remote Memory - Opcode Matched", + "Counter": "0,1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.REMOTE_OPCODE", + "Filter": "CBoFilter1[28:20]", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisif= ed by an opcode, inserted into the TOR that are satisifed by remote caches= or remote memory.", + "UMask": "0x81", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Writebacks", + "Counter": "0,1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.WB", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Write transactions insert= ed into the TOR. This does not include RFO, but actual operations that co= ntain data being sent from the core.", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; Any", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.ALL", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All valid TO= R entries. This includes requests that reside in the TOR for a short time,= such as LLC Hits that do not need to snoop cores or requests that get reje= cted and have to be retried through one of the ingress queues. The TOR is = more commonly a bottleneck in skews with smaller core counts, where the rat= io of RTIDs to TOR entries is larger. Note that there are reserved TOR ent= ries for various request types, so it is possible that a given request type= be blocked with an occupancy that is less than 20. Also note that general= ly requests will not be able to arbitrate into the TOR pipeline if there ar= e no available TOR slots.", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; Evictions", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.EVICTION", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding eviction transactions in the TOR. Evictions can be quick, such a= s when the line is in the F, S, or E states and no core valid bits are set.= They can also be longer if either CV bits are set (so the cores need to b= e snooped) and/or if there is a HitM (in which case it is necessary to writ= e the request out to memory).", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", + "UMask": "0x28", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; Local Memory - Opcode Matched", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE", + "Filter": "CBoFilter1[28:20]", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding transactions, satisifed by an opcode, in the TOR that are satis= ifed by locally HOMed memory.", + "UMask": "0x21", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; Miss All", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.MISS_ALL", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding miss requests in the TOR. 'Miss' means the allocation requires a= n RTID. This generally means that the request was sent to memory or MMIO.", + "UMask": "0xA", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", + "UMask": "0x2A", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; Misses to Local Memory - Opcod= e Matched", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE", + "Filter": "CBoFilter1[28:20]", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding Miss transactions, satisifed by an opcode, in the TOR that are sa= tisifed by locally HOMed memory.", + "UMask": "0x23", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; Miss Opcode Match", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE", + "Filter": "CBoFilter1[28:20]", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries = for miss transactions that match an opcode. This generally means that the r= equest was sent to memory or MMIO.", + "UMask": "0x3", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", + "UMask": "0x8A", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; Misses to Remote Memory - Opco= de Matched", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE", + "Filter": "CBoFilter1[28:20]", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding Miss transactions, satisifed by an opcode, in the TOR that are sa= tisifed by remote caches or remote memory.", + "UMask": "0x83", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; NID Matched", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.NID_ALL", + "Filter": "CBoFilter1[15:0]", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of NI= D matched outstanding requests in the TOR. The NID is programmed in Cn_MSR= _PMON_BOX_FILTER.nid.In conjunction with STATE =3D I, it is possible to mon= itor misses to specific NIDs in the system.", + "UMask": "0x48", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; NID Matched Evictions", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.NID_EVICTION", + "Filter": "CBoFilter1[15:0]", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding NID matched eviction transactions in the TOR .", + "UMask": "0x44", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; NID Matched", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_ALL", + "Filter": "CBoFilter1[15:0]", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding Miss requests in the TOR that match a NID.", + "UMask": "0x4A", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; NID and Opcode Matched Miss", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE", + "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding Miss requests in the TOR that match a NID and an opcode.", + "UMask": "0x43", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; NID and Opcode Matched", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.NID_OPCODE", + "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries = that match a NID and an opcode.", + "UMask": "0x41", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; NID Matched Writebacks", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.NID_WB", + "Filter": "CBoFilter1[15:0]", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); NID matched = write transactions int the TOR.", + "UMask": "0x50", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; Opcode Match", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.OPCODE", + "Filter": "CBoFilter1[28:20]", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries = that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc).", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", + "UMask": "0x88", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; Remote Memory - Opcode Matched= ", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE_OPCODE", + "Filter": "CBoFilter1[28:20]", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding transactions, satisifed by an opcode, in the TOR that are satis= ifed by remote caches or remote memory.", + "UMask": "0x81", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; Writebacks", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.WB", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Write transa= ctions in the TOR. This does not include RFO, but actual operations that = contain data being sent from the core.", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "Onto AD Ring", + "Counter": "0,1", + "EventCode": "0x4", + "EventName": "UNC_C_TxR_ADS_USED.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Onto AK Ring", + "Counter": "0,1", + "EventCode": "0x4", + "EventName": "UNC_C_TxR_ADS_USED.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Onto BL Ring", + "Counter": "0,1", + "EventCode": "0x4", + "EventName": "UNC_C_TxR_ADS_USED.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Egress Allocations; AD - Cachebo", + "Counter": "0,1", + "EventCode": "0x2", + "EventName": "UNC_C_TxR_INSERTS.AD_CACHE", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Cbo Egress. = The Egress is used to queue up requests destined for the ring.; Ring transa= ctions from the Cachebo destined for the AD ring. Some example include out= bound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Egress Allocations; AD - Corebo", + "Counter": "0,1", + "EventCode": "0x2", + "EventName": "UNC_C_TxR_INSERTS.AD_CORE", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Cbo Egress. = The Egress is used to queue up requests destined for the ring.; Ring transa= ctions from the Corebo destined for the AD ring. This is commonly used for= outbound requests.", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "Egress Allocations; AK - Cachebo", + "Counter": "0,1", + "EventCode": "0x2", + "EventName": "UNC_C_TxR_INSERTS.AK_CACHE", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Cbo Egress. = The Egress is used to queue up requests destined for the ring.; Ring transa= ctions from the Cachebo destined for the AK ring. This is commonly used fo= r credit returns and GO responses.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Egress Allocations; AK - Corebo", + "Counter": "0,1", + "EventCode": "0x2", + "EventName": "UNC_C_TxR_INSERTS.AK_CORE", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Cbo Egress. = The Egress is used to queue up requests destined for the ring.; Ring transa= ctions from the Corebo destined for the AK ring. This is commonly used for= snoop responses coming from the core and destined for a Cachebo.", + "UMask": "0x20", + "Unit": "CBO" + }, + { + "BriefDescription": "Egress Allocations; BL - Cacheno", + "Counter": "0,1", + "EventCode": "0x2", + "EventName": "UNC_C_TxR_INSERTS.BL_CACHE", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Cbo Egress. = The Egress is used to queue up requests destined for the ring.; Ring transa= ctions from the Cachebo destined for the BL ring. This is commonly used to= send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Egress Allocations; BL - Corebo", + "Counter": "0,1", + "EventCode": "0x2", + "EventName": "UNC_C_TxR_INSERTS.BL_CORE", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Cbo Egress. = The Egress is used to queue up requests destined for the ring.; Ring transa= ctions from the Corebo destined for the BL ring. This is commonly used for= transfering writeback data to the cache.", + "UMask": "0x40", + "Unit": "CBO" + }, + { + "BriefDescription": "Egress Allocations; IV - Cachebo", + "Counter": "0,1", + "EventCode": "0x2", + "EventName": "UNC_C_TxR_INSERTS.IV_CACHE", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Cbo Egress. = The Egress is used to queue up requests destined for the ring.; Ring transa= ctions from the Cachebo destined for the IV ring. This is commonly used fo= r snoops to the cores.", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "Injection Starvation; Onto AD Ring (to core)", + "Counter": "0,1", + "EventCode": "0x3", + "EventName": "UNC_C_TxR_STARVED.AD_CORE", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the Egress cannot send a transaction onto the ring for = a long period of time.; cycles that the core AD egress spent in starvation", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "Injection Starvation; Onto AK Ring", + "Counter": "0,1", + "EventCode": "0x3", + "EventName": "UNC_C_TxR_STARVED.AK_BOTH", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the Egress cannot send a transaction onto the ring for = a long period of time.; cycles that both AK egresses spent in starvation", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Injection Starvation; Onto IV Ring", + "Counter": "0,1", + "EventCode": "0x3", + "EventName": "UNC_C_TxR_STARVED.IV", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the Egress cannot send a transaction onto the ring for = a long period of time.; cycles that the cachebo IV egress spent in starvati= on", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "QPI Address/Opcode Match; AD Opcodes", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_H_ADDR_OPC_MATCH.AD", + "Filter": "HA_OpcodeMatch[5:0]", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "QPI Address/Opcode Match; Address", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_H_ADDR_OPC_MATCH.ADDR", + "Filter": "HA_AddrMatch0[31:6], HA_AddrMatch1[13:0]", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "QPI Address/Opcode Match; AK Opcodes", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_H_ADDR_OPC_MATCH.AK", + "Filter": "HA_OpcodeMatch[5:0]", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "QPI Address/Opcode Match; BL Opcodes", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_H_ADDR_OPC_MATCH.BL", + "Filter": "HA_OpcodeMatch[5:0]", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "QPI Address/Opcode Match; Address & Opcode Ma= tch", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_H_ADDR_OPC_MATCH.FILT", + "Filter": "HA_AddrMatch0[31:6], HA_AddrMatch1[13:0], HA_OpcodeMatc= h[5:0]", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "QPI Address/Opcode Match; Opcode", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_H_ADDR_OPC_MATCH.OPC", + "Filter": "HA_OpcodeMatch[5:0]", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "BT Bypass", + "Counter": "0,1,2,3", + "EventCode": "0x52", + "EventName": "UNC_H_BT_BYPASS", + "PerPkg": "1", + "PublicDescription": "Number of transactions that bypass the BT (f= ifo) to HT", + "Unit": "HA" + }, + { + "BriefDescription": "BT Cycles Not Empty", + "Counter": "0,1,2,3", + "EventCode": "0x42", + "EventName": "UNC_H_BT_CYCLES_NE", + "PerPkg": "1", + "PublicDescription": "Cycles the Backup Tracker (BT) is not empty.= The BT is the actual HOM tracker in IVT.", + "Unit": "HA" + }, + { + "BriefDescription": "BT Cycles Not Empty: Local", + "Counter": "0,1,2,3", + "EventCode": "0x42", + "EventName": "UNC_H_BT_CYCLES_NE.LOCAL", + "PerPkg": "1", + "PublicDescription": "Cycles the Backup Tracker (BT) is not empty.= The BT is the actual HOM tracker in IVT.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "BT Cycles Not Empty: Remote", + "Counter": "0,1,2,3", + "EventCode": "0x42", + "EventName": "UNC_H_BT_CYCLES_NE.REMOTE", + "PerPkg": "1", + "PublicDescription": "Cycles the Backup Tracker (BT) is not empty.= The BT is the actual HOM tracker in IVT.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "BT Occupancy; Local", + "Counter": "0,1,2,3", + "EventCode": "0x43", + "EventName": "UNC_H_BT_OCCUPANCY.LOCAL", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the HA BT pool = in every cycle. This can be used with the not empty stat to calculate aver= age queue occupancy or the allocations stat in order to calculate average q= ueue latency. HA BTs are allocated as soon as a request enters the HA and = is released after the snoop response and data return (or post in the case o= f a write) and the response is returned on the ring.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "BT Occupancy; Reads Local", + "Counter": "0,1,2,3", + "EventCode": "0x43", + "EventName": "UNC_H_BT_OCCUPANCY.READS_LOCAL", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the HA BT pool = in every cycle. This can be used with the not empty stat to calculate aver= age queue occupancy or the allocations stat in order to calculate average q= ueue latency. HA BTs are allocated as soon as a request enters the HA and = is released after the snoop response and data return (or post in the case o= f a write) and the response is returned on the ring.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "BT Occupancy; Reads Remote", + "Counter": "0,1,2,3", + "EventCode": "0x43", + "EventName": "UNC_H_BT_OCCUPANCY.READS_REMOTE", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the HA BT pool = in every cycle. This can be used with the not empty stat to calculate aver= age queue occupancy or the allocations stat in order to calculate average q= ueue latency. HA BTs are allocated as soon as a request enters the HA and = is released after the snoop response and data return (or post in the case o= f a write) and the response is returned on the ring.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "BT Occupancy; Remote", + "Counter": "0,1,2,3", + "EventCode": "0x43", + "EventName": "UNC_H_BT_OCCUPANCY.REMOTE", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the HA BT pool = in every cycle. This can be used with the not empty stat to calculate aver= age queue occupancy or the allocations stat in order to calculate average q= ueue latency. HA BTs are allocated as soon as a request enters the HA and = is released after the snoop response and data return (or post in the case o= f a write) and the response is returned on the ring.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "BT Occupancy; Writes Local", + "Counter": "0,1,2,3", + "EventCode": "0x43", + "EventName": "UNC_H_BT_OCCUPANCY.WRITES_LOCAL", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the HA BT pool = in every cycle. This can be used with the not empty stat to calculate aver= age queue occupancy or the allocations stat in order to calculate average q= ueue latency. HA BTs are allocated as soon as a request enters the HA and = is released after the snoop response and data return (or post in the case o= f a write) and the response is returned on the ring.", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "BT Occupancy; Writes Remote", + "Counter": "0,1,2,3", + "EventCode": "0x43", + "EventName": "UNC_H_BT_OCCUPANCY.WRITES_REMOTE", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the HA BT pool = in every cycle. This can be used with the not empty stat to calculate aver= age queue occupancy or the allocations stat in order to calculate average q= ueue latency. HA BTs are allocated as soon as a request enters the HA and = is released after the snoop response and data return (or post in the case o= f a write) and the response is returned on the ring.", + "UMask": "0x20", + "Unit": "HA" + }, + { + "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the HA does= not issue transaction from BT to HT.; Cycles unable to issue from BT due t= o incoming BL data hazard", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "BT to HT Not Issued; Incoming Snoop Hazard", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the HA does= not issue transaction from BT to HT.; Cycles unable to issue from BT due t= o incoming snoop hazard", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.RSPACKCFLT_HAZARD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the HA does= not issue transaction from BT to HT.; Cycles unable to issue from BT due t= o incoming BL data hazard", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.WBMDATA_HAZARD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the HA does= not issue transaction from BT to HT.; Cycles unable to issue from BT due t= o incoming BL data hazard", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "HA to iMC Bypass; Not Taken", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when the HA was a= ble to bypass was attempted. This is a latency optimization for situations= when there is light loadings on the memory subsystem. This can be filted = by when the bypass was taken and when it was not.; Filter for transactions = that could not take the bypass.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA to iMC Bypass; Taken", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_H_BYPASS_IMC.TAKEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when the HA was a= ble to bypass was attempted. This is a latency optimization for situations= when there is light loadings on the memory subsystem. This can be filted = by when the bypass was taken and when it was not.; Filter for transactions = that succeeded in taking the bypass.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "uclks", + "Counter": "0,1,2,3", + "EventName": "UNC_H_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Counts the number of uclks in the HA. This = will be slightly different than the count in the Ubox because of enable/fre= eze delays. The HA is on the other side of the die from the fixed Ubox ucl= k counter, so the drift could be somewhat larger than in units that are clo= ser like the QPI Agent.", + "Unit": "HA" + }, + { + "BriefDescription": "Conflict Checks; Acknowledge Conflicts", + "Counter": "0,1,2,3", + "EventCode": "0xb", + "EventName": "UNC_H_CONFLICT_CYCLES.ACKCNFLTS", + "PerPkg": "1", + "PublicDescription": "Count the number of Ackcnflts", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "Conflict Checks; Cmp Fwds", + "Counter": "0,1,2,3", + "EventCode": "0xb", + "EventName": "UNC_H_CONFLICT_CYCLES.CMP_FWDS", + "PerPkg": "1", + "PublicDescription": "Count the number of Cmp_Fwd. This will give = the number of late conflicts.", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "Conflict Checks; Conflict Detected", + "Counter": "0,1,2,3", + "EventCode": "0xb", + "EventName": "UNC_H_CONFLICT_CYCLES.CONFLICT", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that we are hand= ling conflicts.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Conflict Checks; Last in conflict chain", + "Counter": "0,1,2,3", + "EventCode": "0xb", + "EventName": "UNC_H_CONFLICT_CYCLES.LAST", + "PerPkg": "1", + "PublicDescription": "Count every last conflictor in conflict chai= n. Can be used to compute the average conflict chain length as (#Ackcnflts/= #LastConflictor)+1. This can be used to give a feel for the conflict chain = lenghts while analyzing lock kernels.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "Direct2Core Messages Sent", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_H_DIRECT2CORE_COUNT", + "PerPkg": "1", + "PublicDescription": "Number of Direct2Core messages sent", + "Unit": "HA" + }, + { + "BriefDescription": "Cycles when Direct2Core was Disabled", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_H_DIRECT2CORE_CYCLES_DISABLED", + "PerPkg": "1", + "PublicDescription": "Number of cycles in which Direct2Core was di= sabled", + "Unit": "HA" + }, + { + "BriefDescription": "Number of Reads that had Direct2Core Overridd= en", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_H_DIRECT2CORE_TXN_OVERRIDE", + "PerPkg": "1", + "PublicDescription": "Number of Reads where Direct2Core overridden= ", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Lat Opt Return", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_H_DIRECTORY_LAT_OPT", + "PerPkg": "1", + "PublicDescription": "Directory Latency Optimization Data Return P= ath Taken. When directory mode is enabled and the directory retuned for a r= ead is Dir=3DI, then data can be returned using a faster path if certain co= nditions are met (credits, free pipeline, etc).", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Lookups: Any state", + "Counter": "0,1,2,3", + "EventCode": "0xc", + "EventName": "UNC_H_DIRECTORY_LOOKUP.ANY", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that looke= d up the directory. Can be filtered by requests that had to snoop and thos= e that did not have to.", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Lookups; Snoop Not Needed", + "Counter": "0,1,2,3", + "EventCode": "0xc", + "EventName": "UNC_H_DIRECTORY_LOOKUP.NO_SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that looke= d up the directory. Can be filtered by requests that had to snoop and thos= e that did not have to.; Filters for transactions that did not have to send= any snoops because the directory bit was clear.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Lookups: Snoop A", + "Counter": "0,1,2,3", + "EventCode": "0xc", + "EventName": "UNC_H_DIRECTORY_LOOKUP.SNOOP_A", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that looke= d up the directory. Can be filtered by requests that had to snoop and thos= e that did not have to.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Lookups: Snoop S", + "Counter": "0,1,2,3", + "EventCode": "0xc", + "EventName": "UNC_H_DIRECTORY_LOOKUP.SNOOP_S", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that looke= d up the directory. Can be filtered by requests that had to snoop and thos= e that did not have to.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Lookups; Snoop Needed", + "Counter": "0,1,2,3", + "EventCode": "0xc", + "EventName": "UNC_H_DIRECTORY_LOOKUP.SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that looke= d up the directory. Can be filtered by requests that had to snoop and thos= e that did not have to.; Filters for transactions that had to send one or m= ore snoops because the directory bit was set.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Lookups: A State", + "Counter": "0,1,2,3", + "EventCode": "0xc", + "EventName": "UNC_H_DIRECTORY_LOOKUP.STATE_A", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that looke= d up the directory. Can be filtered by requests that had to snoop and thos= e that did not have to.", + "UMask": "0x80", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Lookups: I State", + "Counter": "0,1,2,3", + "EventCode": "0xc", + "EventName": "UNC_H_DIRECTORY_LOOKUP.STATE_I", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that looke= d up the directory. Can be filtered by requests that had to snoop and thos= e that did not have to.", + "UMask": "0x20", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Lookups: S State", + "Counter": "0,1,2,3", + "EventCode": "0xc", + "EventName": "UNC_H_DIRECTORY_LOOKUP.STATE_S", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that looke= d up the directory. Can be filtered by requests that had to snoop and thos= e that did not have to.", + "UMask": "0x40", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Updates: A2I", + "Counter": "0,1,2,3", + "EventCode": "0xd", + "EventName": "UNC_H_DIRECTORY_UPDATE.A2I", + "PerPkg": "1", + "PublicDescription": "Counts the number of directory updates that = were required. These result in writes to the memory controller. This can = be filtered by directory sets and directory clears.", + "UMask": "0x20", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Updates: A2S", + "Counter": "0,1,2,3", + "EventCode": "0xd", + "EventName": "UNC_H_DIRECTORY_UPDATE.A2S", + "PerPkg": "1", + "PublicDescription": "Counts the number of directory updates that = were required. These result in writes to the memory controller. This can = be filtered by directory sets and directory clears.", + "UMask": "0x40", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Updates; Any Directory Update", + "Counter": "0,1,2,3", + "EventCode": "0xd", + "EventName": "UNC_H_DIRECTORY_UPDATE.ANY", + "PerPkg": "1", + "PublicDescription": "Counts the number of directory updates that = were required. These result in writes to the memory controller. This can = be filtered by directory sets and directory clears.", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Updates; Directory Clear", + "Counter": "0,1,2,3", + "EventCode": "0xD", + "EventName": "UNC_H_DIRECTORY_UPDATE.CLEAR", + "PerPkg": "1", + "PublicDescription": "Counts the number of directory updates that = were required. These result in writes to the memory controller. This can = be filtered by directory sets and directory clears.; Filter for directory c= lears. This occurs when snoops were sent and all returned with RspI.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Updates: I2A", + "Counter": "0,1,2,3", + "EventCode": "0xd", + "EventName": "UNC_H_DIRECTORY_UPDATE.I2A", + "PerPkg": "1", + "PublicDescription": "Counts the number of directory updates that = were required. These result in writes to the memory controller. This can = be filtered by directory sets and directory clears.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Updates: I2S", + "Counter": "0,1,2,3", + "EventCode": "0xd", + "EventName": "UNC_H_DIRECTORY_UPDATE.I2S", + "PerPkg": "1", + "PublicDescription": "Counts the number of directory updates that = were required. These result in writes to the memory controller. This can = be filtered by directory sets and directory clears.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Updates: S2A", + "Counter": "0,1,2,3", + "EventCode": "0xd", + "EventName": "UNC_H_DIRECTORY_UPDATE.S2A", + "PerPkg": "1", + "PublicDescription": "Counts the number of directory updates that = were required. These result in writes to the memory controller. This can = be filtered by directory sets and directory clears.", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Updates: S2I", + "Counter": "0,1,2,3", + "EventCode": "0xd", + "EventName": "UNC_H_DIRECTORY_UPDATE.S2I", + "PerPkg": "1", + "PublicDescription": "Counts the number of directory updates that = were required. These result in writes to the memory controller. This can = be filtered by directory sets and directory clears.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Updates; Directory Set", + "Counter": "0,1,2,3", + "EventCode": "0xD", + "EventName": "UNC_H_DIRECTORY_UPDATE.SET", + "PerPkg": "1", + "PublicDescription": "Counts the number of directory updates that = were required. These result in writes to the memory controller. This can = be filtered by directory sets and directory clears.; Filter for directory s= ets. This occurs when a remote read transaction requests memory, bringing = it to a remote cache.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "AD QPI Link 2 Credit Accumulator", + "Counter": "0,1,2,3", + "EventCode": "0x59", + "EventName": "UNC_H_IGR_AD_QPI2_ACCUMULATOR", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of credits available = to the QPI Link 2 AD Ingress buffer.", + "Unit": "HA" + }, + { + "BriefDescription": "BL QPI Link 2 Credit Accumulator", + "Counter": "0,1,2,3", + "EventCode": "0x5a", + "EventName": "UNC_H_IGR_BL_QPI2_ACCUMULATOR", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of credits available = to the QPI Link 2 BL Ingress buffer.", + "Unit": "HA" + }, + { + "BriefDescription": "AD QPI Link 2 Credit Accumulator", + "Counter": "0,1,2,3", + "EventCode": "0x59", + "EventName": "UNC_H_IGR_CREDITS_AD_QPI2", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of credits available = to the QPI Link 2 AD Ingress buffer.", + "Unit": "HA" + }, + { + "BriefDescription": "BL QPI Link 2 Credit Accumulator", + "Counter": "0,1,2,3", + "EventCode": "0x5A", + "EventName": "UNC_H_IGR_CREDITS_BL_QPI2", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of credits available = to the QPI Link 2 BL Ingress buffer.", + "Unit": "HA" + }, + { + "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI= Link 0", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the HA does= not have credits to send messages to the QPI Agent. This can be filtered = by the different credit pools and the different links.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI= Link 1", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the HA does= not have credits to send messages to the QPI Agent. This can be filtered = by the different credit pools and the different links.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI= Link 0", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the HA does= not have credits to send messages to the QPI Agent. This can be filtered = by the different credit pools and the different links.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI= Link 1", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the HA does= not have credits to send messages to the QPI Agent. This can be filtered = by the different credit pools and the different links.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "HA to iMC Normal Priority Reads Issued; Norma= l Priority", + "Counter": "0,1,2,3", + "EventCode": "0x17", + "EventName": "UNC_H_IMC_READS.NORMAL", + "PerPkg": "1", + "PublicDescription": "Count of the number of reads issued to any o= f the memory controller channels. This can be filtered by the priority of = the reads.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Retry Events", + "Counter": "0,1,2,3", + "EventCode": "0x1e", + "EventName": "UNC_H_IMC_RETRY", + "PerPkg": "1", + "Unit": "HA" + }, + { + "BriefDescription": "HA to iMC Full Line Writes Issued; All Writes= ", + "Counter": "0,1,2,3", + "EventCode": "0x1a", + "EventName": "UNC_H_IMC_WRITES.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the total number of full line writes = issued from the HA into the memory controller. This counts for all four ch= annels. It can be filtered by full/partial and ISOCH/non-ISOCH.", + "UMask": "0xF", + "Unit": "HA" + }, + { + "BriefDescription": "HA to iMC Full Line Writes Issued; Full Line = Non-ISOCH", + "Counter": "0,1,2,3", + "EventCode": "0x1a", + "EventName": "UNC_H_IMC_WRITES.FULL", + "PerPkg": "1", + "PublicDescription": "Counts the total number of full line writes = issued from the HA into the memory controller. This counts for all four ch= annels. It can be filtered by full/partial and ISOCH/non-ISOCH.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Full= Line", + "Counter": "0,1,2,3", + "EventCode": "0x1a", + "EventName": "UNC_H_IMC_WRITES.FULL_ISOCH", + "PerPkg": "1", + "PublicDescription": "Counts the total number of full line writes = issued from the HA into the memory controller. This counts for all four ch= annels. It can be filtered by full/partial and ISOCH/non-ISOCH.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "HA to iMC Full Line Writes Issued; Partial No= n-ISOCH", + "Counter": "0,1,2,3", + "EventCode": "0x1a", + "EventName": "UNC_H_IMC_WRITES.PARTIAL", + "PerPkg": "1", + "PublicDescription": "Counts the total number of full line writes = issued from the HA into the memory controller. This counts for all four ch= annels. It can be filtered by full/partial and ISOCH/non-ISOCH.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Part= ial", + "Counter": "0,1,2,3", + "EventCode": "0x1a", + "EventName": "UNC_H_IMC_WRITES.PARTIAL_ISOCH", + "PerPkg": "1", + "PublicDescription": "Counts the total number of full line writes = issued from the HA into the memory controller. This counts for all four ch= annels. It can be filtered by full/partial and ISOCH/non-ISOCH.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "IODC Conflicts; Any Conflict", + "Counter": "0,1,2,3", + "EventCode": "0x57", + "EventName": "UNC_H_IODC_CONFLICTS.ANY", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "IODC Conflicts; Last Conflict", + "Counter": "0,1,2,3", + "EventCode": "0x57", + "EventName": "UNC_H_IODC_CONFLICTS.LAST", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "IODC Conflicts: Remote InvItoE - Same RTID", + "Counter": "0,1,2,3", + "EventCode": "0x57", + "EventName": "UNC_H_IODC_CONFLICTS.REMOTE_INVI2E_SAME_RTID", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "IODC Conflicts: Remote (Other) - Same Addr", + "Counter": "0,1,2,3", + "EventCode": "0x57", + "EventName": "UNC_H_IODC_CONFLICTS.REMOTE_OTHER_SAME_ADDR", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "IODC Inserts", + "Counter": "0,1,2,3", + "EventCode": "0x56", + "EventName": "UNC_H_IODC_INSERTS", + "PerPkg": "1", + "PublicDescription": "IODC Allocations", + "Unit": "HA" + }, + { + "BriefDescription": "Num IODC 0 Length Writes", + "Counter": "0,1,2,3", + "EventCode": "0x58", + "EventName": "UNC_H_IODC_OLEN_WBMTOI", + "PerPkg": "1", + "PublicDescription": "Num IODC 0 Length Writebacks M to I - All of= which are dropped.", + "Unit": "HA" + }, + { + "BriefDescription": "OSB Snoop Broadcast; Local InvItoE", + "Counter": "0,1,2,3", + "EventCode": "0x53", + "EventName": "UNC_H_OSB.INVITOE_LOCAL", + "PerPkg": "1", + "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 p= er request causing OSB snoops to be broadcast. Does not count all the snoop= s generated by OSB.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "OSB Snoop Broadcast; Local Reads", + "Counter": "0,1,2,3", + "EventCode": "0x53", + "EventName": "UNC_H_OSB.READS_LOCAL", + "PerPkg": "1", + "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 p= er request causing OSB snoops to be broadcast. Does not count all the snoop= s generated by OSB.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "OSB Snoop Broadcast; Remote", + "Counter": "0,1,2,3", + "EventCode": "0x53", + "EventName": "UNC_H_OSB.REMOTE", + "PerPkg": "1", + "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 p= er request causing OSB snoops to be broadcast. Does not count all the snoop= s generated by OSB.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "OSB Early Data Return; All", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "UNC_H_OSB_EDR.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that broad= cast snoop due to OSB, but found clean data in memory and was able to do ea= rly data return", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "OSB Early Data Return; Reads to Local I", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "UNC_H_OSB_EDR.READS_LOCAL_I", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that broad= cast snoop due to OSB, but found clean data in memory and was able to do ea= rly data return", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "OSB Early Data Return; Reads to Local S", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "UNC_H_OSB_EDR.READS_LOCAL_S", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that broad= cast snoop due to OSB, but found clean data in memory and was able to do ea= rly data return", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "OSB Early Data Return; Reads to Remote I", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "UNC_H_OSB_EDR.READS_REMOTE_I", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that broad= cast snoop due to OSB, but found clean data in memory and was able to do ea= rly data return", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "OSB Early Data Return; Reads to Remote S", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "UNC_H_OSB_EDR.READS_REMOTE_S", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that broad= cast snoop due to OSB, but found clean data in memory and was able to do ea= rly data return", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "Read and Write Requests; Local InvItoEs", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts the total number of read requests mad= e into the Home Agent. Reads include all read opcodes (including RFO). Wri= tes include all writes (streaming, evictions, HitM, etc).; This filter incl= udes only InvItoEs coming from the local socket.", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "Read and Write Requests; Remote InvItoEs", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the total number of read requests mad= e into the Home Agent. Reads include all read opcodes (including RFO). Wri= tes include all writes (streaming, evictions, HitM, etc).; This filter incl= udes only InvItoEs coming from remote sockets.", + "UMask": "0x20", + "Unit": "HA" + }, + { + "BriefDescription": "Read and Write Requests; Reads", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_H_REQUESTS.READS", + "PerPkg": "1", + "PublicDescription": "Counts the total number of read requests mad= e into the Home Agent. Reads include all read opcodes (including RFO). Wri= tes include all writes (streaming, evictions, HitM, etc).; Incoming ead req= uests. This is a good proxy for LLC Read Misses (including RFOs).", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "Read and Write Requests; Local Reads", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_H_REQUESTS.READS_LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts the total number of read requests mad= e into the Home Agent. Reads include all read opcodes (including RFO). Wri= tes include all writes (streaming, evictions, HitM, etc).; This filter incl= udes only read requests coming from the local socket. This is a good proxy= for LLC Read Misses (including RFOs) from the local socket.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Read and Write Requests; Remote Reads", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_H_REQUESTS.READS_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the total number of read requests mad= e into the Home Agent. Reads include all read opcodes (including RFO). Wri= tes include all writes (streaming, evictions, HitM, etc).; This filter incl= udes only read requests coming from the remote socket. This is a good prox= y for LLC Read Misses (including RFOs) from the remote socket.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Read and Write Requests; Writes", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_H_REQUESTS.WRITES", + "PerPkg": "1", + "PublicDescription": "Counts the total number of read requests mad= e into the Home Agent. Reads include all read opcodes (including RFO). Wri= tes include all writes (streaming, evictions, HitM, etc).; Incoming write r= equests.", + "UMask": "0xC", + "Unit": "HA" + }, + { + "BriefDescription": "Read and Write Requests; Local Writes", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_H_REQUESTS.WRITES_LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts the total number of read requests mad= e into the Home Agent. Reads include all read opcodes (including RFO). Wri= tes include all writes (streaming, evictions, HitM, etc).; This filter incl= udes only writes coming from the local socket.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "Read and Write Requests; Remote Writes", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_H_REQUESTS.WRITES_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the total number of read requests mad= e into the Home Agent. Reads include all read opcodes (including RFO). Wri= tes include all writes (streaming, evictions, HitM, etc).; This filter incl= udes only writes coming from remote sockets.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "HA AD Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", + "EventCode": "0x3E", + "EventName": "UNC_H_RING_AD_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0xCC", + "Unit": "HA" + }, + { + "BriefDescription": "HA AD Ring in Use; Counterclockwise and Even = on VRing 0", + "Counter": "0,1,2,3", + "EventCode": "0x3e", + "EventName": "UNC_H_RING_AD_USED.CCW_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Even rin= g polarity on Virtual Ring 0.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd o= n VRing 0", + "Counter": "0,1,2,3", + "EventCode": "0x3e", + "EventName": "UNC_H_RING_AD_USED.CCW_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Odd ring= polarity on Virtual Ring 0.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "HA AD Ring in Use; Counterclockwise and Even = on VRing 1", + "Counter": "0,1,2,3", + "EventCode": "0x3e", + "EventName": "UNC_H_RING_AD_USED.CCW_VR1_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Even rin= g polarity on Virtual Ring 1.", + "UMask": "0x40", + "Unit": "HA" + }, + { + "BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd o= n VRing 1", + "Counter": "0,1,2,3", + "EventCode": "0x3e", + "EventName": "UNC_H_RING_AD_USED.CCW_VR1_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Odd ring= polarity on Virtual Ring 1.", + "UMask": "0x80", + "Unit": "HA" + }, + { + "BriefDescription": "HA AD Ring in Use; Clockwise", + "Counter": "0,1,2,3", + "EventCode": "0x3E", + "EventName": "UNC_H_RING_AD_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x33", + "Unit": "HA" + }, + { + "BriefDescription": "HA AD Ring in Use; Clockwise and Even on VRin= g 0", + "Counter": "0,1,2,3", + "EventCode": "0x3e", + "EventName": "UNC_H_RING_AD_USED.CW_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Even ring polar= ity on Virtual Ring 0.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "HA AD Ring in Use; Clockwise and Odd on VRing= 0", + "Counter": "0,1,2,3", + "EventCode": "0x3e", + "EventName": "UNC_H_RING_AD_USED.CW_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Odd ring polari= ty on Virtual Ring 0.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA AD Ring in Use; Clockwise and Even on VRin= g 1", + "Counter": "0,1,2,3", + "EventCode": "0x3e", + "EventName": "UNC_H_RING_AD_USED.CW_VR1_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Even ring polar= ity on Virtual Ring 1.", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "HA AD Ring in Use; Clockwise and Odd on VRing= 1", + "Counter": "0,1,2,3", + "EventCode": "0x3e", + "EventName": "UNC_H_RING_AD_USED.CW_VR1_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Odd ring polari= ty on Virtual Ring 1.", + "UMask": "0x20", + "Unit": "HA" + }, + { + "BriefDescription": "HA AK Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", + "EventCode": "0x3F", + "EventName": "UNC_H_RING_AK_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0xCC", + "Unit": "HA" + }, + { + "BriefDescription": "HA AK Ring in Use; Counterclockwise and Even = on VRing 0", + "Counter": "0,1,2,3", + "EventCode": "0x3f", + "EventName": "UNC_H_RING_AK_USED.CCW_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Even rin= g polarity on Virtual Ring 0.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd o= n VRing 0", + "Counter": "0,1,2,3", + "EventCode": "0x3f", + "EventName": "UNC_H_RING_AK_USED.CCW_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Odd ring= polarity on Virtual Ring 0.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "HA AK Ring in Use; Counterclockwise and Even = on VRing 1", + "Counter": "0,1,2,3", + "EventCode": "0x3f", + "EventName": "UNC_H_RING_AK_USED.CCW_VR1_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Even rin= g polarity on Virtual Ring 1.", + "UMask": "0x40", + "Unit": "HA" + }, + { + "BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd o= n VRing 1", + "Counter": "0,1,2,3", + "EventCode": "0x3f", + "EventName": "UNC_H_RING_AK_USED.CCW_VR1_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Odd ring= polarity on Virtual Ring 1.", + "UMask": "0x80", + "Unit": "HA" + }, + { + "BriefDescription": "HA AK Ring in Use; Clockwise", + "Counter": "0,1,2,3", + "EventCode": "0x3F", + "EventName": "UNC_H_RING_AK_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x33", + "Unit": "HA" + }, + { + "BriefDescription": "HA AK Ring in Use; Clockwise and Even on VRin= g 0", + "Counter": "0,1,2,3", + "EventCode": "0x3f", + "EventName": "UNC_H_RING_AK_USED.CW_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Even ring polar= ity on Virtual Ring 0.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "HA AK Ring in Use; Clockwise and Odd on VRing= 0", + "Counter": "0,1,2,3", + "EventCode": "0x3f", + "EventName": "UNC_H_RING_AK_USED.CW_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Odd ring polari= ty on Virtual Ring 0.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA AK Ring in Use; Clockwise and Even on VRin= g 1", + "Counter": "0,1,2,3", + "EventCode": "0x3f", + "EventName": "UNC_H_RING_AK_USED.CW_VR1_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Even ring polar= ity on Virtual Ring 1.", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "HA AK Ring in Use; Clockwise and Odd on VRing= 1", + "Counter": "0,1,2,3", + "EventCode": "0x3f", + "EventName": "UNC_H_RING_AK_USED.CW_VR1_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Odd ring polari= ty on Virtual Ring 1.", + "UMask": "0x20", + "Unit": "HA" + }, + { + "BriefDescription": "HA BL Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_H_RING_BL_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0xCC", + "Unit": "HA" + }, + { + "BriefDescription": "HA BL Ring in Use; Counterclockwise and Even = on VRing 0", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_H_RING_BL_USED.CCW_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Even rin= g polarity on Virtual Ring 0.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd o= n VRing 0", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_H_RING_BL_USED.CCW_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Odd ring= polarity on Virtual Ring 0.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "HA BL Ring in Use; Counterclockwise and Even = on VRing 1", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_H_RING_BL_USED.CCW_VR1_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Even rin= g polarity on Virtual Ring 1.", + "UMask": "0x40", + "Unit": "HA" + }, + { + "BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd o= n VRing 1", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_H_RING_BL_USED.CCW_VR1_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Odd ring= polarity on Virtual Ring 1.", + "UMask": "0x80", + "Unit": "HA" + }, + { + "BriefDescription": "HA BL Ring in Use; Clockwise", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_H_RING_BL_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x33", + "Unit": "HA" + }, + { + "BriefDescription": "HA BL Ring in Use; Clockwise and Even on VRin= g 0", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_H_RING_BL_USED.CW_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Even ring polar= ity on Virtual Ring 0.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "HA BL Ring in Use; Clockwise and Odd on VRing= 0", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_H_RING_BL_USED.CW_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Odd ring polari= ty on Virtual Ring 0.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA BL Ring in Use; Clockwise and Even on VRin= g 1", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_H_RING_BL_USED.CW_VR1_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Even ring polar= ity on Virtual Ring 1.", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "HA BL Ring in Use; Clockwise and Odd on VRing= 1", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_H_RING_BL_USED.CW_VR1_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Odd ring polari= ty on Virtual Ring 1.", + "UMask": "0x20", + "Unit": "HA" + }, + { + "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o regular credits available for posting reads from the HA into the iMC. In= order to send reads into the memory controller, the HA must first acquire = a credit for the iMC's RPQ (read pending queue). This queue is broken into= regular credits/buffers that are used by general reads, and special reques= ts such as ISOCH reads. This count only tracks the regular credits Common= high banwidth workloads should be able to make use of all of the regular b= uffers, but it will be difficult (and uncommon) to make use of both the reg= ular and special buffers at the same time. One can filter based on the mem= ory controller channel. One or more channels can be tracked at a given tim= e.; Filter for memory controller channel 0 only.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o regular credits available for posting reads from the HA into the iMC. In= order to send reads into the memory controller, the HA must first acquire = a credit for the iMC's RPQ (read pending queue). This queue is broken into= regular credits/buffers that are used by general reads, and special reques= ts such as ISOCH reads. This count only tracks the regular credits Common= high banwidth workloads should be able to make use of all of the regular b= uffers, but it will be difficult (and uncommon) to make use of both the reg= ular and special buffers at the same time. One can filter based on the mem= ory controller channel. One or more channels can be tracked at a given tim= e.; Filter for memory controller channel 1 only.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o regular credits available for posting reads from the HA into the iMC. In= order to send reads into the memory controller, the HA must first acquire = a credit for the iMC's RPQ (read pending queue). This queue is broken into= regular credits/buffers that are used by general reads, and special reques= ts such as ISOCH reads. This count only tracks the regular credits Common= high banwidth workloads should be able to make use of all of the regular b= uffers, but it will be difficult (and uncommon) to make use of both the reg= ular and special buffers at the same time. One can filter based on the mem= ory controller channel. One or more channels can be tracked at a given tim= e.; Filter for memory controller channel 2 only.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o regular credits available for posting reads from the HA into the iMC. In= order to send reads into the memory controller, the HA must first acquire = a credit for the iMC's RPQ (read pending queue). This queue is broken into= regular credits/buffers that are used by general reads, and special reques= ts such as ISOCH reads. This count only tracks the regular credits Common= high banwidth workloads should be able to make use of all of the regular b= uffers, but it will be difficult (and uncommon) to make use of both the reg= ular and special buffers at the same time. One can filter based on the mem= ory controller channel. One or more channels can be tracked at a given tim= e.; Filter for memory controller channel 3 only.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x16", + "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o special credits available for posting reads from the HA into the iMC. In= order to send reads into the memory controller, the HA must first acquire = a credit for the iMC's RPQ (read pending queue). This queue is broken into= regular credits/buffers that are used by general reads, and special reques= ts such as ISOCH reads. This count only tracks the special credits. This = statistic is generally not interesting for general IA workloads, but may be= of interest for understanding the characteristics of systems using ISOCH. = One can filter based on the memory controller channel. One or more channe= ls can be tracked at a given time.; Filter for memory controller channel 0 = only.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x16", + "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o special credits available for posting reads from the HA into the iMC. In= order to send reads into the memory controller, the HA must first acquire = a credit for the iMC's RPQ (read pending queue). This queue is broken into= regular credits/buffers that are used by general reads, and special reques= ts such as ISOCH reads. This count only tracks the special credits. This = statistic is generally not interesting for general IA workloads, but may be= of interest for understanding the characteristics of systems using ISOCH. = One can filter based on the memory controller channel. One or more channe= ls can be tracked at a given time.; Filter for memory controller channel 1 = only.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x16", + "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o special credits available for posting reads from the HA into the iMC. In= order to send reads into the memory controller, the HA must first acquire = a credit for the iMC's RPQ (read pending queue). This queue is broken into= regular credits/buffers that are used by general reads, and special reques= ts such as ISOCH reads. This count only tracks the special credits. This = statistic is generally not interesting for general IA workloads, but may be= of interest for understanding the characteristics of systems using ISOCH. = One can filter based on the memory controller channel. One or more channe= ls can be tracked at a given time.; Filter for memory controller channel 2 = only.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 3", + "Counter": "0,1,2,3", + "EventCode": "0x16", + "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o special credits available for posting reads from the HA into the iMC. In= order to send reads into the memory controller, the HA must first acquire = a credit for the iMC's RPQ (read pending queue). This queue is broken into= regular credits/buffers that are used by general reads, and special reques= ts such as ISOCH reads. This count only tracks the special credits. This = statistic is generally not interesting for general IA workloads, but may be= of interest for understanding the characteristics of systems using ISOCH. = One can filter based on the memory controller channel. One or more channe= ls can be tracked at a given time.; Filter for memory controller channel 3 = only.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received; RSPCNFLCT*", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT", + "PerPkg": "1", + "PublicDescription": "Counts the total number of RspI snoop respon= ses received. Whenever a snoops are issued, one or more snoop responses wi= ll be returned depending on the topology of the system. In systems larger= than 2s, when multiple snoops are returned this will count all the snoops = that are received. For example, if 3 snoops were issued and returned RspI,= RspS, and RspSFwd; then each of these sub-events would increment by 1.; Fi= lters for snoops responses of RspConflict. This is returned when a snoop f= inds an existing outstanding transaction in a remote caching agent when it = CAMs that caching agent. This triggers conflict resolution hardware. This= covers both RspCnflct and RspCnflctWbI.", + "UMask": "0x40", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received; RspI", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_H_SNOOP_RESP.RSPI", + "PerPkg": "1", + "PublicDescription": "Counts the total number of RspI snoop respon= ses received. Whenever a snoops are issued, one or more snoop responses wi= ll be returned depending on the topology of the system. In systems larger= than 2s, when multiple snoops are returned this will count all the snoops = that are received. For example, if 3 snoops were issued and returned RspI,= RspS, and RspSFwd; then each of these sub-events would increment by 1.; Fi= lters for snoops responses of RspI. RspI is returned when the remote cache= does not have the data, or when the remote cache silently evicts data (suc= h as when an RFO hits non-modified data).", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received; RspIFwd", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_H_SNOOP_RESP.RSPIFWD", + "PerPkg": "1", + "PublicDescription": "Counts the total number of RspI snoop respon= ses received. Whenever a snoops are issued, one or more snoop responses wi= ll be returned depending on the topology of the system. In systems larger= than 2s, when multiple snoops are returned this will count all the snoops = that are received. For example, if 3 snoops were issued and returned RspI,= RspS, and RspSFwd; then each of these sub-events would increment by 1.; Fi= lters for snoop responses of RspIFwd. This is returned when a remote cachi= ng agent forwards data and the requesting agent is able to acquire the data= in E or M states. This is commonly returned with RFO transactions. It ca= n be either a HitM or a HitFE.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received; RspS", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_H_SNOOP_RESP.RSPS", + "PerPkg": "1", + "PublicDescription": "Counts the total number of RspI snoop respon= ses received. Whenever a snoops are issued, one or more snoop responses wi= ll be returned depending on the topology of the system. In systems larger= than 2s, when multiple snoops are returned this will count all the snoops = that are received. For example, if 3 snoops were issued and returned RspI,= RspS, and RspSFwd; then each of these sub-events would increment by 1.; Fi= lters for snoop responses of RspS. RspS is returned when a remote cache ha= s data but is not forwarding it. It is a way to let the requesting socket = know that it cannot allocate the data in E state. No data is sent with S R= spS.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received; RspSFwd", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_H_SNOOP_RESP.RSPSFWD", + "PerPkg": "1", + "PublicDescription": "Counts the total number of RspI snoop respon= ses received. Whenever a snoops are issued, one or more snoop responses wi= ll be returned depending on the topology of the system. In systems larger= than 2s, when multiple snoops are returned this will count all the snoops = that are received. For example, if 3 snoops were issued and returned RspI,= RspS, and RspSFwd; then each of these sub-events would increment by 1.; Fi= lters for a snoop response of RspSFwd. This is returned when a remote cach= ing agent forwards data but holds on to its currentl copy. This is common = for data and code reads that hit in a remote socket in E or F state.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received; Rsp*Fwd*WB", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB", + "PerPkg": "1", + "PublicDescription": "Counts the total number of RspI snoop respon= ses received. Whenever a snoops are issued, one or more snoop responses wi= ll be returned depending on the topology of the system. In systems larger= than 2s, when multiple snoops are returned this will count all the snoops = that are received. For example, if 3 snoops were issued and returned RspI,= RspS, and RspSFwd; then each of these sub-events would increment by 1.; Fi= lters for a snoop response of Rsp*Fwd*WB. This snoop response is only used= in 4s systems. It is used when a snoop HITM's in a remote caching agent a= nd it directly forwards data to a requestor, and simultaneously returns dat= a to the home to be written back to memory.", + "UMask": "0x20", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received; Rsp*WB", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_H_SNOOP_RESP.RSP_WB", + "PerPkg": "1", + "PublicDescription": "Counts the total number of RspI snoop respon= ses received. Whenever a snoops are issued, one or more snoop responses wi= ll be returned depending on the topology of the system. In systems larger= than 2s, when multiple snoops are returned this will count all the snoops = that are received. For example, if 3 snoops were issued and returned RspI,= RspS, and RspSFwd; then each of these sub-events would increment by 1.; Fi= lters for a snoop response of RspIWB or RspSWB. This is returned when a no= n-RFO request hits in M state. Data and Code Reads can return either RspIW= B or RspSWB depending on how the system has been configured. InvItoE trans= actions will also return RspIWB because they must acquire ownership.", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received Local; Other", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.OTHER", + "PerPkg": "1", + "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for all other snoop responses.", + "UMask": "0x80", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspCnflct", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT", + "PerPkg": "1", + "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for snoops responses of RspConflict. This is returned= when a snoop finds an existing outstanding transaction in a remote caching= agent when it CAMs that caching agent. This triggers conflict resolution = hardware. This covers both RspCnflct and RspCnflctWbI.", + "UMask": "0x40", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspI", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPI", + "PerPkg": "1", + "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for snoops responses of RspI. RspI is returned when t= he remote cache does not have the data, or when the remote cache silently e= victs data (such as when an RFO hits non-modified data).", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspIFwd", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPIFWD", + "PerPkg": "1", + "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for snoop responses of RspIFwd. This is returned when= a remote caching agent forwards data and the requesting agent is able to a= cquire the data in E or M states. This is commonly returned with RFO trans= actions. It can be either a HitM or a HitFE.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspS", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPS", + "PerPkg": "1", + "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for snoop responses of RspS. RspS is returned when a = remote cache has data but is not forwarding it. It is a way to let the req= uesting socket know that it cannot allocate the data in E state. No data i= s sent with S RspS.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspSFwd", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD", + "PerPkg": "1", + "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for a snoop response of RspSFwd. This is returned whe= n a remote caching agent forwards data but holds on to its currentl copy. = This is common for data and code reads that hit in a remote socket in E or = F state.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxFWDxWB", + "PerPkg": "1", + "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for a snoop response of Rsp*Fwd*WB. This snoop respon= se is only used in 4s systems. It is used when a snoop HITM's in a remote = caching agent and it directly forwards data to a requestor, and simultaneou= sly returns data to the home to be written back to memory.", + "UMask": "0x20", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received Local; Rsp*WB", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB", + "PerPkg": "1", + "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for a snoop response of RspIWB or RspSWB. This is ret= urned when a non-RFO request hits in M state. Data and Code Reads can retu= rn either RspIWB or RspSWB depending on how the system has been configured.= InvItoE transactions will also return RspIWB because they must acquire ow= nership.", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 0", + "Counter": "0,1,2,3", + "EventCode": "0x1b", + "EventName": "UNC_H_TAD_REQUESTS_G0.REGION0", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 0 to 7. This event is usef= ul for understanding how applications are using the memory that is spread a= cross the different memory regions. It is particularly useful for Monroe s= ystems that use the TAD to enable individual channels to enter self-refresh= to save power.; Filters request made to TAD Region 0", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 1", + "Counter": "0,1,2,3", + "EventCode": "0x1b", + "EventName": "UNC_H_TAD_REQUESTS_G0.REGION1", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 0 to 7. This event is usef= ul for understanding how applications are using the memory that is spread a= cross the different memory regions. It is particularly useful for Monroe s= ystems that use the TAD to enable individual channels to enter self-refresh= to save power.; Filters request made to TAD Region 1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 2", + "Counter": "0,1,2,3", + "EventCode": "0x1b", + "EventName": "UNC_H_TAD_REQUESTS_G0.REGION2", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 0 to 7. This event is usef= ul for understanding how applications are using the memory that is spread a= cross the different memory regions. It is particularly useful for Monroe s= ystems that use the TAD to enable individual channels to enter self-refresh= to save power.; Filters request made to TAD Region 2", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 3", + "Counter": "0,1,2,3", + "EventCode": "0x1b", + "EventName": "UNC_H_TAD_REQUESTS_G0.REGION3", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 0 to 7. This event is usef= ul for understanding how applications are using the memory that is spread a= cross the different memory regions. It is particularly useful for Monroe s= ystems that use the TAD to enable individual channels to enter self-refresh= to save power.; Filters request made to TAD Region 3", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 4", + "Counter": "0,1,2,3", + "EventCode": "0x1b", + "EventName": "UNC_H_TAD_REQUESTS_G0.REGION4", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 0 to 7. This event is usef= ul for understanding how applications are using the memory that is spread a= cross the different memory regions. It is particularly useful for Monroe s= ystems that use the TAD to enable individual channels to enter self-refresh= to save power.; Filters request made to TAD Region 4", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 5", + "Counter": "0,1,2,3", + "EventCode": "0x1b", + "EventName": "UNC_H_TAD_REQUESTS_G0.REGION5", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 0 to 7. This event is usef= ul for understanding how applications are using the memory that is spread a= cross the different memory regions. It is particularly useful for Monroe s= ystems that use the TAD to enable individual channels to enter self-refresh= to save power.; Filters request made to TAD Region 5", + "UMask": "0x20", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 6", + "Counter": "0,1,2,3", + "EventCode": "0x1b", + "EventName": "UNC_H_TAD_REQUESTS_G0.REGION6", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 0 to 7. This event is usef= ul for understanding how applications are using the memory that is spread a= cross the different memory regions. It is particularly useful for Monroe s= ystems that use the TAD to enable individual channels to enter self-refresh= to save power.; Filters request made to TAD Region 6", + "UMask": "0x40", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 7", + "Counter": "0,1,2,3", + "EventCode": "0x1b", + "EventName": "UNC_H_TAD_REQUESTS_G0.REGION7", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 0 to 7. This event is usef= ul for understanding how applications are using the memory that is spread a= cross the different memory regions. It is particularly useful for Monroe s= ystems that use the TAD to enable individual channels to enter self-refresh= to save power.; Filters request made to TAD Region 7", + "UMask": "0x80", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Re= gion 10", + "Counter": "0,1,2,3", + "EventCode": "0x1c", + "EventName": "UNC_H_TAD_REQUESTS_G1.REGION10", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 8 to 10. This event is use= ful for understanding how applications are using the memory that is spread = across the different memory regions. It is particularly useful for Monroe = systems that use the TAD to enable individual channels to enter self-refres= h to save power.; Filters request made to TAD Region 10", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Re= gion 11", + "Counter": "0,1,2,3", + "EventCode": "0x1c", + "EventName": "UNC_H_TAD_REQUESTS_G1.REGION11", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 8 to 10. This event is use= ful for understanding how applications are using the memory that is spread = across the different memory regions. It is particularly useful for Monroe = systems that use the TAD to enable individual channels to enter self-refres= h to save power.; Filters request made to TAD Region 11", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Re= gion 8", + "Counter": "0,1,2,3", + "EventCode": "0x1c", + "EventName": "UNC_H_TAD_REQUESTS_G1.REGION8", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 8 to 10. This event is use= ful for understanding how applications are using the memory that is spread = across the different memory regions. It is particularly useful for Monroe = systems that use the TAD to enable individual channels to enter self-refres= h to save power.; Filters request made to TAD Region 8", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Re= gion 9", + "Counter": "0,1,2,3", + "EventCode": "0x1c", + "EventName": "UNC_H_TAD_REQUESTS_G1.REGION9", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 8 to 10. This event is use= ful for understanding how applications are using the memory that is spread = across the different memory regions. It is particularly useful for Monroe = systems that use the TAD to enable individual channels to enter self-refres= h to save power.; Filters request made to TAD Region 9", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Tracker Cycles Not Empty", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_H_TRACKER_CYCLES_NE", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the local H= A tracker pool is not empty. This can be used with edge detect to identify= the number of situations when the pool became empty. This should not be c= onfused with RTID credit usage -- which must be tracked inside each cbo ind= ividually -- but represents the actual tracker buffer structure. In other = words, this buffer could be completely empty, but there may still be credit= s in use by the CBos. This stat can be used in conjunction with the occupa= ncy accumulation stat in order to calculate average queue occpancy. HA tra= ckers are allocated as soon as a request enters the HA if an HT (Home Track= er) entry is available and is released after the snoop response and data re= turn (or post in the case of a write) and the response is returned on the r= ing.", + "Unit": "HA" + }, + { + "BriefDescription": "Outbound NDR Ring Transactions; Non-data Resp= onses", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "UNC_H_TxR_AD.HOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of outbound transactions o= n the AD ring. This can be filtered by the NDR and SNP message classes. S= ee the filter descriptions for more details.; Filter for outbound NDR trans= actions sent on the AD ring. NDR stands for non-data response and is gener= ally used for completions that do not include data. AD NDR is used for tra= nsactions to remote sockets.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Full; All", + "Counter": "0,1,2,3", + "EventCode": "0x2a", + "EventName": "UNC_H_TxR_AD_CYCLES_FULL.ALL", + "PerPkg": "1", + "PublicDescription": "AD Egress Full; Cycles full from both schedu= lers", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Full; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x2a", + "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED0", + "PerPkg": "1", + "PublicDescription": "AD Egress Full; Filter for cycles full from= scheduler bank 0", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Full; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x2a", + "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED1", + "PerPkg": "1", + "PublicDescription": "AD Egress Full; Filter for cycles full from= scheduler bank 1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Not Empty; All", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_H_TxR_AD_CYCLES_NE.ALL", + "PerPkg": "1", + "PublicDescription": "AD Egress Not Empty; Cycles full from both s= chedulers", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Not Empty; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED0", + "PerPkg": "1", + "PublicDescription": "AD Egress Not Empty; Filter for cycles not e= mpty from scheduler bank 0", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Not Empty; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED1", + "PerPkg": "1", + "PublicDescription": "AD Egress Not Empty; Filter for cycles not e= mpty from scheduler bank 1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Allocations; All", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_H_TxR_AD_INSERTS.ALL", + "PerPkg": "1", + "PublicDescription": "AD Egress Allocations; Allocations from both= schedulers", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Allocations; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_H_TxR_AD_INSERTS.SCHED0", + "PerPkg": "1", + "PublicDescription": "AD Egress Allocations; Filter for allocation= s from scheduler bank 0", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Allocations; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_H_TxR_AD_INSERTS.SCHED1", + "PerPkg": "1", + "PublicDescription": "AD Egress Allocations; Filter for allocation= s from scheduler bank 1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Occupancy; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "UNC_H_TxR_AD_OCCUPANCY.SCHED0", + "PerPkg": "1", + "PublicDescription": "AD Egress Occupancy; Filter for occupancy fr= om scheduler bank 0", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Occupancy; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "UNC_H_TxR_AD_OCCUPANCY.SCHED1", + "PerPkg": "1", + "PublicDescription": "AD Egress Occupancy; Filter for occupancy fr= om scheduler bank 1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Outbound Ring Transactions on AK: CRD Transac= tions to Cbo", + "Counter": "0,1,2,3", + "EventCode": "0xe", + "EventName": "UNC_H_TxR_AK.CRD_CBO", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Full; All", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_H_TxR_AK_CYCLES_FULL.ALL", + "PerPkg": "1", + "PublicDescription": "AK Egress Full; Cycles full from both schedu= lers", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Full; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED0", + "PerPkg": "1", + "PublicDescription": "AK Egress Full; Filter for cycles full from= scheduler bank 0", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Full; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED1", + "PerPkg": "1", + "PublicDescription": "AK Egress Full; Filter for cycles full from= scheduler bank 1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Not Empty; All", + "Counter": "0,1,2,3", + "EventCode": "0x31", + "EventName": "UNC_H_TxR_AK_CYCLES_NE.ALL", + "PerPkg": "1", + "PublicDescription": "AK Egress Not Empty; Cycles full from both s= chedulers", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Not Empty; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x31", + "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED0", + "PerPkg": "1", + "PublicDescription": "AK Egress Not Empty; Filter for cycles not e= mpty from scheduler bank 0", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Not Empty; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x31", + "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED1", + "PerPkg": "1", + "PublicDescription": "AK Egress Not Empty; Filter for cycles not e= mpty from scheduler bank 1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Allocations; All", + "Counter": "0,1,2,3", + "EventCode": "0x2f", + "EventName": "UNC_H_TxR_AK_INSERTS.ALL", + "PerPkg": "1", + "PublicDescription": "AK Egress Allocations; Allocations from both= schedulers", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Allocations; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x2f", + "EventName": "UNC_H_TxR_AK_INSERTS.SCHED0", + "PerPkg": "1", + "PublicDescription": "AK Egress Allocations; Filter for allocation= s from scheduler bank 0", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Allocations; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x2f", + "EventName": "UNC_H_TxR_AK_INSERTS.SCHED1", + "PerPkg": "1", + "PublicDescription": "AK Egress Allocations; Filter for allocation= s from scheduler bank 1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Occupancy; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x30", + "EventName": "UNC_H_TxR_AK_OCCUPANCY.SCHED0", + "PerPkg": "1", + "PublicDescription": "AK Egress Occupancy; Filter for occupancy fr= om scheduler bank 0", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Occupancy; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x30", + "EventName": "UNC_H_TxR_AK_OCCUPANCY.SCHED1", + "PerPkg": "1", + "PublicDescription": "AK Egress Occupancy; Filter for occupancy fr= om scheduler bank 1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to Cache", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "UNC_H_TxR_BL.DRS_CACHE", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS messages sent out o= n the BL ring. This can be filtered by the destination.; Filter for data = being sent to the cache.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to Core", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "UNC_H_TxR_BL.DRS_CORE", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS messages sent out o= n the BL ring. This can be filtered by the destination.; Filter for data = being sent directly to the requesting core.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to QPI", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "UNC_H_TxR_BL.DRS_QPI", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS messages sent out o= n the BL ring. This can be filtered by the destination.; Filter for data = being sent to a remote socket over QPI.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Full; All", + "Counter": "0,1,2,3", + "EventCode": "0x36", + "EventName": "UNC_H_TxR_BL_CYCLES_FULL.ALL", + "PerPkg": "1", + "PublicDescription": "BL Egress Full; Cycles full from both schedu= lers", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Full; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x36", + "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED0", + "PerPkg": "1", + "PublicDescription": "BL Egress Full; Filter for cycles full from= scheduler bank 0", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Full; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x36", + "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED1", + "PerPkg": "1", + "PublicDescription": "BL Egress Full; Filter for cycles full from= scheduler bank 1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Not Empty; All", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_H_TxR_BL_CYCLES_NE.ALL", + "PerPkg": "1", + "PublicDescription": "BL Egress Not Empty; Cycles full from both s= chedulers", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Not Empty; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED0", + "PerPkg": "1", + "PublicDescription": "BL Egress Not Empty; Filter for cycles not e= mpty from scheduler bank 0", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Not Empty; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED1", + "PerPkg": "1", + "PublicDescription": "BL Egress Not Empty; Filter for cycles not e= mpty from scheduler bank 1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Allocations; All", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_H_TxR_BL_INSERTS.ALL", + "PerPkg": "1", + "PublicDescription": "BL Egress Allocations; Allocations from both= schedulers", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Allocations; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_H_TxR_BL_INSERTS.SCHED0", + "PerPkg": "1", + "PublicDescription": "BL Egress Allocations; Filter for allocation= s from scheduler bank 0", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Allocations; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_H_TxR_BL_INSERTS.SCHED1", + "PerPkg": "1", + "PublicDescription": "BL Egress Allocations; Filter for allocation= s from scheduler bank 1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Occupancy: All", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_H_TxR_BL_OCCUPANCY.ALL", + "PerPkg": "1", + "PublicDescription": "BL Egress Occupancy", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Occupancy; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_H_TxR_BL_OCCUPANCY.SCHED0", + "PerPkg": "1", + "PublicDescription": "BL Egress Occupancy; Filter for occupancy fr= om scheduler bank 0", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Occupancy; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_H_TxR_BL_OCCUPANCY.SCHED1", + "PerPkg": "1", + "PublicDescription": "BL Egress Occupancy; Filter for occupancy fr= om scheduler bank 1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Chan= nel 0", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o regular credits available for posting writes from the HA into the iMC. I= n order to send writes into the memory controller, the HA must first acquir= e a credit for the iMC's WPQ (write pending queue). This queue is broken i= nto regular credits/buffers that are used by general writes, and special re= quests such as ISOCH writes. This count only tracks the regular credits C= ommon high banwidth workloads should be able to make use of all of the regu= lar buffers, but it will be difficult (and uncommon) to make use of both th= e regular and special buffers at the same time. One can filter based on th= e memory controller channel. One or more channels can be tracked at a give= n time.; Filter for memory controller channel 0 only.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Chan= nel 1", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o regular credits available for posting writes from the HA into the iMC. I= n order to send writes into the memory controller, the HA must first acquir= e a credit for the iMC's WPQ (write pending queue). This queue is broken i= nto regular credits/buffers that are used by general writes, and special re= quests such as ISOCH writes. This count only tracks the regular credits C= ommon high banwidth workloads should be able to make use of all of the regu= lar buffers, but it will be difficult (and uncommon) to make use of both th= e regular and special buffers at the same time. One can filter based on th= e memory controller channel. One or more channels can be tracked at a give= n time.; Filter for memory controller channel 1 only.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Chan= nel 2", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o regular credits available for posting writes from the HA into the iMC. I= n order to send writes into the memory controller, the HA must first acquir= e a credit for the iMC's WPQ (write pending queue). This queue is broken i= nto regular credits/buffers that are used by general writes, and special re= quests such as ISOCH writes. This count only tracks the regular credits C= ommon high banwidth workloads should be able to make use of all of the regu= lar buffers, but it will be difficult (and uncommon) to make use of both th= e regular and special buffers at the same time. One can filter based on th= e memory controller channel. One or more channels can be tracked at a give= n time.; Filter for memory controller channel 2 only.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Chan= nel 3", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o regular credits available for posting writes from the HA into the iMC. I= n order to send writes into the memory controller, the HA must first acquir= e a credit for the iMC's WPQ (write pending queue). This queue is broken i= nto regular credits/buffers that are used by general writes, and special re= quests such as ISOCH writes. This count only tracks the regular credits C= ommon high banwidth workloads should be able to make use of all of the regu= lar buffers, but it will be difficult (and uncommon) to make use of both th= e regular and special buffers at the same time. One can filter based on th= e memory controller channel. One or more channels can be tracked at a give= n time.; Filter for memory controller channel 3 only.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Chan= nel 0", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o special credits available for posting writes from the HA into the iMC. I= n order to send writes into the memory controller, the HA must first acquir= e a credit for the iMC's WPQ (write pending queue). This queue is broken i= nto regular credits/buffers that are used by general writes, and special re= quests such as ISOCH writes. This count only tracks the special credits. = This statistic is generally not interesting for general IA workloads, but m= ay be of interest for understanding the characteristics of systems using IS= OCH. One can filter based on the memory controller channel. One or more c= hannels can be tracked at a given time.; Filter for memory controller chann= el 0 only.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Chan= nel 1", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o special credits available for posting writes from the HA into the iMC. I= n order to send writes into the memory controller, the HA must first acquir= e a credit for the iMC's WPQ (write pending queue). This queue is broken i= nto regular credits/buffers that are used by general writes, and special re= quests such as ISOCH writes. This count only tracks the special credits. = This statistic is generally not interesting for general IA workloads, but m= ay be of interest for understanding the characteristics of systems using IS= OCH. One can filter based on the memory controller channel. One or more c= hannels can be tracked at a given time.; Filter for memory controller chann= el 1 only.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Chan= nel 2", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o special credits available for posting writes from the HA into the iMC. I= n order to send writes into the memory controller, the HA must first acquir= e a credit for the iMC's WPQ (write pending queue). This queue is broken i= nto regular credits/buffers that are used by general writes, and special re= quests such as ISOCH writes. This count only tracks the special credits. = This statistic is generally not interesting for general IA workloads, but m= ay be of interest for understanding the characteristics of systems using IS= OCH. One can filter based on the memory controller channel. One or more c= hannels can be tracked at a given time.; Filter for memory controller chann= el 2 only.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Chan= nel 3", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3", "PerPkg": "1", - "ScaleUnit": "64Bytes", + "PublicDescription": "Counts the number of cycles when there are n= o special credits available for posting writes from the HA into the iMC. I= n order to send writes into the memory controller, the HA must first acquir= e a credit for the iMC's WPQ (write pending queue). This queue is broken i= nto regular credits/buffers that are used by general writes, and special re= quests such as ISOCH writes. This count only tracks the special credits. = This statistic is generally not interesting for general IA workloads, but m= ay be of interest for understanding the characteristics of systems using IS= OCH. One can filter based on the memory controller channel. One or more c= hannels can be tracked at a given time.; Filter for memory controller chann= el 3 only.", "UMask": "0x8", "Unit": "HA" } diff --git a/tools/perf/pmu-events/arch/x86/ivytown/uncore-interconnect.jso= n b/tools/perf/pmu-events/arch/x86/ivytown/uncore-interconnect.json index b798a860bc81..b50685fbde12 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/uncore-interconnect.json @@ -1,48 +1,1768 @@ [ { - "BriefDescription": "QPI clock ticks. Use to get percentages for Q= PI cycles events", + "BriefDescription": "Number of qfclks", "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_Q_CLOCKTICKS", "PerPkg": "1", + "PublicDescription": "Counts the number of clocks in the QPI LL. = This clock runs at 1/8th the GT/s speed of the QPI link. For example, a 8G= T/s link will have qfclk or 1GHz. JKT does not support dynamic link speeds= , so this frequency is fixed.", "Unit": "QPI LL" }, { - "BriefDescription": "Cycles where receiving QPI link is in half-wi= dth mode", + "BriefDescription": "Count of CTO Events", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_Q_CTO_COUNT", + "ExtSel": "1", + "Filter": "QPIMask0[17:0],QPIMatch0[17:0],QPIMask1[19:16],QPIMatch= 1[19:16]", + "PerPkg": "1", + "PublicDescription": "Counts the number of CTO (cluster trigger ou= ts) events that were asserted across the two slots. If both slots trigger = in a given cycle, the event will increment by 2. You can use edge detect t= o count the number of cases when both events triggered.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egres= s Credits", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS packets that we att= empted to do direct2core on. There are 4 mutually exlusive filters. Filte= r [0] can be used to get successful spawns, while [1:3] provide the differe= nt failure cases. Note that this does not count packets that are not candi= dates for Direct2Core. The only candidates for Direct2Core are DRS packets= destined for Cbos.; The spawn failed because there were not enough Egress = credits. Had there been enough credits, the spawn would have worked as the= RBT bit was set and the RBT tag matched.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egres= s and RBT Miss", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_MISS", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS packets that we att= empted to do direct2core on. There are 4 mutually exlusive filters. Filte= r [0] can be used to get successful spawns, while [1:3] provide the differe= nt failure cases. Note that this does not count packets that are not candi= dates for Direct2Core. The only candidates for Direct2Core are DRS packets= destined for Cbos.; The spawn failed because the RBT tag did not match and= there weren't enough Egress credits. The valid bit was set.", + "UMask": "0x20", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egres= s and RBT Invalid", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS packets that we att= empted to do direct2core on. There are 4 mutually exlusive filters. Filte= r [0] can be used to get successful spawns, while [1:3] provide the differe= nt failure cases. Note that this does not count packets that are not candi= dates for Direct2Core. The only candidates for Direct2Core are DRS packets= destined for Cbos.; The spawn failed because there were not enough Egress = credits AND the RBT bit was not set, but the RBT tag matched.", + "UMask": "0x8", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egres= s and RBT Miss, Invalid", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT_MISS", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS packets that we att= empted to do direct2core on. There are 4 mutually exlusive filters. Filte= r [0] can be used to get successful spawns, while [1:3] provide the differe= nt failure cases. Note that this does not count packets that are not candi= dates for Direct2Core. The only candidates for Direct2Core are DRS packets= destined for Cbos.; The spawn failed because the RBT tag did not match, th= e valid bit was not set and there weren't enough Egress credits.", + "UMask": "0x80", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT M= iss", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.FAILURE_MISS", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS packets that we att= empted to do direct2core on. There are 4 mutually exlusive filters. Filte= r [0] can be used to get successful spawns, while [1:3] provide the differe= nt failure cases. Note that this does not count packets that are not candi= dates for Direct2Core. The only candidates for Direct2Core are DRS packets= destined for Cbos.; The spawn failed because the RBT tag did not match alt= hough the valid bit was set and there were enough Egress credits.", + "UMask": "0x10", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT I= nvalid", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS packets that we att= empted to do direct2core on. There are 4 mutually exlusive filters. Filte= r [0] can be used to get successful spawns, while [1:3] provide the differe= nt failure cases. Note that this does not count packets that are not candi= dates for Direct2Core. The only candidates for Direct2Core are DRS packets= destined for Cbos.; The spawn failed because the route-back table (RBT) sp= ecified that the transaction should not trigger a direct2core tranaction. = This is common for IO transactions. There were enough Egress credits and t= he RBT tag matched but the valid bit was not set.", + "UMask": "0x4", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT M= iss and Invalid", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_MISS", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS packets that we att= empted to do direct2core on. There are 4 mutually exlusive filters. Filte= r [0] can be used to get successful spawns, while [1:3] provide the differe= nt failure cases. Note that this does not count packets that are not candi= dates for Direct2Core. The only candidates for Direct2Core are DRS packets= destined for Cbos.; The spawn failed because the RBT tag did not match and= the valid bit was not set although there were enough Egress credits.", + "UMask": "0x40", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Success", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS packets that we att= empted to do direct2core on. There are 4 mutually exlusive filters. Filte= r [0] can be used to get successful spawns, while [1:3] provide the differe= nt failure cases. Note that this does not count packets that are not candi= dates for Direct2Core. The only candidates for Direct2Core are DRS packets= destined for Cbos.; The spawn was successful. There were sufficient credi= ts, the RBT valid bit was set and there was an RBT tag match. The message = was marked to spawn direct2core.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Cycles in L1", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_Q_L1_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of QPI qfclk cycles spent in L1 power= mode. L1 is a mode that totally shuts down a QPI link. Use edge detect t= o count the number of instances when the QPI link entered L1. Link power s= tates are per link and per direction, so for example the Tx direction could= be in one state while Rx was in another. Because L1 totally shuts down the= link, it takes a good amount of time to exit this mode.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Cycles in L0p", "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_Q_RxL0P_POWER_CYCLES", - "MetricExpr": "(UNC_Q_RxL0P_POWER_CYCLES / UNC_Q_CLOCKTICKS) * 100= .", - "MetricName": "rxl0p_power_cycles %", "PerPkg": "1", + "PublicDescription": "Number of QPI qfclk cycles spent in L0p powe= r mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing ou= r bandwidth in order to save power. It increases snoop and data transfer l= atencies and decreases overall bandwidth. This mode can be very useful in = NUMA optimized workloads that largely only utilize QPI for snoops and their= responses. Use edge detect to count the number of instances when the QPI = link entered L0p. Link power states are per link and per direction, so for= example the Tx direction could be in one state while Rx was in another.", "Unit": "QPI LL" }, { - "BriefDescription": "Cycles where transmitting QPI link is in half= -width mode", + "BriefDescription": "Cycles in L0", "Counter": "0,1,2,3", - "EventCode": "0xd", - "EventName": "UNC_Q_TxL0P_POWER_CYCLES", - "MetricExpr": "(UNC_Q_TxL0P_POWER_CYCLES / UNC_Q_CLOCKTICKS) * 100= .", - "MetricName": "txl0p_power_cycles %", + "EventCode": "0xf", + "EventName": "UNC_Q_RxL0_POWER_CYCLES", "PerPkg": "1", + "PublicDescription": "Number of QPI qfclk cycles spent in L0 power= mode in the Link Layer. L0 is the default mode which provides the highest= performance with the most power. Use edge detect to count the number of i= nstances that the link entered L0. Link power states are per link and per = direction, so for example the Tx direction could be in one state while Rx w= as in another. The phy layer sometimes leaves L0 for training, which will= not be captured by this event.", "Unit": "QPI LL" }, { - "BriefDescription": "Number of data flits transmitted ", + "BriefDescription": "Rx Flit Buffer Bypassed", "Counter": "0,1,2,3", - "EventName": "UNC_Q_TxL_FLITS_G0.DATA", + "EventCode": "0x9", + "EventName": "UNC_Q_RxL_BYPASSED", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an incoming = flit was able to bypass the flit buffer and pass directly across the BGF an= d into the Egress. This is a latency optimization, and should generally be= the common case. If this value is less than the number of flits transfere= d, it implies that there was queueing getting onto the ring, and thus the t= ransactions saw higher latency.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "CRC Errors Detected; LinkInit", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_CRC_ERRORS.LINK_INIT", + "PerPkg": "1", + "PublicDescription": "Number of CRC errors detected in the QPI Age= nt. Each QPI flit incorporates 8 bits of CRC for error detection. This co= unts the number of flits where the CRC was able to detect an error. After = an error has been detected, the QPI agent will send a request to the transm= itting socket to resend the flit (as well as any flits that came after it).= ; CRC errors detected during link initialization.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "CRC Errors Detected; Normal Operations", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP", "PerPkg": "1", - "ScaleUnit": "8Bytes", + "PublicDescription": "Number of CRC errors detected in the QPI Age= nt. Each QPI flit incorporates 8 bits of CRC for error detection. This co= unts the number of flits where the CRC was able to detect an error. After = an error has been detected, the QPI agent will send a request to the transm= itting socket to resend the flit (as well as any flits that came after it).= ; CRC errors detected during normal operation.", "UMask": "0x2", "Unit": "QPI LL" }, { - "BriefDescription": "Number of non data (control) flits transmitte= d ", + "BriefDescription": "VN0 Credit Consumed; DRS", "Counter": "0,1,2,3", - "EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA", + "EventCode": "0x1e", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN0 c= redit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). Thi= s includes packets that went through the RxQ and those that were bypasssed.= ; VN0 credit for the DRS message class.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VN0 Credit Consumed; HOM", + "Counter": "0,1,2,3", + "EventCode": "0x1e", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN0 c= redit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). Thi= s includes packets that went through the RxQ and those that were bypasssed.= ; VN0 credit for the HOM message class.", + "UMask": "0x8", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VN0 Credit Consumed; NCB", + "Counter": "0,1,2,3", + "EventCode": "0x1e", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN0 c= redit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). Thi= s includes packets that went through the RxQ and those that were bypasssed.= ; VN0 credit for the NCB message class.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VN0 Credit Consumed; NCS", + "Counter": "0,1,2,3", + "EventCode": "0x1e", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN0 c= redit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). Thi= s includes packets that went through the RxQ and those that were bypasssed.= ; VN0 credit for the NCS message class.", + "UMask": "0x4", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VN0 Credit Consumed; NDR", + "Counter": "0,1,2,3", + "EventCode": "0x1e", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN0 c= redit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). Thi= s includes packets that went through the RxQ and those that were bypasssed.= ; VN0 credit for the NDR message class.", + "UMask": "0x20", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VN0 Credit Consumed; SNP", + "Counter": "0,1,2,3", + "EventCode": "0x1e", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN0 c= redit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). Thi= s includes packets that went through the RxQ and those that were bypasssed.= ; VN0 credit for the SNP message class.", + "UMask": "0x10", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VN1 Credit Consumed; DRS", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.DRS", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN1 c= redit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). Thi= s includes packets that went through the RxQ and those that were bypasssed.= ; VN1 credit for the DRS message class.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VN1 Credit Consumed; HOM", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.HOM", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN1 c= redit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). Thi= s includes packets that went through the RxQ and those that were bypasssed.= ; VN1 credit for the HOM message class.", + "UMask": "0x8", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VN1 Credit Consumed; NCB", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCB", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN1 c= redit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). Thi= s includes packets that went through the RxQ and those that were bypasssed.= ; VN1 credit for the NCB message class.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VN1 Credit Consumed; NCS", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCS", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN1 c= redit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). Thi= s includes packets that went through the RxQ and those that were bypasssed.= ; VN1 credit for the NCS message class.", + "UMask": "0x4", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VN1 Credit Consumed; NDR", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NDR", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN1 c= redit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). Thi= s includes packets that went through the RxQ and those that were bypasssed.= ; VN1 credit for the NDR message class.", + "UMask": "0x20", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VN1 Credit Consumed; SNP", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.SNP", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN1 c= redit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). Thi= s includes packets that went through the RxQ and those that were bypasssed.= ; VN1 credit for the SNP message class.", + "UMask": "0x10", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VNA Credit Consumed", + "Counter": "0,1,2,3", + "EventCode": "0x1d", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VNA", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VNA c= redit was consumed (i.e. message uses a VNA credit for the Rx Buffer). Thi= s includes packets that went through the RxQ and those that were bypasssed.= ", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Cycles Not Empty", + "Counter": "0,1,2,3", + "EventCode": "0xa", + "EventName": "UNC_Q_RxL_CYCLES_NE", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ= was not empty. Generally, when data is transmitted across QPI, it will by= pass the RxQ and pass directly to the ring interface. If things back up ge= tting transmitted onto the ring, however, it may need to allocate into this= buffer, thus increasing the latency. This event can be used in conjunctio= n with the Flit Buffer Occupancy Accumulator event to calculate the average= occupancy.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN0", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ= was not empty. Generally, when data is transmitted across QPI, it will by= pass the RxQ and pass directly to the ring interface. If things back up ge= tting transmitted onto the ring, however, it may need to allocate into this= buffer, thus increasing the latency. This event can be used in conjunctio= n with the Flit Buffer Occupancy Accumulator event to calculate the average= occupancy. This monitors DRS flits only.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN1", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ= was not empty. Generally, when data is transmitted across QPI, it will by= pass the RxQ and pass directly to the ring interface. If things back up ge= tting transmitted onto the ring, however, it may need to allocate into this= buffer, thus increasing the latency. This event can be used in conjunctio= n with the Flit Buffer Occupancy Accumulator event to calculate the average= occupancy. This monitors DRS flits only.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN0", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ= was not empty. Generally, when data is transmitted across QPI, it will by= pass the RxQ and pass directly to the ring interface. If things back up ge= tting transmitted onto the ring, however, it may need to allocate into this= buffer, thus increasing the latency. This event can be used in conjunctio= n with the Flit Buffer Occupancy Accumulator event to calculate the average= occupancy. This monitors HOM flits only.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN1", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ= was not empty. Generally, when data is transmitted across QPI, it will by= pass the RxQ and pass directly to the ring interface. If things back up ge= tting transmitted onto the ring, however, it may need to allocate into this= buffer, thus increasing the latency. This event can be used in conjunctio= n with the Flit Buffer Occupancy Accumulator event to calculate the average= occupancy. This monitors HOM flits only.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN0", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ= was not empty. Generally, when data is transmitted across QPI, it will by= pass the RxQ and pass directly to the ring interface. If things back up ge= tting transmitted onto the ring, however, it may need to allocate into this= buffer, thus increasing the latency. This event can be used in conjunctio= n with the Flit Buffer Occupancy Accumulator event to calculate the average= occupancy. This monitors NCB flits only.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN1", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ= was not empty. Generally, when data is transmitted across QPI, it will by= pass the RxQ and pass directly to the ring interface. If things back up ge= tting transmitted onto the ring, however, it may need to allocate into this= buffer, thus increasing the latency. This event can be used in conjunctio= n with the Flit Buffer Occupancy Accumulator event to calculate the average= occupancy. This monitors NCB flits only.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN0", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ= was not empty. Generally, when data is transmitted across QPI, it will by= pass the RxQ and pass directly to the ring interface. If things back up ge= tting transmitted onto the ring, however, it may need to allocate into this= buffer, thus increasing the latency. This event can be used in conjunctio= n with the Flit Buffer Occupancy Accumulator event to calculate the average= occupancy. This monitors NCS flits only.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN1", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ= was not empty. Generally, when data is transmitted across QPI, it will by= pass the RxQ and pass directly to the ring interface. If things back up ge= tting transmitted onto the ring, however, it may need to allocate into this= buffer, thus increasing the latency. This event can be used in conjunctio= n with the Flit Buffer Occupancy Accumulator event to calculate the average= occupancy. This monitors NCS flits only.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN0", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ= was not empty. Generally, when data is transmitted across QPI, it will by= pass the RxQ and pass directly to the ring interface. If things back up ge= tting transmitted onto the ring, however, it may need to allocate into this= buffer, thus increasing the latency. This event can be used in conjunctio= n with the Flit Buffer Occupancy Accumulator event to calculate the average= occupancy. This monitors NDR flits only.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN1", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ= was not empty. Generally, when data is transmitted across QPI, it will by= pass the RxQ and pass directly to the ring interface. If things back up ge= tting transmitted onto the ring, however, it may need to allocate into this= buffer, thus increasing the latency. This event can be used in conjunctio= n with the Flit Buffer Occupancy Accumulator event to calculate the average= occupancy. This monitors NDR flits only.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN0", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ= was not empty. Generally, when data is transmitted across QPI, it will by= pass the RxQ and pass directly to the ring interface. If things back up ge= tting transmitted onto the ring, however, it may need to allocate into this= buffer, thus increasing the latency. This event can be used in conjunctio= n with the Flit Buffer Occupancy Accumulator event to calculate the average= occupancy. This monitors SNP flits only.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN1", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ= was not empty. Generally, when data is transmitted across QPI, it will by= pass the RxQ and pass directly to the ring interface. If things back up ge= tting transmitted onto the ring, however, it may need to allocate into this= buffer, thus increasing the latency. This event can be used in conjunctio= n with the Flit Buffer Occupancy Accumulator event to calculate the average= occupancy. This monitors SNP flits only.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 0; Data Tx Flits", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_Q_RxL_FLITS_G0.DATA", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the= QPI Link. It includes filters for Idle, protocol, and Data Flits. Each f= lit is made up of 80 bits of information (in addition to some ECC data). I= n full-width (L0) mode, flits are made up of four fits, each of which conta= ins 20 bits of data (along with some additional ECC data). In half-width = (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many= fits to transmit a flit. When one talks about QPI speed (for example, 8.0= GT/s), the transfers here refer to fits. Therefore, in L0, the system wil= l transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate th= e bandwidth of the link by taking: flits*80b/time. Note that this is not t= he same as data bandwidth. For example, when we are transfering a 64B cach= eline across QPI, we will break it into 9 flits -- 1 with header informatio= n and 8 with 64 bits of actual data and an additional 16 bits of other info= rmation. To calculate data bandwidth, one should therefore do: data flits = * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flitsrece= ived over QPI. Each flit contains 64b of data. This includes both DRS and= NCB data flits (coherent and non-coherent). This can be used to calculate= the data bandwidth of the QPI link. One can get a good picture of the QPI= -link characteristics by evaluating the protocol flits, data flits, and idl= e/null flits. This does not include the header flits that go in data packe= ts.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 0; Idle and Null Flits= ", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_Q_RxL_FLITS_G0.IDLE", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the= QPI Link. It includes filters for Idle, protocol, and Data Flits. Each f= lit is made up of 80 bits of information (in addition to some ECC data). I= n full-width (L0) mode, flits are made up of four fits, each of which conta= ins 20 bits of data (along with some additional ECC data). In half-width = (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many= fits to transmit a flit. When one talks about QPI speed (for example, 8.0= GT/s), the transfers here refer to fits. Therefore, in L0, the system wil= l transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate th= e bandwidth of the link by taking: flits*80b/time. Note that this is not t= he same as data bandwidth. For example, when we are transfering a 64B cach= eline across QPI, we will break it into 9 flits -- 1 with header informatio= n and 8 with 64 bits of actual data and an additional 16 bits of other info= rmation. To calculate data bandwidth, one should therefore do: data flits = * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of flits received= over QPI that do not hold protocol payload. When QPI is not in a power sa= ving state, it continuously transmits flits across the link. When there ar= e no protocol flits to send, it will send IDLE and NULL flits across. The= se flits sometimes do carry a payload, such as credit returns, but are gene= rall not considered part of the QPI bandwidth.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 0; Non-Data protocol T= x Flits", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_Q_RxL_FLITS_G0.NON_DATA", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the= QPI Link. It includes filters for Idle, protocol, and Data Flits. Each f= lit is made up of 80 bits of information (in addition to some ECC data). I= n full-width (L0) mode, flits are made up of four fits, each of which conta= ins 20 bits of data (along with some additional ECC data). In half-width = (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many= fits to transmit a flit. When one talks about QPI speed (for example, 8.0= GT/s), the transfers here refer to fits. Therefore, in L0, the system wil= l transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate th= e bandwidth of the link by taking: flits*80b/time. Note that this is not t= he same as data bandwidth. For example, when we are transfering a 64B cach= eline across QPI, we will break it into 9 flits -- 1 with header informatio= n and 8 with 64 bits of actual data and an additional 16 bits of other info= rmation. To calculate data bandwidth, one should therefore do: data flits = * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-d= ata flits received across QPI. This basically tracks the protocol overhead= on the QPI link. One can get a good picture of the QPI-link characteristi= cs by evaluating the protocol flits, data flits, and idle/null flits. This= includes the header flits for data packets.", + "UMask": "0x4", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 1; DRS Flits (both Hea= der and Data)", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.DRS", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for SNP, HOM, and DRS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transfering a 64B cacheline across = QPI, we will break it into 9 flits -- 1 with header information and 8 with = 64 bits of actual data and an additional 16 bits of other information. To = calculate data bandwidth, one should therefore do: data flits * 8B / time.;= Counts the total number of flits received over QPI on the DRS (Data Respon= se) channel. DRS flits are used to transmit data with coherency. This doe= s not count data flits received over the NCB channel which transmits non-co= herent data.", + "UMask": "0x18", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 1; DRS Data Flits", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for SNP, HOM, and DRS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transfering a 64B cacheline across = QPI, we will break it into 9 flits -- 1 with header information and 8 with = 64 bits of actual data and an additional 16 bits of other information. To = calculate data bandwidth, one should therefore do: data flits * 8B / time.;= Counts the total number of data flits received over QPI on the DRS (Data R= esponse) channel. DRS flits are used to transmit data with coherency. Thi= s does not count data flits received over the NCB channel which transmits n= on-coherent data. This includes only the data flits (not the header).", + "UMask": "0x8", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 1; DRS Header Flits", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for SNP, HOM, and DRS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transfering a 64B cacheline across = QPI, we will break it into 9 flits -- 1 with header information and 8 with = 64 bits of actual data and an additional 16 bits of other information. To = calculate data bandwidth, one should therefore do: data flits * 8B / time.;= Counts the total number of protocol flits received over QPI on the DRS (Da= ta Response) channel. DRS flits are used to transmit data with coherency. = This does not count data flits received over the NCB channel which transmi= ts non-coherent data. This includes only the header flits (not the data). = This includes extended headers.", + "UMask": "0x10", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 1; HOM Flits", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.HOM", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for SNP, HOM, and DRS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transfering a 64B cacheline across = QPI, we will break it into 9 flits -- 1 with header information and 8 with = 64 bits of actual data and an additional 16 bits of other information. To = calculate data bandwidth, one should therefore do: data flits * 8B / time.;= Counts the number of flits received over QPI on the home channel.", + "UMask": "0x6", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 1; HOM Non-Request Fli= ts", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ", + "ExtSel": "1", "PerPkg": "1", - "ScaleUnit": "8Bytes", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for SNP, HOM, and DRS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transfering a 64B cacheline across = QPI, we will break it into 9 flits -- 1 with header information and 8 with = 64 bits of actual data and an additional 16 bits of other information. To = calculate data bandwidth, one should therefore do: data flits * 8B / time.;= Counts the number of non-request flits received over QPI on the home chann= el. These are most commonly snoop responses, and this event can be used as= a proxy for that.", "UMask": "0x4", "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 1; HOM Request Flits", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for SNP, HOM, and DRS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transfering a 64B cacheline across = QPI, we will break it into 9 flits -- 1 with header information and 8 with = 64 bits of actual data and an additional 16 bits of other information. To = calculate data bandwidth, one should therefore do: data flits * 8B / time.;= Counts the number of data request received over QPI on the home channel. = This basically counts the number of remote memory requests received over QP= I. In conjunction with the local read count in the Home Agent, one can cal= culate the number of LLC Misses.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 1; SNP Flits", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.SNP", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for SNP, HOM, and DRS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transfering a 64B cacheline across = QPI, we will break it into 9 flits -- 1 with header information and 8 with = 64 bits of actual data and an additional 16 bits of other information. To = calculate data bandwidth, one should therefore do: data flits * 8B / time.;= Counts the number of snoop request flits received over QPI. These request= s are contained in the snoop channel. This does not include snoop response= s, which are received on the home channel.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 2; Non-Coherent Rx Fli= ts", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_FLITS_G2.NCB", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for NDR, NCB, and NCS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transfering a 64B cacheline across = QPI, we will break it into 9 flits -- 1 with header information and 8 with = 64 bits of actual data and an additional 16 bits of other information. To = calculate data bandwidth, one should therefore do: data flits * 8B / time.;= Number of Non-Coherent Bypass flits. These packets are generally used to = transmit non-coherent data across QPI.", + "UMask": "0xC", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 2; Non-Coherent data R= x Flits", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_FLITS_G2.NCB_DATA", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for NDR, NCB, and NCS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transfering a 64B cacheline across = QPI, we will break it into 9 flits -- 1 with header information and 8 with = 64 bits of actual data and an additional 16 bits of other information. To = calculate data bandwidth, one should therefore do: data flits * 8B / time.;= Number of Non-Coherent Bypass data flits. These flits are generally used = to transmit non-coherent data across QPI. This does not include a count of= the DRS (coherent) data flits. This only counts the data flits, not the N= CB headers.", + "UMask": "0x4", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 2; Non-Coherent non-da= ta Rx Flits", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_FLITS_G2.NCB_NONDATA", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for NDR, NCB, and NCS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transfering a 64B cacheline across = QPI, we will break it into 9 flits -- 1 with header information and 8 with = 64 bits of actual data and an additional 16 bits of other information. To = calculate data bandwidth, one should therefore do: data flits * 8B / time.;= Number of Non-Coherent Bypass non-data flits. These packets are generally= used to transmit non-coherent data across QPI, and the flits counted here = are for headers and other non-data flits. This includes extended headers.", + "UMask": "0x8", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 2; Non-Coherent standa= rd Rx Flits", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_FLITS_G2.NCS", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for NDR, NCB, and NCS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transfering a 64B cacheline across = QPI, we will break it into 9 flits -- 1 with header information and 8 with = 64 bits of actual data and an additional 16 bits of other information. To = calculate data bandwidth, one should therefore do: data flits * 8B / time.;= Number of NCS (non-coherent standard) flits received over QPI. This inc= ludes extended headers.", + "UMask": "0x10", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 2; Non-Data Response R= x Flits - AD", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for NDR, NCB, and NCS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transfering a 64B cacheline across = QPI, we will break it into 9 flits -- 1 with header information and 8 with = 64 bits of actual data and an additional 16 bits of other information. To = calculate data bandwidth, one should therefore do: data flits * 8B / time.;= Counts the total number of flits received over the NDR (Non-Data Response)= channel. This channel is used to send a variety of protocol flits includi= ng grants and completions. This is only for NDR packets to the local socke= t which use the AK ring.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 2; Non-Data Response R= x Flits - AK", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for NDR, NCB, and NCS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transfering a 64B cacheline across = QPI, we will break it into 9 flits -- 1 with header information and 8 with = 64 bits of actual data and an additional 16 bits of other information. To = calculate data bandwidth, one should therefore do: data flits * 8B / time.;= Counts the total number of flits received over the NDR (Non-Data Response)= channel. This channel is used to send a variety of protocol flits includi= ng grants and completions. This is only for NDR packets destined for Route= -thru to a remote socket.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_Q_RxL_INSERTS", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit B= uffer. Generally, when data is transmitted across QPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - DRS", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_Q_RxL_INSERTS_DRS", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit B= uffer. Generally, when data is transmitted across QPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime. This monitors only DRS flits.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_Q_RxL_INSERTS_DRS.VN0", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit B= uffer. Generally, when data is transmitted across QPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime. This monitors only DRS flits.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_Q_RxL_INSERTS_DRS.VN1", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit B= uffer. Generally, when data is transmitted across QPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime. This monitors only DRS flits.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - HOM", + "Counter": "0,1,2,3", + "EventCode": "0xc", + "EventName": "UNC_Q_RxL_INSERTS_HOM", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit B= uffer. Generally, when data is transmitted across QPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime. This monitors only HOM flits.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0xC", + "EventName": "UNC_Q_RxL_INSERTS_HOM.VN0", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit B= uffer. Generally, when data is transmitted across QPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime. This monitors only HOM flits.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0xC", + "EventName": "UNC_Q_RxL_INSERTS_HOM.VN1", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit B= uffer. Generally, when data is transmitted across QPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime. This monitors only HOM flits.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - NCB", + "Counter": "0,1,2,3", + "EventCode": "0xa", + "EventName": "UNC_Q_RxL_INSERTS_NCB", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit B= uffer. Generally, when data is transmitted across QPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime. This monitors only NCB flits.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0xA", + "EventName": "UNC_Q_RxL_INSERTS_NCB.VN0", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit B= uffer. Generally, when data is transmitted across QPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime. This monitors only NCB flits.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0xA", + "EventName": "UNC_Q_RxL_INSERTS_NCB.VN1", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit B= uffer. Generally, when data is transmitted across QPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime. This monitors only NCB flits.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - NCS", + "Counter": "0,1,2,3", + "EventCode": "0xb", + "EventName": "UNC_Q_RxL_INSERTS_NCS", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit B= uffer. Generally, when data is transmitted across QPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime. This monitors only NCS flits.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0xB", + "EventName": "UNC_Q_RxL_INSERTS_NCS.VN0", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit B= uffer. Generally, when data is transmitted across QPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime. This monitors only NCS flits.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0xB", + "EventName": "UNC_Q_RxL_INSERTS_NCS.VN1", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit B= uffer. Generally, when data is transmitted across QPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime. This monitors only NCS flits.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - NDR", + "Counter": "0,1,2,3", + "EventCode": "0xe", + "EventName": "UNC_Q_RxL_INSERTS_NDR", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit B= uffer. Generally, when data is transmitted across QPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime. This monitors only NDR flits.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0xE", + "EventName": "UNC_Q_RxL_INSERTS_NDR.VN0", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit B= uffer. Generally, when data is transmitted across QPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime. This monitors only NDR flits.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0xE", + "EventName": "UNC_Q_RxL_INSERTS_NDR.VN1", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit B= uffer. Generally, when data is transmitted across QPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime. This monitors only NDR flits.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - SNP", + "Counter": "0,1,2,3", + "EventCode": "0xd", + "EventName": "UNC_Q_RxL_INSERTS_SNP", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit B= uffer. Generally, when data is transmitted across QPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime. This monitors only SNP flits.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0xD", + "EventName": "UNC_Q_RxL_INSERTS_SNP.VN0", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit B= uffer. Generally, when data is transmitted across QPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime. This monitors only SNP flits.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0xD", + "EventName": "UNC_Q_RxL_INSERTS_SNP.VN1", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit B= uffer. Generally, when data is transmitted across QPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime. This monitors only SNP flits.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - All Packets", + "Counter": "0,1,2,3", + "EventCode": "0xb", + "EventName": "UNC_Q_RxL_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QP= I RxQ in each cycle. Generally, when data is transmitted across QPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - DRS", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_Q_RxL_OCCUPANCY_DRS", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QP= I RxQ in each cycle. Generally, when data is transmitted across QPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime. This= monitors DRS flits only.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - DRS; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN0", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QP= I RxQ in each cycle. Generally, when data is transmitted across QPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime. This= monitors DRS flits only.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - DRS; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN1", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QP= I RxQ in each cycle. Generally, when data is transmitted across QPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime. This= monitors DRS flits only.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - HOM", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_Q_RxL_OCCUPANCY_HOM", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QP= I RxQ in each cycle. Generally, when data is transmitted across QPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime. This= monitors HOM flits only.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - HOM; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN0", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QP= I RxQ in each cycle. Generally, when data is transmitted across QPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime. This= monitors HOM flits only.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - HOM; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN1", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QP= I RxQ in each cycle. Generally, when data is transmitted across QPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime. This= monitors HOM flits only.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - NCB", + "Counter": "0,1,2,3", + "EventCode": "0x16", + "EventName": "UNC_Q_RxL_OCCUPANCY_NCB", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QP= I RxQ in each cycle. Generally, when data is transmitted across QPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime. This= monitors NCB flits only.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - NCB; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x16", + "EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN0", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QP= I RxQ in each cycle. Generally, when data is transmitted across QPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime. This= monitors NCB flits only.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - NCB; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x16", + "EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN1", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QP= I RxQ in each cycle. Generally, when data is transmitted across QPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime. This= monitors NCB flits only.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - NCS", + "Counter": "0,1,2,3", + "EventCode": "0x17", + "EventName": "UNC_Q_RxL_OCCUPANCY_NCS", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QP= I RxQ in each cycle. Generally, when data is transmitted across QPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime. This= monitors NCS flits only.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - NCS; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x17", + "EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN0", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QP= I RxQ in each cycle. Generally, when data is transmitted across QPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime. This= monitors NCS flits only.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - NCS; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x17", + "EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN1", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QP= I RxQ in each cycle. Generally, when data is transmitted across QPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime. This= monitors NCS flits only.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - NDR", + "Counter": "0,1,2,3", + "EventCode": "0x1a", + "EventName": "UNC_Q_RxL_OCCUPANCY_NDR", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QP= I RxQ in each cycle. Generally, when data is transmitted across QPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime. This= monitors NDR flits only.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - NDR; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x1A", + "EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN0", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QP= I RxQ in each cycle. Generally, when data is transmitted across QPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime. This= monitors NDR flits only.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - NDR; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x1A", + "EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN1", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QP= I RxQ in each cycle. Generally, when data is transmitted across QPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime. This= monitors NDR flits only.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - SNP", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_Q_RxL_OCCUPANCY_SNP", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QP= I RxQ in each cycle. Generally, when data is transmitted across QPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime. This= monitors SNP flits only.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - SNP; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN0", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QP= I RxQ in each cycle. Generally, when data is transmitted across QPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime. This= monitors SNP flits only.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - SNP; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN1", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QP= I RxQ in each cycle. Generally, when data is transmitted across QPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime. This= monitors SNP flits only.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - H= OM", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_DRS", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on = Virtual Network 0; Stalled a packet from the HOM message class because ther= e were not enough BGF credits. In bypass mode, we will stall on the packet= boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - D= RS", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_HOM", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on = Virtual Network 0; Stalled a packet from the DRS message class because ther= e were not enough BGF credits. In bypass mode, we will stall on the packet= boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x8", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - S= NP", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCB", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on = Virtual Network 0; Stalled a packet from the SNP message class because ther= e were not enough BGF credits. In bypass mode, we will stall on the packet= boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - N= DR", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCS", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on = Virtual Network 0; Stalled a packet from the NDR message class because ther= e were not enough BGF credits. In bypass mode, we will stall on the packet= boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x4", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - N= CS", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NDR", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on = Virtual Network 0; Stalled a packet from the NCS message class because ther= e were not enough BGF credits. In bypass mode, we will stall on the packet= boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x20", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - N= CB", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_SNP", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on = Virtual Network 0; Stalled a packet from the NCB message class because ther= e were not enough BGF credits. In bypass mode, we will stall on the packet= boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x10", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN0; Egress Credit= s", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS_VN0.EGRESS_CREDITS", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on = Virtual Network 0; Stalled a packet because there were insufficient BGF cre= dits. For details on a message class granularity, use the Egress Credit Oc= cupancy events.", + "UMask": "0x40", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN0; GV", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS_VN0.GV", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on = Virtual Network 0; Stalled because a GV transition (frequency transition) w= as taking place.", + "UMask": "0x80", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - H= OM", + "Counter": "0,1,2,3", + "EventCode": "0x3a", + "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_DRS", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on = Virtual Network 1.; Stalled a packet from the HOM message class because the= re were not enough BGF credits. In bypass mode, we will stall on the packe= t boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - D= RS", + "Counter": "0,1,2,3", + "EventCode": "0x3a", + "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_HOM", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on = Virtual Network 1.; Stalled a packet from the DRS message class because the= re were not enough BGF credits. In bypass mode, we will stall on the packe= t boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x8", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - S= NP", + "Counter": "0,1,2,3", + "EventCode": "0x3a", + "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCB", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on = Virtual Network 1.; Stalled a packet from the SNP message class because the= re were not enough BGF credits. In bypass mode, we will stall on the packe= t boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - N= DR", + "Counter": "0,1,2,3", + "EventCode": "0x3a", + "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCS", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on = Virtual Network 1.; Stalled a packet from the NDR message class because the= re were not enough BGF credits. In bypass mode, we will stall on the packe= t boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x4", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - N= CS", + "Counter": "0,1,2,3", + "EventCode": "0x3a", + "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NDR", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on = Virtual Network 1.; Stalled a packet from the NCS message class because the= re were not enough BGF credits. In bypass mode, we will stall on the packe= t boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x20", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - N= CB", + "Counter": "0,1,2,3", + "EventCode": "0x3a", + "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_SNP", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on = Virtual Network 1.; Stalled a packet from the NCB message class because the= re were not enough BGF credits. In bypass mode, we will stall on the packe= t boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x10", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Cycles in L0p", + "Counter": "0,1,2,3", + "EventCode": "0xd", + "EventName": "UNC_Q_TxL0P_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of QPI qfclk cycles spent in L0p powe= r mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing ou= r bandwidth in order to save power. It increases snoop and data transfer l= atencies and decreases overall bandwidth. This mode can be very useful in = NUMA optimized workloads that largely only utilize QPI for snoops and their= responses. Use edge detect to count the number of instances when the QPI = link entered L0p. Link power states are per link and per direction, so for= example the Tx direction could be in one state while Rx was in another.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Cycles in L0", + "Counter": "0,1,2,3", + "EventCode": "0xc", + "EventName": "UNC_Q_TxL0_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of QPI qfclk cycles spent in L0 power= mode in the Link Layer. L0 is the default mode which provides the highest= performance with the most power. Use edge detect to count the number of i= nstances that the link entered L0. Link power states are per link and per = direction, so for example the Tx direction could be in one state while Rx w= as in another. The phy layer sometimes leaves L0 for training, which will= not be captured by this event.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Tx Flit Buffer Bypassed", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_Q_TxL_BYPASSED", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an incoming = flit was able to bypass the Tx flit buffer and pass directly out the QPI Li= nk. Generally, when data is transmitted across QPI, it will bypass the TxQ = and pass directly to the link. However, the TxQ will be used with L0p and = when LLR occurs, increasing latency to transfer out to the link.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is al= most full", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL", + "PerPkg": "1", + "PublicDescription": "Number of cycles when the Tx side ran out of= Link Layer Retry credits, causing the Tx to stall.; When LLR is almost ful= l, we block some but not all packets.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is fu= ll", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.FULL", + "PerPkg": "1", + "PublicDescription": "Number of cycles when the Tx side ran out of= Link Layer Retry credits, causing the Tx to stall.; When LLR is totally fu= ll, we are not allowed to send any packets.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Tx Flit Buffer Cycles not Empty", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "UNC_Q_TxL_CYCLES_NE", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the TxQ is = not empty. Generally, when data is transmitted across QPI, it will bypass t= he TxQ and pass directly to the link. However, the TxQ will be used with L= 0p and when LLR occurs, increasing latency to transfer out to the link.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 0; Data Tx Flits", + "Counter": "0,1,2,3", + "EventName": "UNC_Q_TxL_FLITS_G0.DATA", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. It includes filters for Idle, protocol, and Data Flits. E= ach flit is made up of 80 bits of information (in addition to some ECC data= ). In full-width (L0) mode, flits are made up of four fits, each of which = contains 20 bits of data (along with some additional ECC data). In half-w= idth (L0p) mode, the fits are only 10 bits, and therefore it takes twice as= many fits to transmit a flit. When one talks about QPI speed (for example= , 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the syste= m will transfer 1 flit at the rate of 1/4th the QPI speed. One can calcula= te the bandwidth of the link by taking: flits*80b/time. Note that this is = not the same as data bandwidth. For example, when we are transfering a 64B= cacheline across QPI, we will break it into 9 flits -- 1 with header infor= mation and 8 with 64 bits of actual data and an additional 16 bits of other= information. To calculate data bandwidth, one should therefore do: data f= lits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flit= s transmitted over QPI. Each flit contains 64b of data. This includes bot= h DRS and NCB data flits (coherent and non-coherent). This can be used to = calculate the data bandwidth of the QPI link. One can get a good picture o= f the QPI-link characteristics by evaluating the protocol flits, data flits= , and idle/null flits. This does not include the header flits that go in d= ata packets.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 0; Non-Data protoco= l Tx Flits", + "Counter": "0,1,2,3", + "EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. It includes filters for Idle, protocol, and Data Flits. E= ach flit is made up of 80 bits of information (in addition to some ECC data= ). In full-width (L0) mode, flits are made up of four fits, each of which = contains 20 bits of data (along with some additional ECC data). In half-w= idth (L0p) mode, the fits are only 10 bits, and therefore it takes twice as= many fits to transmit a flit. When one talks about QPI speed (for example= , 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the syste= m will transfer 1 flit at the rate of 1/4th the QPI speed. One can calcula= te the bandwidth of the link by taking: flits*80b/time. Note that this is = not the same as data bandwidth. For example, when we are transfering a 64B= cacheline across QPI, we will break it into 9 flits -- 1 with header infor= mation and 8 with 64 bits of actual data and an additional 16 bits of other= information. To calculate data bandwidth, one should therefore do: data f= lits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL = non-data flits transmitted across QPI. This basically tracks the protocol = overhead on the QPI link. One can get a good picture of the QPI-link chara= cteristics by evaluating the protocol flits, data flits, and idle/null flit= s. This includes the header flits for data packets.", + "UMask": "0x4", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 1; DRS Flits (both = Header and Data)", + "Counter": "0,1,2,3", + "EventName": "UNC_Q_TxL_FLITS_G1.DRS", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four fits, each of which contains 20 bi= ts of data (along with some additional ECC data). In half-width (L0p) mod= e, the fits are only 10 bits, and therefore it takes twice as many fits to = transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), t= he transfers here refer to fits. Therefore, in L0, the system will transfe= r 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwid= th of the link by taking: flits*80b/time. Note that this is not the same a= s data bandwidth. For example, when we are transfering a 64B cacheline acr= oss QPI, we will break it into 9 flits -- 1 with header information and 8 w= ith 64 bits of actual data and an additional 16 bits of other information. = To calculate data bandwidth, one should therefore do: data flits * 8B / ti= me.; Counts the total number of flits transmitted over QPI on the DRS (Data= Response) channel. DRS flits are used to transmit data with coherency.", + "UMask": "0x18", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 1; DRS Data Flits", + "Counter": "0,1,2,3", + "EventName": "UNC_Q_TxL_FLITS_G1.DRS_DATA", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four fits, each of which contains 20 bi= ts of data (along with some additional ECC data). In half-width (L0p) mod= e, the fits are only 10 bits, and therefore it takes twice as many fits to = transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), t= he transfers here refer to fits. Therefore, in L0, the system will transfe= r 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwid= th of the link by taking: flits*80b/time. Note that this is not the same a= s data bandwidth. For example, when we are transfering a 64B cacheline acr= oss QPI, we will break it into 9 flits -- 1 with header information and 8 w= ith 64 bits of actual data and an additional 16 bits of other information. = To calculate data bandwidth, one should therefore do: data flits * 8B / ti= me.; Counts the total number of data flits transmitted over QPI on the DRS = (Data Response) channel. DRS flits are used to transmit data with coherenc= y. This does not count data flits transmitted over the NCB channel which t= ransmits non-coherent data. This includes only the data flits (not the hea= der).", + "UMask": "0x8", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 1; DRS Header Flits= ", + "Counter": "0,1,2,3", + "EventName": "UNC_Q_TxL_FLITS_G1.DRS_NONDATA", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four fits, each of which contains 20 bi= ts of data (along with some additional ECC data). In half-width (L0p) mod= e, the fits are only 10 bits, and therefore it takes twice as many fits to = transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), t= he transfers here refer to fits. Therefore, in L0, the system will transfe= r 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwid= th of the link by taking: flits*80b/time. Note that this is not the same a= s data bandwidth. For example, when we are transfering a 64B cacheline acr= oss QPI, we will break it into 9 flits -- 1 with header information and 8 w= ith 64 bits of actual data and an additional 16 bits of other information. = To calculate data bandwidth, one should therefore do: data flits * 8B / ti= me.; Counts the total number of protocol flits transmitted over QPI on the = DRS (Data Response) channel. DRS flits are used to transmit data with cohe= rency. This does not count data flits transmitted over the NCB channel whi= ch transmits non-coherent data. This includes only the header flits (not t= he data). This includes extended headers.", + "UMask": "0x10", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 1; HOM Flits", + "Counter": "0,1,2,3", + "EventName": "UNC_Q_TxL_FLITS_G1.HOM", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four fits, each of which contains 20 bi= ts of data (along with some additional ECC data). In half-width (L0p) mod= e, the fits are only 10 bits, and therefore it takes twice as many fits to = transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), t= he transfers here refer to fits. Therefore, in L0, the system will transfe= r 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwid= th of the link by taking: flits*80b/time. Note that this is not the same a= s data bandwidth. For example, when we are transfering a 64B cacheline acr= oss QPI, we will break it into 9 flits -- 1 with header information and 8 w= ith 64 bits of actual data and an additional 16 bits of other information. = To calculate data bandwidth, one should therefore do: data flits * 8B / ti= me.; Counts the number of flits transmitted over QPI on the home channel.", + "UMask": "0x6", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 1; HOM Non-Request = Flits", + "Counter": "0,1,2,3", + "EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four fits, each of which contains 20 bi= ts of data (along with some additional ECC data). In half-width (L0p) mod= e, the fits are only 10 bits, and therefore it takes twice as many fits to = transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), t= he transfers here refer to fits. Therefore, in L0, the system will transfe= r 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwid= th of the link by taking: flits*80b/time. Note that this is not the same a= s data bandwidth. For example, when we are transfering a 64B cacheline acr= oss QPI, we will break it into 9 flits -- 1 with header information and 8 w= ith 64 bits of actual data and an additional 16 bits of other information. = To calculate data bandwidth, one should therefore do: data flits * 8B / ti= me.; Counts the number of non-request flits transmitted over QPI on the hom= e channel. These are most commonly snoop responses, and this event can be = used as a proxy for that.", + "UMask": "0x4", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 1; HOM Request Flit= s", + "Counter": "0,1,2,3", + "EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four fits, each of which contains 20 bi= ts of data (along with some additional ECC data). In half-width (L0p) mod= e, the fits are only 10 bits, and therefore it takes twice as many fits to = transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), t= he transfers here refer to fits. Therefore, in L0, the system will transfe= r 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwid= th of the link by taking: flits*80b/time. Note that this is not the same a= s data bandwidth. For example, when we are transfering a 64B cacheline acr= oss QPI, we will break it into 9 flits -- 1 with header information and 8 w= ith 64 bits of actual data and an additional 16 bits of other information. = To calculate data bandwidth, one should therefore do: data flits * 8B / ti= me.; Counts the number of data request transmitted over QPI on the home cha= nnel. This basically counts the number of remote memory requests transmitt= ed over QPI. In conjunction with the local read count in the Home Agent, o= ne can calculate the number of LLC Misses.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 1; SNP Flits", + "Counter": "0,1,2,3", + "EventName": "UNC_Q_TxL_FLITS_G1.SNP", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four fits, each of which contains 20 bi= ts of data (along with some additional ECC data). In half-width (L0p) mod= e, the fits are only 10 bits, and therefore it takes twice as many fits to = transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), t= he transfers here refer to fits. Therefore, in L0, the system will transfe= r 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwid= th of the link by taking: flits*80b/time. Note that this is not the same a= s data bandwidth. For example, when we are transfering a 64B cacheline acr= oss QPI, we will break it into 9 flits -- 1 with header information and 8 w= ith 64 bits of actual data and an additional 16 bits of other information. = To calculate data bandwidth, one should therefore do: data flits * 8B / ti= me.; Counts the number of snoop request flits transmitted over QPI. These = requests are contained in the snoop channel. This does not include snoop r= esponses, which are transmitted on the home channel.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 2; Non-Coherent Byp= ass Tx Flits", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_Q_TxL_FLITS_G2.NCB", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for NDR, NCB, and NCS message classes. Each flit is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four fits, each of which contains 20 bi= ts of data (along with some additional ECC data). In half-width (L0p) mod= e, the fits are only 10 bits, and therefore it takes twice as many fits to = transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), t= he transfers here refer to fits. Therefore, in L0, the system will transfe= r 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwid= th of the link by taking: flits*80b/time. Note that this is not the same a= s data bandwidth. For example, when we are transfering a 64B cacheline acr= oss QPI, we will break it into 9 flits -- 1 with header information and 8 w= ith 64 bits of actual data and an additional 16 bits of other information. = To calculate data bandwidth, one should therefore do: data flits * 8B / ti= me.; Number of Non-Coherent Bypass flits. These packets are generally used= to transmit non-coherent data across QPI.", + "UMask": "0xC", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 2; Non-Coherent dat= a Tx Flits", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_Q_TxL_FLITS_G2.NCB_DATA", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for NDR, NCB, and NCS message classes. Each flit is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four fits, each of which contains 20 bi= ts of data (along with some additional ECC data). In half-width (L0p) mod= e, the fits are only 10 bits, and therefore it takes twice as many fits to = transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), t= he transfers here refer to fits. Therefore, in L0, the system will transfe= r 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwid= th of the link by taking: flits*80b/time. Note that this is not the same a= s data bandwidth. For example, when we are transfering a 64B cacheline acr= oss QPI, we will break it into 9 flits -- 1 with header information and 8 w= ith 64 bits of actual data and an additional 16 bits of other information. = To calculate data bandwidth, one should therefore do: data flits * 8B / ti= me.; Number of Non-Coherent Bypass data flits. These flits are generally u= sed to transmit non-coherent data across QPI. This does not include a coun= t of the DRS (coherent) data flits. This only counts the data flits, not t= e NCB headers.", + "UMask": "0x4", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 2; Non-Coherent non= -data Tx Flits", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_Q_TxL_FLITS_G2.NCB_NONDATA", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for NDR, NCB, and NCS message classes. Each flit is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four fits, each of which contains 20 bi= ts of data (along with some additional ECC data). In half-width (L0p) mod= e, the fits are only 10 bits, and therefore it takes twice as many fits to = transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), t= he transfers here refer to fits. Therefore, in L0, the system will transfe= r 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwid= th of the link by taking: flits*80b/time. Note that this is not the same a= s data bandwidth. For example, when we are transfering a 64B cacheline acr= oss QPI, we will break it into 9 flits -- 1 with header information and 8 w= ith 64 bits of actual data and an additional 16 bits of other information. = To calculate data bandwidth, one should therefore do: data flits * 8B / ti= me.; Number of Non-Coherent Bypass non-data flits. These packets are gener= ally used to transmit non-coherent data across QPI, and the flits counted h= ere are for headers and other non-data flits. This includes extended heade= rs.", + "UMask": "0x8", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 2; Non-Coherent sta= ndard Tx Flits", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_Q_TxL_FLITS_G2.NCS", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for NDR, NCB, and NCS message classes. Each flit is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four fits, each of which contains 20 bi= ts of data (along with some additional ECC data). In half-width (L0p) mod= e, the fits are only 10 bits, and therefore it takes twice as many fits to = transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), t= he transfers here refer to fits. Therefore, in L0, the system will transfe= r 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwid= th of the link by taking: flits*80b/time. Note that this is not the same a= s data bandwidth. For example, when we are transfering a 64B cacheline acr= oss QPI, we will break it into 9 flits -- 1 with header information and 8 w= ith 64 bits of actual data and an additional 16 bits of other information. = To calculate data bandwidth, one should therefore do: data flits * 8B / ti= me.; Number of NCS (non-coherent standard) flits transmitted over QPI. T= his includes extended headers.", + "UMask": "0x10", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 2; Non-Data Respons= e Tx Flits - AD", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for NDR, NCB, and NCS message classes. Each flit is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four fits, each of which contains 20 bi= ts of data (along with some additional ECC data). In half-width (L0p) mod= e, the fits are only 10 bits, and therefore it takes twice as many fits to = transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), t= he transfers here refer to fits. Therefore, in L0, the system will transfe= r 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwid= th of the link by taking: flits*80b/time. Note that this is not the same a= s data bandwidth. For example, when we are transfering a 64B cacheline acr= oss QPI, we will break it into 9 flits -- 1 with header information and 8 w= ith 64 bits of actual data and an additional 16 bits of other information. = To calculate data bandwidth, one should therefore do: data flits * 8B / ti= me.; Counts the total number of flits transmitted over the NDR (Non-Data Re= sponse) channel. This channel is used to send a variety of protocol flits = including grants and completions. This is only for NDR packets to the loca= l socket which use the AK ring.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 2; Non-Data Respons= e Tx Flits - AK", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for NDR, NCB, and NCS message classes. Each flit is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four fits, each of which contains 20 bi= ts of data (along with some additional ECC data). In half-width (L0p) mod= e, the fits are only 10 bits, and therefore it takes twice as many fits to = transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), t= he transfers here refer to fits. Therefore, in L0, the system will transfe= r 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwid= th of the link by taking: flits*80b/time. Note that this is not the same a= s data bandwidth. For example, when we are transfering a 64B cacheline acr= oss QPI, we will break it into 9 flits -- 1 with header information and 8 w= ith 64 bits of actual data and an additional 16 bits of other information. = To calculate data bandwidth, one should therefore do: data flits * 8B / ti= me.; Counts the total number of flits transmitted over the NDR (Non-Data Re= sponse) channel. This channel is used to send a variety of protocol flits = including grants and completions. This is only for NDR packets destined fo= r Route-thru to a remote socket.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Tx Flit Buffer Allocations", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_Q_TxL_INSERTS", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Tx Flit B= uffer. Generally, when data is transmitted across QPI, it will bypass the = TxQ and pass directly to the link. However, the TxQ will be used with L0p = and when LLR occurs, increasing latency to transfer out to the link. This = event can be used in conjunction with the Flit Buffer Occupancy event in or= der to calculate the average flit buffer lifetime.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Tx Flit Buffer Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_Q_TxL_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of flits in the TxQ. = Generally, when data is transmitted across QPI, it will bypass the TxQ and= pass directly to the link. However, the TxQ will be used with L0p and whe= n LLR occurs, increasing latency to transfer out to the link. This can be u= sed with the cycles not empty event to track average occupancy, or the allo= cations event to track average lifetime in the TxQ.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x26", + "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN0", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of link layer credits into the R3 (fo= r transactions across the BGF) acquired each cycle. Flow Control FIFO for H= ome messages on AD.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x26", + "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN1", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of link layer credits into the R3 (fo= r transactions across the BGF) acquired each cycle. Flow Control FIFO for H= ome messages on AD.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for V= N0", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN0", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of li= nk layer credits into the R3 (for transactions across the BGF) available in= each cycle. Flow Control FIFO for HOM messages on AD.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for V= N1", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN1", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of li= nk layer credits into the R3 (for transactions across the BGF) available in= each cycle. Flow Control FIFO for HOM messages on AD.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for V= N0", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN0", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of link layer credits into the R3 (fo= r transactions across the BGF) acquired each cycle. Flow Control FIFO for = NDR messages on AD.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for V= N1", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN1", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of link layer credits into the R3 (fo= r transactions across the BGF) acquired each cycle. Flow Control FIFO for = NDR messages on AD.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for V= N0", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN0", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of li= nk layer credits into the R3 (for transactions across the BGF) available in= each cycle. Flow Control FIFO for NDR messages on AD.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for V= N1", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN1", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of li= nk layer credits into the R3 (for transactions across the BGF) available in= each cycle. Flow Control FIFO for NDR messages on AD.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN0", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of link layer credits into the R3 (fo= r transactions across the BGF) acquired each cycle. Flow Control FIFO for = Snoop messages on AD.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN1", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of link layer credits into the R3 (fo= r transactions across the BGF) acquired each cycle. Flow Control FIFO for = Snoop messages on AD.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for V= N0", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN0", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of li= nk layer credits into the R3 (for transactions across the BGF) available in= each cycle. Flow Control FIFO fro Snoop messages on AD.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for V= N1", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN1", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of li= nk layer credits into the R3 (for transactions across the BGF) available in= each cycle. Flow Control FIFO fro Snoop messages on AD.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of credits into the R3 (for transacti= ons across the BGF) acquired each cycle. Local NDR message class to AK Egre= ss.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR: for V= N0", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED.VN0", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of credits into the R3 (for transacti= ons across the BGF) acquired each cycle. Local NDR message class to AK Egre= ss.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR: for V= N1", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED.VN1", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of credits into the R3 (for transacti= ons across the BGF) acquired each cycle. Local NDR message class to AK Egre= ss.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR", + "Counter": "0,1,2,3", + "EventCode": "0x25", + "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of cr= edits into the R3 (for transactions across the BGF) available in each cycle= . Local NDR message class to AK Egress.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR: for V= N0", + "Counter": "0,1,2,3", + "EventCode": "0x25", + "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY.VN0", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of cr= edits into the R3 (for transactions across the BGF) available in each cycle= . Local NDR message class to AK Egress.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR: for V= N1", + "Counter": "0,1,2,3", + "EventCode": "0x25", + "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY.VN1", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of cr= edits into the R3 (for transactions across the BGF) available in each cycle= . Local NDR message class to AK Egress.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2a", + "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN0", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of credits into the R3 (for transacti= ons across the BGF) acquired each cycle. DRS message class to BL Egress.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x2a", + "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN1", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of credits into the R3 (for transacti= ons across the BGF) acquired each cycle. DRS message class to BL Egress.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for Shar= ed VN", + "Counter": "0,1,2,3", + "EventCode": "0x2a", + "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN_SHR", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of credits into the R3 (for transacti= ons across the BGF) acquired each cycle. DRS message class to BL Egress.", + "UMask": "0x4", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for V= N0", + "Counter": "0,1,2,3", + "EventCode": "0x1f", + "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN0", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of cr= edits into the R3 (for transactions across the BGF) available in each cycle= . DRS message class to BL Egress.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for V= N1", + "Counter": "0,1,2,3", + "EventCode": "0x1f", + "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN1", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of cr= edits into the R3 (for transactions across the BGF) available in each cycle= . DRS message class to BL Egress.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for S= hared VN", + "Counter": "0,1,2,3", + "EventCode": "0x1f", + "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN_SHR", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of cr= edits into the R3 (for transactions across the BGF) available in each cycle= . DRS message class to BL Egress.", + "UMask": "0x4", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2b", + "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN0", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of credits into the R3 (for transacti= ons across the BGF) acquired each cycle. NCB message class to BL Egress.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x2b", + "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN1", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of credits into the R3 (for transacti= ons across the BGF) acquired each cycle. NCB message class to BL Egress.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for V= N0", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN0", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of cr= edits into the R3 (for transactions across the BGF) available in each cycle= . NCB message class to BL Egress.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for V= N1", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN1", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of cr= edits into the R3 (for transactions across the BGF) available in each cycle= . NCB message class to BL Egress.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2c", + "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN0", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of credits into the R3 (for transacti= ons across the BGF) acquired each cycle. NCS message class to BL Egress.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x2c", + "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN1", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of credits into the R3 (for transacti= ons across the BGF) acquired each cycle. NCS message class to BL Egress.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for V= N0", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN0", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of cr= edits into the R3 (for transactions across the BGF) available in each cycle= . NCS message class to BL Egress.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for V= N1", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN1", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of cr= edits into the R3 (for transactions across the BGF) available in each cycle= . NCS message class to BL Egress.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VNA Credits Returned", + "Counter": "0,1,2,3", + "EventCode": "0x1c", + "EventName": "UNC_Q_VNA_CREDIT_RETURNS", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of VNA credits returned.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VNA Credits Pending Return - Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0x1b", + "EventName": "UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of VNA credits in the Rx side that ar= e waitng to be returned back across the link.", + "Unit": "QPI LL" } ] diff --git a/tools/perf/pmu-events/arch/x86/ivytown/uncore-memory.json b/to= ols/perf/pmu-events/arch/x86/ivytown/uncore-memory.json index e8917cb59566..63b49b712c62 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/uncore-memory.json @@ -1,77 +1,1812 @@ [ { - "BriefDescription": "Memory page activates for reads and writes", + "BriefDescription": "DRAM Activate Count; Activate due to Write", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_M_ACT_COUNT.BYP", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRAM Activate commands = sent on this channel. Activate commands are issued to open up a page on th= e DRAM devices so that it can be read or written to with a CAS. One can ca= lculate the number of Page Misses by subtracting the number of Page Miss pr= echarges from the number of Activates.", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Activate Count; Activate due to Read", "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_M_ACT_COUNT.RD", "PerPkg": "1", - "UMask": "0x3", + "PublicDescription": "Counts the number of DRAM Activate commands = sent on this channel. Activate commands are issued to open up a page on th= e DRAM devices so that it can be read or written to with a CAS. One can ca= lculate the number of Page Misses by subtracting the number of Page Miss pr= echarges from the number of Activates.", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Activate Count; Activate due to Write", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_M_ACT_COUNT.WR", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRAM Activate commands = sent on this channel. Activate commands are issued to open up a page on th= e DRAM devices so that it can be read or written to with a CAS. One can ca= lculate the number of Page Misses by subtracting the number of Page Miss pr= echarges from the number of Activates.", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "ACT command issued by 2 cycle bypass", + "Counter": "0,1,2,3", + "EventCode": "0xa1", + "EventName": "UNC_M_BYP_CMDS.ACT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "CAS command issued by 2 cycle bypass", + "Counter": "0,1,2,3", + "EventCode": "0xa1", + "EventName": "UNC_M_BYP_CMDS.CAS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "PRE command issued by 2 cycle bypass", + "Counter": "0,1,2,3", + "EventCode": "0xa1", + "EventName": "UNC_M_BYP_CMDS.PRE", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR= _CAS (w/ and w/out auto-pre)", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.ALL", + "PerPkg": "1", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the = total number of DRAM CAS commands issued on this channel.", + "UMask": "0xF", "Unit": "iMC" }, { - "BriefDescription": "Read requests to memory controller. Derived f= rom unc_m_cas_count.rd", + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Re= ads (RD_CAS + Underfills)", "Counter": "0,1,2,3", "EventCode": "0x4", - "EventName": "LLC_MISSES.MEM_READ", + "EventName": "UNC_M_CAS_COUNT.RD", "PerPkg": "1", - "ScaleUnit": "64Bytes", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the = total number of DRAM Read CAS commands issued on this channel (including un= derfills).", "UMask": "0x3", "Unit": "iMC" }, { - "BriefDescription": "Write requests to memory controller. Derived = from unc_m_cas_count.wr", + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD= _CAS (w/ and w/out auto-pre)", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.RD_REG", + "PerPkg": "1", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the = total number or DRAM Read CAS commands issued on this channel. This includ= es both regular RD CAS commands as well as those with implicit Precharge. = AutoPre is only used in systems that are using closed page policy. We do n= ot filter based on major mode, as RD_CAS is not issued during WMM (with the= exception of underfills).", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS is= sued in RMM", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.RD_RMM", + "PerPkg": "1", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill R= ead Issued", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", + "PerPkg": "1", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the = number of underfill reads that are issued by the memory controller. This w= ill generally be about the same as the number of partial writes, but may be= slightly less because of partials hitting in the WPQ. While it is possibl= e for underfills to be issed in both WMM and RMM, this event counts both.", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS is= sued in WMM", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.RD_WMM", + "PerPkg": "1", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR= _CAS (both Modes)", "Counter": "0,1,2,3", "EventCode": "0x4", - "EventName": "LLC_MISSES.MEM_WRITE", + "EventName": "UNC_M_CAS_COUNT.WR", "PerPkg": "1", - "ScaleUnit": "64Bytes", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the = total number of DRAM Write CAS commands issued on this channel.", "UMask": "0xC", "Unit": "iMC" }, { - "BriefDescription": "Memory controller clock ticks. Use to generat= e percentages for memory controller CYCLES events", + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS= (w/ and w/out auto-pre) in Read Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.WR_RMM", + "PerPkg": "1", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the = total number of Opportunistic DRAM Write CAS commands issued on this channe= l while in Read-Major-Mode.", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS= (w/ and w/out auto-pre) in Write Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.WR_WMM", + "PerPkg": "1", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the = total number or DRAM Write CAS commands issued on this channel while in Wri= te-Major-Mode.", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Clockticks", + "Counter": "0,1,2,3", + "EventName": "UNC_M_DCLOCKTICKS", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Precharge All Commands", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "UNC_M_DRAM_PRE_ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that the precharg= e all command was sent.", + "Unit": "iMC" + }, + { + "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_M_DRAM_REFRESH.HIGH", + "PerPkg": "1", + "PublicDescription": "Counts the number of refreshes issued.", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_M_DRAM_REFRESH.PANIC", + "PerPkg": "1", + "PublicDescription": "Counts the number of refreshes issued.", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "ECC Correctable Errors", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS", + "PerPkg": "1", + "PublicDescription": "Counts the number of ECC errors detected and= corrected by the iMC on this channel. This counter is only useful with EC= C DRAM devices. This count will increment one time for each correction reg= ardless of the number of bits corrected. The iMC can correct up to 4 bit e= rrors in independent channel mode and 8 bit erros in lockstep mode.", + "Unit": "iMC" + }, + { + "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_M_MAJOR_MODES.ISOCH", + "PerPkg": "1", + "PublicDescription": "Counts the total number of cycles spent in a= major mode (selected by a filter) on the given channel. Major modea are = channel-wide, and not a per-rank (or dimm or bank) mode.; We group these tw= o modes together so that we can use four counters to track each of the majo= r modes at one time. These major modes are used whenever there is an ISOCH= txn in the memory controller. In these mode, only ISOCH transactions are = processed.", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "Cycles in a Major Mode; Partial Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_M_MAJOR_MODES.PARTIAL", + "PerPkg": "1", + "PublicDescription": "Counts the total number of cycles spent in a= major mode (selected by a filter) on the given channel. Major modea are = channel-wide, and not a per-rank (or dimm or bank) mode.; This major mode i= s used to drain starved underfill reads. Regular reads and writes are bloc= ked and only underfill reads will be processed.", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "Cycles in a Major Mode; Read Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_M_MAJOR_MODES.READ", + "PerPkg": "1", + "PublicDescription": "Counts the total number of cycles spent in a= major mode (selected by a filter) on the given channel. Major modea are = channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major Mode i= s the default mode for the iMC, as reads are generally more critical to for= ward progress than writes.", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Cycles in a Major Mode; Write Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_M_MAJOR_MODES.WRITE", + "PerPkg": "1", + "PublicDescription": "Counts the total number of cycles spent in a= major mode (selected by a filter) on the given channel. Major modea are = channel-wide, and not a per-rank (or dimm or bank) mode.; This mode is trig= gered when the WPQ hits high occupancy and causes writes to be higher prior= ity than reads. This can cause blips in the available read bandwidth in th= e system and temporarily increase read latencies in order to achieve better= bus utilizations and higher bandwidth.", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Channel DLLOFF Cycles", "Counter": "0,1,2,3", - "EventName": "UNC_M_CLOCKTICKS", + "EventCode": "0x84", + "EventName": "UNC_M_POWER_CHANNEL_DLLOFF", "PerPkg": "1", + "PublicDescription": "Number of cycles when all the ranks in the c= hannel are in CKE Slow (DLLOFF) mode.", "Unit": "iMC" }, { - "BriefDescription": "Cycles where DRAM ranks are in power down (CK= E) mode", + "BriefDescription": "Channel PPD Cycles", "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M_POWER_CHANNEL_PPD", - "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100.= ", - "MetricName": "power_channel_ppd %", "PerPkg": "1", + "PublicDescription": "Number of cycles when all the ranks in the c= hannel are in PPD mode. If IBT=3Doff is enabled, then this can be used to = count those cycles. If it is not enabled, then this can count the number o= f cycles when that could have been taken advantage of.", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK0", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK1", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK2", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK3", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK4", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK5", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK6", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK7", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", + "UMask": "0x80", "Unit": "iMC" }, { - "BriefDescription": "Cycles all ranks are in critical thermal thro= ttle", + "BriefDescription": "Critical Throttle Cycles", "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES", - "MetricExpr": "(UNC_M_POWER_CRITICAL_THROTTLE_CYCLES / UNC_M_CLOCK= TICKS) * 100.", - "MetricName": "power_critical_throttle_cycles %", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the iMC is = in critical thermal throttling. When this happens, all traffic is blocked.= This should be rare unless something bad is going on in the platform. Th= ere is no filtering by rank for this event.", "Unit": "iMC" }, { - "BriefDescription": "Cycles Memory is in self refresh power mode", + "BriefDescription": "Clock-Enabled Self-Refresh", "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M_POWER_SELF_REFRESH", - "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100= .", - "MetricName": "power_self_refresh %", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the iMC is = in self-refresh and the iMC still has a clock. This happens in some packag= e C-states. For example, the PCU may ask the iMC to enter self-refresh eve= n though some of the cores are still processing. One use of this is for Mo= nroe technology. Self-refresh is required during package C3 and C6, but th= ere is no clock in the iMC at this time, so it is not possible to count the= se cases.", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.; Thermal throttling is performed= per DIMM. We support 3 DIMMs per channel. This ID allows us to filter by= ID.", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Preemption Count; Read over Read Preempt= ion", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD", + "PerPkg": "1", + "PublicDescription": "Counts the number of times a read in the iMC= preempts another read or write. Generally reads to an open page are issue= d ahead of requests to closed pages. This improves the page hit rate of th= e system. However, high priority requests can cause pages of active reques= ts to be closed in order to get them out. This will reduce the latency of = the high-priority request at the expense of lower bandwidth and increased o= verall average latency.; Filter for when a read preempts another read.", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Preemption Count; Read over Write Preemp= tion", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR", + "PerPkg": "1", + "PublicDescription": "Counts the number of times a read in the iMC= preempts another read or write. Generally reads to an open page are issue= d ahead of requests to closed pages. This improves the page hit rate of th= e system. However, high priority requests can cause pages of active reques= ts to be closed in order to get them out. This will reduce the latency of = the high-priority request at the expense of lower bandwidth and increased o= verall average latency.; Filter for when a read preempts a write.", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Precharge commands.; Precharge due to by= pass", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_M_PRE_COUNT.BYP", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRAM Precharge commands= sent on this channel.", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Precharge commands.; Precharge due to ti= mer expiration", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRAM Precharge commands= sent on this channel.; Counts the number of DRAM Precharge commands sent o= n this channel as a result of the page close counter expiring. This does n= ot include implicit precharge commands sent in auto-precharge mode.", + "UMask": "0x2", "Unit": "iMC" }, { - "BriefDescription": "Memory page conflicts", + "BriefDescription": "DRAM Precharge commands.; Precharges due to p= age miss", "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.PAGE_MISS", "PerPkg": "1", + "PublicDescription": "Counts the number of DRAM Precharge commands= sent on this channel.; Counts the number of DRAM Precharge commands sent o= n this channel as a result of page misses. This does not include explicit = precharge commands sent with CAS commands in Auto-Precharge mode. This doe= s not include PRE commands sent as a result of the page close counter expir= ation.", "UMask": "0x1", "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Precharge commands.; Precharge due to re= ad", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_M_PRE_COUNT.RD", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRAM Precharge commands= sent on this channel.", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Precharge commands.; Precharge due to wr= ite", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_M_PRE_COUNT.WR", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRAM Precharge commands= sent on this channel.", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "Read CAS issued with HIGH priority", + "Counter": "0,1,2,3", + "EventCode": "0xa0", + "EventName": "UNC_M_RD_CAS_PRIO.HIGH", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "Read CAS issued with LOW priority", + "Counter": "0,1,2,3", + "EventCode": "0xa0", + "EventName": "UNC_M_RD_CAS_PRIO.LOW", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Read CAS issued with MEDIUM priority", + "Counter": "0,1,2,3", + "EventCode": "0xa0", + "EventName": "UNC_M_RD_CAS_PRIO.MED", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority= (starved)", + "Counter": "0,1,2,3", + "EventCode": "0xa0", + "EventName": "UNC_M_RD_CAS_PRIO.PANIC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xb0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xb0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xb0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xb0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xb0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xb0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xb0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xb0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Pending Queue Not Empty", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_M_RPQ_CYCLES_NE", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Read Pe= nding Queue is not empty. This can then be used to calculate the average o= ccupancy (in conjunction with the Read Pending Queue Occupancy count). The= RPQ is used to schedule reads out to the memory controller and to track th= e requests. Requests allocate into the RPQ soon after they enter the memor= y controller, and need credits for an entry in this buffer before being sen= t from the HA to the iMC. They deallocate after the CAS command has been i= ssued to memory. This filter is to be used in conjunction with the occupan= cy filter so that one can correctly track the average occupancies for sched= ulable entries and scheduled requests.", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Pending Queue Allocations", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "UNC_M_RPQ_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the Re= ad Pending Queue. This queue is used to schedule reads out to the memory c= ontroller and to track the requests. Requests allocate into the RPQ soon a= fter they enter the memory controller, and need credits for an entry in thi= s buffer before being sent from the HA to the iMC. They deallocate after t= he CAS command has been issued to memory. This includes both ISOCH and non= -ISOCH requests.", + "Unit": "iMC" + }, + { + "BriefDescription": "VMSE MXB write buffer occupancy", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_M_VMSE_MXB_WR_OCCUPANCY", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued i= n RMM", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_M_VMSE_WR_PUSH.RMM", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued i= n WMM", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_M_VMSE_WR_PUSH.WMM", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Transition from WMM to RMM because of low thr= eshold; Transition from WMM to RMM because of starve counter", + "Counter": "0,1,2,3", + "EventCode": "0xc0", + "EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Transition from WMM to RMM because of low thr= eshold", + "Counter": "0,1,2,3", + "EventCode": "0xc0", + "EventName": "UNC_M_WMM_TO_RMM.STARVE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Transition from WMM to RMM because of low thr= eshold", + "Counter": "0,1,2,3", + "EventCode": "0xc0", + "EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue Full Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_M_WPQ_CYCLES_FULL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the Write P= ending Queue is full. When the WPQ is full, the HA will not be able to iss= ue any additional read requests into the iMC. This count should be similar= count in the HA which tracks the number of cycles that the HA has no WPQ c= redits, just somewhat smaller to account for the credit return overhead.", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue Not Empty", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_M_WPQ_CYCLES_NE", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Write P= ending Queue is not empty. This can then be used to calculate the average = queue occupancy (in conjunction with the WPQ Occupancy Accumulation count).= The WPQ is used to schedule write out to the memory controller and to tra= ck the writes. Requests allocate into the WPQ soon after they enter the me= mory controller, and need credits for an entry in this buffer before being = sent from the HA to the iMC. They deallocate after being issued to DRAM. = Write requests themselves are able to complete (from the perspective of the= rest of the system) as soon they have posted to the iMC. This is not to b= e confused with actually performing the write to DRAM. Therefore, the aver= age latency for this queue is actually not useful for deconstruction interm= ediate write latencies.", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue Allocations", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_M_WPQ_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the Wr= ite Pending Queue. This can then be used to calculate the average queuing = latency (in conjunction with the WPQ occupancy count). The WPQ is used to = schedule write out to the memory controller and to track the writes. Reque= sts allocate into the WPQ soon after they enter the memory controller, and = need credits for an entry in this buffer before being sent from the HA to t= he iMC. They deallocate after being issued to DRAM. Write requests themse= lves are able to complete (from the perspective of the rest of the system) = as soon they have posted to the iMC.", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_M_WPQ_READ_HIT", + "PerPkg": "1", + "PublicDescription": "Counts the number of times a request hits in= the WPQ (write-pending queue). The iMC allows writes and reads to pass up= other writes to different addresses. Before a read or a write is issued, = it will first CAM the WPQ to see if there is a write pending to that addres= s. When reads hit, they are able to directly pull their data from the WPQ = instead of going to memory. Writes that hit will overwrite the existing da= ta. Partial writes that hit will not need to do underfill reads and will s= imply update their relevant sections.", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_M_WPQ_WRITE_HIT", + "PerPkg": "1", + "PublicDescription": "Counts the number of times a request hits in= the WPQ (write-pending queue). The iMC allows writes and reads to pass up= other writes to different addresses. Before a read or a write is issued, = it will first CAM the WPQ to see if there is a write pending to that addres= s. When reads hit, they are able to directly pull their data from the WPQ = instead of going to memory. Writes that hit will overwrite the existing da= ta. Partial writes that hit will not need to do underfill reads and will s= imply update their relevant sections.", + "Unit": "iMC" + }, + { + "BriefDescription": "Not getting the requested Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0xc1", + "EventName": "UNC_M_WRONG_MM", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xb8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xb8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xb8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xb8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xb8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xb8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xb8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xb8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" } ] diff --git a/tools/perf/pmu-events/arch/x86/ivytown/uncore-other.json b/too= ls/perf/pmu-events/arch/x86/ivytown/uncore-other.json new file mode 100644 index 000000000000..aa7a5059d79f --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/ivytown/uncore-other.json @@ -0,0 +1,2411 @@ +[ + { + "BriefDescription": "Address Match (Conflict) Count; Conflict Merg= es", + "Counter": "0,1", + "EventCode": "0x17", + "EventName": "UNC_I_ADDRESS_MATCH.MERGE_COUNT", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when an inbound w= rite (from a device to memory or another device) had an address match with = another request in the write cache.; When two requests to the same address = from the same source are received back to back, it is possible to merge the= two of them together.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Address Match (Conflict) Count; Conflict Stal= ls", + "Counter": "0,1", + "EventCode": "0x17", + "EventName": "UNC_I_ADDRESS_MATCH.STALL_COUNT", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when an inbound w= rite (from a device to memory or another device) had an address match with = another request in the write cache.; When it is not possible to merge two c= onflicting requests, a stall event occurs. This is bad for performance.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Write Ack Pending Occupancy; Any Source", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.ANY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of writes that have a= cquired ownership but have not yet returned their data to the uncore. Thes= e writes are generally queued up in the switch trying to get to the head of= their queues so that they can post their data. The queue occuapancy incre= ments when the ACK is received, and decrements when either the data is retu= rned OR a tickle is received and ownership is released. Note that a single= tickle can result in multiple decrements.; Tracks only those requests that= come from the port specified in the IRP_PmonFilter.OrderingQ register. Th= is register allows one to select one specific queue. It is not possible to= monitor multiple queues at a time.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Write Ack Pending Occupancy; Select Source", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.SOURCE", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of writes that have a= cquired ownership but have not yet returned their data to the uncore. Thes= e writes are generally queued up in the switch trying to get to the head of= their queues so that they can post their data. The queue occuapancy incre= ments when the ACK is received, and decrements when either the data is retu= rned OR a tickle is received and ownership is released. Note that a single= tickle can result in multiple decrements.; Tracks all requests from any so= urce port.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Outstanding Write Ownership Occupancy; Any So= urce", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_CACHE_OWN_OCCUPANCY.ANY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of writes (and write = prefetches) that are outstanding in the uncore trying to acquire ownership = in each cycle. This can be used with the write transaction count to calcul= ate the average write latency in the uncore. The occupancy increments when= a write request is issued, and decrements when the data is returned.; Trac= ks all requests from any source port.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Outstanding Write Ownership Occupancy; Select= Source", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_CACHE_OWN_OCCUPANCY.SOURCE", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of writes (and write = prefetches) that are outstanding in the uncore trying to acquire ownership = in each cycle. This can be used with the write transaction count to calcul= ate the average write latency in the uncore. The occupancy increments when= a write request is issued, and decrements when the data is returned.; Trac= ks only those requests that come from the port specified in the IRP_PmonFil= ter.OrderingQ register. This register allows one to select one specific qu= eue. It is not possible to monitor multiple queues at a time.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Outstanding Read Occupancy; Any Source", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_I_CACHE_READ_OCCUPANCY.ANY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of reads that are out= standing in the uncore in each cycle. This can be used with the read trans= action count to calculate the average read latency in the uncore. The occu= pancy increments when a read request is issued, and decrements when the dat= a is returned.; Tracks all requests from any source port.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Outstanding Read Occupancy; Select Source", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_I_CACHE_READ_OCCUPANCY.SOURCE", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of reads that are out= standing in the uncore in each cycle. This can be used with the read trans= action count to calculate the average read latency in the uncore. The occu= pancy increments when a read request is issued, and decrements when the dat= a is returned.; Tracks only those requests that come from the port specifie= d in the IRP_PmonFilter.OrderingQ register. This register allows one to se= lect one specific queue. It is not possible to monitor multiple queues at = a time.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Total Write Cache Occupancy; Any Source", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of reads and writes t= hat are outstanding in the uncore in each cycle. This is effectively the s= um of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests f= rom any source port.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Total Write Cache Occupancy; Select Source", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of reads and writes t= hat are outstanding in the uncore in each cycle. This is effectively the s= um of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks only those req= uests that come from the port specified in the IRP_PmonFilter.OrderingQ reg= ister. This register allows one to select one specific queue. It is not p= ossible to monitor multiple queues at a time.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Outstanding Write Occupancy; Any Source", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_I_CACHE_WRITE_OCCUPANCY.ANY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of writes (and write = prefetches) that are outstanding in the uncore in each cycle. This can be= used with the transaction count event to calculate the average latency in = the uncore. The occupancy increments when the ownership fetch/prefetch is = issued, and decrements the data is returned to the uncore.; Tracks all requ= ests from any source port.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Outstanding Write Occupancy; Select Source", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_I_CACHE_WRITE_OCCUPANCY.SOURCE", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of writes (and write = prefetches) that are outstanding in the uncore in each cycle. This can be= used with the transaction count event to calculate the average latency in = the uncore. The occupancy increments when the ownership fetch/prefetch is = issued, and decrements the data is returned to the uncore.; Tracks only tho= se requests that come from the port specified in the IRP_PmonFilter.Orderin= gQ register. This register allows one to select one specific queue. It is= not possible to monitor multiple queues at a time.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Clocks in the IRP", + "Counter": "0,1", + "EventName": "UNC_I_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Number of clocks in the IRP.", + "Unit": "IRP" + }, + { + "Counter": "0,1", + "EventCode": "0xb", + "EventName": "UNC_I_RxR_AK_CYCLES_FULL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the AK Ingr= ess is full. This queue is where the IRP receives responses from R2PCIe (t= he ring).", + "Unit": "IRP" + }, + { + "BriefDescription": "AK Ingress Occupancy", + "Counter": "0,1", + "EventCode": "0xa", + "EventName": "UNC_I_RxR_AK_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the AK= Ingress. This queue is where the IRP receives responses from R2PCIe (the = ring).", + "Unit": "IRP" + }, + { + "Counter": "0,1", + "EventCode": "0xc", + "EventName": "UNC_I_RxR_AK_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the AK Ingress = in each cycles. This queue is where the IRP receives responses from R2PCIe= (the ring).", + "Unit": "IRP" + }, + { + "Counter": "0,1", + "EventCode": "0x4", + "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the BL Ingr= ess is full. This queue is where the IRP receives data from R2PCIe (the ri= ng). It is used for data returns from read requets as well as outbound MMI= O writes.", + "Unit": "IRP" + }, + { + "BriefDescription": "BL Ingress Occupancy - DRS", + "Counter": "0,1", + "EventCode": "0x1", + "EventName": "UNC_I_RxR_BL_DRS_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the BL= Ingress. This queue is where the IRP receives data from R2PCIe (the ring)= . It is used for data returns from read requets as well as outbound MMIO w= rites.", + "Unit": "IRP" + }, + { + "Counter": "0,1", + "EventCode": "0x7", + "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the BL Ingress = in each cycles. This queue is where the IRP receives data from R2PCIe (the= ring). It is used for data returns from read requets as well as outbound = MMIO writes.", + "Unit": "IRP" + }, + { + "Counter": "0,1", + "EventCode": "0x5", + "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the BL Ingr= ess is full. This queue is where the IRP receives data from R2PCIe (the ri= ng). It is used for data returns from read requets as well as outbound MMI= O writes.", + "Unit": "IRP" + }, + { + "BriefDescription": "BL Ingress Occupancy - NCB", + "Counter": "0,1", + "EventCode": "0x2", + "EventName": "UNC_I_RxR_BL_NCB_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the BL= Ingress. This queue is where the IRP receives data from R2PCIe (the ring)= . It is used for data returns from read requets as well as outbound MMIO w= rites.", + "Unit": "IRP" + }, + { + "Counter": "0,1", + "EventCode": "0x8", + "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the BL Ingress = in each cycles. This queue is where the IRP receives data from R2PCIe (the= ring). It is used for data returns from read requets as well as outbound = MMIO writes.", + "Unit": "IRP" + }, + { + "Counter": "0,1", + "EventCode": "0x6", + "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the BL Ingr= ess is full. This queue is where the IRP receives data from R2PCIe (the ri= ng). It is used for data returns from read requets as well as outbound MMI= O writes.", + "Unit": "IRP" + }, + { + "BriefDescription": "BL Ingress Occupancy - NCS", + "Counter": "0,1", + "EventCode": "0x3", + "EventName": "UNC_I_RxR_BL_NCS_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the BL= Ingress. This queue is where the IRP receives data from R2PCIe (the ring)= . It is used for data returns from read requets as well as outbound MMIO w= rites.", + "Unit": "IRP" + }, + { + "Counter": "0,1", + "EventCode": "0x9", + "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the BL Ingress = in each cycles. This queue is where the IRP receives data from R2PCIe (the= ring). It is used for data returns from read requets as well as outbound = MMIO writes.", + "Unit": "IRP" + }, + { + "BriefDescription": "Tickle Count; Ownership Lost", + "Counter": "0,1", + "EventCode": "0x16", + "EventName": "UNC_I_TICKLES.LOST_OWNERSHIP", + "PerPkg": "1", + "PublicDescription": "Counts the number of tickles that are receiv= ed. This is for both explicit (from Cbo) and implicit (internal conflict) = tickles.; Tracks the number of requests that lost ownership as a result of = a tickle. When a tickle comes in, if the request is not at the head of the= queue in the switch, then that request as well as any requests behind it i= n the switch queue will lose ownership and have to re-acquire it later when= they get to the head of the queue. This will therefore track the number o= f requests that lost ownership and not just the number of tickles.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Tickle Count; Data Returned", + "Counter": "0,1", + "EventCode": "0x16", + "EventName": "UNC_I_TICKLES.TOP_OF_QUEUE", + "PerPkg": "1", + "PublicDescription": "Counts the number of tickles that are receiv= ed. This is for both explicit (from Cbo) and implicit (internal conflict) = tickles.; Tracks the number of cases when a tickle was received but the req= uests was at the head of the queue in the switch. In this case, data is re= turned rather than releasing ownership.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Select Source", + "Counter": "0,1", + "EventCode": "0x15", + "EventName": "UNC_I_TRANSACTIONS.ORDERINGQ", + "Filter": "IRPFilter[4:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions fr= om the IRP to the Uncore. This can be filtered based on request type in ad= dition to the source queue. Note the special filtering equation. We do OR= -reduction on the request type. If the SOURCE bit is set, then we also do = AND qualification based on the source portID.; Tracks only those requests t= hat come from the port specified in the IRP_PmonFilter.OrderingQ register. = This register allows one to select one specific queue. It is not possible= to monitor multiple queues at a time. If this bit is not set, then reques= ts from all sources will be counted.", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count: Read Prefetches", + "Counter": "0,1", + "EventCode": "0x15", + "EventName": "UNC_I_TRANSACTIONS.PD_PREFETCHES", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions fr= om the IRP to the Uncore. This can be filtered based on request type in ad= dition to the source queue. Note the special filtering equation. We do OR= -reduction on the request type. If the SOURCE bit is set, then we also do = AND qualification based on the source portID.", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Read Prefetches", + "Counter": "0,1", + "EventCode": "0x15", + "EventName": "UNC_I_TRANSACTIONS.RD_PREFETCHES", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions fr= om the IRP to the Uncore. This can be filtered based on request type in ad= dition to the source queue. Note the special filtering equation. We do OR= -reduction on the request type. If the SOURCE bit is set, then we also do = AND qualification based on the source portID.; Tracks the number of read pr= efetches.", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Reads", + "Counter": "0,1", + "EventCode": "0x15", + "EventName": "UNC_I_TRANSACTIONS.READS", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions fr= om the IRP to the Uncore. This can be filtered based on request type in ad= dition to the source queue. Note the special filtering equation. We do OR= -reduction on the request type. If the SOURCE bit is set, then we also do = AND qualification based on the source portID.; Tracks only read requests (n= ot including read prefetches).", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Writes", + "Counter": "0,1", + "EventCode": "0x15", + "EventName": "UNC_I_TRANSACTIONS.WRITES", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions fr= om the IRP to the Uncore. This can be filtered based on request type in ad= dition to the source queue. Note the special filtering equation. We do OR= -reduction on the request type. If the SOURCE bit is set, then we also do = AND qualification based on the source portID.; Trackes only write requests.= Each write request should have a prefetch, so there is no need to explici= tly track these requests. For writes that are tickled and have to retry, t= he counter will be incremented for each retry.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "No AD Egress Credit Stalls", + "Counter": "0,1", + "EventCode": "0x18", + "EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number times when it is not possi= ble to issue a request to the R2PCIe because there are no AD Egress Credits= available.", + "Unit": "IRP" + }, + { + "BriefDescription": "No BL Egress Credit Stalls", + "Counter": "0,1", + "EventCode": "0x19", + "EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number times when it is not possi= ble to issue data to the R2PCIe because there are no BL Egress Credits avai= lable.", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", + "EventCode": "0xe", + "EventName": "UNC_I_TxR_DATA_INSERTS_NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of requests issued to the = switch (towards the devices).", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", + "EventCode": "0xf", + "EventName": "UNC_I_TxR_DATA_INSERTS_NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of requests issued to the = switch (towards the devices).", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Request Queue Occupancy", + "Counter": "0,1", + "EventCode": "0xd", + "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumultes the number of outstanding outboun= d requests from the IRP to the switch (towards the devices). This can be u= sed in conjuection with the allocations event in order to calculate average= latency of outbound requests.", + "Unit": "IRP" + }, + { + "BriefDescription": "Write Ordering Stalls", + "Counter": "0,1", + "EventCode": "0x1a", + "EventName": "UNC_I_WRITE_ORDERING_STALL_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are p= ending write ACK's in the switch but the switch->IRP pipeline is not utiliz= ed.", + "Unit": "IRP" + }, + { + "BriefDescription": "Number of uclks in domain", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_R2_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Counts the number of uclks in the R2PCIe ucl= k domain. This could be slightly different than the count in the Ubox beca= use of enable/freeze delays. However, because the R2PCIe is close to the U= box, they generally should not diverge by more than a handful of cycles.", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credit Acquired; DRS", + "Counter": "0,1", + "EventCode": "0x33", + "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of credits that are acquir= ed in the R2PCIe agent for sending transactions into the IIO on either NCB = or NCS are in use. Transactions from the BL ring going into the IIO Agent = must first acquire a credit. These credits are for either the NCB or NCS m= essage classes. NCB, or non-coherent bypass messages are used to transmit = data without coherency (and are common). NCS is used for reads to PCIe (an= d should be used sparingly).; Credits to the IIO for the DRS message class.= ", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credit Acquired; NCB", + "Counter": "0,1", + "EventCode": "0x33", + "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of credits that are acquir= ed in the R2PCIe agent for sending transactions into the IIO on either NCB = or NCS are in use. Transactions from the BL ring going into the IIO Agent = must first acquire a credit. These credits are for either the NCB or NCS m= essage classes. NCB, or non-coherent bypass messages are used to transmit = data without coherency (and are common). NCS is used for reads to PCIe (an= d should be used sparingly).; Credits to the IIO for the NCB message class.= ", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credit Acquired; NCS", + "Counter": "0,1", + "EventCode": "0x33", + "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of credits that are acquir= ed in the R2PCIe agent for sending transactions into the IIO on either NCB = or NCS are in use. Transactions from the BL ring going into the IIO Agent = must first acquire a credit. These credits are for either the NCB or NCS m= essage classes. NCB, or non-coherent bypass messages are used to transmit = data without coherency (and are common). NCS is used for reads to PCIe (an= d should be used sparingly).; Credits to the IIO for the NCS message class.= ", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Failed to Acquire a Credit; DRS", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_R2_IIO_CREDITS_REJECT.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that a request pe= nding in the BL Ingress attempted to acquire either a NCB or NCS credit to = transmit into the IIO, but was rejected because no credits were available. = NCB, or non-coherent bypass messages are used to transmit data without coh= erency (and are common). NCS is used for reads to PCIe (and should be used= sparingly).; Credits to the IIO for the DRS message class.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credits in Use; DRS", + "Counter": "0,1", + "EventCode": "0x32", + "EventName": "UNC_R2_IIO_CREDITS_USED.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when one or more= credits in the R2PCIe agent for sending transactions into the IIO on eithe= r NCB or NCS are in use. Transactions from the BL ring going into the IIO = Agent must first acquire a credit. These credits are for either the NCB or= NCS message classes. NCB, or non-coherent bypass messages are used to tra= nsmit data without coherency (and are common). NCS is used for reads to PC= Ie (and should be used sparingly).; Credits to the IIO for the DRS message = class.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credits in Use; NCB", + "Counter": "0,1", + "EventCode": "0x32", + "EventName": "UNC_R2_IIO_CREDITS_USED.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when one or more= credits in the R2PCIe agent for sending transactions into the IIO on eithe= r NCB or NCS are in use. Transactions from the BL ring going into the IIO = Agent must first acquire a credit. These credits are for either the NCB or= NCS message classes. NCB, or non-coherent bypass messages are used to tra= nsmit data without coherency (and are common). NCS is used for reads to PC= Ie (and should be used sparingly).; Credits to the IIO for the NCB message = class.", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credits in Use; NCS", + "Counter": "0,1", + "EventCode": "0x32", + "EventName": "UNC_R2_IIO_CREDITS_USED.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when one or more= credits in the R2PCIe agent for sending transactions into the IIO on eithe= r NCB or NCS are in use. Transactions from the BL ring going into the IIO = Agent must first acquire a credit. These credits are for either the NCB or= NCS message classes. NCB, or non-coherent bypass messages are used to tra= nsmit data without coherency (and are common). NCS is used for reads to PC= Ie (and should be used sparingly).; Credits to the IIO for the NCS message = class.", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0xCC", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even = on VRing 0", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CCW_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Even rin= g polarity on Virtual Ring 0.", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd o= n VRing 0", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CCW_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Odd ring= polarity on Virtual Ring 0.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even = on VRing 1", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CCW_VR1_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Even rin= g polarity on Virtual Ring 1.", + "UMask": "0x40", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd o= n VRing 1", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CCW_VR1_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Odd ring= polarity on Virtual Ring 1.", + "UMask": "0x80", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Clockwise", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x33", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Clockwise and Even on VRin= g 0", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CW_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Even ring polar= ity on Virtual Ring 0.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd on VRing= 0", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CW_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Odd ring polari= ty on Virtual Ring 0.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Clockwise and Even on VRin= g 1", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CW_VR1_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Even ring polar= ity on Virtual Ring 1.", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd on VRing= 1", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CW_VR1_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Odd ring polari= ty on Virtual Ring 1.", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0xCC", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even = on VRing 0", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CCW_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Even rin= g polarity on Virtual Ring 0.", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd o= n VRing 0", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CCW_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Odd ring= polarity on Virtual Ring 0.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even = on VRing 1", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CCW_VR1_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Even rin= g polarity on Virtual Ring 1.", + "UMask": "0x40", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd o= n VRing 1", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CCW_VR1_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Odd ring= polarity on Virtual Ring 1.", + "UMask": "0x80", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Clockwise", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x33", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Clockwise and Even on VRin= g 0", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CW_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Even ring polar= ity on Virtual Ring 0.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd on VRing= 0", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CW_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Odd ring polari= ty on Virtual Ring 0.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Clockwise and Even on VRin= g 1", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CW_VR1_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Even ring polar= ity on Virtual Ring 1.", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd on VRing= 1", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CW_VR1_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Odd ring polari= ty on Virtual Ring 1.", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0xCC", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even = on VRing 0", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CCW_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Even rin= g polarity on Virtual Ring 0.", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd o= n VRing 0", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CCW_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Odd ring= polarity on Virtual Ring 0.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even = on VRing 1", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CCW_VR1_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Even rin= g polarity on Virtual Ring 1.", + "UMask": "0x40", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd o= n VRing 1", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CCW_VR1_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Odd ring= polarity on Virtual Ring 1.", + "UMask": "0x80", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Clockwise", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x33", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Clockwise and Even on VRin= g 0", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CW_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Even ring polar= ity on Virtual Ring 0.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd on VRing= 0", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CW_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Odd ring polari= ty on Virtual Ring 0.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Clockwise and Even on VRin= g 1", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CW_VR1_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Even ring polar= ity on Virtual Ring 1.", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd on VRing= 1", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CW_VR1_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Odd ring polari= ty on Virtual Ring 1.", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 IV Ring in Use; Any", + "Counter": "0,1,2,3", + "EventCode": "0xA", + "EventName": "UNC_R2_RING_IV_USED.ANY", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sent, but does not include when packets are be= ing sunk into the ring stop. The IV ring is unidirectional. Whether UP or= DN is used is dependent on the system programming. Thereofore, one should= generally set both the UP and DN bits for a given polarity (or both) at a = given time.; Filters any polarity", + "UMask": "0xFF", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 IV Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", + "EventCode": "0xa", + "EventName": "UNC_R2_RING_IV_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sent, but does not include when packets are be= ing sunk into the ring stop. The IV ring is unidirectional. Whether UP or= DN is used is dependent on the system programming. Thereofore, one should= generally set both the UP and DN bits for a given polarity (or both) at a = given time.; Filters for Counterclockwise polarity", + "UMask": "0xCC", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 IV Ring in Use; Clockwise", + "Counter": "0,1,2,3", + "EventCode": "0xa", + "EventName": "UNC_R2_RING_IV_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sent, but does not include when packets are be= ing sunk into the ring stop. The IV ring is unidirectional. Whether UP or= DN is used is dependent on the system programming. Thereofore, one should= generally set both the UP and DN bits for a given polarity (or both) at a = given time.; Filters for Clockwise polarity", + "UMask": "0x33", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "AK Ingress Bounced", + "EventCode": "0x12", + "EventName": "UNC_R2_RxR_AK_BOUNCES", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a request de= stined for the AK ingress bounced.", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "AK Ingress Bounced; Counterclockwise", + "EventCode": "0x12", + "EventName": "UNC_R2_RxR_AK_BOUNCES.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a request de= stined for the AK ingress bounced.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "AK Ingress Bounced; Clockwise", + "EventCode": "0x12", + "EventName": "UNC_R2_RxR_AK_BOUNCES.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a request de= stined for the AK ingress bounced.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; NCB", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_R2_RxR_CYCLES_NE.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe = Ingress is not empty. This tracks one of the three rings that are used by = the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress = Occupancy Accumulator event in order to calculate average queue occupancy. = Multiple ingress buffers can be tracked at a given time using multiple cou= nters.; NCB Ingress Queue", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; NCS", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_R2_RxR_CYCLES_NE.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe = Ingress is not empty. This tracks one of the three rings that are used by = the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress = Occupancy Accumulator event in order to calculate average queue occupancy. = Multiple ingress buffers can be tracked at a given time using multiple cou= nters.; NCS Ingress Queue", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Allocations; NCB", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_R2_RxR_INSERTS.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the R2= PCIe Ingress. This tracks one of the three rings that are used by the R2PC= Ie agent. This can be used in conjunction with the R2PCIe Ingress Occupanc= y Accumulator event in order to calculate average queue latency. Multiple = ingress buffers can be tracked at a given time using multiple counters.; NC= B Ingress Queue", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Allocations; NCS", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_R2_RxR_INSERTS.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the R2= PCIe Ingress. This tracks one of the three rings that are used by the R2PC= Ie agent. This can be used in conjunction with the R2PCIe Ingress Occupanc= y Accumulator event in order to calculate average queue latency. Multiple = ingress buffers can be tracked at a given time using multiple counters.; NC= S Ingress Queue", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Occupancy Accumulator; DRS", + "EventCode": "0x13", + "EventName": "UNC_R2_RxR_OCCUPANCY.DRS", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given R2PCIe = Ingress queue in each cycles. This tracks one of the three ring Ingress bu= ffers. This can be used with the R2PCIe Ingress Not Empty event to calcula= te average occupancy or the R2PCIe Ingress Allocations event in order to ca= lculate average queuing latency.; DRS Ingress Queue", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Full; AD", + "EventCode": "0x25", + "EventName": "UNC_R2_TxR_CYCLES_FULL.AD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe = Egress buffer is full.; AD Egress Queue", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Full; AK", + "EventCode": "0x25", + "EventName": "UNC_R2_TxR_CYCLES_FULL.AK", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe = Egress buffer is full.; AK Egress Queue", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Full; BL", + "EventCode": "0x25", + "EventName": "UNC_R2_TxR_CYCLES_FULL.BL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe = Egress buffer is full.; BL Egress Queue", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Not Empty; AD", + "EventCode": "0x23", + "EventName": "UNC_R2_TxR_CYCLES_NE.AD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe = Egress is not empty. This tracks one of the three rings that are used by t= he R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Oc= cupancy Accumulator event in order to calculate average queue occupancy. O= nly a single Egress queue can be tracked at any given time. It is not poss= ible to filter based on direction or polarity.; AD Egress Queue", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Not Empty; AK", + "EventCode": "0x23", + "EventName": "UNC_R2_TxR_CYCLES_NE.AK", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe = Egress is not empty. This tracks one of the three rings that are used by t= he R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Oc= cupancy Accumulator event in order to calculate average queue occupancy. O= nly a single Egress queue can be tracked at any given time. It is not poss= ible to filter based on direction or polarity.; AK Egress Queue", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Not Empty; BL", + "EventCode": "0x23", + "EventName": "UNC_R2_TxR_CYCLES_NE.BL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe = Egress is not empty. This tracks one of the three rings that are used by t= he R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Oc= cupancy Accumulator event in order to calculate average queue occupancy. O= nly a single Egress queue can be tracked at any given time. It is not poss= ible to filter based on direction or polarity.; BL Egress Queue", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; AD CCW", + "Counter": "0,1", + "EventCode": "0x28", + "EventName": "UNC_R2_TxR_NACK_CCW.AD", + "PerPkg": "1", + "PublicDescription": "AD CounterClockwise Egress Queue", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; AK CCW", + "Counter": "0,1", + "EventCode": "0x28", + "EventName": "UNC_R2_TxR_NACK_CCW.AK", + "PerPkg": "1", + "PublicDescription": "AK CounterClockwise Egress Queue", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; BL CCW", + "Counter": "0,1", + "EventCode": "0x28", + "EventName": "UNC_R2_TxR_NACK_CCW.BL", + "PerPkg": "1", + "PublicDescription": "BL CounterClockwise Egress Queue", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CW NACK; AD CW", + "Counter": "0,1", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.AD", + "PerPkg": "1", + "PublicDescription": "AD Clockwise Egress Queue", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CW NACK; AK CW", + "Counter": "0,1", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.AK", + "PerPkg": "1", + "PublicDescription": "AK Clockwise Egress Queue", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CW NACK; BL CW", + "Counter": "0,1", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.BL", + "PerPkg": "1", + "PublicDescription": "BL Clockwise Egress Queue", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Number of uclks in domain", + "Counter": "0,1,2", + "EventCode": "0x1", + "EventName": "UNC_R3_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Counts the number of uclks in the QPI uclk d= omain. This could be slightly different than the count in the Ubox because= of enable/freeze delays. However, because the QPI Agent is close to the U= box, they generally should not diverge by more than a handful of cycles.", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2c", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO10", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the = AD Ring (covers higher CBoxes); Cbox 10", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2c", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO11", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the = AD Ring (covers higher CBoxes); Cbox 11", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2c", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO12", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the = AD Ring (covers higher CBoxes); Cbox 12", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2c", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO13", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the = AD Ring (covers higher CBoxes); Cbox 13", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2c", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO14", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the = AD Ring (covers higher CBoxes); Cbox 14&16", + "UMask": "0x40", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2c", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO8", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the = AD Ring (covers higher CBoxes); Cbox 8", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2c", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO9", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the = AD Ring (covers higher CBoxes); Cbox 9", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2b", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO0", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the = AD Ring (covers lower CBoxes); Cbox 0", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2b", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO1", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the = AD Ring (covers lower CBoxes); Cbox 1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2b", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO2", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the = AD Ring (covers lower CBoxes); Cbox 2", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2b", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO3", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the = AD Ring (covers lower CBoxes); Cbox 3", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2b", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO4", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the = AD Ring (covers lower CBoxes); Cbox 4", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2b", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO5", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the = AD Ring (covers lower CBoxes); Cbox 5", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2b", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO6", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the = AD Ring (covers lower CBoxes); Cbox 6", + "UMask": "0x40", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2b", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO7", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the = AD Ring (covers lower CBoxes); Cbox 7", + "UMask": "0x80", + "Unit": "R3QPI" + }, + { + "BriefDescription": "HA/R2 AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2f", + "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA0", + "PerPkg": "1", + "PublicDescription": "No credits available to send to either HA or= R2 on the BL Ring; HA0", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "HA/R2 AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2f", + "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA1", + "PerPkg": "1", + "PublicDescription": "No credits available to send to either HA or= R2 on the BL Ring; HA1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "HA/R2 AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2f", + "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCB", + "PerPkg": "1", + "PublicDescription": "No credits available to send to either HA or= R2 on the BL Ring; R2 NCB Messages", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "HA/R2 AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2f", + "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCS", + "PerPkg": "1", + "PublicDescription": "No credits available to send to either HA or= R2 on the BL Ring; R2 NCS Messages", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x29", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_HOM", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the = AD Ring; VN0 HOM Messages", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x29", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_NDR", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the = AD Ring; VN0 NDR Messages", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x29", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the = AD Ring; VN0 SNP Messages", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x29", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_HOM", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the = AD Ring; VN1 HOM Messages", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x29", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_NDR", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the = AD Ring; VN1 NDR Messages", + "UMask": "0x40", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x29", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the = AD Ring; VN1 SNP Messages", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x29", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the = AD Ring; VNA", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 BL Credits Empty", + "Counter": "0,1", + "EventCode": "0x2d", + "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN0_HOM", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the = BL Ring; VN0 HOM Messages", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 BL Credits Empty", + "Counter": "0,1", + "EventCode": "0x2d", + "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN0_NDR", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the = BL Ring; VN0 NDR Messages", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 BL Credits Empty", + "Counter": "0,1", + "EventCode": "0x2d", + "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the = BL Ring; VN0 SNP Messages", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 BL Credits Empty", + "Counter": "0,1", + "EventCode": "0x2d", + "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_HOM", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the = BL Ring; VN1 HOM Messages", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 BL Credits Empty", + "Counter": "0,1", + "EventCode": "0x2d", + "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_NDR", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the = BL Ring; VN1 NDR Messages", + "UMask": "0x40", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 BL Credits Empty", + "Counter": "0,1", + "EventCode": "0x2d", + "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the = BL Ring; VN1 SNP Messages", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 BL Credits Empty", + "Counter": "0,1", + "EventCode": "0x2d", + "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the = BL Ring; VNA", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2a", + "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN0_HOM", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the = AD Ring; VN0 HOM Messages", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2a", + "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN0_NDR", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the = AD Ring; VN0 NDR Messages", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2a", + "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the = AD Ring; VN0 SNP Messages", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2a", + "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_HOM", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the = AD Ring; VN1 HOM Messages", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2a", + "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_NDR", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the = AD Ring; VN1 NDR Messages", + "UMask": "0x40", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2a", + "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the = AD Ring; VN1 SNP Messages", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2a", + "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the = AD Ring; VNA", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", + "EventCode": "0x2e", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_HOM", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the = BL Ring; VN0 HOM Messages", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", + "EventCode": "0x2e", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_NDR", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the = BL Ring; VN0 NDR Messages", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", + "EventCode": "0x2e", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the = BL Ring; VN0 SNP Messages", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", + "EventCode": "0x2e", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_HOM", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the = BL Ring; VN1 HOM Messages", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", + "EventCode": "0x2e", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_NDR", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the = BL Ring; VN1 NDR Messages", + "UMask": "0x40", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", + "EventCode": "0x2e", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the = BL Ring; VN1 SNP Messages", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", + "EventCode": "0x2e", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the = BL Ring; VNA", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Counterclockwise", + "Counter": "0,1,2", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0xCC", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Even = on VRing 0", + "Counter": "0,1,2", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CCW_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Even rin= g polarity on Virtual Ring 0.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Odd o= n VRing 0", + "Counter": "0,1,2", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CCW_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Odd ring= polarity on Virtual Ring 0.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Clockwise", + "Counter": "0,1,2", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x33", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Clockwise and Even on VRin= g 0", + "Counter": "0,1,2", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CW_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Even ring polar= ity on Virtual Ring 0.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Clockwise and Odd on VRing= 0", + "Counter": "0,1,2", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CW_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Odd ring polari= ty on Virtual Ring 0.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Counterclockwise", + "Counter": "0,1,2", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0xCC", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Even = on VRing 0", + "Counter": "0,1,2", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CCW_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Even rin= g polarity on Virtual Ring 0.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Odd o= n VRing 0", + "Counter": "0,1,2", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CCW_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Odd ring= polarity on Virtual Ring 0.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Clockwise", + "Counter": "0,1,2", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x33", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Clockwise and Even on VRin= g 0", + "Counter": "0,1,2", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CW_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Even ring polar= ity on Virtual Ring 0.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Clockwise and Odd on VRing= 0", + "Counter": "0,1,2", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CW_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Odd ring polari= ty on Virtual Ring 0.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Counterclockwise", + "Counter": "0,1,2", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0xCC", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Even = on VRing 0", + "Counter": "0,1,2", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CCW_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Even rin= g polarity on Virtual Ring 0.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Odd o= n VRing 0", + "Counter": "0,1,2", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CCW_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Counterclockwise and Odd ring= polarity on Virtual Ring 0.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Clockwise", + "Counter": "0,1,2", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x33", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Clockwise and Even on VRin= g 0", + "Counter": "0,1,2", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CW_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Even ring polar= ity on Virtual Ring 0.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Clockwise and Odd on VRing= 0", + "Counter": "0,1,2", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CW_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.; Filters for the Clockwise and Odd ring polari= ty on Virtual Ring 0.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R2 IV Ring in Use; Any", + "Counter": "0,1,2", + "EventCode": "0xA", + "EventName": "UNC_R3_RING_IV_USED.ANY", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sent, but does not include when packets are be= ing sunk into the ring stop. The IV ring is unidirectional. Whether UP or= DN is used is dependent on the system programming. Thereofore, one should= generally set both the UP and DN bits for a given polarity (or both) at a = given time.; Filters any polarity", + "UMask": "0xFF", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R2 IV Ring in Use; Counterclockwise", + "Counter": "0,1,2", + "EventCode": "0xa", + "EventName": "UNC_R3_RING_IV_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sent, but does not include when packets are be= ing sunk into the ring stop. The IV ring is unidirectional. Whether UP or= DN is used is dependent on the system programming. Thereofore, one should= generally set both the UP and DN bits for a given polarity (or both) at a = given time.; Filters for Counterclockwise polarity", + "UMask": "0xCC", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R2 IV Ring in Use; Clockwise", + "Counter": "0,1,2", + "EventCode": "0xa", + "EventName": "UNC_R3_RING_IV_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sent, but does not include when packets are be= ing sunk into the ring stop. The IV ring is unidirectional. Whether UP or= DN is used is dependent on the system programming. Thereofore, one should= generally set both the UP and DN bits for a given polarity (or both) at a = given time.; Filters for Clockwise polarity", + "UMask": "0x33", + "Unit": "R3QPI" + }, + { + "BriefDescription": "AD Ingress Bypassed", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_R3_RxR_AD_BYPASSED", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when the AD Ingre= ss was bypassed and an incoming transaction was bypassed directly across th= e BGF and into the qfclk domain.", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Bypassed", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_R3_RxR_BYPASSED.AD", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when the Ingress = was bypassed and an incoming transaction was bypassed directly across the B= GF and into the qfclk domain.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; HOM", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_R3_RxR_CYCLES_NE.HOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI Ing= ress is not empty. This tracks one of the three rings that are used by the= QPI agent. This can be used in conjunction with the QPI Ingress Occupancy= Accumulator event in order to calculate average queue occupancy. Multiple= ingress buffers can be tracked at a given time using multiple counters.; H= OM Ingress Queue", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; NDR", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_R3_RxR_CYCLES_NE.NDR", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI Ing= ress is not empty. This tracks one of the three rings that are used by the= QPI agent. This can be used in conjunction with the QPI Ingress Occupancy= Accumulator event in order to calculate average queue occupancy. Multiple= ingress buffers can be tracked at a given time using multiple counters.; N= DR Ingress Queue", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; SNP", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_R3_RxR_CYCLES_NE.SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI Ing= ress is not empty. This tracks one of the three rings that are used by the= QPI agent. This can be used in conjunction with the QPI Ingress Occupancy= Accumulator event in order to calculate average queue occupancy. Multiple= ingress buffers can be tracked at a given time using multiple counters.; S= NP Ingress Queue", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; DRS", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QP= I Ingress. This tracks one of the three rings that are used by the QPI age= nt. This can be used in conjunction with the QPI Ingress Occupancy Accumul= ator event in order to calculate average queue latency. Multiple ingress b= uffers can be tracked at a given time using multiple counters.; DRS Ingress= Queue", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; HOM", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.HOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QP= I Ingress. This tracks one of the three rings that are used by the QPI age= nt. This can be used in conjunction with the QPI Ingress Occupancy Accumul= ator event in order to calculate average queue latency. Multiple ingress b= uffers can be tracked at a given time using multiple counters.; HOM Ingress= Queue", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; NCB", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QP= I Ingress. This tracks one of the three rings that are used by the QPI age= nt. This can be used in conjunction with the QPI Ingress Occupancy Accumul= ator event in order to calculate average queue latency. Multiple ingress b= uffers can be tracked at a given time using multiple counters.; NCB Ingress= Queue", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; NCS", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QP= I Ingress. This tracks one of the three rings that are used by the QPI age= nt. This can be used in conjunction with the QPI Ingress Occupancy Accumul= ator event in order to calculate average queue latency. Multiple ingress b= uffers can be tracked at a given time using multiple counters.; NCS Ingress= Queue", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; NDR", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.NDR", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QP= I Ingress. This tracks one of the three rings that are used by the QPI age= nt. This can be used in conjunction with the QPI Ingress Occupancy Accumul= ator event in order to calculate average queue latency. Multiple ingress b= uffers can be tracked at a given time using multiple counters.; NDR Ingress= Queue", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; SNP", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QP= I Ingress. This tracks one of the three rings that are used by the QPI age= nt. This can be used in conjunction with the QPI Ingress Occupancy Accumul= ator event in order to calculate average queue latency. Multiple ingress b= uffers can be tracked at a given time using multiple counters.; SNP Ingress= Queue", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Occupancy Accumulator; DRS", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY.DRS", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI Ing= ress queue in each cycles. This tracks one of the three ring Ingress buffe= rs. This can be used with the QPI Ingress Not Empty event to calculate ave= rage occupancy or the QPI Ingress Allocations event in order to calculate a= verage queuing latency.; DRS Ingress Queue", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Occupancy Accumulator; HOM", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY.HOM", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI Ing= ress queue in each cycles. This tracks one of the three ring Ingress buffe= rs. This can be used with the QPI Ingress Not Empty event to calculate ave= rage occupancy or the QPI Ingress Allocations event in order to calculate a= verage queuing latency.; HOM Ingress Queue", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Occupancy Accumulator; NCB", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY.NCB", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI Ing= ress queue in each cycles. This tracks one of the three ring Ingress buffe= rs. This can be used with the QPI Ingress Not Empty event to calculate ave= rage occupancy or the QPI Ingress Allocations event in order to calculate a= verage queuing latency.; NCB Ingress Queue", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Occupancy Accumulator; NCS", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY.NCS", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI Ing= ress queue in each cycles. This tracks one of the three ring Ingress buffe= rs. This can be used with the QPI Ingress Not Empty event to calculate ave= rage occupancy or the QPI Ingress Allocations event in order to calculate a= verage queuing latency.; NCS Ingress Queue", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Occupancy Accumulator; NDR", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY.NDR", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI Ing= ress queue in each cycles. This tracks one of the three ring Ingress buffe= rs. This can be used with the QPI Ingress Not Empty event to calculate ave= rage occupancy or the QPI Ingress Allocations event in order to calculate a= verage queuing latency.; NDR Ingress Queue", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Occupancy Accumulator; SNP", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY.SNP", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI Ing= ress queue in each cycles. This tracks one of the three ring Ingress buffe= rs. This can be used with the QPI Ingress Not Empty event to calculate ave= rage occupancy or the QPI Ingress Allocations event in order to calculate a= verage queuing latency.; SNP Ingress Queue", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Egress NACK; AK CCW", + "Counter": "0,1", + "EventCode": "0x28", + "EventName": "UNC_R3_TxR_NACK_CCW.AD", + "PerPkg": "1", + "PublicDescription": "BL CounterClockwise Egress Queue", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Egress NACK; BL CW", + "Counter": "0,1", + "EventCode": "0x28", + "EventName": "UNC_R3_TxR_NACK_CCW.AK", + "PerPkg": "1", + "PublicDescription": "AD Clockwise Egress Queue", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Egress NACK; BL CCW", + "Counter": "0,1", + "EventCode": "0x28", + "EventName": "UNC_R3_TxR_NACK_CCW.BL", + "PerPkg": "1", + "PublicDescription": "AD CounterClockwise Egress Queue", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Egress NACK; AD CW", + "Counter": "0,1", + "EventCode": "0x26", + "EventName": "UNC_R3_TxR_NACK_CW.AD", + "PerPkg": "1", + "PublicDescription": "AD Clockwise Egress Queue", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Egress NACK; AD CCW", + "Counter": "0,1", + "EventCode": "0x26", + "EventName": "UNC_R3_TxR_NACK_CW.AK", + "PerPkg": "1", + "PublicDescription": "AD CounterClockwise Egress Queue", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Egress NACK; AK CW", + "Counter": "0,1", + "EventCode": "0x26", + "EventName": "UNC_R3_TxR_NACK_CW.BL", + "PerPkg": "1", + "PublicDescription": "BL Clockwise Egress Queue", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Mes= sage Class", + "Counter": "0,1", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire = a DRS VN0 credit. In order for a request to be transferred across QPI, it = must be guaranteed to have a flit buffer on the remote socket to sink into.= There are two credit pools, VNA and VN0. VNA is a shared pool used to ac= hieve high performance. The VN0 pool has reserved entries for each message= class and is used to prevent deadlock. Requests first attempt to acquire = a VNA credit, and then fall back to VN0 if they fail. This therefore count= s the number of times when a request failed to acquire either a VNA or VN0 = credit and is delayed. This should generally be a rare situation.; Filter = for Data Response (DRS). DRS is generally used to transmit data with coher= ency. For example, remote reads and writes, or cache to cache transfers wi= ll transmit their data using DRS.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Mes= sage Class", + "Counter": "0,1", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire = a DRS VN0 credit. In order for a request to be transferred across QPI, it = must be guaranteed to have a flit buffer on the remote socket to sink into.= There are two credit pools, VNA and VN0. VNA is a shared pool used to ac= hieve high performance. The VN0 pool has reserved entries for each message= class and is used to prevent deadlock. Requests first attempt to acquire = a VNA credit, and then fall back to VN0 if they fail. This therefore count= s the number of times when a request failed to acquire either a VNA or VN0 = credit and is delayed. This should generally be a rare situation.; Filter = for the Home (HOM) message class. HOM is generally used to send requests, = request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCB Mes= sage Class", + "Counter": "0,1", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCB", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire = a DRS VN0 credit. In order for a request to be transferred across QPI, it = must be guaranteed to have a flit buffer on the remote socket to sink into.= There are two credit pools, VNA and VN0. VNA is a shared pool used to ac= hieve high performance. The VN0 pool has reserved entries for each message= class and is used to prevent deadlock. Requests first attempt to acquire = a VNA credit, and then fall back to VN0 if they fail. This therefore count= s the number of times when a request failed to acquire either a VNA or VN0 = credit and is delayed. This should generally be a rare situation.; Filter = for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data w= ithout coherency. For example, non-coherent read data returns.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCS Mes= sage Class", + "Counter": "0,1", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCS", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire = a DRS VN0 credit. In order for a request to be transferred across QPI, it = must be guaranteed to have a flit buffer on the remote socket to sink into.= There are two credit pools, VNA and VN0. VNA is a shared pool used to ac= hieve high performance. The VN0 pool has reserved entries for each message= class and is used to prevent deadlock. Requests first attempt to acquire = a VNA credit, and then fall back to VN0 if they fail. This therefore count= s the number of times when a request failed to acquire either a VNA or VN0 = credit and is delayed. This should generally be a rare situation.; Filter = for Non-Coherent Standard (NCS). NCS is commonly used for ?", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Mes= sage Class", + "Counter": "0,1", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire = a DRS VN0 credit. In order for a request to be transferred across QPI, it = must be guaranteed to have a flit buffer on the remote socket to sink into.= There are two credit pools, VNA and VN0. VNA is a shared pool used to ac= hieve high performance. The VN0 pool has reserved entries for each message= class and is used to prevent deadlock. Requests first attempt to acquire = a VNA credit, and then fall back to VN0 if they fail. This therefore count= s the number of times when a request failed to acquire either a VNA or VN0 = credit and is delayed. This should generally be a rare situation.; NDR pac= kets are used to transmit a variety of protocol flits including grants and = completions (CMP).", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Mes= sage Class", + "Counter": "0,1", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire = a DRS VN0 credit. In order for a request to be transferred across QPI, it = must be guaranteed to have a flit buffer on the remote socket to sink into.= There are two credit pools, VNA and VN0. VNA is a shared pool used to ac= hieve high performance. The VN0 pool has reserved entries for each message= class and is used to prevent deadlock. Requests first attempt to acquire = a VNA credit, and then fall back to VN0 if they fail. This therefore count= s the number of times when a request failed to acquire either a VNA or VN0 = credit and is delayed. This should generally be a rare situation.; Filter = for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that= snoop responses flow on the HOM message class.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; DRS Message Class", + "Counter": "0,1", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.DRS", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the= DRS message channel. In order for a request to be transferred across QPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN0. VNA is a shared pool used t= o achieve high performance. The VN0 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN0 if they fail. This counts the = number of times a VN0 credit was used. Note that a single VN0 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN0 will only count a single credit even though it may use multiple= buffers.; Filter for Data Response (DRS). DRS is generally used to transm= it data with coherency. For example, remote reads and writes, or cache to = cache transfers will transmit their data using DRS.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; HOM Message Class", + "Counter": "0,1", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.HOM", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the= DRS message channel. In order for a request to be transferred across QPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN0. VNA is a shared pool used t= o achieve high performance. The VN0 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN0 if they fail. This counts the = number of times a VN0 credit was used. Note that a single VN0 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN0 will only count a single credit even though it may use multiple= buffers.; Filter for the Home (HOM) message class. HOM is generally used = to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; NCB Message Class", + "Counter": "0,1", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.NCB", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the= DRS message channel. In order for a request to be transferred across QPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN0. VNA is a shared pool used t= o achieve high performance. The VN0 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN0 if they fail. This counts the = number of times a VN0 credit was used. Note that a single VN0 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN0 will only count a single credit even though it may use multiple= buffers.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used = to transmit data without coherency. For example, non-coherent read data re= turns.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; NCS Message Class", + "Counter": "0,1", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.NCS", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the= DRS message channel. In order for a request to be transferred across QPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN0. VNA is a shared pool used t= o achieve high performance. The VN0 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN0 if they fail. This counts the = number of times a VN0 credit was used. Note that a single VN0 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN0 will only count a single credit even though it may use multiple= buffers.; Filter for Non-Coherent Standard (NCS). NCS is commonly used fo= r ?", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; NDR Message Class", + "Counter": "0,1", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.NDR", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the= DRS message channel. In order for a request to be transferred across QPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN0. VNA is a shared pool used t= o achieve high performance. The VN0 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN0 if they fail. This counts the = number of times a VN0 credit was used. Note that a single VN0 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN0 will only count a single credit even though it may use multiple= buffers.; NDR packets are used to transmit a variety of protocol flits inc= luding grants and completions (CMP).", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; SNP Message Class", + "Counter": "0,1", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.SNP", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the= DRS message channel. In order for a request to be transferred across QPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN0. VNA is a shared pool used t= o achieve high performance. The VN0 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN0 if they fail. This counts the = number of times a VN0 credit was used. Note that a single VN0 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN0 will only count a single credit even though it may use multiple= buffers.; Filter for Snoop (SNP) message class. SNP is used for outgoing = snoops. Note that snoop responses flow on the HOM message class.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Acquisition Failed on DRS; DRS Mes= sage Class", + "Counter": "0,1", + "EventCode": "0x39", + "EventName": "UNC_R3_VN1_CREDITS_REJECT.DRS", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire = a VN1 credit. In order for a request to be transferred across QPI, it must= be guaranteed to have a flit buffer on the remote socket to sink into. Th= ere are two credit pools, VNA and VN1. VNA is a shared pool used to achiev= e high performance. The VN1 pool has reserved entries for each message cla= ss and is used to prevent deadlock. Requests first attempt to acquire a VN= A credit, and then fall back to VN1 if they fail. This therefore counts th= e number of times when a request failed to acquire either a VNA or VN1 cred= it and is delayed. This should generally be a rare situation.; Filter for = Data Response (DRS). DRS is generally used to transmit data with coherency= . For example, remote reads and writes, or cache to cache transfers will t= ransmit their data using DRS.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Acquisition Failed on DRS; HOM Mes= sage Class", + "Counter": "0,1", + "EventCode": "0x39", + "EventName": "UNC_R3_VN1_CREDITS_REJECT.HOM", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire = a VN1 credit. In order for a request to be transferred across QPI, it must= be guaranteed to have a flit buffer on the remote socket to sink into. Th= ere are two credit pools, VNA and VN1. VNA is a shared pool used to achiev= e high performance. The VN1 pool has reserved entries for each message cla= ss and is used to prevent deadlock. Requests first attempt to acquire a VN= A credit, and then fall back to VN1 if they fail. This therefore counts th= e number of times when a request failed to acquire either a VNA or VN1 cred= it and is delayed. This should generally be a rare situation.; Filter for = the Home (HOM) message class. HOM is generally used to send requests, requ= est responses, and snoop responses.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCB Mes= sage Class", + "Counter": "0,1", + "EventCode": "0x39", + "EventName": "UNC_R3_VN1_CREDITS_REJECT.NCB", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire = a VN1 credit. In order for a request to be transferred across QPI, it must= be guaranteed to have a flit buffer on the remote socket to sink into. Th= ere are two credit pools, VNA and VN1. VNA is a shared pool used to achiev= e high performance. The VN1 pool has reserved entries for each message cla= ss and is used to prevent deadlock. Requests first attempt to acquire a VN= A credit, and then fall back to VN1 if they fail. This therefore counts th= e number of times when a request failed to acquire either a VNA or VN1 cred= it and is delayed. This should generally be a rare situation.; Filter for = Non-Coherent Broadcast (NCB). NCB is generally used to transmit data witho= ut coherency. For example, non-coherent read data returns.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCS Mes= sage Class", + "Counter": "0,1", + "EventCode": "0x39", + "EventName": "UNC_R3_VN1_CREDITS_REJECT.NCS", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire = a VN1 credit. In order for a request to be transferred across QPI, it must= be guaranteed to have a flit buffer on the remote socket to sink into. Th= ere are two credit pools, VNA and VN1. VNA is a shared pool used to achiev= e high performance. The VN1 pool has reserved entries for each message cla= ss and is used to prevent deadlock. Requests first attempt to acquire a VN= A credit, and then fall back to VN1 if they fail. This therefore counts th= e number of times when a request failed to acquire either a VNA or VN1 cred= it and is delayed. This should generally be a rare situation.; Filter for = Non-Coherent Standard (NCS). NCS is commonly used for ?", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NDR Mes= sage Class", + "Counter": "0,1", + "EventCode": "0x39", + "EventName": "UNC_R3_VN1_CREDITS_REJECT.NDR", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire = a VN1 credit. In order for a request to be transferred across QPI, it must= be guaranteed to have a flit buffer on the remote socket to sink into. Th= ere are two credit pools, VNA and VN1. VNA is a shared pool used to achiev= e high performance. The VN1 pool has reserved entries for each message cla= ss and is used to prevent deadlock. Requests first attempt to acquire a VN= A credit, and then fall back to VN1 if they fail. This therefore counts th= e number of times when a request failed to acquire either a VNA or VN1 cred= it and is delayed. This should generally be a rare situation.; NDR packets= are used to transmit a variety of protocol flits including grants and comp= letions (CMP).", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Acquisition Failed on DRS; SNP Mes= sage Class", + "Counter": "0,1", + "EventCode": "0x39", + "EventName": "UNC_R3_VN1_CREDITS_REJECT.SNP", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire = a VN1 credit. In order for a request to be transferred across QPI, it must= be guaranteed to have a flit buffer on the remote socket to sink into. Th= ere are two credit pools, VNA and VN1. VNA is a shared pool used to achiev= e high performance. The VN1 pool has reserved entries for each message cla= ss and is used to prevent deadlock. Requests first attempt to acquire a VN= A credit, and then fall back to VN1 if they fail. This therefore counts th= e number of times when a request failed to acquire either a VNA or VN1 cred= it and is delayed. This should generally be a rare situation.; Filter for = Snoop (SNP) message class. SNP is used for outgoing snoops. Note that sno= op responses flow on the HOM message class.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Used; DRS Message Class", + "Counter": "0,1", + "EventCode": "0x38", + "EventName": "UNC_R3_VN1_CREDITS_USED.DRS", + "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the= DRS message channel. In order for a request to be transferred across QPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN1. VNA is a shared pool used t= o achieve high performance. The VN1 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN1 if they fail. This counts the = number of times a VN1 credit was used. Note that a single VN1 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN1 will only count a single credit even though it may use multiple= buffers.; Filter for Data Response (DRS). DRS is generally used to transm= it data with coherency. For example, remote reads and writes, or cache to = cache transfers will transmit their data using DRS.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Used; HOM Message Class", + "Counter": "0,1", + "EventCode": "0x38", + "EventName": "UNC_R3_VN1_CREDITS_USED.HOM", + "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the= DRS message channel. In order for a request to be transferred across QPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN1. VNA is a shared pool used t= o achieve high performance. The VN1 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN1 if they fail. This counts the = number of times a VN1 credit was used. Note that a single VN1 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN1 will only count a single credit even though it may use multiple= buffers.; Filter for the Home (HOM) message class. HOM is generally used = to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Used; NCB Message Class", + "Counter": "0,1", + "EventCode": "0x38", + "EventName": "UNC_R3_VN1_CREDITS_USED.NCB", + "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the= DRS message channel. In order for a request to be transferred across QPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN1. VNA is a shared pool used t= o achieve high performance. The VN1 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN1 if they fail. This counts the = number of times a VN1 credit was used. Note that a single VN1 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN1 will only count a single credit even though it may use multiple= buffers.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used = to transmit data without coherency. For example, non-coherent read data re= turns.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Used; NCS Message Class", + "Counter": "0,1", + "EventCode": "0x38", + "EventName": "UNC_R3_VN1_CREDITS_USED.NCS", + "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the= DRS message channel. In order for a request to be transferred across QPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN1. VNA is a shared pool used t= o achieve high performance. The VN1 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN1 if they fail. This counts the = number of times a VN1 credit was used. Note that a single VN1 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN1 will only count a single credit even though it may use multiple= buffers.; Filter for Non-Coherent Standard (NCS). NCS is commonly used fo= r ?", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Used; NDR Message Class", + "Counter": "0,1", + "EventCode": "0x38", + "EventName": "UNC_R3_VN1_CREDITS_USED.NDR", + "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the= DRS message channel. In order for a request to be transferred across QPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN1. VNA is a shared pool used t= o achieve high performance. The VN1 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN1 if they fail. This counts the = number of times a VN1 credit was used. Note that a single VN1 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN1 will only count a single credit even though it may use multiple= buffers.; NDR packets are used to transmit a variety of protocol flits inc= luding grants and completions (CMP).", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Used; SNP Message Class", + "Counter": "0,1", + "EventCode": "0x38", + "EventName": "UNC_R3_VN1_CREDITS_USED.SNP", + "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the= DRS message channel. In order for a request to be transferred across QPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN1. VNA is a shared pool used t= o achieve high performance. The VN1 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN1 if they fail. This counts the = number of times a VN1 credit was used. Note that a single VN1 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN1 will only count a single credit even though it may use multiple= buffers.; Filter for Snoop (SNP) message class. SNP is used for outgoing = snoops. Note that snoop responses flow on the HOM message class.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA credit Acquisitions", + "Counter": "0,1", + "EventCode": "0x33", + "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED", + "PerPkg": "1", + "PublicDescription": "Number of QPI VNA Credit acquisitions. This= event can be used in conjunction with the VNA In-Use Accumulator to calcul= ate the average lifetime of a credit holder. VNA credits are used by all m= essage classes in order to communicate across QPI. If a packet is unable t= o acquire credits, it will then attempt to use credts from the VN0 pool. N= ote that a single packet may require multiple flit buffers (i.e. when data = is being transfered). Therefore, this event will increment by the number o= f credits acquired in each cycle. Filtering based on message class is not = provided. One can count the number of packets transfered in a given messag= e class using an qfclk event.", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA credit Acquisitions; HOM Message Class", + "Counter": "0,1", + "EventCode": "0x33", + "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.AD", + "PerPkg": "1", + "PublicDescription": "Number of QPI VNA Credit acquisitions. This= event can be used in conjunction with the VNA In-Use Accumulator to calcul= ate the average lifetime of a credit holder. VNA credits are used by all m= essage classes in order to communicate across QPI. If a packet is unable t= o acquire credits, it will then attempt to use credts from the VN0 pool. N= ote that a single packet may require multiple flit buffers (i.e. when data = is being transfered). Therefore, this event will increment by the number o= f credits acquired in each cycle. Filtering based on message class is not = provided. One can count the number of packets transfered in a given messag= e class using an qfclk event.; Filter for the Home (HOM) message class. HO= M is generally used to send requests, request responses, and snoop response= s.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA credit Acquisitions; HOM Message Class", + "Counter": "0,1", + "EventCode": "0x33", + "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.BL", + "PerPkg": "1", + "PublicDescription": "Number of QPI VNA Credit acquisitions. This= event can be used in conjunction with the VNA In-Use Accumulator to calcul= ate the average lifetime of a credit holder. VNA credits are used by all m= essage classes in order to communicate across QPI. If a packet is unable t= o acquire credits, it will then attempt to use credts from the VN0 pool. N= ote that a single packet may require multiple flit buffers (i.e. when data = is being transfered). Therefore, this event will increment by the number o= f credits acquired in each cycle. Filtering based on message class is not = provided. One can count the number of packets transfered in a given messag= e class using an qfclk event.; Filter for the Home (HOM) message class. HO= M is generally used to send requests, request responses, and snoop response= s.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; DRS Message Class", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions = that were rejected because the VNA credit pool was full (or almost full). = It is possible to filter this event by message class. Some packets use mor= e than one flit buffer, and therefore must acquire multiple credits. There= fore, one could get a reject even if the VNA credits were not fully used up= . The VNA pool is generally used to provide the bulk of the QPI bandwidth = (as opposed to the VN0 pool which is used to guarantee forward progress). = VNA credits can run out if the flit buffer on the receiving side starts to = queue up substantially. This can happen if the rest of the uncore is unabl= e to drain the requests fast enough.; Filter for Data Response (DRS). DRS = is generally used to transmit data with coherency. For example, remote rea= ds and writes, or cache to cache transfers will transmit their data using D= RS.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; HOM Message Class", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions = that were rejected because the VNA credit pool was full (or almost full). = It is possible to filter this event by message class. Some packets use mor= e than one flit buffer, and therefore must acquire multiple credits. There= fore, one could get a reject even if the VNA credits were not fully used up= . The VNA pool is generally used to provide the bulk of the QPI bandwidth = (as opposed to the VN0 pool which is used to guarantee forward progress). = VNA credits can run out if the flit buffer on the receiving side starts to = queue up substantially. This can happen if the rest of the uncore is unabl= e to drain the requests fast enough.; Filter for the Home (HOM) message cla= ss. HOM is generally used to send requests, request responses, and snoop r= esponses.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; NCB Message Class", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions = that were rejected because the VNA credit pool was full (or almost full). = It is possible to filter this event by message class. Some packets use mor= e than one flit buffer, and therefore must acquire multiple credits. There= fore, one could get a reject even if the VNA credits were not fully used up= . The VNA pool is generally used to provide the bulk of the QPI bandwidth = (as opposed to the VN0 pool which is used to guarantee forward progress). = VNA credits can run out if the flit buffer on the receiving side starts to = queue up substantially. This can happen if the rest of the uncore is unabl= e to drain the requests fast enough.; Filter for Non-Coherent Broadcast (NC= B). NCB is generally used to transmit data without coherency. For example= , non-coherent read data returns.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; NCS Message Class", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCS", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions = that were rejected because the VNA credit pool was full (or almost full). = It is possible to filter this event by message class. Some packets use mor= e than one flit buffer, and therefore must acquire multiple credits. There= fore, one could get a reject even if the VNA credits were not fully used up= . The VNA pool is generally used to provide the bulk of the QPI bandwidth = (as opposed to the VN0 pool which is used to guarantee forward progress). = VNA credits can run out if the flit buffer on the receiving side starts to = queue up substantially. This can happen if the rest of the uncore is unabl= e to drain the requests fast enough.; Filter for Non-Coherent Standard (NCS= ).", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; NDR Message Class", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions = that were rejected because the VNA credit pool was full (or almost full). = It is possible to filter this event by message class. Some packets use mor= e than one flit buffer, and therefore must acquire multiple credits. There= fore, one could get a reject even if the VNA credits were not fully used up= . The VNA pool is generally used to provide the bulk of the QPI bandwidth = (as opposed to the VN0 pool which is used to guarantee forward progress). = VNA credits can run out if the flit buffer on the receiving side starts to = queue up substantially. This can happen if the rest of the uncore is unabl= e to drain the requests fast enough.; NDR packets are used to transmit a va= riety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; SNP Message Class", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions = that were rejected because the VNA credit pool was full (or almost full). = It is possible to filter this event by message class. Some packets use mor= e than one flit buffer, and therefore must acquire multiple credits. There= fore, one could get a reject even if the VNA credits were not fully used up= . The VNA pool is generally used to provide the bulk of the QPI bandwidth = (as opposed to the VN0 pool which is used to guarantee forward progress). = VNA credits can run out if the flit buffer on the receiving side starts to = queue up substantially. This can happen if the rest of the uncore is unabl= e to drain the requests fast enough.; Filter for Snoop (SNP) message class.= SNP is used for outgoing snoops. Note that snoop responses flow on the H= OM message class.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Cycles with no VNA credits available", + "Counter": "0,1", + "EventCode": "0x31", + "EventName": "UNC_R3_VNA_CREDIT_CYCLES_OUT", + "PerPkg": "1", + "PublicDescription": "Number of QPI uclk cycles when the transmitt= ed has no VNA credits available and therefore cannot send any requests on t= his channel. Note that this does not mean that no flits can be transmitted= , as those holding VN0 credits will still (potentially) be able to transmit= . Generally it is the goal of the uncore that VNA credits should not run o= ut, as this can substantially throttle back useful QPI bandwidth.", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Cycles with 1 or more VNA credits in use", + "Counter": "0,1", + "EventCode": "0x32", + "EventName": "UNC_R3_VNA_CREDIT_CYCLES_USED", + "PerPkg": "1", + "PublicDescription": "Number of QPI uclk cycles with one or more V= NA credits in use. This event can be used in conjunction with the VNA In-U= se Accumulator to calculate the average number of used VNA credits.", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VLW Received", + "Counter": "0,1", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were r= eceived from Uncore. Specify the thread to filter on using NCUPMONCTRLGLC= TR.ThreadID.", + "UMask": "0x8", + "Unit": "UBOX" + }, + { + "BriefDescription": "VLW Received", + "Counter": "0,1", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.INT_PRIO", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were r= eceived from Uncore. Specify the thread to filter on using NCUPMONCTRLGLC= TR.ThreadID.", + "UMask": "0x10", + "Unit": "UBOX" + }, + { + "BriefDescription": "VLW Received", + "Counter": "0,1", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.IPI_RCVD", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were r= eceived from Uncore. Specify the thread to filter on using NCUPMONCTRLGLC= TR.ThreadID.", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "VLW Received", + "Counter": "0,1", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were r= eceived from Uncore. Specify the thread to filter on using NCUPMONCTRLGLC= TR.ThreadID.", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "VLW Received", + "Counter": "0,1", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.VLW_RCVD", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were r= eceived from Uncore. Specify the thread to filter on using NCUPMONCTRLGLC= TR.ThreadID.", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "Filter Match", + "Counter": "0,1", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.DISABLE", + "PerPkg": "1", + "PublicDescription": "Filter match per thread (w/ or w/o Filter En= able). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "Filter Match", + "Counter": "0,1", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.ENABLE", + "Filter": "UBoxFilter[3:0]", + "PerPkg": "1", + "PublicDescription": "Filter match per thread (w/ or w/o Filter En= able). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "Filter Match", + "Counter": "0,1", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE", + "PerPkg": "1", + "PublicDescription": "Filter match per thread (w/ or w/o Filter En= able). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x8", + "Unit": "UBOX" + }, + { + "BriefDescription": "Filter Match", + "Counter": "0,1", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE", + "Filter": "UBoxFilter[3:0]", + "PerPkg": "1", + "PublicDescription": "Filter match per thread (w/ or w/o Filter En= able). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "IDI Lock/SplitLock Cycles", + "Counter": "0,1", + "EventCode": "0x44", + "EventName": "UNC_U_LOCK_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of times an IDI Lock/SplitLock sequen= ce was started", + "Unit": "UBOX" + }, + { + "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK", + "Counter": "0,1", + "EventCode": "0x45", + "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", + "PerPkg": "1", + "PublicDescription": "PHOLD cycles. Filter from source CoreID.", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "RACU Request", + "Counter": "0,1", + "EventCode": "0x46", + "EventName": "UNC_U_RACU_REQUESTS", + "PerPkg": "1", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Correctable Machine Check= ", + "Counter": "0,1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.CMC", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one= or all cores", + "UMask": "0x10", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Livelock", + "Counter": "0,1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.LIVELOCK", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one= or all cores; Filter by core", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; LTError", + "Counter": "0,1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.LTERROR", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one= or all cores; Filter by core", + "UMask": "0x8", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Monitor T0", + "Counter": "0,1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one= or all cores; Filter by core", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Monitor T1", + "Counter": "0,1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one= or all cores; Filter by core", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Other", + "Counter": "0,1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.OTHER", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one= or all cores; PREQ, PSMI, P2U, Thermal, PCUSMI, PMI", + "UMask": "0x80", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Trap", + "Counter": "0,1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.TRAP", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one= or all cores", + "UMask": "0x40", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Che= ck", + "Counter": "0,1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.UMC", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one= or all cores", + "UMask": "0x20", + "Unit": "UBOX" + } +] diff --git a/tools/perf/pmu-events/arch/x86/ivytown/uncore-power.json b/too= ls/perf/pmu-events/arch/x86/ivytown/uncore-power.json index 635c09fda1d9..304d861c368f 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/uncore-power.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/uncore-power.json @@ -1,176 +1,539 @@ [ { - "BriefDescription": "PCU clock ticks. Use to get percentages of PC= U cycles events", + "BriefDescription": "pclk Cycles", "Counter": "0,1,2,3", "EventName": "UNC_P_CLOCKTICKS", "PerPkg": "1", + "PublicDescription": "The PCU runs off a fixed 800 MHz clock. Thi= s event counts the number of pclk cycles measured while the counter was ena= bled. The pclk, like the Memory Controller's dclk, counts at a constant ra= te making it a good measure of actual wall time.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles that the uncore w= as running at a frequency greater than or equal to the frequency that is co= nfigured in the filter. (filter_band0=3DXXX, with XXX in 100Mhz units). On= e can also use inversion (filter_inv=3D1) to track cycles when we were less= than the configured frequency", + "BriefDescription": "Core 0 C State Transition Cycles", "Counter": "0,1,2,3", - "EventCode": "0xb", - "EventName": "UNC_P_FREQ_BAND0_CYCLES", - "MetricExpr": "(UNC_P_FREQ_BAND0_CYCLES / UNC_P_CLOCKTICKS) * 100.= ", - "MetricName": "freq_band0_cycles %", + "EventCode": "0x70", + "EventName": "UNC_P_CORE0_TRANSITION_CYCLES", "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles that the uncore w= as running at a frequency greater than or equal to the frequency that is co= nfigured in the filter. (filter_band1=3DXXX, with XXX in 100Mhz units). On= e can also use inversion (filter_inv=3D1) to track cycles when we were less= than the configured frequency", + "BriefDescription": "Core 10 C State Transition Cycles", "Counter": "0,1,2,3", - "EventCode": "0xc", - "EventName": "UNC_P_FREQ_BAND1_CYCLES", - "MetricExpr": "(UNC_P_FREQ_BAND1_CYCLES / UNC_P_CLOCKTICKS) * 100.= ", - "MetricName": "freq_band1_cycles %", + "EventCode": "0x7a", + "EventName": "UNC_P_CORE10_TRANSITION_CYCLES", "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles that the uncore w= as running at a frequency greater than or equal to the frequency that is co= nfigured in the filter. (filter_band2=3DXXX, with XXX in 100Mhz units). On= e can also use inversion (filter_inv=3D1) to track cycles when we were less= than the configured frequency", + "BriefDescription": "Core 11 C State Transition Cycles", "Counter": "0,1,2,3", - "EventCode": "0xd", - "EventName": "UNC_P_FREQ_BAND2_CYCLES", - "MetricExpr": "(UNC_P_FREQ_BAND2_CYCLES / UNC_P_CLOCKTICKS) * 100.= ", - "MetricName": "freq_band2_cycles %", + "EventCode": "0x7b", + "EventName": "UNC_P_CORE11_TRANSITION_CYCLES", "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles that the uncore w= as running at a frequency greater than or equal to the frequency that is co= nfigured in the filter. (filter_band3=3DXXX, with XXX in 100Mhz units). On= e can also use inversion (filter_inv=3D1) to track cycles when we were less= than the configured frequency", + "BriefDescription": "Core 12 C State Transition Cycles", "Counter": "0,1,2,3", - "EventCode": "0xe", - "EventName": "UNC_P_FREQ_BAND3_CYCLES", - "MetricExpr": "(UNC_P_FREQ_BAND3_CYCLES / UNC_P_CLOCKTICKS) * 100.= ", - "MetricName": "freq_band3_cycles %", + "EventCode": "0x7c", + "EventName": "UNC_P_CORE12_TRANSITION_CYCLES", "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of times that the uncore tr= ansitioned a frequency greater than or equal to the frequency that is confi= gured in the filter. (filter_band0=3DXXX, with XXX in 100Mhz units). One c= an also use inversion (filter_inv=3D1) to track cycles when we were less th= an the configured frequency. Derived from unc_p_freq_band0_cycles", + "BriefDescription": "Core 13 C State Transition Cycles", "Counter": "0,1,2,3", - "EventCode": "0xb", - "EventName": "UNC_P_FREQ_BAND0_TRANSITIONS", - "Filter": "edge=3D1", - "MetricExpr": "(UNC_P_FREQ_BAND0_CYCLES / UNC_P_CLOCKTICKS) * 100.= ", - "MetricName": "freq_band0_cycles %", + "EventCode": "0x7d", + "EventName": "UNC_P_CORE13_TRANSITION_CYCLES", "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of times that the uncore tr= ansitioned to a frequency greater than or equal to the frequency that is co= nfigured in the filter. (filter_band1=3DXXX, with XXX in 100Mhz units). On= e can also use inversion (filter_inv=3D1) to track cycles when we were less= than the configured frequency. Derived from unc_p_freq_band1_cycles", + "BriefDescription": "Core 14 C State Transition Cycles", "Counter": "0,1,2,3", - "EventCode": "0xc", - "EventName": "UNC_P_FREQ_BAND1_TRANSITIONS", - "Filter": "edge=3D1", - "MetricExpr": "(UNC_P_FREQ_BAND1_CYCLES / UNC_P_CLOCKTICKS) * 100.= ", - "MetricName": "freq_band1_cycles %", + "EventCode": "0x7e", + "EventName": "UNC_P_CORE14_TRANSITION_CYCLES", "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles that the uncore t= ransitioned to a frequency greater than or equal to the frequency that is c= onfigured in the filter. (filter_band2=3DXXX, with XXX in 100Mhz units). O= ne can also use inversion (filter_inv=3D1) to track cycles when we were les= s than the configured frequency. Derived from unc_p_freq_band2_cycles", + "BriefDescription": "Core 1 C State Transition Cycles", "Counter": "0,1,2,3", - "EventCode": "0xd", - "EventName": "UNC_P_FREQ_BAND2_TRANSITIONS", - "Filter": "edge=3D1", - "MetricExpr": "(UNC_P_FREQ_BAND2_CYCLES / UNC_P_CLOCKTICKS) * 100.= ", - "MetricName": "freq_band2_cycles %", + "EventCode": "0x71", + "EventName": "UNC_P_CORE1_TRANSITION_CYCLES", "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles that the uncore t= ransitioned to a frequency greater than or equal to the frequency that is c= onfigured in the filter. (filter_band3=3DXXX, with XXX in 100Mhz units). O= ne can also use inversion (filter_inv=3D1) to track cycles when we were les= s than the configured frequency. Derived from unc_p_freq_band3_cycles", + "BriefDescription": "Core 2 C State Transition Cycles", "Counter": "0,1,2,3", - "EventCode": "0xe", - "EventName": "UNC_P_FREQ_BAND3_TRANSITIONS", - "Filter": "edge=3D1", - "MetricExpr": "(UNC_P_FREQ_BAND3_CYCLES / UNC_P_CLOCKTICKS) * 100.= ", - "MetricName": "freq_band3_cycles %", + "EventCode": "0x72", + "EventName": "UNC_P_CORE2_TRANSITION_CYCLES", "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", "Unit": "PCU" }, { - "BriefDescription": "This is an occupancy event that tracks the nu= mber of cores that are in C0. It can be used by itself to get the average = number of cores in C0, with threshholding to generate histograms, or with o= ther PCU events and occupancy triggering to capture other details", + "BriefDescription": "Core 3 C State Transition Cycles", "Counter": "0,1,2,3", - "EventCode": "0x80", - "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", - "Filter": "occ_sel=3D1", - "MetricExpr": "(UNC_P_POWER_STATE_OCCUPANCY.CORES_C0 / UNC_P_CLOCK= TICKS) * 100.", - "MetricName": "power_state_occupancy.cores_c0 %", + "EventCode": "0x73", + "EventName": "UNC_P_CORE3_TRANSITION_CYCLES", "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", "Unit": "PCU" }, { - "BriefDescription": "This is an occupancy event that tracks the nu= mber of cores that are in C3. It can be used by itself to get the average = number of cores in C0, with threshholding to generate histograms, or with o= ther PCU events and occupancy triggering to capture other details", + "BriefDescription": "Core 4 C State Transition Cycles", "Counter": "0,1,2,3", - "EventCode": "0x80", - "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", - "Filter": "occ_sel=3D2", - "MetricExpr": "(UNC_P_POWER_STATE_OCCUPANCY.CORES_C3 / UNC_P_CLOCK= TICKS) * 100.", - "MetricName": "power_state_occupancy.cores_c3 %", + "EventCode": "0x74", + "EventName": "UNC_P_CORE4_TRANSITION_CYCLES", "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", "Unit": "PCU" }, { - "BriefDescription": "This is an occupancy event that tracks the nu= mber of cores that are in C6. It can be used by itself to get the average = number of cores in C0, with threshholding to generate histograms, or with o= ther PCU events ", + "BriefDescription": "Core 5 C State Transition Cycles", "Counter": "0,1,2,3", - "EventCode": "0x80", - "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", - "Filter": "occ_sel=3D3", - "MetricExpr": "(UNC_P_POWER_STATE_OCCUPANCY.CORES_C6 / UNC_P_CLOCK= TICKS) * 100.", - "MetricName": "power_state_occupancy.cores_c6 %", + "EventCode": "0x75", + "EventName": "UNC_P_CORE5_TRANSITION_CYCLES", "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles that we are in ex= ternal PROCHOT mode. This mode is triggered when a sensor off the die dete= rmines that something off-die (like DRAM) is too hot and must throttle to a= void damaging the chip", + "BriefDescription": "Core 6 C State Transition Cycles", "Counter": "0,1,2,3", - "EventCode": "0xa", - "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES", - "MetricExpr": "(UNC_P_PROCHOT_EXTERNAL_CYCLES / UNC_P_CLOCKTICKS) = * 100.", - "MetricName": "prochot_external_cycles %", + "EventCode": "0x76", + "EventName": "UNC_P_CORE6_TRANSITION_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", + "Unit": "PCU" + }, + { + "BriefDescription": "Core 7 C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x77", + "EventName": "UNC_P_CORE7_TRANSITION_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", + "Unit": "PCU" + }, + { + "BriefDescription": "Core 8 C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x78", + "EventName": "UNC_P_CORE8_TRANSITION_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", + "Unit": "PCU" + }, + { + "BriefDescription": "Core 9 C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x79", + "EventName": "UNC_P_CORE9_TRANSITION_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", + "Unit": "PCU" + }, + { + "BriefDescription": "Deep C State Rejection - Core 0", + "Counter": "0,1,2,3", + "EventCode": "0x17", + "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE0", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of times that a deep C state was requ= ested, but the delayed C state algorithm rejected the deep sleep state. In= other words, a wake event occurred before the timer expired that causes a = transition into the deeper C state.", + "Unit": "PCU" + }, + { + "BriefDescription": "Deep C State Rejection - Core 1", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE1", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of times that a deep C state was requ= ested, but the delayed C state algorithm rejected the deep sleep state. In= other words, a wake event occurred before the timer expired that causes a = transition into the deeper C state.", + "Unit": "PCU" + }, + { + "BriefDescription": "Deep C State Rejection - Core 10", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE10", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of times that a deep C state was requ= ested, but the delayed C state algorithm rejected the deep sleep state. In= other words, a wake event occurred before the timer expired that causes a = transition into the deeper C state.", + "Unit": "PCU" + }, + { + "BriefDescription": "Deep C State Rejection - Core 11", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE11", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of times that a deep C state was requ= ested, but the delayed C state algorithm rejected the deep sleep state. In= other words, a wake event occurred before the timer expired that causes a = transition into the deeper C state.", + "Unit": "PCU" + }, + { + "BriefDescription": "Deep C State Rejection - Core 12", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE12", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of times that a deep C state was requ= ested, but the delayed C state algorithm rejected the deep sleep state. In= other words, a wake event occurred before the timer expired that causes a = transition into the deeper C state.", + "Unit": "PCU" + }, + { + "BriefDescription": "Deep C State Rejection - Core 13", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE13", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of times that a deep C state was requ= ested, but the delayed C state algorithm rejected the deep sleep state. In= other words, a wake event occurred before the timer expired that causes a = transition into the deeper C state.", + "Unit": "PCU" + }, + { + "BriefDescription": "Deep C State Rejection - Core 14", + "Counter": "0,1,2,3", + "EventCode": "0x25", + "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE14", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of times that a deep C state was requ= ested, but the delayed C state algorithm rejected the deep sleep state. In= other words, a wake event occurred before the timer expired that causes a = transition into the deeper C state.", + "Unit": "PCU" + }, + { + "BriefDescription": "Deep C State Rejection - Core 2", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE2", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of times that a deep C state was requ= ested, but the delayed C state algorithm rejected the deep sleep state. In= other words, a wake event occurred before the timer expired that causes a = transition into the deeper C state.", + "Unit": "PCU" + }, + { + "BriefDescription": "Deep C State Rejection - Core 3", + "Counter": "0,1,2,3", + "EventCode": "0x1a", + "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE3", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of times that a deep C state was requ= ested, but the delayed C state algorithm rejected the deep sleep state. In= other words, a wake event occurred before the timer expired that causes a = transition into the deeper C state.", + "Unit": "PCU" + }, + { + "BriefDescription": "Deep C State Rejection - Core 4", + "Counter": "0,1,2,3", + "EventCode": "0x1b", + "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE4", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of times that a deep C state was requ= ested, but the delayed C state algorithm rejected the deep sleep state. In= other words, a wake event occurred before the timer expired that causes a = transition into the deeper C state.", + "Unit": "PCU" + }, + { + "BriefDescription": "Deep C State Rejection - Core 5", + "Counter": "0,1,2,3", + "EventCode": "0x1c", + "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE5", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of times that a deep C state was requ= ested, but the delayed C state algorithm rejected the deep sleep state. In= other words, a wake event occurred before the timer expired that causes a = transition into the deeper C state.", + "Unit": "PCU" + }, + { + "BriefDescription": "Deep C State Rejection - Core 6", + "Counter": "0,1,2,3", + "EventCode": "0x1d", + "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE6", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of times that a deep C state was requ= ested, but the delayed C state algorithm rejected the deep sleep state. In= other words, a wake event occurred before the timer expired that causes a = transition into the deeper C state.", + "Unit": "PCU" + }, + { + "BriefDescription": "Deep C State Rejection - Core 7", + "Counter": "0,1,2,3", + "EventCode": "0x1e", + "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE7", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of times that a deep C state was requ= ested, but the delayed C state algorithm rejected the deep sleep state. In= other words, a wake event occurred before the timer expired that causes a = transition into the deeper C state.", + "Unit": "PCU" + }, + { + "BriefDescription": "Deep C State Rejection - Core 8", + "Counter": "0,1,2,3", + "EventCode": "0x1f", + "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE8", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of times that a deep C state was requ= ested, but the delayed C state algorithm rejected the deep sleep state. In= other words, a wake event occurred before the timer expired that causes a = transition into the deeper C state.", + "Unit": "PCU" + }, + { + "BriefDescription": "Deep C State Rejection - Core 9", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE9", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of times that a deep C state was requ= ested, but the delayed C state algorithm rejected the deep sleep state. In= other words, a wake event occurred before the timer expired that causes a = transition into the deeper C state.", + "Unit": "PCU" + }, + { + "BriefDescription": "Core 0 C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x1e", + "EventName": "UNC_P_DEMOTIONS_CORE0", + "Filter": "PCUFilter[7:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core 1 C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x1f", + "EventName": "UNC_P_DEMOTIONS_CORE1", + "Filter": "PCUFilter[7:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core 10 C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x42", + "EventName": "UNC_P_DEMOTIONS_CORE10", + "Filter": "PCUFilter[7:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core 11 C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x43", + "EventName": "UNC_P_DEMOTIONS_CORE11", + "Filter": "PCUFilter[7:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core 12 C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x44", + "EventName": "UNC_P_DEMOTIONS_CORE12", + "Filter": "PCUFilter[7:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core 13 C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x45", + "EventName": "UNC_P_DEMOTIONS_CORE13", + "Filter": "PCUFilter[7:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core 14 C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x46", + "EventName": "UNC_P_DEMOTIONS_CORE14", + "Filter": "PCUFilter[7:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core 2 C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_P_DEMOTIONS_CORE2", + "Filter": "PCUFilter[7:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core 3 C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_P_DEMOTIONS_CORE3", + "Filter": "PCUFilter[7:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core 4 C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_P_DEMOTIONS_CORE4", + "Filter": "PCUFilter[7:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core 5 C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_P_DEMOTIONS_CORE5", + "Filter": "PCUFilter[7:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core 6 C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_P_DEMOTIONS_CORE6", + "Filter": "PCUFilter[7:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core 7 C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x25", + "EventName": "UNC_P_DEMOTIONS_CORE7", + "Filter": "PCUFilter[7:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core 8 C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_P_DEMOTIONS_CORE8", + "Filter": "PCUFilter[7:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core 9 C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_P_DEMOTIONS_CORE9", + "Filter": "PCUFilter[7:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Frequency Residency", + "Counter": "0,1,2,3", + "EventCode": "0xb", + "EventName": "UNC_P_FREQ_BAND0_CYCLES", + "Filter": "PCUFilter[7:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the uncore = was running at a frequency greater than or equal to the frequency that is c= onfigured in the filter. One can use all four counters with this event, so= it is possible to track up to 4 configurable bands. One can use edge dete= ct in conjunction with this event to track the number of times that we tran= sitioned into a frequency greater than or equal to the configurable frequen= cy. One can also use inversion to track cycles when we were less than the c= onfigured frequency.", + "Unit": "PCU" + }, + { + "BriefDescription": "Frequency Residency", + "Counter": "0,1,2,3", + "EventCode": "0xc", + "EventName": "UNC_P_FREQ_BAND1_CYCLES", + "Filter": "PCUFilter[15:8]", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the uncore = was running at a frequency greater than or equal to the frequency that is c= onfigured in the filter. One can use all four counters with this event, so= it is possible to track up to 4 configurable bands. One can use edge dete= ct in conjunction with this event to track the number of times that we tran= sitioned into a frequency greater than or equal to the configurable frequen= cy. One can also use inversion to track cycles when we were less than the c= onfigured frequency.", + "Unit": "PCU" + }, + { + "BriefDescription": "Frequency Residency", + "Counter": "0,1,2,3", + "EventCode": "0xd", + "EventName": "UNC_P_FREQ_BAND2_CYCLES", + "Filter": "PCUFilter[23:16]", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the uncore = was running at a frequency greater than or equal to the frequency that is c= onfigured in the filter. One can use all four counters with this event, so= it is possible to track up to 4 configurable bands. One can use edge dete= ct in conjunction with this event to track the number of times that we tran= sitioned into a frequency greater than or equal to the configurable frequen= cy. One can also use inversion to track cycles when we were less than the c= onfigured frequency.", + "Unit": "PCU" + }, + { + "BriefDescription": "Frequency Residency", + "Counter": "0,1,2,3", + "EventCode": "0xe", + "EventName": "UNC_P_FREQ_BAND3_CYCLES", + "Filter": "PCUFilter[31:24]", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the uncore = was running at a frequency greater than or equal to the frequency that is c= onfigured in the filter. One can use all four counters with this event, so= it is possible to track up to 4 configurable bands. One can use edge dete= ct in conjunction with this event to track the number of times that we tran= sitioned into a frequency greater than or equal to the configurable frequen= cy. One can also use inversion to track cycles when we were less than the c= onfigured frequency.", + "Unit": "PCU" + }, + { + "BriefDescription": "Current Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_P_FREQ_MAX_CURRENT_CYCLES", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when current is = the upper limit on frequency.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles when temperature = is the upper limit on frequency", + "BriefDescription": "Thermal Strongest Upper Limit Cycles", "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES", - "MetricExpr": "(UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES / UNC_P_CLOCKT= ICKS) * 100.", - "MetricName": "freq_max_limit_thermal_cycles %", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when thermal con= ditions are the upper limit on frequency. This is related to the THERMAL_T= HROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are abo= ve the thermal temperature. This event (STRONGEST_UPPER_LIMIT) is sampled = at the output of the algorithm that determines the actual frequency, while = THERMAL_THROTTLE looks at the input.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles when the OS is th= e upper limit on frequency", + "BriefDescription": "OS Strongest Upper Limit Cycles", "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_P_FREQ_MAX_OS_CYCLES", - "MetricExpr": "(UNC_P_FREQ_MAX_OS_CYCLES / UNC_P_CLOCKTICKS) * 100= .", - "MetricName": "freq_max_os_cycles %", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the OS is t= he upper limit on frequency.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles when power is the= upper limit on frequency", + "BriefDescription": "Power Strongest Upper Limit Cycles", "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES", - "MetricExpr": "(UNC_P_FREQ_MAX_POWER_CYCLES / UNC_P_CLOCKTICKS) * = 100.", - "MetricName": "freq_max_power_cycles %", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when power is th= e upper limit on frequency.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles when current is t= he upper limit on frequency", + "BriefDescription": "IO P Limit Strongest Lower Limit Cycles", "Counter": "0,1,2,3", - "EventCode": "0x7", - "EventName": "UNC_P_FREQ_MAX_CURRENT_CYCLES", - "MetricExpr": "(UNC_P_FREQ_MAX_CURRENT_CYCLES / UNC_P_CLOCKTICKS) = * 100.", - "MetricName": "freq_max_current_cycles %", + "EventCode": "0x61", + "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when IO P Limit = is preventing us from dropping the frequency lower. This algorithm monitor= s the needs to the IO subsystem on both local and remote sockets and will m= aintain a frequency high enough to maintain good IO BW. This is necessary = for when all the IA cores on a socket are idle but a user still would like = to maintain high IO Bandwidth.", + "Unit": "PCU" + }, + { + "BriefDescription": "Perf P Limit Strongest Lower Limit Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x62", + "EventName": "UNC_P_FREQ_MIN_PERF_P_CYCLES", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when Perf P Limi= t is preventing us from dropping the frequency lower. Perf P Limit is an a= lgorithm that takes input from remote sockets when determining if a socket = should drop it's frequency down. This is largely to minimize increases in = snoop and remote read latencies.", "Unit": "PCU" }, { @@ -178,96 +541,165 @@ "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_P_FREQ_TRANS_CYCLES", - "MetricExpr": "(UNC_P_FREQ_TRANS_CYCLES / UNC_P_CLOCKTICKS) * 100.= ", - "MetricName": "freq_trans_cycles %", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the system = is changing frequency. This can not be filtered by thread ID. One can als= o use it with the occupancy counter that monitors number of threads in C0 t= o estimate the performance impact that frequency transitions had on the sys= tem.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles that the uncore w= as running at a frequency greater than or equal to 1.2Ghz. Derived from unc= _p_freq_band0_cycles", + "BriefDescription": "Memory Phase Shedding Cycles", "Counter": "0,1,2,3", - "EventCode": "0xb", - "EventName": "UNC_P_FREQ_GE_1200MHZ_CYCLES", - "Filter": "filter_band0=3D12", - "MetricExpr": "(UNC_P_FREQ_GE_1200MHZ_CYCLES / UNC_P_CLOCKTICKS) *= 100.", - "MetricName": "freq_ge_1200mhz_cycles %", + "EventCode": "0x2f", + "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the PCU has= triggered memory phase shedding. This is a mode that can be run in the iM= C physicals that saves power at the expense of additional latency.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles that the uncore w= as running at a frequency greater than or equal to 2Ghz. Derived from unc_p= _freq_band1_cycles", + "BriefDescription": "Package C State Exit Latency", "Counter": "0,1,2,3", - "EventCode": "0xc", - "EventName": "UNC_P_FREQ_GE_2000MHZ_CYCLES", - "Filter": "filter_band1=3D20", - "MetricExpr": "(UNC_P_FREQ_GE_2000MHZ_CYCLES / UNC_P_CLOCKTICKS) *= 100.", - "MetricName": "freq_ge_2000mhz_cycles %", + "EventCode": "0x26", + "EventName": "UNC_P_PKG_C_EXIT_LATENCY", + "ExtSel": "1", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the package= is transitioning from package C2 to C3.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles that the uncore w= as running at a frequency greater than or equal to 3Ghz. Derived from unc_p= _freq_band2_cycles", + "BriefDescription": "Package C State Exit Latency", "Counter": "0,1,2,3", - "EventCode": "0xd", - "EventName": "UNC_P_FREQ_GE_3000MHZ_CYCLES", - "Filter": "filter_band2=3D30", - "MetricExpr": "(UNC_P_FREQ_GE_3000MHZ_CYCLES / UNC_P_CLOCKTICKS) *= 100.", - "MetricName": "freq_ge_3000mhz_cycles %", + "EventCode": "0x26", + "EventName": "UNC_P_PKG_C_EXIT_LATENCY_SEL", + "ExtSel": "1", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the package= is transitioning from package C2 to C3.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles that the uncore w= as running at a frequency greater than or equal to 4Ghz. Derived from unc_p= _freq_band3_cycles", + "BriefDescription": "Package C State Residency - C0", "Counter": "0,1,2,3", - "EventCode": "0xe", - "EventName": "UNC_P_FREQ_GE_4000MHZ_CYCLES", - "Filter": "filter_band3=3D40", - "MetricExpr": "(UNC_P_FREQ_GE_4000MHZ_CYCLES / UNC_P_CLOCKTICKS) *= 100.", - "MetricName": "freq_ge_4000mhz_cycles %", + "EventCode": "0x2a", + "EventName": "UNC_P_PKG_C_STATE_RESIDENCY_C0_CYCLES", + "ExtSel": "1", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the package= is in C0", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of times that the uncore tr= ansitioned to a frequency greater than or equal to 1.2Ghz. Derived from unc= _p_freq_band0_cycles", + "BriefDescription": "Package C State Residency - C2", "Counter": "0,1,2,3", - "EventCode": "0xb", - "EventName": "UNC_P_FREQ_GE_1200MHZ_TRANSITIONS", - "Filter": "edge=3D1,filter_band0=3D12", - "MetricExpr": "(UNC_P_FREQ_GE_1200MHZ_CYCLES / UNC_P_CLOCKTICKS) *= 100.", - "MetricName": "freq_ge_1200mhz_cycles %", + "EventCode": "0x2b", + "EventName": "UNC_P_PKG_C_STATE_RESIDENCY_C2_CYCLES", + "ExtSel": "1", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the package= is in C2", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of times that the uncore tr= ansitioned to a frequency greater than or equal to 2Ghz. Derived from unc_p= _freq_band1_cycles", + "BriefDescription": "Package C State Residency - C3", "Counter": "0,1,2,3", - "EventCode": "0xc", - "EventName": "UNC_P_FREQ_GE_2000MHZ_TRANSITIONS", - "Filter": "edge=3D1,filter_band1=3D20", - "MetricExpr": "(UNC_P_FREQ_GE_2000MHZ_CYCLES / UNC_P_CLOCKTICKS) *= 100.", - "MetricName": "freq_ge_2000mhz_cycles %", + "EventCode": "0x2c", + "EventName": "UNC_P_PKG_C_STATE_RESIDENCY_C3_CYCLES", + "ExtSel": "1", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the package= is in C3", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles that the uncore t= ransitioned to a frequency greater than or equal to 3Ghz. Derived from unc_= p_freq_band2_cycles", + "BriefDescription": "Package C State Residency - C6", "Counter": "0,1,2,3", - "EventCode": "0xd", - "EventName": "UNC_P_FREQ_GE_3000MHZ_TRANSITIONS", - "Filter": "edge=3D1,filter_band2=3D30", - "MetricExpr": "(UNC_P_FREQ_GE_3000MHZ_CYCLES / UNC_P_CLOCKTICKS) *= 100.", - "MetricName": "freq_ge_3000mhz_cycles %", + "EventCode": "0x2d", + "EventName": "UNC_P_PKG_C_STATE_RESIDENCY_C6_CYCLES", + "ExtSel": "1", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the package= is in C6", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles that the uncore t= ransitioned to a frequency greater than or equal to 4Ghz. Derived from unc_= p_freq_band3_cycles", + "BriefDescription": "Number of cores in C-State; C0 and C1", "Counter": "0,1,2,3", - "EventCode": "0xe", - "EventName": "UNC_P_FREQ_GE_4000MHZ_TRANSITIONS", - "Filter": "edge=3D1,filter_band3=3D40", - "MetricExpr": "(UNC_P_FREQ_GE_4000MHZ_CYCLES / UNC_P_CLOCKTICKS) *= 100.", - "MetricName": "freq_ge_4000mhz_cycles %", + "EventCode": "0x80", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", + "PerPkg": "1", + "PublicDescription": "This is an occupancy event that tracks the n= umber of cores that are in the chosen C-State. It can be used by itself to= get the average number of cores in that C-state with threshholding to gene= rate histograms, or with other PCU events and occupancy triggering to captu= re other details.", + "Unit": "PCU" + }, + { + "BriefDescription": "Number of cores in C-State; C3", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", + "PerPkg": "1", + "PublicDescription": "This is an occupancy event that tracks the n= umber of cores that are in the chosen C-State. It can be used by itself to= get the average number of cores in that C-state with threshholding to gene= rate histograms, or with other PCU events and occupancy triggering to captu= re other details.", + "Unit": "PCU" + }, + { + "BriefDescription": "Number of cores in C-State; C6 and C7", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", + "PerPkg": "1", + "PublicDescription": "This is an occupancy event that tracks the n= umber of cores that are in the chosen C-State. It can be used by itself to= get the average number of cores in that C-state with threshholding to gene= rate histograms, or with other PCU events and occupancy triggering to captu= re other details.", + "Unit": "PCU" + }, + { + "BriefDescription": "External Prochot", + "Counter": "0,1,2,3", + "EventCode": "0xa", + "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that we are in e= xternal PROCHOT mode. This mode is triggered when a sensor off the die det= ermines that something off-die (like DRAM) is too hot and must throttle to = avoid damaging the chip.", + "Unit": "PCU" + }, + { + "BriefDescription": "Internal Prochot", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that we are in I= nteral PROCHOT mode. This mode is triggered when a sensor on the die deter= mines that we are too hot and must throttle to avoid damaging the chip.", + "Unit": "PCU" + }, + { + "BriefDescription": "Total Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x63", + "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions across all cores.", + "Unit": "PCU" + }, + { + "BriefDescription": "Cycles Changing Voltage", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_P_VOLT_TRANS_CYCLES_CHANGE", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the system = is changing voltage. There is no filtering supported with this event. One= can use it as a simple event, or use it conjunction with the occupancy eve= nts to monitor the number of cores or threads that were impacted by the tra= nsition. This event is calculated by or'ing together the increasing and de= creasing events.", + "Unit": "PCU" + }, + { + "BriefDescription": "Cycles Decreasing Voltage", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_P_VOLT_TRANS_CYCLES_DECREASE", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the system = is decreasing voltage. There is no filtering supported with this event. O= ne can use it as a simple event, or use it conjunction with the occupancy e= vents to monitor the number of cores or threads that were impacted by the t= ransition.", + "Unit": "PCU" + }, + { + "BriefDescription": "Cycles Increasing Voltage", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_P_VOLT_TRANS_CYCLES_INCREASE", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the system = is increasing voltage. There is no filtering supported with this event. O= ne can use it as a simple event, or use it conjunction with the occupancy e= vents to monitor the number of cores or threads that were impacted by the t= ransition.", + "Unit": "PCU" + }, + { + "BriefDescription": "VR Hot", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_P_VR_HOT_CYCLES", "PerPkg": "1", "Unit": "PCU" } diff --git a/tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json b/t= ools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json index da6a3e09a782..6624d02ad715 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json @@ -195,4 +195,4 @@ "SampleAfterValue": "100007", "UMask": "0x20" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index dbb1197805d3..4b8e248d6588 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -13,7 +13,7 @@ GenuineIntel-6-3F,v25,haswellx,core GenuineIntel-6-(7D|7E|A7),v1.14,icelake,core GenuineIntel-6-6[AC],v1.15,icelakex,core GenuineIntel-6-3A,v22,ivybridge,core -GenuineIntel-6-3E,v19,ivytown,core +GenuineIntel-6-3E,v21,ivytown,core GenuineIntel-6-2D,v20,jaketown,core GenuineIntel-6-57,v9,knightslanding,core GenuineIntel-6-85,v9,knightslanding,core --=20 2.37.1.359.gd136c6c3e2-goog From nobody Wed Apr 15 05:45:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5DA84C19F29 for ; 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Wed, 27 Jul 2022 15:09:26 -0700 (PDT) Date: Wed, 27 Jul 2022 15:08:18 -0700 In-Reply-To: <20220727220832.2865794-1-irogers@google.com> Message-Id: <20220727220832.2865794-17-irogers@google.com> Mime-Version: 1.0 References: <20220727220832.2865794-1-irogers@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH v3 16/30] perf vendor events: Update Intel jaketown From: Ian Rogers To: perry.taylor@intel.com, caleb.biggers@intel.com, kshipra.bopardikar@intel.com, Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Sedat Dilek Cc: Stephane Eranian , Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Update to v21, the metrics are based on TMA 4.4 full. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/downloa= d_and_gen.py to download and generate the latest events and metrics. Manually copy the jaketown files into perf and update mapfile.csv. Tested on a non-jaketown with 'perf test': 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/jaketown/cache.json | 2 +- .../arch/x86/jaketown/floating-point.json | 2 +- .../arch/x86/jaketown/frontend.json | 2 +- .../arch/x86/jaketown/jkt-metrics.json | 11 +- .../pmu-events/arch/x86/jaketown/memory.json | 2 +- .../pmu-events/arch/x86/jaketown/other.json | 2 +- .../arch/x86/jaketown/pipeline.json | 16 +- .../arch/x86/jaketown/uncore-cache.json | 1960 ++++++++++++++++- .../x86/jaketown/uncore-interconnect.json | 824 ++++++- .../arch/x86/jaketown/uncore-memory.json | 445 +++- .../arch/x86/jaketown/uncore-other.json | 1551 +++++++++++++ .../arch/x86/jaketown/uncore-power.json | 362 +-- .../arch/x86/jaketown/virtual-memory.json | 2 +- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 14 files changed, 4910 insertions(+), 273 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/jaketown/uncore-other.js= on diff --git a/tools/perf/pmu-events/arch/x86/jaketown/cache.json b/tools/per= f/pmu-events/arch/x86/jaketown/cache.json index 97c7e0ceed18..f98649fb92b4 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/cache.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/cache.json @@ -1263,4 +1263,4 @@ "SampleAfterValue": "100003", "UMask": "0x10" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/jaketown/floating-point.json b/= tools/perf/pmu-events/arch/x86/jaketown/floating-point.json index 713878fd062b..eb2ff2cfdf6b 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/floating-point.json @@ -135,4 +135,4 @@ "SampleAfterValue": "2000003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/jaketown/frontend.json b/tools/= perf/pmu-events/arch/x86/jaketown/frontend.json index 4bc0954448d2..0b4dbce2f1c0 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/frontend.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/frontend.json @@ -311,4 +311,4 @@ "SampleAfterValue": "2000003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json b/too= ls/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json index 2800264c12aa..2711cbe536b8 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json @@ -124,7 +124,7 @@ "MetricName": "FLOPc_SMT" }, { - "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is at least 1 uop executed)", + "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per-core", "MetricExpr": "UOPS_DISPATCHED.THREAD / (( cpu@UOPS_DISPATCHED.COR= E\\,cmask\\=3D1@ / 2 ) if #SMT_on else cpu@UOPS_DISPATCHED.CORE\\,cmask\\= =3D1@)", "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" @@ -141,6 +141,12 @@ "MetricGroup": "Summary;TmaL1", "MetricName": "Instructions" }, + { + "BriefDescription": "Average number of Uops retired in cycles wher= e at least one uop has retired.", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE= _SLOTS\\,cmask\\=3D1@", + "MetricGroup": "Pipeline;Ret", + "MetricName": "Retire" + }, { "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MIT= E_UOPS + IDQ.MS_UOPS ) )", @@ -163,7 +169,8 @@ "BriefDescription": "Giga Floating Point Operations Per Second", "MetricExpr": "( ( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_CO= MP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 = * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * S= IMD_FP_256.PACKED_SINGLE ) / 1000000000 ) / duration_time", "MetricGroup": "Cor;Flops;HPC", - "MetricName": "GFLOPs" + "MetricName": "GFLOPs", + "PublicDescription": "Giga Floating Point Operations Per Second. A= ggregate across all supported options of: FP precisions, scalar and vector = instructions, vector-width and AMX engine." }, { "BriefDescription": "Average Frequency Utilization relative nomina= l frequency", diff --git a/tools/perf/pmu-events/arch/x86/jaketown/memory.json b/tools/pe= rf/pmu-events/arch/x86/jaketown/memory.json index 29b70f21a44b..23756ca9b7da 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/memory.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/memory.json @@ -419,4 +419,4 @@ "SampleAfterValue": "100003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/jaketown/other.json b/tools/per= f/pmu-events/arch/x86/jaketown/other.json index e251f535ec09..2f873ab14156 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/other.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/other.json @@ -55,4 +55,4 @@ "SampleAfterValue": "2000003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json b/tools/= perf/pmu-events/arch/x86/jaketown/pipeline.json index 87737c92c067..61a3db4d67d5 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json @@ -410,8 +410,8 @@ }, { "BriefDescription": "Reference cycles when the core is not in halt= state.", - "Counter": "Fixed counter 3", - "CounterHTOff": "Fixed counter 3", + "Counter": "Fixed counter 2", + "CounterHTOff": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PublicDescription": "This event counts the number of reference cy= cles when the core is not in a halt state. The core enters the halt state w= hen it is running the HLT instruction or the MWAIT instruction. This event = is not affected by core frequency changes (for example, P states, TM2 trans= itions) but has the same incrementing frequency as the time stamp counter. = This event can approximate elapsed time while the core was not in a halt st= ate. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK eve= nt. It is counted on a dedicated fixed counter, leaving the four (eight whe= n Hyperthreading is disabled) programmable counters available for other eve= nts.", "SampleAfterValue": "2000003", @@ -439,8 +439,8 @@ }, { "BriefDescription": "Core cycles when the thread is not in halt st= ate.", - "Counter": "Fixed counter 2", - "CounterHTOff": "Fixed counter 2", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "PublicDescription": "This event counts the number of core cycles = while the thread is not in a halt state. The thread enters the halt state w= hen it is running the HLT instruction. This event is a component in many ke= y event ratios. The core frequency may change from time to time due to tran= sitions associated with Enhanced Intel SpeedStep Technology or TM2. For thi= s reason this event may have a changing ratio with regards to time. When th= e core frequency is constant, this event can approximate elapsed time while= the core was not in the halt state. It is counted on a dedicated fixed cou= nter, leaving the four (eight when Hyperthreading is disabled) programmable= counters available for other events.", "SampleAfterValue": "2000003", @@ -542,8 +542,8 @@ }, { "BriefDescription": "Instructions retired from execution.", - "Counter": "Fixed counter 1", - "CounterHTOff": "Fixed counter 1", + "Counter": "Fixed counter 0", + "CounterHTOff": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PublicDescription": "This event counts the number of instructions= retired from execution. For instructions that consist of multiple micro-op= s, this event counts the retirement of the last micro-op of the instruction= . Counting continues during hardware interrupts, traps, and inside interrup= t handlers.", "SampleAfterValue": "2000003", @@ -599,7 +599,7 @@ "UMask": "0x3" }, { - "BriefDescription": "Number of occurences waiting for the checkpoi= nts in Resource Allocation Table (RAT) to be recovered after Nuke due to al= l other cases except JEClear (e.g. whenever a ucode assist is needed like S= SE exception, memory disambiguation, etc...).", + "BriefDescription": "Number of occurrences waiting for the checkpo= ints in Resource Allocation Table (RAT) to be recovered after Nuke due to a= ll other cases except JEClear (e.g. whenever a ucode assist is needed like = SSE exception, memory disambiguation, etc...).", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", @@ -1199,4 +1199,4 @@ "SampleAfterValue": "2000003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-cache.json b/to= ols/perf/pmu-events/arch/x86/jaketown/uncore-cache.json index 3fa61d962607..cf28ffa778ba 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-cache.json @@ -1,210 +1,1976 @@ [ { - "BriefDescription": "Uncore cache clock ticks", + "BriefDescription": "Uncore Clocks", "Counter": "0,1,2,3", "EventName": "UNC_C_CLOCKTICKS", "PerPkg": "1", "Unit": "CBO" }, { - "BriefDescription": "All LLC Misses (code+ data rd + data wr - inc= luding demand and prefetch)", + "BriefDescription": "Counter 0 Occupancy", + "Counter": "1,2,3", + "EventCode": "0x1f", + "EventName": "UNC_C_COUNTER0_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Since occupancy counts can only be captured = in the Cbo's 0 counter, this event allows a user to capture occupancy relat= ed information by filtering the Cb0 occupancy count captured in Counter 0. = The filtering available is found in the control register - threshold, inv= ert and edge detect. E.g. setting threshold to 1 can effectively monitor = how many cycles the monitored queue has an entry.", + "Unit": "CBO" + }, + { + "BriefDescription": "Cache Lookups; Data Read Request", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.DATA_READ", + "Filter": "CBoFilter[22:18]", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set filter mask bit 0 and select a sta= te or states to match. Otherwise, the event will count nothing. CBoGlCtr= l[22:18] bits correspond to [FMESI] state.", + "UMask": "0x3", + "Unit": "CBO" + }, + { + "BriefDescription": "Cache Lookups; RTID", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.NID", + "Filter": "CBoFilter[22:18], CBoFilter[17:10]", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set filter mask bit 0 and select a sta= te or states to match. Otherwise, the event will count nothing. CBoGlCtr= l[22:18] bits correspond to [FMESI] state.", + "UMask": "0x41", + "Unit": "CBO" + }, + { + "BriefDescription": "Cache Lookups; External Snoop Request", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP", + "Filter": "CBoFilter[22:18]", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set filter mask bit 0 and select a sta= te or states to match. Otherwise, the event will count nothing. CBoGlCtr= l[22:18] bits correspond to [FMESI] state.", + "UMask": "0x9", + "Unit": "CBO" + }, + { + "BriefDescription": "Cache Lookups; Write Requests", "Counter": "0,1", "EventCode": "0x34", - "EventName": "UNC_C_LLC_LOOKUP.ANY", - "Filter": "filter_state=3D0x1", + "EventName": "UNC_C_LLC_LOOKUP.WRITE", + "Filter": "CBoFilter[22:18]", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set filter mask bit 0 and select a sta= te or states to match. Otherwise, the event will count nothing. CBoGlCtr= l[22:18] bits correspond to [FMESI] state.", + "UMask": "0x5", + "Unit": "CBO" + }, + { + "BriefDescription": "Lines Victimized; Lines in E state", + "Counter": "0,1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.E_STATE", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Lines Victimized", + "Counter": "0,1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.MISS", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x11", + "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x8", "Unit": "CBO" }, { - "BriefDescription": "M line evictions from LLC (writebacks to memo= ry)", + "BriefDescription": "Lines Victimized; Lines in M state", "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.M_STATE", "PerPkg": "1", - "ScaleUnit": "64Bytes", + "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x1", "Unit": "CBO" }, { - "BriefDescription": "LLC misses - demand and prefetch data reads -= excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode.demand= ", + "BriefDescription": "Lines Victimized; Victimized Lines that Match= NID", "Counter": "0,1", - "EventCode": "0x35", - "EventName": "LLC_MISSES.DATA_READ", - "Filter": "filter_opc=3D0x182", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.NID", + "Filter": "CBoFilter[17:10]", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", + "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x40", "Unit": "CBO" }, { - "BriefDescription": "LLC misses - Uncacheable reads. Derived from = unc_c_tor_inserts.miss_opcode.uncacheable", + "BriefDescription": "Lines Victimized; Lines in S State", "Counter": "0,1", - "EventCode": "0x35", - "EventName": "LLC_MISSES.UNCACHEABLE", - "Filter": "filter_opc=3D0x187", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.S_STATE", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", + "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x4", "Unit": "CBO" }, { - "BriefDescription": "PCIe allocating writes that miss LLC - DDIO m= isses. Derived from unc_c_tor_inserts.miss_opcode.ddio_miss", + "BriefDescription": "Cbo Misc; RFO HitS", "Counter": "0,1", - "EventCode": "0x35", - "EventName": "LLC_MISSES.PCIE_WRITE", - "Filter": "filter_opc=3D0x19c", + "EventCode": "0x39", + "EventName": "UNC_C_MISC.RFO_HIT_S", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", + "PublicDescription": "Miscellaneous events in the Cbo.", + "UMask": "0x8", "Unit": "CBO" }, { - "BriefDescription": "LLC misses for ItoM writes (as part of fast s= tring memcpy stores). Derived from unc_c_tor_inserts.miss_opcode.itom_write= ", + "BriefDescription": "Cbo Misc; Silent Snoop Eviction", "Counter": "0,1", - "EventCode": "0x35", - "EventName": "LLC_MISSES.ITOM_WRITE", - "Filter": "filter_opc=3D0x1c8", + "EventCode": "0x39", + "EventName": "UNC_C_MISC.RSPI_WAS_FSE", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", + "PublicDescription": "Miscellaneous events in the Cbo.", + "UMask": "0x1", "Unit": "CBO" }, { - "BriefDescription": "Streaming stores (full cache line). Derived f= rom unc_c_tor_inserts.opcode.streaming_full", + "BriefDescription": "Cbo Misc", "Counter": "0,1", - "EventCode": "0x35", - "EventName": "LLC_REFERENCES.STREAMING_FULL", - "Filter": "filter_opc=3D0x18c", + "EventCode": "0x39", + "EventName": "UNC_C_MISC.STARTED", + "PerPkg": "1", + "PublicDescription": "Miscellaneous events in the Cbo.", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Cbo Misc; Write Combining Aliasing", + "Counter": "0,1", + "EventCode": "0x39", + "EventName": "UNC_C_MISC.WC_ALIASING", + "PerPkg": "1", + "PublicDescription": "Miscellaneous events in the Cbo.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "AD Ring In Use; Down and Even", + "Counter": "2,3", + "EventCode": "0x1b", + "EventName": "UNC_C_RING_AD_USED.DOWN_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop. We really have two rings in JKT -- a clockwis= e ring and a counter-clockwise ring. On the left side of the ring, the 'UP= ' direction is on the clockwise ring and 'DN' is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "AD Ring In Use; Down and Odd", + "Counter": "2,3", + "EventCode": "0x1b", + "EventName": "UNC_C_RING_AD_USED.DOWN_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop. We really have two rings in JKT -- a clockwis= e ring and a counter-clockwise ring. On the left side of the ring, the 'UP= ' direction is on the clockwise ring and 'DN' is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "AD Ring In Use; Up and Even", + "Counter": "2,3", + "EventCode": "0x1b", + "EventName": "UNC_C_RING_AD_USED.UP_EVEN", "PerPkg": "1", - "ScaleUnit": "64Bytes", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop. We really have two rings in JKT -- a clockwis= e ring and a counter-clockwise ring. On the left side of the ring, the 'UP= ' direction is on the clockwise ring and 'DN' is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", "UMask": "0x1", "Unit": "CBO" }, { - "BriefDescription": "Streaming stores (partial cache line). Derive= d from unc_c_tor_inserts.opcode.streaming_partial", + "BriefDescription": "AD Ring In Use; Up and Odd", + "Counter": "2,3", + "EventCode": "0x1b", + "EventName": "UNC_C_RING_AD_USED.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop. We really have two rings in JKT -- a clockwis= e ring and a counter-clockwise ring. On the left side of the ring, the 'UP= ' direction is on the clockwise ring and 'DN' is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "AK Ring In Use; Down and Even", + "Counter": "2,3", + "EventCode": "0x1c", + "EventName": "UNC_C_RING_AK_USED.DOWN_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in JKT -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the 'UP' = direction is on the clockwise ring and 'DN' is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "AK Ring In Use; Down and Odd", + "Counter": "2,3", + "EventCode": "0x1c", + "EventName": "UNC_C_RING_AK_USED.DOWN_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in JKT -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the 'UP' = direction is on the clockwise ring and 'DN' is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "AK Ring In Use; Up and Even", + "Counter": "2,3", + "EventCode": "0x1c", + "EventName": "UNC_C_RING_AK_USED.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in JKT -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the 'UP' = direction is on the clockwise ring and 'DN' is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "AK Ring In Use; Up and Odd", + "Counter": "2,3", + "EventCode": "0x1c", + "EventName": "UNC_C_RING_AK_USED.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in JKT -- a clockwise = ring and a counter-clockwise ring. On the left side of the ring, the 'UP' = direction is on the clockwise ring and 'DN' is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "BL Ring in Use; Down and Even", + "Counter": "2,3", + "EventCode": "0x1d", + "EventName": "UNC_C_RING_BL_USED.DOWN_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in JKT -- a clockwise= ring and a counter-clockwise ring. On the left side of the ring, the 'UP'= direction is on the clockwise ring and 'DN' is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "BL Ring in Use; Down and Odd", + "Counter": "2,3", + "EventCode": "0x1d", + "EventName": "UNC_C_RING_BL_USED.DOWN_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in JKT -- a clockwise= ring and a counter-clockwise ring. On the left side of the ring, the 'UP'= direction is on the clockwise ring and 'DN' is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "BL Ring in Use; Up and Even", + "Counter": "2,3", + "EventCode": "0x1d", + "EventName": "UNC_C_RING_BL_USED.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in JKT -- a clockwise= ring and a counter-clockwise ring. On the left side of the ring, the 'UP'= direction is on the clockwise ring and 'DN' is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "BL Ring in Use; Up and Odd", + "Counter": "2,3", + "EventCode": "0x1d", + "EventName": "UNC_C_RING_BL_USED.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.We really have two rings in JKT -- a clockwise= ring and a counter-clockwise ring. On the left side of the ring, the 'UP'= direction is on the clockwise ring and 'DN' is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Number of LLC responses that bounced on the R= ing.; Acknowledgements to core", "Counter": "0,1", - "EventCode": "0x35", - "EventName": "LLC_REFERENCES.STREAMING_PARTIAL", - "Filter": "filter_opc=3D0x18d", + "EventCode": "0x5", + "EventName": "UNC_C_RING_BOUNCES.AK_CORE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Number of LLC responses that bounced on the R= ing.; Data Responses to core", + "Counter": "0,1", + "EventCode": "0x5", + "EventName": "UNC_C_RING_BOUNCES.BL_CORE", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Number of LLC responses that bounced on the R= ing.; Snoops of processor's cache.", + "Counter": "0,1", + "EventCode": "0x5", + "EventName": "UNC_C_RING_BOUNCES.IV_CORE", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "BL Ring in Use; Any", + "Counter": "2,3", + "EventCode": "0x1e", + "EventName": "UNC_C_RING_IV_USED.ANY", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop. There is only 1 IV ring in JKT. Therefore, i= f one wants to monitor the 'Even' ring, they should select both UP_EVEN and= DN_EVEN. To monitor the 'Odd' ring, they should select both UP_ODD and DN= _ODD.", + "UMask": "0xf", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_C_RxR_EXT_STARVED.IPQ", + "PerPkg": "1", + "PublicDescription": "Counts cycles in external starvation. This = occurs when one of the ingress queues is being starved by the other queues.= ", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_C_RxR_EXT_STARVED.IRQ", "PerPkg": "1", - "ScaleUnit": "64Bytes", + "PublicDescription": "Counts cycles in external starvation. This = occurs when one of the ingress queues is being starved by the other queues.= ", "UMask": "0x1", "Unit": "CBO" }, { - "BriefDescription": "Partial PCIe reads. Derived from unc_c_tor_in= serts.opcode.pcie_partial", + "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ", "Counter": "0,1", - "EventCode": "0x35", - "EventName": "LLC_REFERENCES.PCIE_PARTIAL_READ", - "Filter": "filter_opc=3D0x195", + "EventCode": "0x12", + "EventName": "UNC_C_RxR_EXT_STARVED.ISMQ", "PerPkg": "1", - "ScaleUnit": "64Bytes", + "PublicDescription": "Counts cycles in external starvation. This = occurs when one of the ingress queues is being starved by the other queues.= ", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_C_RxR_EXT_STARVED.ISMQ_BIDS", + "PerPkg": "1", + "PublicDescription": "Counts cycles in external starvation. This = occurs when one of the ingress queues is being starved by the other queues.= ", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Allocations; IPQ", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_C_RxR_INSERTS.IPQ", + "PerPkg": "1", + "PublicDescription": "Counts number of allocations per cycle into = the specified Ingress queue.", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Allocations; IRQ", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_C_RxR_INSERTS.IRQ", + "PerPkg": "1", + "PublicDescription": "Counts number of allocations per cycle into = the specified Ingress queue.", "UMask": "0x1", "Unit": "CBO" }, { - "BriefDescription": "PCIe allocating writes that hit in LLC (DDIO = hits). Derived from unc_c_tor_inserts.opcode.ddio_hit", + "BriefDescription": "Ingress Allocations; IRQ Rejected", "Counter": "0,1", - "EventCode": "0x35", - "EventName": "LLC_REFERENCES.PCIE_WRITE", - "Filter": "filter_opc=3D0x19c", + "EventCode": "0x13", + "EventName": "UNC_C_RxR_INSERTS.IRQ_REJECTED", "PerPkg": "1", - "ScaleUnit": "64Bytes", + "PublicDescription": "Counts number of allocations per cycle into = the specified Ingress queue.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Allocations; VFIFO", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_C_RxR_INSERTS.VFIFO", + "PerPkg": "1", + "PublicDescription": "Counts number of allocations per cycle into = the specified Ingress queue.", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Internal Starvation Cycles; IPQ", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "UNC_C_RxR_INT_STARVED.IPQ", + "PerPkg": "1", + "PublicDescription": "Counts cycles in internal starvation. This = occurs when one (or more) of the entries in the ingress queue are being sta= rved out by other entries in that queue.", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Internal Starvation Cycles; IRQ", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "UNC_C_RxR_INT_STARVED.IRQ", + "PerPkg": "1", + "PublicDescription": "Counts cycles in internal starvation. This = occurs when one (or more) of the entries in the ingress queue are being sta= rved out by other entries in that queue.", "UMask": "0x1", "Unit": "CBO" }, { - "BriefDescription": "PCIe read current. Derived from unc_c_tor_ins= erts.opcode.pcie_read_current", + "BriefDescription": "Ingress Internal Starvation Cycles; ISMQ", "Counter": "0,1", - "EventCode": "0x35", - "EventName": "LLC_REFERENCES.PCIE_READ", - "Filter": "filter_opc=3D0x19e", + "EventCode": "0x14", + "EventName": "UNC_C_RxR_INT_STARVED.ISMQ", "PerPkg": "1", - "ScaleUnit": "64Bytes", + "PublicDescription": "Counts cycles in internal starvation. This = occurs when one (or more) of the entries in the ingress queue are being sta= rved out by other entries in that queue.", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "Probe Queue Retries; Address Conflict", + "Counter": "0,1", + "EventCode": "0x31", + "EventName": "UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT", + "PerPkg": "1", + "PublicDescription": "Number of times a snoop (probe) request had = to retry. Filters exist to cover some of the common cases retries.", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Probe Queue Retries; Any Reject", + "Counter": "0,1", + "EventCode": "0x31", + "EventName": "UNC_C_RxR_IPQ_RETRY.ANY", + "PerPkg": "1", + "PublicDescription": "Number of times a snoop (probe) request had = to retry. Filters exist to cover some of the common cases retries.", "UMask": "0x1", "Unit": "CBO" }, { - "BriefDescription": "ItoM write hits (as part of fast string memcp= y stores). Derived from unc_c_tor_inserts.opcode.itom_write_hit", + "BriefDescription": "Probe Queue Retries; No Egress Credits", "Counter": "0,1", - "EventCode": "0x35", - "EventName": "LLC_REFERENCES.ITOM_WRITE", - "Filter": "filter_opc=3D0x1c8", + "EventCode": "0x31", + "EventName": "UNC_C_RxR_IPQ_RETRY.FULL", + "PerPkg": "1", + "PublicDescription": "Number of times a snoop (probe) request had = to retry. Filters exist to cover some of the common cases retries.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Probe Queue Retries; No QPI Credits", + "Counter": "0,1", + "EventCode": "0x31", + "EventName": "UNC_C_RxR_IPQ_RETRY.QPI_CREDITS", + "PerPkg": "1", + "PublicDescription": "Number of times a snoop (probe) request had = to retry. Filters exist to cover some of the common cases retries.", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Request Queue Rejects; Address Confli= ct", + "Counter": "0,1", + "EventCode": "0x32", + "EventName": "UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Request Queue Rejects; Any Reject", + "Counter": "0,1", + "EventCode": "0x32", + "EventName": "UNC_C_RxR_IRQ_RETRY.ANY", "PerPkg": "1", - "ScaleUnit": "64Bytes", "UMask": "0x1", "Unit": "CBO" }, { - "BriefDescription": "PCIe non-snoop reads. Derived from unc_c_tor_= inserts.opcode.pcie_read", + "BriefDescription": "Ingress Request Queue Rejects; No Egress Cred= its", "Counter": "0,1", - "EventCode": "0x35", - "EventName": "LLC_REFERENCES.PCIE_NS_READ", - "Filter": "filter_opc=3D0x1e4", + "EventCode": "0x32", + "EventName": "UNC_C_RxR_IRQ_RETRY.FULL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Request Queue Rejects; No QPI Credits= ", + "Counter": "0,1", + "EventCode": "0x32", + "EventName": "UNC_C_RxR_IRQ_RETRY.QPI_CREDITS", "PerPkg": "1", - "ScaleUnit": "64Bytes", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Request Queue Rejects; No RTIDs", + "Counter": "0,1", + "EventCode": "0x32", + "EventName": "UNC_C_RxR_IRQ_RETRY.RTID", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "ISMQ Retries; Any Reject", + "Counter": "0,1", + "EventCode": "0x33", + "EventName": "UNC_C_RxR_ISMQ_RETRY.ANY", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x1", "Unit": "CBO" }, { - "BriefDescription": "PCIe non-snoop writes (partial). Derived from= unc_c_tor_inserts.opcode.pcie_partial_write", + "BriefDescription": "ISMQ Retries; No Egress Credits", "Counter": "0,1", - "EventCode": "0x35", - "EventName": "LLC_REFERENCES.PCIE_NS_PARTIAL_WRITE", - "Filter": "filter_opc=3D0x1e5", + "EventCode": "0x33", + "EventName": "UNC_C_RxR_ISMQ_RETRY.FULL", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "ISMQ Retries; No IIO Credits", + "Counter": "0,1", + "EventCode": "0x33", + "EventName": "UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", + "UMask": "0x20", + "Unit": "CBO" + }, + { + "BriefDescription": "ISMQ Retries; No QPI Credits", + "Counter": "0,1", + "EventCode": "0x33", + "EventName": "UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "ISMQ Retries; No RTIDs", + "Counter": "0,1", + "EventCode": "0x33", + "EventName": "UNC_C_RxR_ISMQ_RETRY.RTID", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Occupancy; IPQ", + "EventCode": "0x11", + "EventName": "UNC_C_RxR_OCCUPANCY.IPQ", + "PerPkg": "1", + "PublicDescription": "Counts number of entries in the specified In= gress queue in each cycle.", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Occupancy; IRQ", + "EventCode": "0x11", + "EventName": "UNC_C_RxR_OCCUPANCY.IRQ", "PerPkg": "1", - "ScaleUnit": "64Bytes", + "PublicDescription": "Counts number of entries in the specified In= gress queue in each cycle.", "UMask": "0x1", "Unit": "CBO" }, { - "BriefDescription": "PCIe non-snoop writes (full line). Derived fr= om unc_c_tor_inserts.opcode.pcie_full_write", + "BriefDescription": "Ingress Occupancy; IRQ Rejected", + "EventCode": "0x11", + "EventName": "UNC_C_RxR_OCCUPANCY.IRQ_REJECTED", + "PerPkg": "1", + "PublicDescription": "Counts number of entries in the specified In= gress queue in each cycle.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Occupancy; VFIFO", + "EventCode": "0x11", + "EventName": "UNC_C_RxR_OCCUPANCY.VFIFO", + "PerPkg": "1", + "PublicDescription": "Counts number of entries in the specified In= gress queue in each cycle.", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Evictions", "Counter": "0,1", "EventCode": "0x35", - "EventName": "LLC_REFERENCES.PCIE_NS_WRITE", - "Filter": "filter_opc=3D0x1e6", + "EventName": "UNC_C_TOR_INSERTS.EVICTION", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' a= nd set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", + "UMask": "0x4", "Unit": "CBO" }, { - "BriefDescription": "Occupancy counter for all LLC misses; we divi= de this by UNC_C_CLOCKTICKS to get average Q depth", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.MISS_ALL", - "Filter": "filter_opc=3D0x182", - "MetricExpr": "(UNC_C_TOR_OCCUPANCY.MISS_ALL / UNC_C_CLOCKTICKS) *= 100.", - "MetricName": "tor_occupancy.miss_all %", + "BriefDescription": "TOR Inserts; Miss All", + "Counter": "0,1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.MISS_ALL", "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' a= nd set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", "UMask": "0xa", "Unit": "CBO" }, { - "BriefDescription": "Occupancy counter for LLC data reads (demand = and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode.llc_data_rea= d", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.LLC_DATA_READ", + "BriefDescription": "TOR Inserts; Miss Opcode Match", + "Counter": "0,1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", + "Filter": "CBoFilter[31:23]", "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' a= nd set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", "UMask": "0x3", "Unit": "CBO" }, { - "BriefDescription": "read requests to home agent", - "Counter": "0,1,2,3", - "EventCode": "0x1", - "EventName": "UNC_H_REQUESTS.READS", + "BriefDescription": "TOR Inserts; NID Matched", + "Counter": "0,1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.NID_ALL", + "Filter": "CBoFilter[17:10]", "PerPkg": "1", - "UMask": "0x3", - "Unit": "HA" + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' a= nd set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", + "UMask": "0x48", + "Unit": "CBO" }, { - "BriefDescription": "write requests to home agent", - "Counter": "0,1,2,3", - "EventCode": "0x1", - "EventName": "UNC_H_REQUESTS.WRITES", + "BriefDescription": "TOR Inserts; NID Matched Evictions", + "Counter": "0,1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION", + "Filter": "CBoFilter[17:10]", "PerPkg": "1", - "UMask": "0xc", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' a= nd set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", + "UMask": "0x44", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; NID Matched Miss All", + "Counter": "0,1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL", + "Filter": "CBoFilter[17:10]", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' a= nd set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", + "UMask": "0x4a", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; NID and Opcode Matched Miss", + "Counter": "0,1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE", + "Filter": "CBoFilter[31:23], CBoFilter[17:10]", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' a= nd set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", + "UMask": "0x43", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; NID and Opcode Matched", + "Counter": "0,1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.NID_OPCODE", + "Filter": "CBoFilter[31:23], CBoFilter[17:10]", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' a= nd set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", + "UMask": "0x41", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; NID Matched Writebacks", + "Counter": "0,1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.NID_WB", + "Filter": "CBoFilter[17:10]", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' a= nd set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", + "UMask": "0x50", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Opcode Match", + "Counter": "0,1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.OPCODE", + "Filter": "CBoFilter[31:23]", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' a= nd set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Writebacks", + "Counter": "0,1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.WB", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' a= nd set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; Any", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.ALL", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select 'MI= SS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; Evictions", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.EVICTION", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select 'MI= SS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; Miss All", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.MISS_ALL", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select 'MI= SS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", + "UMask": "0xa", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; Miss Opcode Match", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE", + "Filter": "CBoFilter[31:23]", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select 'MI= SS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", + "UMask": "0x3", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; NID Matched", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.NID_ALL", + "Filter": "CBoFilter[17:10]", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select 'MI= SS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", + "UMask": "0x48", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; NID Matched Evictions", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.NID_EVICTION", + "Filter": "CBoFilter[17:10]", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select 'MI= SS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", + "UMask": "0x44", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; NID Matched", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_ALL", + "Filter": "CBoFilter[17:10]", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select 'MI= SS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", + "UMask": "0x4a", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; NID and Opcode Matched Miss", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE", + "Filter": "CBoFilter[31:23], CBoFilter[17:10]", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select 'MI= SS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", + "UMask": "0x43", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; NID and Opcode Matched", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.NID_OPCODE", + "Filter": "CBoFilter[31:23], CBoFilter[17:10]", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select 'MI= SS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", + "UMask": "0x41", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; Opcode Match", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.OPCODE", + "Filter": "CBoFilter[31:23]", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select 'MI= SS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Egress Allocations; AD - Cachebo", + "Counter": "0,1", + "EventCode": "0x2", + "EventName": "UNC_C_TxR_INSERTS.AD_CACHE", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Cbo Egress. = The Egress is used to queue up requests destined for the ring.", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Egress Allocations; AD - Corebo", + "Counter": "0,1", + "EventCode": "0x2", + "EventName": "UNC_C_TxR_INSERTS.AD_CORE", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Cbo Egress. = The Egress is used to queue up requests destined for the ring.", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "Egress Allocations; AK - Cachebo", + "Counter": "0,1", + "EventCode": "0x2", + "EventName": "UNC_C_TxR_INSERTS.AK_CACHE", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Cbo Egress. = The Egress is used to queue up requests destined for the ring.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Egress Allocations; AK - Corebo", + "Counter": "0,1", + "EventCode": "0x2", + "EventName": "UNC_C_TxR_INSERTS.AK_CORE", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Cbo Egress. = The Egress is used to queue up requests destined for the ring.", + "UMask": "0x20", + "Unit": "CBO" + }, + { + "BriefDescription": "Egress Allocations; BL - Cacheno", + "Counter": "0,1", + "EventCode": "0x2", + "EventName": "UNC_C_TxR_INSERTS.BL_CACHE", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Cbo Egress. = The Egress is used to queue up requests destined for the ring.", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Egress Allocations; BL - Corebo", + "Counter": "0,1", + "EventCode": "0x2", + "EventName": "UNC_C_TxR_INSERTS.BL_CORE", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Cbo Egress. = The Egress is used to queue up requests destined for the ring.", + "UMask": "0x40", + "Unit": "CBO" + }, + { + "BriefDescription": "Egress Allocations; IV - Cachebo", + "Counter": "0,1", + "EventCode": "0x2", + "EventName": "UNC_C_TxR_INSERTS.IV_CACHE", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Cbo Egress. = The Egress is used to queue up requests destined for the ring.", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "Injection Starvation; Onto AK Ring", + "Counter": "0,1", + "EventCode": "0x3", + "EventName": "UNC_C_TxR_STARVED.AK", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the Egress cannot send a transaction onto the ring for = a long period of time.", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Injection Starvation; Onto BL Ring", + "Counter": "0,1", + "EventCode": "0x3", + "EventName": "UNC_C_TxR_STARVED.BL", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the Egress cannot send a transaction onto the ring for = a long period of time.", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "QPI Address/Opcode Match; Address & Opcode Ma= tch", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_H_ADDR_OPC_MATCH.FILT", + "Filter": "HA_AddrMatch0[31:6], HA_AddrMatch1[13:0], HA_OpcodeMatc= h[5:0]", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "HA to iMC Bypass; Not Taken", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when the HA was a= ble to bypass was attempted. This is a latency optimization for situations= when there is light loadings on the memory subsystem. This can be filted = by when the bypass was taken and when it was not.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA to iMC Bypass; Taken", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_H_BYPASS_IMC.TAKEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when the HA was a= ble to bypass was attempted. This is a latency optimization for situations= when there is light loadings on the memory subsystem. This can be filted = by when the bypass was taken and when it was not.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "uclks", + "Counter": "0,1,2,3", + "EventName": "UNC_H_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Counts the number of uclks in the HA. This = will be slightly different than the count in the Ubox because of enable/fre= eze delays. The HA is on the other side of the die from the fixed Ubox ucl= k counter, so the drift could be somewhat larger than in units that are clo= ser like the QPI Agent.", + "Unit": "HA" + }, + { + "BriefDescription": "Conflict Checks; Conflict Detected", + "Counter": "0,1,2,3", + "EventCode": "0xb", + "EventName": "UNC_H_CONFLICT_CYCLES.CONFLICT", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Conflict Checks; No Conflict", + "Counter": "0,1,2,3", + "EventCode": "0xb", + "EventName": "UNC_H_CONFLICT_CYCLES.NO_CONFLICT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Direct2Core Messages Sent", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_H_DIRECT2CORE_COUNT", + "PerPkg": "1", + "PublicDescription": "Number of Direct2Core messages sent", + "Unit": "HA" + }, + { + "BriefDescription": "Cycles when Direct2Core was Disabled", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_H_DIRECT2CORE_CYCLES_DISABLED", + "PerPkg": "1", + "PublicDescription": "Number of cycles in which Direct2Core was di= sabled", + "Unit": "HA" + }, + { + "BriefDescription": "Number of Reads that had Direct2Core Overridd= en", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_H_DIRECT2CORE_TXN_OVERRIDE", + "PerPkg": "1", + "PublicDescription": "Number of Reads where Direct2Core overridden= ", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Lookups; Snoop Not Needed", + "Counter": "0,1,2,3", + "EventCode": "0xc", + "EventName": "UNC_H_DIRECTORY_LOOKUP.NO_SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that looke= d up the directory. Can be filtered by requests that had to snoop and thos= e that did not have to.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Lookups; Snoop Needed", + "Counter": "0,1,2,3", + "EventCode": "0xc", + "EventName": "UNC_H_DIRECTORY_LOOKUP.SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that looke= d up the directory. Can be filtered by requests that had to snoop and thos= e that did not have to.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Updates; Any Directory Update", + "Counter": "0,1,2,3", + "EventCode": "0xd", + "EventName": "UNC_H_DIRECTORY_UPDATE.ANY", + "PerPkg": "1", + "PublicDescription": "Counts the number of directory updates that = were required. These result in writes to the memory controller. This can = be filtered by directory sets and directory clears.", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Updates; Directory Clear", + "Counter": "0,1,2,3", + "EventCode": "0xd", + "EventName": "UNC_H_DIRECTORY_UPDATE.CLEAR", + "PerPkg": "1", + "PublicDescription": "Counts the number of directory updates that = were required. These result in writes to the memory controller. This can = be filtered by directory sets and directory clears.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Updates; Directory Set", + "Counter": "0,1,2,3", + "EventCode": "0xd", + "EventName": "UNC_H_DIRECTORY_UPDATE.SET", + "PerPkg": "1", + "PublicDescription": "Counts the number of directory updates that = were required. These result in writes to the memory controller. This can = be filtered by directory sets and directory clears.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI= Link 0", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the HA does= not have credits to send messages to the QPI Agent. This can be filtered = by the different credit pools and the different links.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI= Link 1", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the HA does= not have credits to send messages to the QPI Agent. This can be filtered = by the different credit pools and the different links.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI= Link 0", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the HA does= not have credits to send messages to the QPI Agent. This can be filtered = by the different credit pools and the different links.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI= Link 1", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the HA does= not have credits to send messages to the QPI Agent. This can be filtered = by the different credit pools and the different links.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "Retry Events", + "Counter": "0,1,2,3", + "EventCode": "0x1e", + "EventName": "UNC_H_IMC_RETRY", + "PerPkg": "1", + "Unit": "HA" + }, + { + "BriefDescription": "HA to iMC Full Line Writes Issued; All Writes= ", + "Counter": "0,1,2,3", + "EventCode": "0x1a", + "EventName": "UNC_H_IMC_WRITES.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the total number of full line writes = issued from the HA into the memory controller. This counts for all four ch= annels. It can be filtered by full/partial and ISOCH/non-ISOCH.", + "UMask": "0xf", + "Unit": "HA" + }, + { + "BriefDescription": "HA to iMC Full Line Writes Issued; Full Line = Non-ISOCH", + "Counter": "0,1,2,3", + "EventCode": "0x1a", + "EventName": "UNC_H_IMC_WRITES.FULL", + "PerPkg": "1", + "PublicDescription": "Counts the total number of full line writes = issued from the HA into the memory controller. This counts for all four ch= annels. It can be filtered by full/partial and ISOCH/non-ISOCH.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Full= Line", + "Counter": "0,1,2,3", + "EventCode": "0x1a", + "EventName": "UNC_H_IMC_WRITES.FULL_ISOCH", + "PerPkg": "1", + "PublicDescription": "Counts the total number of full line writes = issued from the HA into the memory controller. This counts for all four ch= annels. It can be filtered by full/partial and ISOCH/non-ISOCH.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "HA to iMC Full Line Writes Issued; Partial No= n-ISOCH", + "Counter": "0,1,2,3", + "EventCode": "0x1a", + "EventName": "UNC_H_IMC_WRITES.PARTIAL", + "PerPkg": "1", + "PublicDescription": "Counts the total number of full line writes = issued from the HA into the memory controller. This counts for all four ch= annels. It can be filtered by full/partial and ISOCH/non-ISOCH.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Part= ial", + "Counter": "0,1,2,3", + "EventCode": "0x1a", + "EventName": "UNC_H_IMC_WRITES.PARTIAL_ISOCH", + "PerPkg": "1", + "PublicDescription": "Counts the total number of full line writes = issued from the HA into the memory controller. This counts for all four ch= annels. It can be filtered by full/partial and ISOCH/non-ISOCH.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "Read and Write Requests; Reads", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_H_REQUESTS.READS", + "PerPkg": "1", + "PublicDescription": "Counts the total number of read requests mad= e into the Home Agent. Reads include all read opcodes (including RFO). Wri= tes include all writes (streaming, evictions, HitM, etc).", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "Read and Write Requests; Writes", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_H_REQUESTS.WRITES", + "PerPkg": "1", + "PublicDescription": "Counts the total number of read requests mad= e into the Home Agent. Reads include all read opcodes (including RFO). Wri= tes include all writes (streaming, evictions, HitM, etc).", + "UMask": "0xc", + "Unit": "HA" + }, + { + "BriefDescription": "HA AD Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x3e", + "EventName": "UNC_H_RING_AD_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x3e", + "EventName": "UNC_H_RING_AD_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "HA AD Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x3e", + "EventName": "UNC_H_RING_AD_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "HA AD Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x3e", + "EventName": "UNC_H_RING_AD_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA AK Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x3f", + "EventName": "UNC_H_RING_AK_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x3f", + "EventName": "UNC_H_RING_AK_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "HA AK Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x3f", + "EventName": "UNC_H_RING_AK_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "HA AK Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x3f", + "EventName": "UNC_H_RING_AK_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA BL Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_H_RING_BL_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_H_RING_BL_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "HA BL Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_H_RING_BL_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "HA BL Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_H_RING_BL_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o 'regular' credits available for posting reads from the HA into the iMC. = In order to send reads into the memory controller, the HA must first acquir= e a credit for the iMC's RPQ (read pending queue). This queue is broken in= to regular credits/buffers that are used by general reads, and 'special' re= quests such as ISOCH reads. This count only tracks the regular credits Co= mmon high banwidth workloads should be able to make use of all of the regul= ar buffers, but it will be difficult (and uncommon) to make use of both the= regular and special buffers at the same time. One can filter based on the= memory controller channel. One or more channels can be tracked at a given= time.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o 'regular' credits available for posting reads from the HA into the iMC. = In order to send reads into the memory controller, the HA must first acquir= e a credit for the iMC's RPQ (read pending queue). This queue is broken in= to regular credits/buffers that are used by general reads, and 'special' re= quests such as ISOCH reads. This count only tracks the regular credits Co= mmon high banwidth workloads should be able to make use of all of the regul= ar buffers, but it will be difficult (and uncommon) to make use of both the= regular and special buffers at the same time. One can filter based on the= memory controller channel. One or more channels can be tracked at a given= time.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o 'regular' credits available for posting reads from the HA into the iMC. = In order to send reads into the memory controller, the HA must first acquir= e a credit for the iMC's RPQ (read pending queue). This queue is broken in= to regular credits/buffers that are used by general reads, and 'special' re= quests such as ISOCH reads. This count only tracks the regular credits Co= mmon high banwidth workloads should be able to make use of all of the regul= ar buffers, but it will be difficult (and uncommon) to make use of both the= regular and special buffers at the same time. One can filter based on the= memory controller channel. One or more channels can be tracked at a given= time.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o 'regular' credits available for posting reads from the HA into the iMC. = In order to send reads into the memory controller, the HA must first acquir= e a credit for the iMC's RPQ (read pending queue). This queue is broken in= to regular credits/buffers that are used by general reads, and 'special' re= quests such as ISOCH reads. This count only tracks the regular credits Co= mmon high banwidth workloads should be able to make use of all of the regul= ar buffers, but it will be difficult (and uncommon) to make use of both the= regular and special buffers at the same time. One can filter based on the= memory controller channel. One or more channels can be tracked at a given= time.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x16", + "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o 'special' credits available for posting reads from the HA into the iMC. = In order to send reads into the memory controller, the HA must first acquir= e a credit for the iMC's RPQ (read pending queue). This queue is broken in= to regular credits/buffers that are used by general reads, and 'special' re= quests such as ISOCH reads. This count only tracks the 'special' credits. = This statistic is generally not interesting for general IA workloads, but = may be of interest for understanding the characteristics of systems using I= SOCH. One can filter based on the memory controller channel. One or more = channels can be tracked at a given time.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x16", + "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o 'special' credits available for posting reads from the HA into the iMC. = In order to send reads into the memory controller, the HA must first acquir= e a credit for the iMC's RPQ (read pending queue). This queue is broken in= to regular credits/buffers that are used by general reads, and 'special' re= quests such as ISOCH reads. This count only tracks the 'special' credits. = This statistic is generally not interesting for general IA workloads, but = may be of interest for understanding the characteristics of systems using I= SOCH. One can filter based on the memory controller channel. One or more = channels can be tracked at a given time.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x16", + "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o 'special' credits available for posting reads from the HA into the iMC. = In order to send reads into the memory controller, the HA must first acquir= e a credit for the iMC's RPQ (read pending queue). This queue is broken in= to regular credits/buffers that are used by general reads, and 'special' re= quests such as ISOCH reads. This count only tracks the 'special' credits. = This statistic is generally not interesting for general IA workloads, but = may be of interest for understanding the characteristics of systems using I= SOCH. One can filter based on the memory controller channel. One or more = channels can be tracked at a given time.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 3", + "Counter": "0,1,2,3", + "EventCode": "0x16", + "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o 'special' credits available for posting reads from the HA into the iMC. = In order to send reads into the memory controller, the HA must first acquir= e a credit for the iMC's RPQ (read pending queue). This queue is broken in= to regular credits/buffers that are used by general reads, and 'special' re= quests such as ISOCH reads. This count only tracks the 'special' credits. = This statistic is generally not interesting for general IA workloads, but = may be of interest for understanding the characteristics of systems using I= SOCH. One can filter based on the memory controller channel. One or more = channels can be tracked at a given time.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 0", + "Counter": "0,1,2,3", + "EventCode": "0x1b", + "EventName": "UNC_H_TAD_REQUESTS_G0.REGION0", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 0 to 7. This event is usef= ul for understanding how applications are using the memory that is spread a= cross the different memory regions. It is particularly useful for 'Monroe'= systems that use the TAD to enable individual channels to enter self-refre= sh to save power.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 1", + "Counter": "0,1,2,3", + "EventCode": "0x1b", + "EventName": "UNC_H_TAD_REQUESTS_G0.REGION1", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 0 to 7. This event is usef= ul for understanding how applications are using the memory that is spread a= cross the different memory regions. It is particularly useful for 'Monroe'= systems that use the TAD to enable individual channels to enter self-refre= sh to save power.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 2", + "Counter": "0,1,2,3", + "EventCode": "0x1b", + "EventName": "UNC_H_TAD_REQUESTS_G0.REGION2", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 0 to 7. This event is usef= ul for understanding how applications are using the memory that is spread a= cross the different memory regions. It is particularly useful for 'Monroe'= systems that use the TAD to enable individual channels to enter self-refre= sh to save power.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 3", + "Counter": "0,1,2,3", + "EventCode": "0x1b", + "EventName": "UNC_H_TAD_REQUESTS_G0.REGION3", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 0 to 7. This event is usef= ul for understanding how applications are using the memory that is spread a= cross the different memory regions. It is particularly useful for 'Monroe'= systems that use the TAD to enable individual channels to enter self-refre= sh to save power.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 4", + "Counter": "0,1,2,3", + "EventCode": "0x1b", + "EventName": "UNC_H_TAD_REQUESTS_G0.REGION4", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 0 to 7. This event is usef= ul for understanding how applications are using the memory that is spread a= cross the different memory regions. It is particularly useful for 'Monroe'= systems that use the TAD to enable individual channels to enter self-refre= sh to save power.", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 5", + "Counter": "0,1,2,3", + "EventCode": "0x1b", + "EventName": "UNC_H_TAD_REQUESTS_G0.REGION5", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 0 to 7. This event is usef= ul for understanding how applications are using the memory that is spread a= cross the different memory regions. It is particularly useful for 'Monroe'= systems that use the TAD to enable individual channels to enter self-refre= sh to save power.", + "UMask": "0x20", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 6", + "Counter": "0,1,2,3", + "EventCode": "0x1b", + "EventName": "UNC_H_TAD_REQUESTS_G0.REGION6", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 0 to 7. This event is usef= ul for understanding how applications are using the memory that is spread a= cross the different memory regions. It is particularly useful for 'Monroe'= systems that use the TAD to enable individual channels to enter self-refre= sh to save power.", + "UMask": "0x40", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 7", + "Counter": "0,1,2,3", + "EventCode": "0x1b", + "EventName": "UNC_H_TAD_REQUESTS_G0.REGION7", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 0 to 7. This event is usef= ul for understanding how applications are using the memory that is spread a= cross the different memory regions. It is particularly useful for 'Monroe'= systems that use the TAD to enable individual channels to enter self-refre= sh to save power.", + "UMask": "0x80", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Re= gion 10", + "Counter": "0,1,2,3", + "EventCode": "0x1c", + "EventName": "UNC_H_TAD_REQUESTS_G1.REGION10", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 8 to 10. This event is use= ful for understanding how applications are using the memory that is spread = across the different memory regions. It is particularly useful for 'Monroe= ' systems that use the TAD to enable individual channels to enter self-refr= esh to save power.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Re= gion 11", + "Counter": "0,1,2,3", + "EventCode": "0x1c", + "EventName": "UNC_H_TAD_REQUESTS_G1.REGION11", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 8 to 10. This event is use= ful for understanding how applications are using the memory that is spread = across the different memory regions. It is particularly useful for 'Monroe= ' systems that use the TAD to enable individual channels to enter self-refr= esh to save power.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Re= gion 8", + "Counter": "0,1,2,3", + "EventCode": "0x1c", + "EventName": "UNC_H_TAD_REQUESTS_G1.REGION8", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 8 to 10. This event is use= ful for understanding how applications are using the memory that is spread = across the different memory regions. It is particularly useful for 'Monroe= ' systems that use the TAD to enable individual channels to enter self-refr= esh to save power.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Re= gion 9", + "Counter": "0,1,2,3", + "EventCode": "0x1c", + "EventName": "UNC_H_TAD_REQUESTS_G1.REGION9", + "PerPkg": "1", + "PublicDescription": "Counts the number of HA requests to a given = TAD region. There are up to 11 TAD (target address decode) regions in each= home agent. All requests destined for the memory controller must first be= decoded to determine which TAD region they are in. This event is filtered= based on the TAD region ID, and covers regions 8 to 10. This event is use= ful for understanding how applications are using the memory that is spread = across the different memory regions. It is particularly useful for 'Monroe= ' systems that use the TAD to enable individual channels to enter self-refr= esh to save power.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Tracker Allocations; All Requests", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "UNC_H_TRACKER_INSERTS.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the lo= cal HA tracker pool. This can be used in conjunction with the occupancy ac= cumulation event in order to calculate average latency. One cannot filter = between reads and writes. HA trackers are allocated as soon as a request e= nters the HA and is released after the snoop response and data return (or p= ost in the case of a write) and the response is returned on the ring.", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "Outbound NDR Ring Transactions; Non-data Resp= onses", + "Counter": "0,1,2,3", + "EventCode": "0xf", + "EventName": "UNC_H_TxR_AD.NDR", + "PerPkg": "1", + "PublicDescription": "Counts the number of outbound transactions o= n the AD ring. This can be filtered by the NDR and SNP message classes. S= ee the filter descriptions for more details.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Outbound NDR Ring Transactions; Snoops", + "Counter": "0,1,2,3", + "EventCode": "0xf", + "EventName": "UNC_H_TxR_AD.SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of outbound transactions o= n the AD ring. This can be filtered by the NDR and SNP message classes. S= ee the filter descriptions for more details.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Full; All", + "Counter": "0,1,2,3", + "EventCode": "0x2a", + "EventName": "UNC_H_TxR_AD_CYCLES_FULL.ALL", + "PerPkg": "1", + "PublicDescription": "AD Egress Full", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Full; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x2a", + "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED0", + "PerPkg": "1", + "PublicDescription": "AD Egress Full", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Full; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x2a", + "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED1", + "PerPkg": "1", + "PublicDescription": "AD Egress Full", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Not Empty; All", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_H_TxR_AD_CYCLES_NE.ALL", + "PerPkg": "1", + "PublicDescription": "AD Egress Not Empty", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Not Empty; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED0", + "PerPkg": "1", + "PublicDescription": "AD Egress Not Empty", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Not Empty; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED1", + "PerPkg": "1", + "PublicDescription": "AD Egress Not Empty", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Allocations; All", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_H_TxR_AD_INSERTS.ALL", + "PerPkg": "1", + "PublicDescription": "AD Egress Allocations", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Allocations; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_H_TxR_AD_INSERTS.SCHED0", + "PerPkg": "1", + "PublicDescription": "AD Egress Allocations", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Allocations; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_H_TxR_AD_INSERTS.SCHED1", + "PerPkg": "1", + "PublicDescription": "AD Egress Allocations", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Occupancy; All", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "UNC_H_TxR_AD_OCCUPANCY.ALL", + "PerPkg": "1", + "PublicDescription": "AD Egress Occupancy", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Occupancy; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "UNC_H_TxR_AD_OCCUPANCY.SCHED0", + "PerPkg": "1", + "PublicDescription": "AD Egress Occupancy", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Occupancy; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "UNC_H_TxR_AD_OCCUPANCY.SCHED1", + "PerPkg": "1", + "PublicDescription": "AD Egress Occupancy", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Full; All", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_H_TxR_AK_CYCLES_FULL.ALL", + "PerPkg": "1", + "PublicDescription": "AK Egress Full", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Full; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED0", + "PerPkg": "1", + "PublicDescription": "AK Egress Full", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Full; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED1", + "PerPkg": "1", + "PublicDescription": "AK Egress Full", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Not Empty; All", + "Counter": "0,1,2,3", + "EventCode": "0x31", + "EventName": "UNC_H_TxR_AK_CYCLES_NE.ALL", + "PerPkg": "1", + "PublicDescription": "AK Egress Not Empty", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Not Empty; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x31", + "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED0", + "PerPkg": "1", + "PublicDescription": "AK Egress Not Empty", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Not Empty; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x31", + "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED1", + "PerPkg": "1", + "PublicDescription": "AK Egress Not Empty", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Allocations; All", + "Counter": "0,1,2,3", + "EventCode": "0x2f", + "EventName": "UNC_H_TxR_AK_INSERTS.ALL", + "PerPkg": "1", + "PublicDescription": "AK Egress Allocations", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Allocations; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x2f", + "EventName": "UNC_H_TxR_AK_INSERTS.SCHED0", + "PerPkg": "1", + "PublicDescription": "AK Egress Allocations", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Allocations; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x2f", + "EventName": "UNC_H_TxR_AK_INSERTS.SCHED1", + "PerPkg": "1", + "PublicDescription": "AK Egress Allocations", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Outbound NDR Ring Transactions", + "Counter": "0,1,2,3", + "EventCode": "0xe", + "EventName": "UNC_H_TxR_AK_NDR", + "PerPkg": "1", + "PublicDescription": "Counts the number of outbound NDR transactio= ns sent on the AK ring. NDR stands for 'non-data response' and is generall= y used for completions that do not include data. AK NDR is used for messag= es to the local socket.", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Occupancy; All", + "Counter": "0,1,2,3", + "EventCode": "0x30", + "EventName": "UNC_H_TxR_AK_OCCUPANCY.ALL", + "PerPkg": "1", + "PublicDescription": "AK Egress Occupancy", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Occupancy; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x30", + "EventName": "UNC_H_TxR_AK_OCCUPANCY.SCHED0", + "PerPkg": "1", + "PublicDescription": "AK Egress Occupancy", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Occupancy; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x30", + "EventName": "UNC_H_TxR_AK_OCCUPANCY.SCHED1", + "PerPkg": "1", + "PublicDescription": "AK Egress Occupancy", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to Cache", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "UNC_H_TxR_BL.DRS_CACHE", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS messages sent out o= n the BL ring. This can be filtered by the destination.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to Core", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "UNC_H_TxR_BL.DRS_CORE", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS messages sent out o= n the BL ring. This can be filtered by the destination.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to QPI", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "UNC_H_TxR_BL.DRS_QPI", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS messages sent out o= n the BL ring. This can be filtered by the destination.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Full; All", + "Counter": "0,1,2,3", + "EventCode": "0x36", + "EventName": "UNC_H_TxR_BL_CYCLES_FULL.ALL", + "PerPkg": "1", + "PublicDescription": "BL Egress Full", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Full; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x36", + "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED0", + "PerPkg": "1", + "PublicDescription": "BL Egress Full", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Full; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x36", + "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED1", + "PerPkg": "1", + "PublicDescription": "BL Egress Full", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Not Empty; All", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_H_TxR_BL_CYCLES_NE.ALL", + "PerPkg": "1", + "PublicDescription": "BL Egress Not Empty", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Not Empty; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED0", + "PerPkg": "1", + "PublicDescription": "BL Egress Not Empty", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Not Empty; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED1", + "PerPkg": "1", + "PublicDescription": "BL Egress Not Empty", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Allocations; All", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_H_TxR_BL_INSERTS.ALL", + "PerPkg": "1", + "PublicDescription": "BL Egress Allocations", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Allocations; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_H_TxR_BL_INSERTS.SCHED0", + "PerPkg": "1", + "PublicDescription": "BL Egress Allocations", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Allocations; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_H_TxR_BL_INSERTS.SCHED1", + "PerPkg": "1", + "PublicDescription": "BL Egress Allocations", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Occupancy; All", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_H_TxR_BL_OCCUPANCY.ALL", + "PerPkg": "1", + "PublicDescription": "BL Egress Occupancy", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Occupancy; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_H_TxR_BL_OCCUPANCY.SCHED0", + "PerPkg": "1", + "PublicDescription": "BL Egress Occupancy", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Occupancy; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_H_TxR_BL_OCCUPANCY.SCHED1", + "PerPkg": "1", + "PublicDescription": "BL Egress Occupancy", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Chan= nel 0", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o 'regular' credits available for posting writes from the HA into the iMC. = In order to send writes into the memory controller, the HA must first acqu= ire a credit for the iMC's WPQ (write pending queue). This queue is broken= into regular credits/buffers that are used by general writes, and 'special= ' requests such as ISOCH writes. This count only tracks the regular credit= s Common high banwidth workloads should be able to make use of all of the = regular buffers, but it will be difficult (and uncommon) to make use of bot= h the regular and special buffers at the same time. One can filter based o= n the memory controller channel. One or more channels can be tracked at a = given time.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Chan= nel 1", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o 'regular' credits available for posting writes from the HA into the iMC. = In order to send writes into the memory controller, the HA must first acqu= ire a credit for the iMC's WPQ (write pending queue). This queue is broken= into regular credits/buffers that are used by general writes, and 'special= ' requests such as ISOCH writes. This count only tracks the regular credit= s Common high banwidth workloads should be able to make use of all of the = regular buffers, but it will be difficult (and uncommon) to make use of bot= h the regular and special buffers at the same time. One can filter based o= n the memory controller channel. One or more channels can be tracked at a = given time.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Chan= nel 2", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o 'regular' credits available for posting writes from the HA into the iMC. = In order to send writes into the memory controller, the HA must first acqu= ire a credit for the iMC's WPQ (write pending queue). This queue is broken= into regular credits/buffers that are used by general writes, and 'special= ' requests such as ISOCH writes. This count only tracks the regular credit= s Common high banwidth workloads should be able to make use of all of the = regular buffers, but it will be difficult (and uncommon) to make use of bot= h the regular and special buffers at the same time. One can filter based o= n the memory controller channel. One or more channels can be tracked at a = given time.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Chan= nel 3", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o 'regular' credits available for posting writes from the HA into the iMC. = In order to send writes into the memory controller, the HA must first acqu= ire a credit for the iMC's WPQ (write pending queue). This queue is broken= into regular credits/buffers that are used by general writes, and 'special= ' requests such as ISOCH writes. This count only tracks the regular credit= s Common high banwidth workloads should be able to make use of all of the = regular buffers, but it will be difficult (and uncommon) to make use of bot= h the regular and special buffers at the same time. One can filter based o= n the memory controller channel. One or more channels can be tracked at a = given time.", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Chan= nel 0", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o 'special' credits available for posting writes from the HA into the iMC. = In order to send writes into the memory controller, the HA must first acqu= ire a credit for the iMC's WPQ (write pending queue). This queue is broken= into regular credits/buffers that are used by general writes, and 'special= ' requests such as ISOCH writes. This count only tracks the 'special' cred= its. This statistic is generally not interesting for general IA workloads,= but may be of interest for understanding the characteristics of systems us= ing ISOCH. One can filter based on the memory controller channel. One or = more channels can be tracked at a given time.", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Chan= nel 1", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o 'special' credits available for posting writes from the HA into the iMC. = In order to send writes into the memory controller, the HA must first acqu= ire a credit for the iMC's WPQ (write pending queue). This queue is broken= into regular credits/buffers that are used by general writes, and 'special= ' requests such as ISOCH writes. This count only tracks the 'special' cred= its. This statistic is generally not interesting for general IA workloads,= but may be of interest for understanding the characteristics of systems us= ing ISOCH. One can filter based on the memory controller channel. One or = more channels can be tracked at a given time.", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Chan= nel 2", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o 'special' credits available for posting writes from the HA into the iMC. = In order to send writes into the memory controller, the HA must first acqu= ire a credit for the iMC's WPQ (write pending queue). This queue is broken= into regular credits/buffers that are used by general writes, and 'special= ' requests such as ISOCH writes. This count only tracks the 'special' cred= its. This statistic is generally not interesting for general IA workloads,= but may be of interest for understanding the characteristics of systems us= ing ISOCH. One can filter based on the memory controller channel. One or = more channels can be tracked at a given time.", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Chan= nel 3", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are n= o 'special' credits available for posting writes from the HA into the iMC. = In order to send writes into the memory controller, the HA must first acqu= ire a credit for the iMC's WPQ (write pending queue). This queue is broken= into regular credits/buffers that are used by general writes, and 'special= ' requests such as ISOCH writes. This count only tracks the 'special' cred= its. This statistic is generally not interesting for general IA workloads,= but may be of interest for understanding the characteristics of systems us= ing ISOCH. One can filter based on the memory controller channel. One or = more channels can be tracked at a given time.", + "UMask": "0x8", "Unit": "HA" } ] diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-interconnect.js= on b/tools/perf/pmu-events/arch/x86/jaketown/uncore-interconnect.json index 1b53c0e609e3..750870fd1cb1 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-interconnect.json @@ -1,48 +1,850 @@ [ { - "BriefDescription": "QPI clock ticks. Used to get percentages of Q= PI cycles events", + "BriefDescription": "Number of qfclks", "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_Q_CLOCKTICKS", "PerPkg": "1", + "PublicDescription": "Counts the number of clocks in the QPI LL. = This clock runs at 1/8th the 'GT/s' speed of the QPI link. For example, a = 8GT/s link will have qfclk or 1GHz. JKT does not support dynamic link spee= ds, so this frequency is fixed.", "Unit": "QPI LL" }, { - "BriefDescription": "Cycles where receiving QPI link is in half-wi= dth mode", + "BriefDescription": "Count of CTO Events", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_Q_CTO_COUNT", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of CTO (cluster trigger ou= ts) events that were asserted across the two slots. If both slots trigger = in a given cycle, the event will increment by 2. You can use edge detect t= o count the number of cases when both events triggered.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egres= s Credits", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS packets that we att= empted to do direct2core on. There are 4 mutually exlusive filters. Filte= r [0] can be used to get successful spawns, while [1:3] provide the differe= nt failure cases. Note that this does not count packets that are not candi= dates for Direct2Core. The only candidates for Direct2Core are DRS packets= destined for Cbos.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egres= s and RBT", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS packets that we att= empted to do direct2core on. There are 4 mutually exlusive filters. Filte= r [0] can be used to get successful spawns, while [1:3] provide the differe= nt failure cases. Note that this does not count packets that are not candi= dates for Direct2Core. The only candidates for Direct2Core are DRS packets= destined for Cbos.", + "UMask": "0x8", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT N= ot Set", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS packets that we att= empted to do direct2core on. There are 4 mutually exlusive filters. Filte= r [0] can be used to get successful spawns, while [1:3] provide the differe= nt failure cases. Note that this does not count packets that are not candi= dates for Direct2Core. The only candidates for Direct2Core are DRS packets= destined for Cbos.", + "UMask": "0x4", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Success", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.SUCCESS", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS packets that we att= empted to do direct2core on. There are 4 mutually exlusive filters. Filte= r [0] can be used to get successful spawns, while [1:3] provide the differe= nt failure cases. Note that this does not count packets that are not candi= dates for Direct2Core. The only candidates for Direct2Core are DRS packets= destined for Cbos.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Cycles in L1", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_Q_L1_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of QPI qfclk cycles spent in L1 power= mode. L1 is a mode that totally shuts down a QPI link. Use edge detect t= o count the number of instances when the QPI link entered L1. Link power s= tates are per link and per direction, so for example the Tx direction could= be in one state while Rx was in another. Because L1 totally shuts down the= link, it takes a good amount of time to exit this mode.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Cycles in L0p", "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_Q_RxL0P_POWER_CYCLES", - "MetricExpr": "(UNC_Q_RxL0P_POWER_CYCLES / UNC_Q_CLOCKTICKS) * 100= .", - "MetricName": "rxl0p_power_cycles %", "PerPkg": "1", + "PublicDescription": "Number of QPI qfclk cycles spent in L0p powe= r mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing ou= r bandwidth in order to save power. It increases snoop and data transfer l= atencies and decreases overall bandwidth. This mode can be very useful in = NUMA optimized workloads that largely only utilize QPI for snoops and their= responses. Use edge detect to count the number of instances when the QPI = link entered L0p. Link power states are per link and per direction, so for= example the Tx direction could be in one state while Rx was in another.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Cycles in L0", + "Counter": "0,1,2,3", + "EventCode": "0xf", + "EventName": "UNC_Q_RxL0_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of QPI qfclk cycles spent in L0 power= mode in the Link Layer. L0 is the default mode which provides the highest= performance with the most power. Use edge detect to count the number of i= nstances that the link entered L0. Link power states are per link and per = direction, so for example the Tx direction could be in one state while Rx w= as in another. The phy layer sometimes leaves L0 for training, which will= not be captured by this event.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Bypassed", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_Q_RxL_BYPASSED", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an incoming = flit was able to bypass the flit buffer and pass directly across the BGF an= d into the Egress. This is a latency optimization, and should generally be= the common case. If this value is less than the number of flits transfere= d, it implies that there was queueing getting onto the ring, and thus the t= ransactions saw higher latency.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "CRC Errors Detected; LinkInit", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_CRC_ERRORS.LINK_INIT", + "PerPkg": "1", + "PublicDescription": "Number of CRC errors detected in the QPI Age= nt. Each QPI flit incorporates 8 bits of CRC for error detection. This co= unts the number of flits where the CRC was able to detect an error. After = an error has been detected, the QPI agent will send a request to the transm= itting socket to resend the flit (as well as any flits that came after it).= ", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "CRC Errors Detected; Normal Operations", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP", + "PerPkg": "1", + "PublicDescription": "Number of CRC errors detected in the QPI Age= nt. Each QPI flit incorporates 8 bits of CRC for error detection. This co= unts the number of flits where the CRC was able to detect an error. After = an error has been detected, the QPI agent will send a request to the transm= itting socket to resend the flit (as well as any flits that came after it).= ", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VN0 Credit Consumed; DRS", + "Counter": "0,1,2,3", + "EventCode": "0x1e", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN0 c= redit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). Thi= s includes packets that went through the RxQ and those that were bypasssed.= ", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VN0 Credit Consumed; HOM", + "Counter": "0,1,2,3", + "EventCode": "0x1e", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN0 c= redit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). Thi= s includes packets that went through the RxQ and those that were bypasssed.= ", + "UMask": "0x8", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VN0 Credit Consumed; NCB", + "Counter": "0,1,2,3", + "EventCode": "0x1e", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN0 c= redit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). Thi= s includes packets that went through the RxQ and those that were bypasssed.= ", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VN0 Credit Consumed; NCS", + "Counter": "0,1,2,3", + "EventCode": "0x1e", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN0 c= redit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). Thi= s includes packets that went through the RxQ and those that were bypasssed.= ", + "UMask": "0x4", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VN0 Credit Consumed; NDR", + "Counter": "0,1,2,3", + "EventCode": "0x1e", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN0 c= redit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). Thi= s includes packets that went through the RxQ and those that were bypasssed.= ", + "UMask": "0x20", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VN0 Credit Consumed; SNP", + "Counter": "0,1,2,3", + "EventCode": "0x1e", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN0 c= redit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). Thi= s includes packets that went through the RxQ and those that were bypasssed.= ", + "UMask": "0x10", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VNA Credit Consumed", + "Counter": "0,1,2,3", + "EventCode": "0x1d", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VNA", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VNA c= redit was consumed (i.e. message uses a VNA credit for the Rx Buffer). Thi= s includes packets that went through the RxQ and those that were bypasssed.= ", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Cycles Not Empty", + "Counter": "0,1,2,3", + "EventCode": "0xa", + "EventName": "UNC_Q_RxL_CYCLES_NE", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ= was not empty. Generally, when data is transmitted across QPI, it will by= pass the RxQ and pass directly to the ring interface. If things back up ge= tting transmitted onto the ring, however, it may need to allocate into this= buffer, thus increasing the latency. This event can be used in conjunctio= n with the Flit Buffer Occupancy Accumulator event to calculate the average= occupancy.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 0; Data Tx Flits", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_Q_RxL_FLITS_G0.DATA", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the= QPI Link. It includes filters for Idle, protocol, and Data Flits. Each '= flit' is made up of 80 bits of information (in addition to some ECC data). = In full-width (L0) mode, flits are made up of four 'fits', each of which c= ontains 20 bits of data (along with some additional ECC data). In half-wi= dth (L0p) mode, the fits are only 10 bits, and therefore it takes twice as = many fits to transmit a flit. When one talks about QPI 'speed' (for exampl= e, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the = system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can = calculate the bandwidth of the link by taking: flits*80b/time. Note that t= his is not the same as 'data' bandwidth. For example, when we are transfer= ing a 64B cacheline across QPI, we will break it into 9 flits -- 1 with hea= der information and 8 with 64 bits of actual 'data' and an additional 16 bi= ts of other information. To calculate 'data' bandwidth, one should therefo= re do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 0; Idle and Null Flits= ", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_Q_RxL_FLITS_G0.IDLE", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the= QPI Link. It includes filters for Idle, protocol, and Data Flits. Each '= flit' is made up of 80 bits of information (in addition to some ECC data). = In full-width (L0) mode, flits are made up of four 'fits', each of which c= ontains 20 bits of data (along with some additional ECC data). In half-wi= dth (L0p) mode, the fits are only 10 bits, and therefore it takes twice as = many fits to transmit a flit. When one talks about QPI 'speed' (for exampl= e, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the = system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can = calculate the bandwidth of the link by taking: flits*80b/time. Note that t= his is not the same as 'data' bandwidth. For example, when we are transfer= ing a 64B cacheline across QPI, we will break it into 9 flits -- 1 with hea= der information and 8 with 64 bits of actual 'data' and an additional 16 bi= ts of other information. To calculate 'data' bandwidth, one should therefo= re do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 0; Non-Data protocol T= x Flits", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_Q_RxL_FLITS_G0.NON_DATA", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the= QPI Link. It includes filters for Idle, protocol, and Data Flits. Each '= flit' is made up of 80 bits of information (in addition to some ECC data). = In full-width (L0) mode, flits are made up of four 'fits', each of which c= ontains 20 bits of data (along with some additional ECC data). In half-wi= dth (L0p) mode, the fits are only 10 bits, and therefore it takes twice as = many fits to transmit a flit. When one talks about QPI 'speed' (for exampl= e, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the = system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can = calculate the bandwidth of the link by taking: flits*80b/time. Note that t= his is not the same as 'data' bandwidth. For example, when we are transfer= ing a 64B cacheline across QPI, we will break it into 9 flits -- 1 with hea= der information and 8 with 64 bits of actual 'data' and an additional 16 bi= ts of other information. To calculate 'data' bandwidth, one should therefo= re do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.", + "UMask": "0x4", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 1; DRS Flits (both Hea= der and Data)", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.DRS", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three 'groups' that allow us to track flits. It= includes filters for SNP, HOM, and DRS message classes. Each 'flit' is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four 'fits', each of which contains 20 = bits of data (along with some additional ECC data). In half-width (L0p) m= ode, the fits are only 10 bits, and therefore it takes twice as many fits t= o transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s= ), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will= transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate t= he bandwidth of the link by taking: flits*80b/time. Note that this is not = the same as 'data' bandwidth. For example, when we are transfering a 64B c= acheline across QPI, we will break it into 9 flits -- 1 with header informa= tion and 8 with 64 bits of actual 'data' and an additional 16 bits of other= information. To calculate 'data' bandwidth, one should therefore do: data= flits * 8B / time.", + "UMask": "0x18", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 1; DRS Data Flits", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three 'groups' that allow us to track flits. It= includes filters for SNP, HOM, and DRS message classes. Each 'flit' is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four 'fits', each of which contains 20 = bits of data (along with some additional ECC data). In half-width (L0p) m= ode, the fits are only 10 bits, and therefore it takes twice as many fits t= o transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s= ), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will= transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate t= he bandwidth of the link by taking: flits*80b/time. Note that this is not = the same as 'data' bandwidth. For example, when we are transfering a 64B c= acheline across QPI, we will break it into 9 flits -- 1 with header informa= tion and 8 with 64 bits of actual 'data' and an additional 16 bits of other= information. To calculate 'data' bandwidth, one should therefore do: data= flits * 8B / time.", + "UMask": "0x8", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 1; DRS Header Flits", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three 'groups' that allow us to track flits. It= includes filters for SNP, HOM, and DRS message classes. Each 'flit' is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four 'fits', each of which contains 20 = bits of data (along with some additional ECC data). In half-width (L0p) m= ode, the fits are only 10 bits, and therefore it takes twice as many fits t= o transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s= ), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will= transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate t= he bandwidth of the link by taking: flits*80b/time. Note that this is not = the same as 'data' bandwidth. For example, when we are transfering a 64B c= acheline across QPI, we will break it into 9 flits -- 1 with header informa= tion and 8 with 64 bits of actual 'data' and an additional 16 bits of other= information. To calculate 'data' bandwidth, one should therefore do: data= flits * 8B / time.", + "UMask": "0x10", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 1; HOM Flits", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.HOM", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three 'groups' that allow us to track flits. It= includes filters for SNP, HOM, and DRS message classes. Each 'flit' is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four 'fits', each of which contains 20 = bits of data (along with some additional ECC data). In half-width (L0p) m= ode, the fits are only 10 bits, and therefore it takes twice as many fits t= o transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s= ), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will= transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate t= he bandwidth of the link by taking: flits*80b/time. Note that this is not = the same as 'data' bandwidth. For example, when we are transfering a 64B c= acheline across QPI, we will break it into 9 flits -- 1 with header informa= tion and 8 with 64 bits of actual 'data' and an additional 16 bits of other= information. To calculate 'data' bandwidth, one should therefore do: data= flits * 8B / time.", + "UMask": "0x6", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 1; HOM Non-Request Fli= ts", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three 'groups' that allow us to track flits. It= includes filters for SNP, HOM, and DRS message classes. Each 'flit' is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four 'fits', each of which contains 20 = bits of data (along with some additional ECC data). In half-width (L0p) m= ode, the fits are only 10 bits, and therefore it takes twice as many fits t= o transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s= ), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will= transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate t= he bandwidth of the link by taking: flits*80b/time. Note that this is not = the same as 'data' bandwidth. For example, when we are transfering a 64B c= acheline across QPI, we will break it into 9 flits -- 1 with header informa= tion and 8 with 64 bits of actual 'data' and an additional 16 bits of other= information. To calculate 'data' bandwidth, one should therefore do: data= flits * 8B / time.", + "UMask": "0x4", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 1; HOM Request Flits", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three 'groups' that allow us to track flits. It= includes filters for SNP, HOM, and DRS message classes. Each 'flit' is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four 'fits', each of which contains 20 = bits of data (along with some additional ECC data). In half-width (L0p) m= ode, the fits are only 10 bits, and therefore it takes twice as many fits t= o transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s= ), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will= transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate t= he bandwidth of the link by taking: flits*80b/time. Note that this is not = the same as 'data' bandwidth. For example, when we are transfering a 64B c= acheline across QPI, we will break it into 9 flits -- 1 with header informa= tion and 8 with 64 bits of actual 'data' and an additional 16 bits of other= information. To calculate 'data' bandwidth, one should therefore do: data= flits * 8B / time.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 1; SNP Flits", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.SNP", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three 'groups' that allow us to track flits. It= includes filters for SNP, HOM, and DRS message classes. Each 'flit' is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four 'fits', each of which contains 20 = bits of data (along with some additional ECC data). In half-width (L0p) m= ode, the fits are only 10 bits, and therefore it takes twice as many fits t= o transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s= ), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will= transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate t= he bandwidth of the link by taking: flits*80b/time. Note that this is not = the same as 'data' bandwidth. For example, when we are transfering a 64B c= acheline across QPI, we will break it into 9 flits -- 1 with header informa= tion and 8 with 64 bits of actual 'data' and an additional 16 bits of other= information. To calculate 'data' bandwidth, one should therefore do: data= flits * 8B / time.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 2; Non-Coherent Rx Fli= ts", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_FLITS_G2.NCB", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three 'groups' that allow us to track flits. It= includes filters for NDR, NCB, and NCS message classes. Each 'flit' is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four 'fits', each of which contains 20 = bits of data (along with some additional ECC data). In half-width (L0p) m= ode, the fits are only 10 bits, and therefore it takes twice as many fits t= o transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s= ), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will= transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate t= he bandwidth of the link by taking: flits*80b/time. Note that this is not = the same as 'data' bandwidth. For example, when we are transfering a 64B c= acheline across QPI, we will break it into 9 flits -- 1 with header informa= tion and 8 with 64 bits of actual 'data' and an additional 16 bits of other= information. To calculate 'data' bandwidth, one should therefore do: data= flits * 8B / time.", + "UMask": "0xc", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 2; Non-Coherent data R= x Flits", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_FLITS_G2.NCB_DATA", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three 'groups' that allow us to track flits. It= includes filters for NDR, NCB, and NCS message classes. Each 'flit' is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four 'fits', each of which contains 20 = bits of data (along with some additional ECC data). In half-width (L0p) m= ode, the fits are only 10 bits, and therefore it takes twice as many fits t= o transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s= ), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will= transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate t= he bandwidth of the link by taking: flits*80b/time. Note that this is not = the same as 'data' bandwidth. For example, when we are transfering a 64B c= acheline across QPI, we will break it into 9 flits -- 1 with header informa= tion and 8 with 64 bits of actual 'data' and an additional 16 bits of other= information. To calculate 'data' bandwidth, one should therefore do: data= flits * 8B / time.", + "UMask": "0x4", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 2; Non-Coherent non-da= ta Rx Flits", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_FLITS_G2.NCB_NONDATA", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three 'groups' that allow us to track flits. It= includes filters for NDR, NCB, and NCS message classes. Each 'flit' is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four 'fits', each of which contains 20 = bits of data (along with some additional ECC data). In half-width (L0p) m= ode, the fits are only 10 bits, and therefore it takes twice as many fits t= o transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s= ), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will= transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate t= he bandwidth of the link by taking: flits*80b/time. Note that this is not = the same as 'data' bandwidth. For example, when we are transfering a 64B c= acheline across QPI, we will break it into 9 flits -- 1 with header informa= tion and 8 with 64 bits of actual 'data' and an additional 16 bits of other= information. To calculate 'data' bandwidth, one should therefore do: data= flits * 8B / time.", + "UMask": "0x8", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 2; Non-Coherent standa= rd Rx Flits", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_FLITS_G2.NCS", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three 'groups' that allow us to track flits. It= includes filters for NDR, NCB, and NCS message classes. Each 'flit' is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four 'fits', each of which contains 20 = bits of data (along with some additional ECC data). In half-width (L0p) m= ode, the fits are only 10 bits, and therefore it takes twice as many fits t= o transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s= ), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will= transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate t= he bandwidth of the link by taking: flits*80b/time. Note that this is not = the same as 'data' bandwidth. For example, when we are transfering a 64B c= acheline across QPI, we will break it into 9 flits -- 1 with header informa= tion and 8 with 64 bits of actual 'data' and an additional 16 bits of other= information. To calculate 'data' bandwidth, one should therefore do: data= flits * 8B / time.", + "UMask": "0x10", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 2; Non-Data Response R= x Flits - AD", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three 'groups' that allow us to track flits. It= includes filters for NDR, NCB, and NCS message classes. Each 'flit' is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four 'fits', each of which contains 20 = bits of data (along with some additional ECC data). In half-width (L0p) m= ode, the fits are only 10 bits, and therefore it takes twice as many fits t= o transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s= ), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will= transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate t= he bandwidth of the link by taking: flits*80b/time. Note that this is not = the same as 'data' bandwidth. For example, when we are transfering a 64B c= acheline across QPI, we will break it into 9 flits -- 1 with header informa= tion and 8 with 64 bits of actual 'data' and an additional 16 bits of other= information. To calculate 'data' bandwidth, one should therefore do: data= flits * 8B / time.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 2; Non-Data Response R= x Flits - AK", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three 'groups' that allow us to track flits. It= includes filters for NDR, NCB, and NCS message classes. Each 'flit' is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four 'fits', each of which contains 20 = bits of data (along with some additional ECC data). In half-width (L0p) m= ode, the fits are only 10 bits, and therefore it takes twice as many fits t= o transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s= ), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will= transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate t= he bandwidth of the link by taking: flits*80b/time. Note that this is not = the same as 'data' bandwidth. For example, when we are transfering a 64B c= acheline across QPI, we will break it into 9 flits -- 1 with header informa= tion and 8 with 64 bits of actual 'data' and an additional 16 bits of other= information. To calculate 'data' bandwidth, one should therefore do: data= flits * 8B / time.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_Q_RxL_INSERTS", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit B= uffer. Generally, when data is transmitted across QPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - DRS", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_Q_RxL_INSERTS_DRS", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit B= uffer. Generally, when data is transmitted across QPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime. This monitors only DRS flits.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - HOM", + "Counter": "0,1,2,3", + "EventCode": "0xc", + "EventName": "UNC_Q_RxL_INSERTS_HOM", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit B= uffer. Generally, when data is transmitted across QPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime. This monitors only HOM flits.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - NCB", + "Counter": "0,1,2,3", + "EventCode": "0xa", + "EventName": "UNC_Q_RxL_INSERTS_NCB", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit B= uffer. Generally, when data is transmitted across QPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime. This monitors only NCB flits.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - NCS", + "Counter": "0,1,2,3", + "EventCode": "0xb", + "EventName": "UNC_Q_RxL_INSERTS_NCS", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit B= uffer. Generally, when data is transmitted across QPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime. This monitors only NCS flits.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - NDR", + "Counter": "0,1,2,3", + "EventCode": "0xe", + "EventName": "UNC_Q_RxL_INSERTS_NDR", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit B= uffer. Generally, when data is transmitted across QPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime. This monitors only NDR flits.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - SNP", + "Counter": "0,1,2,3", + "EventCode": "0xd", + "EventName": "UNC_Q_RxL_INSERTS_SNP", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit B= uffer. Generally, when data is transmitted across QPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime. This monitors only SNP flits.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - All Packets", + "Counter": "0,1,2,3", + "EventCode": "0xb", + "EventName": "UNC_Q_RxL_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QP= I RxQ in each cycle. Generally, when data is transmitted across QPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - DRS", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_Q_RxL_OCCUPANCY_DRS", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QP= I RxQ in each cycle. Generally, when data is transmitted across QPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime. This= monitors DRS flits only.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - HOM", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_Q_RxL_OCCUPANCY_HOM", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QP= I RxQ in each cycle. Generally, when data is transmitted across QPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime. This= monitors HOM flits only.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - NCB", + "Counter": "0,1,2,3", + "EventCode": "0x16", + "EventName": "UNC_Q_RxL_OCCUPANCY_NCB", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QP= I RxQ in each cycle. Generally, when data is transmitted across QPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime. This= monitors NCB flits only.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - NCS", + "Counter": "0,1,2,3", + "EventCode": "0x17", + "EventName": "UNC_Q_RxL_OCCUPANCY_NCS", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QP= I RxQ in each cycle. Generally, when data is transmitted across QPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime. This= monitors NCS flits only.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - NDR", + "Counter": "0,1,2,3", + "EventCode": "0x1a", + "EventName": "UNC_Q_RxL_OCCUPANCY_NDR", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QP= I RxQ in each cycle. Generally, when data is transmitted across QPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime. This= monitors NDR flits only.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - SNP", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_Q_RxL_OCCUPANCY_SNP", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QP= I RxQ in each cycle. Generally, when data is transmitted across QPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime. This= monitors SNP flits only.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI; BGF Stall - HOM", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS.BGF_DRS", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI; BGF Stall - DRS", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS.BGF_HOM", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI.", + "UMask": "0x8", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI; BGF Stall - SNP", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS.BGF_NCB", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI; BGF Stall - NDR", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS.BGF_NCS", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI.", + "UMask": "0x4", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI; BGF Stall - NCS", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS.BGF_NDR", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI.", + "UMask": "0x20", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI; BGF Stall - NCB", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS.BGF_SNP", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI.", + "UMask": "0x10", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI; Egress Credits", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS.EGRESS_CREDITS", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI.", + "UMask": "0x40", "Unit": "QPI LL" }, { - "BriefDescription": "Cycles where transmitting QPI link is in half= -width mode", + "BriefDescription": "Stalls Sending to R3QPI; GV", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS.GV", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI.", + "UMask": "0x80", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Cycles in L0p", "Counter": "0,1,2,3", "EventCode": "0xd", "EventName": "UNC_Q_TxL0P_POWER_CYCLES", - "MetricExpr": "(UNC_Q_TxL0P_POWER_CYCLES / UNC_Q_CLOCKTICKS) * 100= .", - "MetricName": "txl0p_power_cycles %", "PerPkg": "1", + "PublicDescription": "Number of QPI qfclk cycles spent in L0p powe= r mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing ou= r bandwidth in order to save power. It increases snoop and data transfer l= atencies and decreases overall bandwidth. This mode can be very useful in = NUMA optimized workloads that largely only utilize QPI for snoops and their= responses. Use edge detect to count the number of instances when the QPI = link entered L0p. Link power states are per link and per direction, so for= example the Tx direction could be in one state while Rx was in another.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Cycles in L0", + "Counter": "0,1,2,3", + "EventCode": "0xc", + "EventName": "UNC_Q_TxL0_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of QPI qfclk cycles spent in L0 power= mode in the Link Layer. L0 is the default mode which provides the highest= performance with the most power. Use edge detect to count the number of i= nstances that the link entered L0. Link power states are per link and per = direction, so for example the Tx direction could be in one state while Rx w= as in another. The phy layer sometimes leaves L0 for training, which will= not be captured by this event.", "Unit": "QPI LL" }, { - "BriefDescription": "Number of data flits transmitted ", + "BriefDescription": "Tx Flit Buffer Bypassed", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_Q_TxL_BYPASSED", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an incoming = flit was able to bypass the Tx flit buffer and pass directly out the QPI Li= nk. Generally, when data is transmitted across QPI, it will bypass the TxQ = and pass directly to the link. However, the TxQ will be used with L0p and = when LLR occurs, increasing latency to transfer out to the link.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is al= most full", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL", + "PerPkg": "1", + "PublicDescription": "Number of cycles when the Tx side ran out of= Link Layer Retry credits, causing the Tx to stall.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is fu= ll", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.FULL", + "PerPkg": "1", + "PublicDescription": "Number of cycles when the Tx side ran out of= Link Layer Retry credits, causing the Tx to stall.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Tx Flit Buffer Cycles not Empty", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "UNC_Q_TxL_CYCLES_NE", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the TxQ is = not empty. Generally, when data is transmitted across QPI, it will bypass t= he TxQ and pass directly to the link. However, the TxQ will be used with L= 0p and when LLR occurs, increasing latency to transfer out to the link.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 0; Data Tx Flits", "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G0.DATA", "PerPkg": "1", - "ScaleUnit": "8Bytes", + "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. It includes filters for Idle, protocol, and Data Flits. E= ach 'flit' is made up of 80 bits of information (in addition to some ECC da= ta). In full-width (L0) mode, flits are made up of four 'fits', each of wh= ich contains 20 bits of data (along with some additional ECC data). In ha= lf-width (L0p) mode, the fits are only 10 bits, and therefore it takes twic= e as many fits to transmit a flit. When one talks about QPI 'speed' (for e= xample, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0,= the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One= can calculate the bandwidth of the link by taking: flits*80b/time. Note t= hat this is not the same as 'data' bandwidth. For example, when we are tra= nsfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 wit= h header information and 8 with 64 bits of actual 'data' and an additional = 16 bits of other information. To calculate 'data' bandwidth, one should th= erefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.", "UMask": "0x2", "Unit": "QPI LL" }, { - "BriefDescription": "Number of non data (control) flits transmitte= d ", + "BriefDescription": "Flits Transferred - Group 0; Idle and Null Fl= its", + "Counter": "0,1,2,3", + "EventName": "UNC_Q_TxL_FLITS_G0.IDLE", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. It includes filters for Idle, protocol, and Data Flits. E= ach 'flit' is made up of 80 bits of information (in addition to some ECC da= ta). In full-width (L0) mode, flits are made up of four 'fits', each of wh= ich contains 20 bits of data (along with some additional ECC data). In ha= lf-width (L0p) mode, the fits are only 10 bits, and therefore it takes twic= e as many fits to transmit a flit. When one talks about QPI 'speed' (for e= xample, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0,= the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One= can calculate the bandwidth of the link by taking: flits*80b/time. Note t= hat this is not the same as 'data' bandwidth. For example, when we are tra= nsfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 wit= h header information and 8 with 64 bits of actual 'data' and an additional = 16 bits of other information. To calculate 'data' bandwidth, one should th= erefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 0; Non-Data protoco= l Tx Flits", "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA", "PerPkg": "1", - "ScaleUnit": "8Bytes", + "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. It includes filters for Idle, protocol, and Data Flits. E= ach 'flit' is made up of 80 bits of information (in addition to some ECC da= ta). In full-width (L0) mode, flits are made up of four 'fits', each of wh= ich contains 20 bits of data (along with some additional ECC data). In ha= lf-width (L0p) mode, the fits are only 10 bits, and therefore it takes twic= e as many fits to transmit a flit. When one talks about QPI 'speed' (for e= xample, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0,= the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One= can calculate the bandwidth of the link by taking: flits*80b/time. Note t= hat this is not the same as 'data' bandwidth. For example, when we are tra= nsfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 wit= h header information and 8 with 64 bits of actual 'data' and an additional = 16 bits of other information. To calculate 'data' bandwidth, one should th= erefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.", + "UMask": "0x4", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 1; DRS Flits (both = Header and Data)", + "Counter": "0,1,2,3", + "EventName": "UNC_Q_TxL_FLITS_G1.DRS", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three 'groups' that allow us to track flits.= It includes filters for SNP, HOM, and DRS message classes. Each 'flit' i= s made up of 80 bits of information (in addition to some ECC data). In ful= l-width (L0) mode, flits are made up of four 'fits', each of which contains= 20 bits of data (along with some additional ECC data). In half-width (L0= p) mode, the fits are only 10 bits, and therefore it takes twice as many fi= ts to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 = GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system = will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calcula= te the bandwidth of the link by taking: flits*80b/time. Note that this is = not the same as 'data' bandwidth. For example, when we are transfering a 6= 4B cacheline across QPI, we will break it into 9 flits -- 1 with header inf= ormation and 8 with 64 bits of actual 'data' and an additional 16 bits of o= ther information. To calculate 'data' bandwidth, one should therefore do: = data flits * 8B / time.", + "UMask": "0x18", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 1; DRS Data Flits", + "Counter": "0,1,2,3", + "EventName": "UNC_Q_TxL_FLITS_G1.DRS_DATA", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three 'groups' that allow us to track flits.= It includes filters for SNP, HOM, and DRS message classes. Each 'flit' i= s made up of 80 bits of information (in addition to some ECC data). In ful= l-width (L0) mode, flits are made up of four 'fits', each of which contains= 20 bits of data (along with some additional ECC data). In half-width (L0= p) mode, the fits are only 10 bits, and therefore it takes twice as many fi= ts to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 = GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system = will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calcula= te the bandwidth of the link by taking: flits*80b/time. Note that this is = not the same as 'data' bandwidth. For example, when we are transfering a 6= 4B cacheline across QPI, we will break it into 9 flits -- 1 with header inf= ormation and 8 with 64 bits of actual 'data' and an additional 16 bits of o= ther information. To calculate 'data' bandwidth, one should therefore do: = data flits * 8B / time.", + "UMask": "0x8", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 1; DRS Header Flits= ", + "Counter": "0,1,2,3", + "EventName": "UNC_Q_TxL_FLITS_G1.DRS_NONDATA", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three 'groups' that allow us to track flits.= It includes filters for SNP, HOM, and DRS message classes. Each 'flit' i= s made up of 80 bits of information (in addition to some ECC data). In ful= l-width (L0) mode, flits are made up of four 'fits', each of which contains= 20 bits of data (along with some additional ECC data). In half-width (L0= p) mode, the fits are only 10 bits, and therefore it takes twice as many fi= ts to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 = GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system = will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calcula= te the bandwidth of the link by taking: flits*80b/time. Note that this is = not the same as 'data' bandwidth. For example, when we are transfering a 6= 4B cacheline across QPI, we will break it into 9 flits -- 1 with header inf= ormation and 8 with 64 bits of actual 'data' and an additional 16 bits of o= ther information. To calculate 'data' bandwidth, one should therefore do: = data flits * 8B / time.", + "UMask": "0x10", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 1; HOM Flits", + "Counter": "0,1,2,3", + "EventName": "UNC_Q_TxL_FLITS_G1.HOM", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three 'groups' that allow us to track flits.= It includes filters for SNP, HOM, and DRS message classes. Each 'flit' i= s made up of 80 bits of information (in addition to some ECC data). In ful= l-width (L0) mode, flits are made up of four 'fits', each of which contains= 20 bits of data (along with some additional ECC data). In half-width (L0= p) mode, the fits are only 10 bits, and therefore it takes twice as many fi= ts to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 = GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system = will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calcula= te the bandwidth of the link by taking: flits*80b/time. Note that this is = not the same as 'data' bandwidth. For example, when we are transfering a 6= 4B cacheline across QPI, we will break it into 9 flits -- 1 with header inf= ormation and 8 with 64 bits of actual 'data' and an additional 16 bits of o= ther information. To calculate 'data' bandwidth, one should therefore do: = data flits * 8B / time.", + "UMask": "0x6", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 1; HOM Non-Request = Flits", + "Counter": "0,1,2,3", + "EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three 'groups' that allow us to track flits.= It includes filters for SNP, HOM, and DRS message classes. Each 'flit' i= s made up of 80 bits of information (in addition to some ECC data). In ful= l-width (L0) mode, flits are made up of four 'fits', each of which contains= 20 bits of data (along with some additional ECC data). In half-width (L0= p) mode, the fits are only 10 bits, and therefore it takes twice as many fi= ts to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 = GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system = will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calcula= te the bandwidth of the link by taking: flits*80b/time. Note that this is = not the same as 'data' bandwidth. For example, when we are transfering a 6= 4B cacheline across QPI, we will break it into 9 flits -- 1 with header inf= ormation and 8 with 64 bits of actual 'data' and an additional 16 bits of o= ther information. To calculate 'data' bandwidth, one should therefore do: = data flits * 8B / time.", "UMask": "0x4", "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 1; HOM Request Flit= s", + "Counter": "0,1,2,3", + "EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three 'groups' that allow us to track flits.= It includes filters for SNP, HOM, and DRS message classes. Each 'flit' i= s made up of 80 bits of information (in addition to some ECC data). In ful= l-width (L0) mode, flits are made up of four 'fits', each of which contains= 20 bits of data (along with some additional ECC data). In half-width (L0= p) mode, the fits are only 10 bits, and therefore it takes twice as many fi= ts to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 = GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system = will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calcula= te the bandwidth of the link by taking: flits*80b/time. Note that this is = not the same as 'data' bandwidth. For example, when we are transfering a 6= 4B cacheline across QPI, we will break it into 9 flits -- 1 with header inf= ormation and 8 with 64 bits of actual 'data' and an additional 16 bits of o= ther information. To calculate 'data' bandwidth, one should therefore do: = data flits * 8B / time.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 1; SNP Flits", + "Counter": "0,1,2,3", + "EventName": "UNC_Q_TxL_FLITS_G1.SNP", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three 'groups' that allow us to track flits.= It includes filters for SNP, HOM, and DRS message classes. Each 'flit' i= s made up of 80 bits of information (in addition to some ECC data). In ful= l-width (L0) mode, flits are made up of four 'fits', each of which contains= 20 bits of data (along with some additional ECC data). In half-width (L0= p) mode, the fits are only 10 bits, and therefore it takes twice as many fi= ts to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 = GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system = will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calcula= te the bandwidth of the link by taking: flits*80b/time. Note that this is = not the same as 'data' bandwidth. For example, when we are transfering a 6= 4B cacheline across QPI, we will break it into 9 flits -- 1 with header inf= ormation and 8 with 64 bits of actual 'data' and an additional 16 bits of o= ther information. To calculate 'data' bandwidth, one should therefore do: = data flits * 8B / time.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 2; Non-Coherent Byp= ass Tx Flits", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_Q_TxL_FLITS_G2.NCB", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three 'groups' that allow us to track flits.= It includes filters for NDR, NCB, and NCS message classes. Each 'flit' i= s made up of 80 bits of information (in addition to some ECC data). In ful= l-width (L0) mode, flits are made up of four 'fits', each of which contains= 20 bits of data (along with some additional ECC data). In half-width (L0= p) mode, the fits are only 10 bits, and therefore it takes twice as many fi= ts to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 = GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system = will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calcula= te the bandwidth of the link by taking: flits*80b/time. Note that this is = not the same as 'data' bandwidth. For example, when we are transfering a 6= 4B cacheline across QPI, we will break it into 9 flits -- 1 with header inf= ormation and 8 with 64 bits of actual 'data' and an additional 16 bits of o= ther information. To calculate 'data' bandwidth, one should therefore do: = data flits * 8B / time.", + "UMask": "0xc", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 2; Non-Coherent dat= a Tx Flits", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_Q_TxL_FLITS_G2.NCB_DATA", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three 'groups' that allow us to track flits.= It includes filters for NDR, NCB, and NCS message classes. Each 'flit' i= s made up of 80 bits of information (in addition to some ECC data). In ful= l-width (L0) mode, flits are made up of four 'fits', each of which contains= 20 bits of data (along with some additional ECC data). In half-width (L0= p) mode, the fits are only 10 bits, and therefore it takes twice as many fi= ts to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 = GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system = will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calcula= te the bandwidth of the link by taking: flits*80b/time. Note that this is = not the same as 'data' bandwidth. For example, when we are transfering a 6= 4B cacheline across QPI, we will break it into 9 flits -- 1 with header inf= ormation and 8 with 64 bits of actual 'data' and an additional 16 bits of o= ther information. To calculate 'data' bandwidth, one should therefore do: = data flits * 8B / time.", + "UMask": "0x4", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 2; Non-Coherent non= -data Tx Flits", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_Q_TxL_FLITS_G2.NCB_NONDATA", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three 'groups' that allow us to track flits.= It includes filters for NDR, NCB, and NCS message classes. Each 'flit' i= s made up of 80 bits of information (in addition to some ECC data). In ful= l-width (L0) mode, flits are made up of four 'fits', each of which contains= 20 bits of data (along with some additional ECC data). In half-width (L0= p) mode, the fits are only 10 bits, and therefore it takes twice as many fi= ts to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 = GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system = will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calcula= te the bandwidth of the link by taking: flits*80b/time. Note that this is = not the same as 'data' bandwidth. For example, when we are transfering a 6= 4B cacheline across QPI, we will break it into 9 flits -- 1 with header inf= ormation and 8 with 64 bits of actual 'data' and an additional 16 bits of o= ther information. To calculate 'data' bandwidth, one should therefore do: = data flits * 8B / time.", + "UMask": "0x8", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 2; Non-Coherent sta= ndard Tx Flits", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_Q_TxL_FLITS_G2.NCS", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three 'groups' that allow us to track flits.= It includes filters for NDR, NCB, and NCS message classes. Each 'flit' i= s made up of 80 bits of information (in addition to some ECC data). In ful= l-width (L0) mode, flits are made up of four 'fits', each of which contains= 20 bits of data (along with some additional ECC data). In half-width (L0= p) mode, the fits are only 10 bits, and therefore it takes twice as many fi= ts to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 = GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system = will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calcula= te the bandwidth of the link by taking: flits*80b/time. Note that this is = not the same as 'data' bandwidth. For example, when we are transfering a 6= 4B cacheline across QPI, we will break it into 9 flits -- 1 with header inf= ormation and 8 with 64 bits of actual 'data' and an additional 16 bits of o= ther information. To calculate 'data' bandwidth, one should therefore do: = data flits * 8B / time.", + "UMask": "0x10", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 2; Non-Data Respons= e Tx Flits - AD", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three 'groups' that allow us to track flits.= It includes filters for NDR, NCB, and NCS message classes. Each 'flit' i= s made up of 80 bits of information (in addition to some ECC data). In ful= l-width (L0) mode, flits are made up of four 'fits', each of which contains= 20 bits of data (along with some additional ECC data). In half-width (L0= p) mode, the fits are only 10 bits, and therefore it takes twice as many fi= ts to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 = GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system = will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calcula= te the bandwidth of the link by taking: flits*80b/time. Note that this is = not the same as 'data' bandwidth. For example, when we are transfering a 6= 4B cacheline across QPI, we will break it into 9 flits -- 1 with header inf= ormation and 8 with 64 bits of actual 'data' and an additional 16 bits of o= ther information. To calculate 'data' bandwidth, one should therefore do: = data flits * 8B / time.", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 2; Non-Data Respons= e Tx Flits - AK", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three 'groups' that allow us to track flits.= It includes filters for NDR, NCB, and NCS message classes. Each 'flit' i= s made up of 80 bits of information (in addition to some ECC data). In ful= l-width (L0) mode, flits are made up of four 'fits', each of which contains= 20 bits of data (along with some additional ECC data). In half-width (L0= p) mode, the fits are only 10 bits, and therefore it takes twice as many fi= ts to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 = GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system = will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calcula= te the bandwidth of the link by taking: flits*80b/time. Note that this is = not the same as 'data' bandwidth. For example, when we are transfering a 6= 4B cacheline across QPI, we will break it into 9 flits -- 1 with header inf= ormation and 8 with 64 bits of actual 'data' and an additional 16 bits of o= ther information. To calculate 'data' bandwidth, one should therefore do: = data flits * 8B / time.", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Tx Flit Buffer Allocations", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_Q_TxL_INSERTS", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Tx Flit B= uffer. Generally, when data is transmitted across QPI, it will bypass the = TxQ and pass directly to the link. However, the TxQ will be used with L0p = and when LLR occurs, increasing latency to transfer out to the link. This = event can be used in conjunction with the Flit Buffer Occupancy event in or= der to calculate the average flit buffer lifetime.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Tx Flit Buffer Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_Q_TxL_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of flits in the TxQ. = Generally, when data is transmitted across QPI, it will bypass the TxQ and= pass directly to the link. However, the TxQ will be used with L0p and whe= n LLR occurs, increasing latency to transfer out to the link. This can be u= sed with the cycles not empty event to track average occupancy, or the allo= cations event to track average lifetime in the TxQ.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VNA Credits Returned", + "Counter": "0,1,2,3", + "EventCode": "0x1c", + "EventName": "UNC_Q_VNA_CREDIT_RETURNS", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of VNA credits returned.", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VNA Credits Pending Return - Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0x1b", + "EventName": "UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of VNA credits in the Rx side that ar= e waitng to be returned back across the link.", + "Unit": "QPI LL" } ] diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-memory.json b/t= ools/perf/pmu-events/arch/x86/jaketown/uncore-memory.json index 8551cebeba23..a165a77947a0 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-memory.json @@ -1,82 +1,493 @@ [ { - "BriefDescription": "Memory page activates", + "BriefDescription": "DRAM Activate Count", "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_M_ACT_COUNT", "PerPkg": "1", + "PublicDescription": "Counts the number of DRAM Activate commands = sent on this channel. Activate commands are issued to open up a page on th= e DRAM devices so that it can be read or written to with a CAS. One can ca= lculate the number of Page Misses by subtracting the number of Page Miss pr= echarges from the number of Activates.", "Unit": "iMC" }, { - "BriefDescription": "read requests to memory controller. Derived f= rom unc_m_cas_count.rd", + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR= _CAS (w/ and w/out auto-pre)", "Counter": "0,1,2,3", "EventCode": "0x4", - "EventName": "LLC_MISSES.MEM_READ", + "EventName": "UNC_M_CAS_COUNT.ALL", "PerPkg": "1", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands", + "UMask": "0xf", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Re= ads (RD_CAS + Underfills)", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.RD", + "PerPkg": "1", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands", "UMask": "0x3", "Unit": "iMC" }, { - "BriefDescription": "write requests to memory controller. Derived = from unc_m_cas_count.wr", + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD= _CAS (w/ and w/out auto-pre)", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.RD_REG", + "PerPkg": "1", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill R= ead Issued", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", + "PerPkg": "1", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR= _CAS (both Modes)", "Counter": "0,1,2,3", "EventCode": "0x4", - "EventName": "LLC_MISSES.MEM_WRITE", + "EventName": "UNC_M_CAS_COUNT.WR", "PerPkg": "1", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands", "UMask": "0xc", "Unit": "iMC" }, { - "BriefDescription": "Memory controller clock ticks. Used to get pe= rcentages of memory controller cycles events", + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS= (w/ and w/out auto-pre) in Read Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.WR_RMM", + "PerPkg": "1", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS= (w/ and w/out auto-pre) in Write Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.WR_WMM", + "PerPkg": "1", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "uclks", "Counter": "0,1,2,3", "EventName": "UNC_M_CLOCKTICKS", "PerPkg": "1", + "PublicDescription": "Uncore Fixed Counter - uclks", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Precharge All Commands", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "UNC_M_DRAM_PRE_ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that the precharg= e all command was sent.", + "Unit": "iMC" + }, + { + "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_M_DRAM_REFRESH.HIGH", + "PerPkg": "1", + "PublicDescription": "Counts the number of refreshes issued.", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_M_DRAM_REFRESH.PANIC", + "PerPkg": "1", + "PublicDescription": "Counts the number of refreshes issued.", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "ECC Correctable Errors", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS", + "PerPkg": "1", + "PublicDescription": "Counts the number of ECC errors detected and= corrected by the iMC on this channel. This counter is only useful with EC= C DRAM devices. This count will increment one time for each correction reg= ardless of the number of bits corrected. The iMC can correct up to 4 bit e= rrors in independent channel mode and 8 bit erros in lockstep mode.", + "Unit": "iMC" + }, + { + "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_M_MAJOR_MODES.ISOCH", + "PerPkg": "1", + "PublicDescription": "Counts the total number of cycles spent in a= major mode (selected by a filter) on the given channel. Major modea are = channel-wide, and not a per-rank (or dimm or bank) mode.", + "UMask": "0x8", "Unit": "iMC" }, { - "BriefDescription": "Cycles where DRAM ranks are in power down (CK= E) mode", + "BriefDescription": "Cycles in a Major Mode; Partial Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_M_MAJOR_MODES.PARTIAL", + "PerPkg": "1", + "PublicDescription": "Counts the total number of cycles spent in a= major mode (selected by a filter) on the given channel. Major modea are = channel-wide, and not a per-rank (or dimm or bank) mode.", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "Cycles in a Major Mode; Read Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_M_MAJOR_MODES.READ", + "PerPkg": "1", + "PublicDescription": "Counts the total number of cycles spent in a= major mode (selected by a filter) on the given channel. Major modea are = channel-wide, and not a per-rank (or dimm or bank) mode.", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Cycles in a Major Mode; Write Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_M_MAJOR_MODES.WRITE", + "PerPkg": "1", + "PublicDescription": "Counts the total number of cycles spent in a= major mode (selected by a filter) on the given channel. Major modea are = channel-wide, and not a per-rank (or dimm or bank) mode.", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Channel DLLOFF Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_M_POWER_CHANNEL_DLLOFF", + "PerPkg": "1", + "PublicDescription": "Number of cycles when all the ranks in the c= hannel are in CKE Slow (DLLOFF) mode.", + "Unit": "iMC" + }, + { + "BriefDescription": "Channel PPD Cycles", "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M_POWER_CHANNEL_PPD", - "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100.= ", - "MetricName": "power_channel_ppd %", "PerPkg": "1", + "PublicDescription": "Number of cycles when all the ranks in the c= hannel are in PPD mode. If IBT=3Doff is enabled, then this can be used to = count those cycles. If it is not enabled, then this can count the number o= f cycles when that could have been taken advantage of.", "Unit": "iMC" }, { - "BriefDescription": "Cycles all ranks are in critical thermal thro= ttle", + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK0", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK1", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK2", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK3", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK4", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK5", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK6", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK7", + "PerPkg": "1", + "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "Critical Throttle Cycles", "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES", - "MetricExpr": "(UNC_M_POWER_CRITICAL_THROTTLE_CYCLES / UNC_M_CLOCK= TICKS) * 100.", - "MetricName": "power_critical_throttle_cycles %", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the iMC is = in critical thermal throttling. When this happens, all traffic is blocked.= This should be rare unless something bad is going on in the platform. Th= ere is no filtering by rank for this event.", "Unit": "iMC" }, { - "BriefDescription": "Cycles Memory is in self refresh power mode", + "BriefDescription": "Clock-Enabled Self-Refresh", "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M_POWER_SELF_REFRESH", - "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100= .", - "MetricName": "power_self_refresh %", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the iMC is = in self-refresh and the iMC still has a clock. This happens in some packag= e C-states. For example, the PCU may ask the iMC to enter self-refresh eve= n though some of the cores are still processing. One use of this is for Mo= nroe technology. Self-refresh is required during package C3 and C6, but th= ere is no clock in the iMC at this time, so it is not possible to count the= se cases.", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Preemption Count; Read over Read Preempt= ion", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD", + "PerPkg": "1", + "PublicDescription": "Counts the number of times a read in the iMC= preempts another read or write. Generally reads to an open page are issue= d ahead of requests to closed pages. This improves the page hit rate of th= e system. However, high priority requests can cause pages of active reques= ts to be closed in order to get them out. This will reduce the latency of = the high-priority request at the expense of lower bandwidth and increased o= verall average latency.", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Preemption Count; Read over Write Preemp= tion", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR", + "PerPkg": "1", + "PublicDescription": "Counts the number of times a read in the iMC= preempts another read or write. Generally reads to an open page are issue= d ahead of requests to closed pages. This improves the page hit rate of th= e system. However, high priority requests can cause pages of active reques= ts to be closed in order to get them out. This will reduce the latency of = the high-priority request at the expense of lower bandwidth and increased o= verall average latency.", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Precharge commands.; Precharge due to ti= mer expiration", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRAM Precharge commands= sent on this channel.", + "UMask": "0x2", "Unit": "iMC" }, { - "BriefDescription": "Memory page conflicts", + "BriefDescription": "DRAM Precharge commands.; Precharges due to p= age miss", "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.PAGE_MISS", "PerPkg": "1", + "PublicDescription": "Counts the number of DRAM Precharge commands= sent on this channel.", "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "Occupancy counter for memory read queue", + "BriefDescription": "Read Pending Queue Full Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_M_RPQ_CYCLES_FULL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the Read Pe= nding Queue is full. When the RPQ is full, the HA will not be able to issu= e any additional read requests into the iMC. This count should be similar = count in the HA which tracks the number of cycles that the HA has no RPQ cr= edits, just somewhat smaller to account for the credit return overhead. We= generally do not expect to see RPQ become full except for potentially duri= ng Write Major Mode or while running with slow DRAM. This event only track= s non-ISOC queue entries.", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Pending Queue Not Empty", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_M_RPQ_CYCLES_NE", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Read Pe= nding Queue is not empty. This can then be used to calculate the average o= ccupancy (in conjunction with the Read Pending Queue Occupancy count). The= RPQ is used to schedule reads out to the memory controller and to track th= e requests. Requests allocate into the RPQ soon after they enter the memor= y controller, and need credits for an entry in this buffer before being sen= t from the HA to the iMC. They deallocate after the CAS command has been i= ssued to memory. This filter is to be used in conjunction with the occupan= cy filter so that one can correctly track the average occupancies for sched= ulable entries and scheduled requests.", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Pending Queue Allocations", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "UNC_M_RPQ_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the Re= ad Pending Queue. This queue is used to schedule reads out to the memory c= ontroller and to track the requests. Requests allocate into the RPQ soon a= fter they enter the memory controller, and need credits for an entry in thi= s buffer before being sent from the HA to the iMC. They deallocate after t= he CAS command has been issued to memory. This includes both ISOCH and non= -ISOCH requests.", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Pending Queue Occupancy", "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M_RPQ_OCCUPANCY", "PerPkg": "1", + "PublicDescription": "Accumulates the occupancies of the Read Pend= ing Queue each cycle. This can then be used to calculate both the average = occupancy (in conjunction with the number of cycles not empty) and the aver= age latency (in conjunction with the number of allocations). The RPQ is us= ed to schedule reads out to the memory controller and to track the requests= . Requests allocate into the RPQ soon after they enter the memory controll= er, and need credits for an entry in this buffer before being sent from the= HA to the iMC. They deallocate after the CAS command has been issued to me= mory.", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue Full Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_M_WPQ_CYCLES_FULL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the Write P= ending Queue is full. When the WPQ is full, the HA will not be able to iss= ue any additional read requests into the iMC. This count should be similar= count in the HA which tracks the number of cycles that the HA has no WPQ c= redits, just somewhat smaller to account for the credit return overhead.", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue Not Empty", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_M_WPQ_CYCLES_NE", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Write P= ending Queue is not empty. This can then be used to calculate the average = queue occupancy (in conjunction with the WPQ Occupancy Accumulation count).= The WPQ is used to schedule write out to the memory controller and to tra= ck the writes. Requests allocate into the WPQ soon after they enter the me= mory controller, and need credits for an entry in this buffer before being = sent from the HA to the iMC. They deallocate after being issued to DRAM. = Write requests themselves are able to complete (from the perspective of the= rest of the system) as soon they have 'posted' to the iMC. This is not to= be confused with actually performing the write to DRAM. Therefore, the av= erage latency for this queue is actually not useful for deconstruction inte= rmediate write latencies.", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue Allocations", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_M_WPQ_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the Wr= ite Pending Queue. This can then be used to calculate the average queuing = latency (in conjunction with the WPQ occupancy count). The WPQ is used to = schedule write out to the memory controller and to track the writes. Reque= sts allocate into the WPQ soon after they enter the memory controller, and = need credits for an entry in this buffer before being sent from the HA to t= he iMC. They deallocate after being issued to DRAM. Write requests themse= lves are able to complete (from the perspective of the rest of the system) = as soon they have 'posted' to the iMC.", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0x81", + "EventName": "UNC_M_WPQ_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancies of the Write Pen= ding Queue each cycle. This can then be used to calculate both the average= queue occupancy (in conjunction with the number of cycles not empty) and t= he average latency (in conjunction with the number of allocations). The WP= Q is used to schedule write out to the memory controller and to track the w= rites. Requests allocate into the WPQ soon after they enter the memory con= troller, and need credits for an entry in this buffer before being sent fro= m the HA to the iMC. They deallocate after being issued to DRAM. Write re= quests themselves are able to complete (from the perspective of the rest of= the system) as soon they have 'posted' to the iMC. This is not to be conf= used with actually performing the write to DRAM. Therefore, the average la= tency for this queue is actually not useful for deconstruction intermediate= write latencies. So, we provide filtering based on if the request has pos= ted or not. By using the 'not posted' filter, we can track how long writes= spent in the iMC before completions were sent to the HA. The 'posted' fil= ter, on the other hand, provides information about how much queueing is act= ually happenning in the iMC for writes before they are actually issued to m= emory. High average occupancies will generally coincide with high write ma= jor mode counts.", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_M_WPQ_READ_HIT", + "PerPkg": "1", + "PublicDescription": "Counts the number of times a request hits in= the WPQ (write-pending queue). The iMC allows writes and reads to pass up= other writes to different addresses. Before a read or a write is issued, = it will first CAM the WPQ to see if there is a write pending to that addres= s. When reads hit, they are able to directly pull their data from the WPQ = instead of going to memory. Writes that hit will overwrite the existing da= ta. Partial writes that hit will not need to do underfill reads and will s= imply update their relevant sections.", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_M_WPQ_WRITE_HIT", + "PerPkg": "1", + "PublicDescription": "Counts the number of times a request hits in= the WPQ (write-pending queue). The iMC allows writes and reads to pass up= other writes to different addresses. Before a read or a write is issued, = it will first CAM the WPQ to see if there is a write pending to that addres= s. When reads hit, they are able to directly pull their data from the WPQ = instead of going to memory. Writes that hit will overwrite the existing da= ta. Partial writes that hit will not need to do underfill reads and will s= imply update their relevant sections.", "Unit": "iMC" } ] diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-other.json b/to= ols/perf/pmu-events/arch/x86/jaketown/uncore-other.json new file mode 100644 index 000000000000..99fc673c59e9 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-other.json @@ -0,0 +1,1551 @@ +[ + { + "BriefDescription": "Address Match (Conflict) Count; Conflict Merg= es", + "Counter": "0,1", + "EventCode": "0x17", + "EventName": "UNC_I_ADDRESS_MATCH.MERGE_COUNT", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when an inbound w= rite (from a device to memory or another device) had an address match with = another request in the write cache.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Address Match (Conflict) Count; Conflict Stal= ls", + "Counter": "0,1", + "EventCode": "0x17", + "EventName": "UNC_I_ADDRESS_MATCH.STALL_COUNT", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when an inbound w= rite (from a device to memory or another device) had an address match with = another request in the write cache.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Write Ack Pending Occupancy; Any Source", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.ANY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of writes that have a= cquired ownership but have not yet returned their data to the uncore. Thes= e writes are generally queued up in the switch trying to get to the head of= their queues so that they can post their data. The queue occuapancy incre= ments when the ACK is received, and decrements when either the data is retu= rned OR a tickle is received and ownership is released. Note that a single= tickle can result in multiple decrements.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Write Ack Pending Occupancy; Select Source", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.SOURCE", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of writes that have a= cquired ownership but have not yet returned their data to the uncore. Thes= e writes are generally queued up in the switch trying to get to the head of= their queues so that they can post their data. The queue occuapancy incre= ments when the ACK is received, and decrements when either the data is retu= rned OR a tickle is received and ownership is released. Note that a single= tickle can result in multiple decrements.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Outstanding Write Ownership Occupancy; Any So= urce", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_CACHE_OWN_OCCUPANCY.ANY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of writes (and write = prefetches) that are outstanding in the uncore trying to acquire ownership = in each cycle. This can be used with the write transaction count to calcul= ate the average write latency in the uncore. The occupancy increments when= a write request is issued, and decrements when the data is returned.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Outstanding Write Ownership Occupancy; Select= Source", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_CACHE_OWN_OCCUPANCY.SOURCE", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of writes (and write = prefetches) that are outstanding in the uncore trying to acquire ownership = in each cycle. This can be used with the write transaction count to calcul= ate the average write latency in the uncore. The occupancy increments when= a write request is issued, and decrements when the data is returned.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Outstanding Read Occupancy; Any Source", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_I_CACHE_READ_OCCUPANCY.ANY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of reads that are out= standing in the uncore in each cycle. This can be used with the read trans= action count to calculate the average read latency in the uncore. The occu= pancy increments when a read request is issued, and decrements when the dat= a is returned.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Outstanding Read Occupancy; Select Source", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_I_CACHE_READ_OCCUPANCY.SOURCE", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of reads that are out= standing in the uncore in each cycle. This can be used with the read trans= action count to calculate the average read latency in the uncore. The occu= pancy increments when a read request is issued, and decrements when the dat= a is returned.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Total Write Cache Occupancy; Any Source", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of reads and writes t= hat are outstanding in the uncore in each cycle. This is effectively the s= um of the READ_OCCUPANCY and WRITE_OCCUPANCY events.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Total Write Cache Occupancy; Select Source", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of reads and writes t= hat are outstanding in the uncore in each cycle. This is effectively the s= um of the READ_OCCUPANCY and WRITE_OCCUPANCY events.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Outstanding Write Occupancy; Any Source", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_I_CACHE_WRITE_OCCUPANCY.ANY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of writes (and write = prefetches) that are outstanding in the uncore in each cycle. This can be= used with the transaction count event to calculate the average latency in = the uncore. The occupancy increments when the ownership fetch/prefetch is = issued, and decrements the data is returned to the uncore.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Outstanding Write Occupancy; Select Source", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_I_CACHE_WRITE_OCCUPANCY.SOURCE", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of writes (and write = prefetches) that are outstanding in the uncore in each cycle. This can be= used with the transaction count event to calculate the average latency in = the uncore. The occupancy increments when the ownership fetch/prefetch is = issued, and decrements the data is returned to the uncore.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Clocks in the IRP", + "Counter": "0,1", + "EventName": "UNC_I_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Number of clocks in the IRP.", + "Unit": "IRP" + }, + { + "Counter": "0,1", + "EventCode": "0xB", + "EventName": "UNC_I_RxR_AK_CYCLES_FULL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the AK Ingr= ess is full. This queue is where the IRP receives responses from R2PCIe (t= he ring).", + "Unit": "IRP" + }, + { + "BriefDescription": "AK Ingress Occupancy", + "Counter": "0,1", + "EventCode": "0xA", + "EventName": "UNC_I_RxR_AK_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the AK= Ingress. This queue is where the IRP receives responses from R2PCIe (the = ring).", + "Unit": "IRP" + }, + { + "Counter": "0,1", + "EventCode": "0xC", + "EventName": "UNC_I_RxR_AK_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the AK Ingress = in each cycles. This queue is where the IRP receives responses from R2PCIe= (the ring).", + "Unit": "IRP" + }, + { + "Counter": "0,1", + "EventCode": "0x4", + "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the BL Ingr= ess is full. This queue is where the IRP receives data from R2PCIe (the ri= ng). It is used for data returns from read requets as well as outbound MMI= O writes.", + "Unit": "IRP" + }, + { + "BriefDescription": "BL Ingress Occupancy - DRS", + "Counter": "0,1", + "EventCode": "0x1", + "EventName": "UNC_I_RxR_BL_DRS_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the BL= Ingress. This queue is where the IRP receives data from R2PCIe (the ring)= . It is used for data returns from read requets as well as outbound MMIO w= rites.", + "Unit": "IRP" + }, + { + "Counter": "0,1", + "EventCode": "0x7", + "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the BL Ingress = in each cycles. This queue is where the IRP receives data from R2PCIe (the= ring). It is used for data returns from read requets as well as outbound = MMIO writes.", + "Unit": "IRP" + }, + { + "Counter": "0,1", + "EventCode": "0x5", + "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the BL Ingr= ess is full. This queue is where the IRP receives data from R2PCIe (the ri= ng). It is used for data returns from read requets as well as outbound MMI= O writes.", + "Unit": "IRP" + }, + { + "BriefDescription": "BL Ingress Occupancy - NCB", + "Counter": "0,1", + "EventCode": "0x2", + "EventName": "UNC_I_RxR_BL_NCB_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the BL= Ingress. This queue is where the IRP receives data from R2PCIe (the ring)= . It is used for data returns from read requets as well as outbound MMIO w= rites.", + "Unit": "IRP" + }, + { + "Counter": "0,1", + "EventCode": "0x8", + "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the BL Ingress = in each cycles. This queue is where the IRP receives data from R2PCIe (the= ring). It is used for data returns from read requets as well as outbound = MMIO writes.", + "Unit": "IRP" + }, + { + "Counter": "0,1", + "EventCode": "0x6", + "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the BL Ingr= ess is full. This queue is where the IRP receives data from R2PCIe (the ri= ng). It is used for data returns from read requets as well as outbound MMI= O writes.", + "Unit": "IRP" + }, + { + "BriefDescription": "BL Ingress Occupancy - NCS", + "Counter": "0,1", + "EventCode": "0x3", + "EventName": "UNC_I_RxR_BL_NCS_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the BL= Ingress. This queue is where the IRP receives data from R2PCIe (the ring)= . It is used for data returns from read requets as well as outbound MMIO w= rites.", + "Unit": "IRP" + }, + { + "Counter": "0,1", + "EventCode": "0x9", + "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the BL Ingress = in each cycles. This queue is where the IRP receives data from R2PCIe (the= ring). It is used for data returns from read requets as well as outbound = MMIO writes.", + "Unit": "IRP" + }, + { + "BriefDescription": "Tickle Count; Ownership Lost", + "Counter": "0,1", + "EventCode": "0x16", + "EventName": "UNC_I_TICKLES.LOST_OWNERSHIP", + "PerPkg": "1", + "PublicDescription": "Counts the number of tickles that are receiv= ed. This is for both explicit (from Cbo) and implicit (internal conflict) = tickles.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Tickle Count; Data Returned", + "Counter": "0,1", + "EventCode": "0x16", + "EventName": "UNC_I_TICKLES.TOP_OF_QUEUE", + "PerPkg": "1", + "PublicDescription": "Counts the number of tickles that are receiv= ed. This is for both explicit (from Cbo) and implicit (internal conflict) = tickles.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Select Source", + "Counter": "0,1", + "EventCode": "0x15", + "EventName": "UNC_I_TRANSACTIONS.ORDERINGQ", + "Filter": "IRPFilter[4:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of 'Inbound' transactions = from the IRP to the Uncore. This can be filtered based on request type in = addition to the source queue. Note the special filtering equation. We do = OR-reduction on the request type. If the SOURCE bit is set, then we also d= o AND qualification based on the source portID.", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Read Prefetches", + "Counter": "0,1", + "EventCode": "0x15", + "EventName": "UNC_I_TRANSACTIONS.PD_PREFETCHES", + "PerPkg": "1", + "PublicDescription": "Counts the number of 'Inbound' transactions = from the IRP to the Uncore. This can be filtered based on request type in = addition to the source queue. Note the special filtering equation. We do = OR-reduction on the request type. If the SOURCE bit is set, then we also d= o AND qualification based on the source portID.", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Reads", + "Counter": "0,1", + "EventCode": "0x15", + "EventName": "UNC_I_TRANSACTIONS.READS", + "PerPkg": "1", + "PublicDescription": "Counts the number of 'Inbound' transactions = from the IRP to the Uncore. This can be filtered based on request type in = addition to the source queue. Note the special filtering equation. We do = OR-reduction on the request type. If the SOURCE bit is set, then we also d= o AND qualification based on the source portID.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Writes", + "Counter": "0,1", + "EventCode": "0x15", + "EventName": "UNC_I_TRANSACTIONS.WRITES", + "PerPkg": "1", + "PublicDescription": "Counts the number of 'Inbound' transactions = from the IRP to the Uncore. This can be filtered based on request type in = addition to the source queue. Note the special filtering equation. We do = OR-reduction on the request type. If the SOURCE bit is set, then we also d= o AND qualification based on the source portID.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "No AD Egress Credit Stalls", + "Counter": "0,1", + "EventCode": "0x18", + "EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number times when it is not possi= ble to issue a request to the R2PCIe because there are no AD Egress Credits= available.", + "Unit": "IRP" + }, + { + "BriefDescription": "No BL Egress Credit Stalls", + "Counter": "0,1", + "EventCode": "0x19", + "EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number times when it is not possi= ble to issue data to the R2PCIe because there are no BL Egress Credits avai= lable.", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", + "EventCode": "0xE", + "EventName": "UNC_I_TxR_DATA_INSERTS_NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of requests issued to the = switch (towards the devices).", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", + "EventCode": "0xF", + "EventName": "UNC_I_TxR_DATA_INSERTS_NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of requests issued to the = switch (towards the devices).", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Request Queue Occupancy", + "Counter": "0,1", + "EventCode": "0xD", + "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumultes the number of outstanding outboun= d requests from the IRP to the switch (towards the devices). This can be u= sed in conjuection with the allocations event in order to calculate average= latency of outbound requests.", + "Unit": "IRP" + }, + { + "BriefDescription": "Write Ordering Stalls", + "Counter": "0,1", + "EventCode": "0x1A", + "EventName": "UNC_I_WRITE_ORDERING_STALL_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are p= ending write ACK's in the switch but the switch->IRP pipeline is not utiliz= ed.", + "Unit": "IRP" + }, + { + "BriefDescription": "Number of uclks in domain", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_R2_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Counts the number of uclks in the R2PCIe ucl= k domain. This could be slightly different than the count in the Ubox beca= use of enable/freeze delays. However, because the R2PCIe is close to the U= box, they generally should not diverge by more than a handful of cycles.", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credit Acquired; DRS", + "Counter": "0,1", + "EventCode": "0x33", + "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of credits that are acquir= ed in the R2PCIe agent for sending transactions into the IIO on either NCB = or NCS are in use. Transactions from the BL ring going into the IIO Agent = must first acquire a credit. These credits are for either the NCB or NCS m= essage classes. NCB, or non-coherent bypass messages are used to transmit = data without coherency (and are common). NCS is used for reads to PCIe (an= d should be used sparingly).", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credit Acquired; NCB", + "Counter": "0,1", + "EventCode": "0x33", + "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of credits that are acquir= ed in the R2PCIe agent for sending transactions into the IIO on either NCB = or NCS are in use. Transactions from the BL ring going into the IIO Agent = must first acquire a credit. These credits are for either the NCB or NCS m= essage classes. NCB, or non-coherent bypass messages are used to transmit = data without coherency (and are common). NCS is used for reads to PCIe (an= d should be used sparingly).", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credit Acquired; NCS", + "Counter": "0,1", + "EventCode": "0x33", + "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of credits that are acquir= ed in the R2PCIe agent for sending transactions into the IIO on either NCB = or NCS are in use. Transactions from the BL ring going into the IIO Agent = must first acquire a credit. These credits are for either the NCB or NCS m= essage classes. NCB, or non-coherent bypass messages are used to transmit = data without coherency (and are common). NCS is used for reads to PCIe (an= d should be used sparingly).", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Failed to Acquire a Credit; DRS", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_R2_IIO_CREDITS_REJECT.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that a request pe= nding in the BL Ingress attempted to acquire either a NCB or NCS credit to = transmit into the IIO, but was rejected because no credits were available. = NCB, or non-coherent bypass messages are used to transmit data without coh= erency (and are common). NCS is used for reads to PCIe (and should be used= sparingly).", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Failed to Acquire a Credit; NCB", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_R2_IIO_CREDITS_REJECT.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that a request pe= nding in the BL Ingress attempted to acquire either a NCB or NCS credit to = transmit into the IIO, but was rejected because no credits were available. = NCB, or non-coherent bypass messages are used to transmit data without coh= erency (and are common). NCS is used for reads to PCIe (and should be used= sparingly).", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Failed to Acquire a Credit; NCS", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_R2_IIO_CREDITS_REJECT.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that a request pe= nding in the BL Ingress attempted to acquire either a NCB or NCS credit to = transmit into the IIO, but was rejected because no credits were available. = NCB, or non-coherent bypass messages are used to transmit data without coh= erency (and are common). NCS is used for reads to PCIe (and should be used= sparingly).", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credits in Use; DRS", + "Counter": "0,1", + "EventCode": "0x32", + "EventName": "UNC_R2_IIO_CREDITS_USED.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when one or more= credits in the R2PCIe agent for sending transactions into the IIO on eithe= r NCB or NCS are in use. Transactions from the BL ring going into the IIO = Agent must first acquire a credit. These credits are for either the NCB or= NCS message classes. NCB, or non-coherent bypass messages are used to tra= nsmit data without coherency (and are common). NCS is used for reads to PC= Ie (and should be used sparingly).", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credits in Use; NCB", + "Counter": "0,1", + "EventCode": "0x32", + "EventName": "UNC_R2_IIO_CREDITS_USED.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when one or more= credits in the R2PCIe agent for sending transactions into the IIO on eithe= r NCB or NCS are in use. Transactions from the BL ring going into the IIO = Agent must first acquire a credit. These credits are for either the NCB or= NCS message classes. NCB, or non-coherent bypass messages are used to tra= nsmit data without coherency (and are common). NCS is used for reads to PC= Ie (and should be used sparingly).", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credits in Use; NCS", + "Counter": "0,1", + "EventCode": "0x32", + "EventName": "UNC_R2_IIO_CREDITS_USED.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when one or more= credits in the R2PCIe agent for sending transactions into the IIO on eithe= r NCB or NCS are in use. Transactions from the BL ring going into the IIO = Agent must first acquire a credit. These credits are for either the NCB or= NCS message classes. NCB, or non-coherent bypass messages are used to tra= nsmit data without coherency (and are common). NCS is used for reads to PC= Ie (and should be used sparingly).", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 IV Ring in Use; Any", + "Counter": "0,1,2,3", + "EventCode": "0xa", + "EventName": "UNC_R2_RING_IV_USED.ANY", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sunk into the ring stop. The IV ring is unidirectional. Whether UP or= DN is used is dependent on the system programming. Thereofore, one should= generally set both the UP and DN bits for a given polarity (or both) at a = given time.", + "UMask": "0xf", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "AK Ingress Bounced", + "EventCode": "0x12", + "EventName": "UNC_R2_RxR_AK_BOUNCES", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a request de= stined for the AK ingress bounced.", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; DRS", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_R2_RxR_CYCLES_NE.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe = Ingress is not empty. This tracks one of the three rings that are used by = the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress = Occupancy Accumulator event in order to calculate average queue occupancy. = Multiple ingress buffers can be tracked at a given time using multiple cou= nters.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; NCB", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_R2_RxR_CYCLES_NE.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe = Ingress is not empty. This tracks one of the three rings that are used by = the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress = Occupancy Accumulator event in order to calculate average queue occupancy. = Multiple ingress buffers can be tracked at a given time using multiple cou= nters.", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; NCS", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_R2_RxR_CYCLES_NE.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe = Ingress is not empty. This tracks one of the three rings that are used by = the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress = Occupancy Accumulator event in order to calculate average queue occupancy. = Multiple ingress buffers can be tracked at a given time using multiple cou= nters.", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Full; AD", + "EventCode": "0x25", + "EventName": "UNC_R2_TxR_CYCLES_FULL.AD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe = Egress buffer is full.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Full; AK", + "EventCode": "0x25", + "EventName": "UNC_R2_TxR_CYCLES_FULL.AK", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe = Egress buffer is full.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Full; BL", + "EventCode": "0x25", + "EventName": "UNC_R2_TxR_CYCLES_FULL.BL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe = Egress buffer is full.", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Not Empty; AD", + "EventCode": "0x23", + "EventName": "UNC_R2_TxR_CYCLES_NE.AD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe = Egress is not empty. This tracks one of the three rings that are used by t= he R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Oc= cupancy Accumulator event in order to calculate average queue occupancy. O= nly a single Egress queue can be tracked at any given time. It is not poss= ible to filter based on direction or polarity.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Not Empty; AK", + "EventCode": "0x23", + "EventName": "UNC_R2_TxR_CYCLES_NE.AK", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe = Egress is not empty. This tracks one of the three rings that are used by t= he R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Oc= cupancy Accumulator event in order to calculate average queue occupancy. O= nly a single Egress queue can be tracked at any given time. It is not poss= ible to filter based on direction or polarity.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Not Empty; BL", + "EventCode": "0x23", + "EventName": "UNC_R2_TxR_CYCLES_NE.BL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe = Egress is not empty. This tracks one of the three rings that are used by t= he R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Oc= cupancy Accumulator event in order to calculate average queue occupancy. O= nly a single Egress queue can be tracked at any given time. It is not poss= ible to filter based on direction or polarity.", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress NACK; AD", + "Counter": "0,1", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACKS.AD", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that the Egress r= eceived a NACK from the ring and could not issue a transaction.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress NACK; AK", + "Counter": "0,1", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACKS.AK", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that the Egress r= eceived a NACK from the ring and could not issue a transaction.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress NACK; BL", + "Counter": "0,1", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACKS.BL", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that the Egress r= eceived a NACK from the ring and could not issue a transaction.", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Number of uclks in domain", + "Counter": "0,1,2", + "EventCode": "0x1", + "EventName": "UNC_R3_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Counts the number of uclks in the QPI uclk d= omain. This could be slightly different than the count in the Ubox because= of enable/freeze delays. However, because the QPI Agent is close to the U= box, they generally should not diverge by more than a handful of cycles.", + "Unit": "R3QPI" + }, + { + "BriefDescription": "to IIO BL Credit Acquired", + "Counter": "0,1", + "EventCode": "0x20", + "EventName": "UNC_R3_IIO_CREDITS_ACQUIRED.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the NCS/NCB/DRS c= redit is acquried in the QPI for sending messages on BL to the IIO. There = is one credit for each of these three message classes (three credits total)= . NCS is used for reads to PCIe space, NCB is used for transfering data wi= thout coherency, and DRS is used for transfering data with coherency (cacha= ble PCI transactions). This event can only track one message class at a ti= me.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "to IIO BL Credit Acquired", + "Counter": "0,1", + "EventCode": "0x20", + "EventName": "UNC_R3_IIO_CREDITS_ACQUIRED.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the NCS/NCB/DRS c= redit is acquried in the QPI for sending messages on BL to the IIO. There = is one credit for each of these three message classes (three credits total)= . NCS is used for reads to PCIe space, NCB is used for transfering data wi= thout coherency, and DRS is used for transfering data with coherency (cacha= ble PCI transactions). This event can only track one message class at a ti= me.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "to IIO BL Credit Acquired", + "Counter": "0,1", + "EventCode": "0x20", + "EventName": "UNC_R3_IIO_CREDITS_ACQUIRED.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the NCS/NCB/DRS c= redit is acquried in the QPI for sending messages on BL to the IIO. There = is one credit for each of these three message classes (three credits total)= . NCS is used for reads to PCIe space, NCB is used for transfering data wi= thout coherency, and DRS is used for transfering data with coherency (cacha= ble PCI transactions). This event can only track one message class at a ti= me.", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "to IIO BL Credit Rejected", + "Counter": "0,1", + "EventCode": "0x21", + "EventName": "UNC_R3_IIO_CREDITS_REJECT.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that a request at= tempted to acquire an NCS/NCB/DRS credit in the QPI for sending messages on= BL to the IIO but was rejected because no credit was available. There is = one credit for each of these three message classes (three credits total). = NCS is used for reads to PCIe space, NCB is used for transfering data witho= ut coherency, and DRS is used for transfering data with coherency (cachable= PCI transactions). This event can only track one message class at a time.= ", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "to IIO BL Credit Rejected", + "Counter": "0,1", + "EventCode": "0x21", + "EventName": "UNC_R3_IIO_CREDITS_REJECT.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that a request at= tempted to acquire an NCS/NCB/DRS credit in the QPI for sending messages on= BL to the IIO but was rejected because no credit was available. There is = one credit for each of these three message classes (three credits total). = NCS is used for reads to PCIe space, NCB is used for transfering data witho= ut coherency, and DRS is used for transfering data with coherency (cachable= PCI transactions). This event can only track one message class at a time.= ", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "to IIO BL Credit Rejected", + "Counter": "0,1", + "EventCode": "0x21", + "EventName": "UNC_R3_IIO_CREDITS_REJECT.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that a request at= tempted to acquire an NCS/NCB/DRS credit in the QPI for sending messages on= BL to the IIO but was rejected because no credit was available. There is = one credit for each of these three message classes (three credits total). = NCS is used for reads to PCIe space, NCB is used for transfering data witho= ut coherency, and DRS is used for transfering data with coherency (cachable= PCI transactions). This event can only track one message class at a time.= ", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "to IIO BL Credit In Use", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_R3_IIO_CREDITS_USED.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the NCS/NCB= /DRS credit is in use in the QPI for sending messages on BL to the IIO. Th= ere is one credit for each of these three message classes (three credits to= tal). NCS is used for reads to PCIe space, NCB is used for transfering dat= a without coherency, and DRS is used for transfering data with coherency (c= achable PCI transactions). This event can only track one message class at = a time.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "to IIO BL Credit In Use", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_R3_IIO_CREDITS_USED.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the NCS/NCB= /DRS credit is in use in the QPI for sending messages on BL to the IIO. Th= ere is one credit for each of these three message classes (three credits to= tal). NCS is used for reads to PCIe space, NCB is used for transfering dat= a without coherency, and DRS is used for transfering data with coherency (c= achable PCI transactions). This event can only track one message class at = a time.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "to IIO BL Credit In Use", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_R3_IIO_CREDITS_USED.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the NCS/NCB= /DRS credit is in use in the QPI for sending messages on BL to the IIO. Th= ere is one credit for each of these three message classes (three credits to= tal). NCS is used for reads to PCIe space, NCB is used for transfering dat= a without coherency, and DRS is used for transfering data with coherency (c= achable PCI transactions). This event can only track one message class at = a time.", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Clockwise and Even", + "Counter": "0,1,2", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Clockwise and Odd", + "Counter": "0,1,2", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sent, but does not include when packets are be= ing sunk into the ring stop.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sent, but does not include when packets are be= ing sunk into the ring stop.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Clockwise and Even", + "Counter": "0,1,2", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sent, but does not include when packets are be= ing sunk into the ring stop.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Clockwise and Odd", + "Counter": "0,1,2", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sent, but does not include when packets are be= ing sunk into the ring stop.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Clockwise and Even", + "Counter": "0,1,2", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Clockwise and Odd", + "Counter": "0,1,2", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sunk, but does not include when packets are be= ing sent from the ring stop.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 IV Ring in Use; Any", + "Counter": "0,1,2", + "EventCode": "0xa", + "EventName": "UNC_R3_RING_IV_USED.ANY", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring= is being used at this ring stop. This includes when packets are passing b= y and when packets are being sent, but does not include when packets are be= ing sunk into the ring stop. The IV ring is unidirectional. Whether UP or= DN is used is dependent on the system programming. Thereofore, one should= generally set both the UP and DN bits for a given polarity (or both) at a = given time.", + "UMask": "0xf", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Bypassed", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_R3_RxR_BYPASSED.AD", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when the Ingress = was bypassed and an incoming transaction was bypassed directly across the B= GF and into the qfclk domain.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; DRS", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_R3_RxR_CYCLES_NE.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI Ing= ress is not empty. This tracks one of the three rings that are used by the= QPI agent. This can be used in conjunction with the QPI Ingress Occupancy= Accumulator event in order to calculate average queue occupancy. Multiple= ingress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; HOM", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_R3_RxR_CYCLES_NE.HOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI Ing= ress is not empty. This tracks one of the three rings that are used by the= QPI agent. This can be used in conjunction with the QPI Ingress Occupancy= Accumulator event in order to calculate average queue occupancy. Multiple= ingress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; NCB", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_R3_RxR_CYCLES_NE.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI Ing= ress is not empty. This tracks one of the three rings that are used by the= QPI agent. This can be used in conjunction with the QPI Ingress Occupancy= Accumulator event in order to calculate average queue occupancy. Multiple= ingress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; NCS", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_R3_RxR_CYCLES_NE.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI Ing= ress is not empty. This tracks one of the three rings that are used by the= QPI agent. This can be used in conjunction with the QPI Ingress Occupancy= Accumulator event in order to calculate average queue occupancy. Multiple= ingress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; NDR", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_R3_RxR_CYCLES_NE.NDR", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI Ing= ress is not empty. This tracks one of the three rings that are used by the= QPI agent. This can be used in conjunction with the QPI Ingress Occupancy= Accumulator event in order to calculate average queue occupancy. Multiple= ingress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; SNP", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_R3_RxR_CYCLES_NE.SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI Ing= ress is not empty. This tracks one of the three rings that are used by the= QPI agent. This can be used in conjunction with the QPI Ingress Occupancy= Accumulator event in order to calculate average queue occupancy. Multiple= ingress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; DRS", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QP= I Ingress. This tracks one of the three rings that are used by the QPI age= nt. This can be used in conjunction with the QPI Ingress Occupancy Accumul= ator event in order to calculate average queue latency. Multiple ingress b= uffers can be tracked at a given time using multiple counters.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; HOM", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.HOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QP= I Ingress. This tracks one of the three rings that are used by the QPI age= nt. This can be used in conjunction with the QPI Ingress Occupancy Accumul= ator event in order to calculate average queue latency. Multiple ingress b= uffers can be tracked at a given time using multiple counters.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; NCB", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QP= I Ingress. This tracks one of the three rings that are used by the QPI age= nt. This can be used in conjunction with the QPI Ingress Occupancy Accumul= ator event in order to calculate average queue latency. Multiple ingress b= uffers can be tracked at a given time using multiple counters.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; NCS", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QP= I Ingress. This tracks one of the three rings that are used by the QPI age= nt. This can be used in conjunction with the QPI Ingress Occupancy Accumul= ator event in order to calculate average queue latency. Multiple ingress b= uffers can be tracked at a given time using multiple counters.", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; NDR", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.NDR", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QP= I Ingress. This tracks one of the three rings that are used by the QPI age= nt. This can be used in conjunction with the QPI Ingress Occupancy Accumul= ator event in order to calculate average queue latency. Multiple ingress b= uffers can be tracked at a given time using multiple counters.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; SNP", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QP= I Ingress. This tracks one of the three rings that are used by the QPI age= nt. This can be used in conjunction with the QPI Ingress Occupancy Accumul= ator event in order to calculate average queue latency. Multiple ingress b= uffers can be tracked at a given time using multiple counters.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Occupancy Accumulator; DRS", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY.DRS", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI Ing= ress queue in each cycles. This tracks one of the three ring Ingress buffe= rs. This can be used with the QPI Ingress Not Empty event to calculate ave= rage occupancy or the QPI Ingress Allocations event in order to calculate a= verage queuing latency.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Occupancy Accumulator; HOM", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY.HOM", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI Ing= ress queue in each cycles. This tracks one of the three ring Ingress buffe= rs. This can be used with the QPI Ingress Not Empty event to calculate ave= rage occupancy or the QPI Ingress Allocations event in order to calculate a= verage queuing latency.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Occupancy Accumulator; NCB", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY.NCB", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI Ing= ress queue in each cycles. This tracks one of the three ring Ingress buffe= rs. This can be used with the QPI Ingress Not Empty event to calculate ave= rage occupancy or the QPI Ingress Allocations event in order to calculate a= verage queuing latency.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Occupancy Accumulator; NCS", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY.NCS", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI Ing= ress queue in each cycles. This tracks one of the three ring Ingress buffe= rs. This can be used with the QPI Ingress Not Empty event to calculate ave= rage occupancy or the QPI Ingress Allocations event in order to calculate a= verage queuing latency.", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Occupancy Accumulator; NDR", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY.NDR", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI Ing= ress queue in each cycles. This tracks one of the three ring Ingress buffe= rs. This can be used with the QPI Ingress Not Empty event to calculate ave= rage occupancy or the QPI Ingress Allocations event in order to calculate a= verage queuing latency.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Occupancy Accumulator; SNP", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY.SNP", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI Ing= ress queue in each cycles. This tracks one of the three ring Ingress buffe= rs. This can be used with the QPI Ingress Not Empty event to calculate ave= rage occupancy or the QPI Ingress Allocations event in order to calculate a= verage queuing latency.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Mes= sage Class", + "Counter": "0,1", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire = a DRS VN0 credit. In order for a request to be transferred across QPI, it = must be guaranteed to have a flit buffer on the remote socket to sink into.= There are two credit pools, VNA and VN0. VNA is a shared pool used to ac= hieve high performance. The VN0 pool has reserved entries for each message= class and is used to prevent deadlock. Requests first attempt to acquire = a VNA credit, and then fall back to VN0 if they fail. This therefore count= s the number of times when a request failed to acquire either a VNA or VN0 = credit and is delayed. This should generally be a rare situation.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Mes= sage Class", + "Counter": "0,1", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire = a DRS VN0 credit. In order for a request to be transferred across QPI, it = must be guaranteed to have a flit buffer on the remote socket to sink into.= There are two credit pools, VNA and VN0. VNA is a shared pool used to ac= hieve high performance. The VN0 pool has reserved entries for each message= class and is used to prevent deadlock. Requests first attempt to acquire = a VNA credit, and then fall back to VN0 if they fail. This therefore count= s the number of times when a request failed to acquire either a VNA or VN0 = credit and is delayed. This should generally be a rare situation.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCB Mes= sage Class", + "Counter": "0,1", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCB", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire = a DRS VN0 credit. In order for a request to be transferred across QPI, it = must be guaranteed to have a flit buffer on the remote socket to sink into.= There are two credit pools, VNA and VN0. VNA is a shared pool used to ac= hieve high performance. The VN0 pool has reserved entries for each message= class and is used to prevent deadlock. Requests first attempt to acquire = a VNA credit, and then fall back to VN0 if they fail. This therefore count= s the number of times when a request failed to acquire either a VNA or VN0 = credit and is delayed. This should generally be a rare situation.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCS Mes= sage Class", + "Counter": "0,1", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCS", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire = a DRS VN0 credit. In order for a request to be transferred across QPI, it = must be guaranteed to have a flit buffer on the remote socket to sink into.= There are two credit pools, VNA and VN0. VNA is a shared pool used to ac= hieve high performance. The VN0 pool has reserved entries for each message= class and is used to prevent deadlock. Requests first attempt to acquire = a VNA credit, and then fall back to VN0 if they fail. This therefore count= s the number of times when a request failed to acquire either a VNA or VN0 = credit and is delayed. This should generally be a rare situation.", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Mes= sage Class", + "Counter": "0,1", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire = a DRS VN0 credit. In order for a request to be transferred across QPI, it = must be guaranteed to have a flit buffer on the remote socket to sink into.= There are two credit pools, VNA and VN0. VNA is a shared pool used to ac= hieve high performance. The VN0 pool has reserved entries for each message= class and is used to prevent deadlock. Requests first attempt to acquire = a VNA credit, and then fall back to VN0 if they fail. This therefore count= s the number of times when a request failed to acquire either a VNA or VN0 = credit and is delayed. This should generally be a rare situation.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Mes= sage Class", + "Counter": "0,1", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire = a DRS VN0 credit. In order for a request to be transferred across QPI, it = must be guaranteed to have a flit buffer on the remote socket to sink into.= There are two credit pools, VNA and VN0. VNA is a shared pool used to ac= hieve high performance. The VN0 pool has reserved entries for each message= class and is used to prevent deadlock. Requests first attempt to acquire = a VNA credit, and then fall back to VN0 if they fail. This therefore count= s the number of times when a request failed to acquire either a VNA or VN0 = credit and is delayed. This should generally be a rare situation.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; DRS Message Class", + "Counter": "0,1", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.DRS", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the= DRS message channel. In order for a request to be transferred across QPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN0. VNA is a shared pool used t= o achieve high performance. The VN0 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN0 if they fail. This counts the = number of times a VN0 credit was used. Note that a single VN0 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN0 will only count a single credit even though it may use multiple= buffers.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; HOM Message Class", + "Counter": "0,1", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.HOM", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the= DRS message channel. In order for a request to be transferred across QPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN0. VNA is a shared pool used t= o achieve high performance. The VN0 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN0 if they fail. This counts the = number of times a VN0 credit was used. Note that a single VN0 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN0 will only count a single credit even though it may use multiple= buffers.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; NCB Message Class", + "Counter": "0,1", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.NCB", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the= DRS message channel. In order for a request to be transferred across QPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN0. VNA is a shared pool used t= o achieve high performance. The VN0 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN0 if they fail. This counts the = number of times a VN0 credit was used. Note that a single VN0 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN0 will only count a single credit even though it may use multiple= buffers.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; NCS Message Class", + "Counter": "0,1", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.NCS", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the= DRS message channel. In order for a request to be transferred across QPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN0. VNA is a shared pool used t= o achieve high performance. The VN0 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN0 if they fail. This counts the = number of times a VN0 credit was used. Note that a single VN0 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN0 will only count a single credit even though it may use multiple= buffers.", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; NDR Message Class", + "Counter": "0,1", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.NDR", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the= DRS message channel. In order for a request to be transferred across QPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN0. VNA is a shared pool used t= o achieve high performance. The VN0 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN0 if they fail. This counts the = number of times a VN0 credit was used. Note that a single VN0 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN0 will only count a single credit even though it may use multiple= buffers.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; SNP Message Class", + "Counter": "0,1", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.SNP", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the= DRS message channel. In order for a request to be transferred across QPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN0. VNA is a shared pool used t= o achieve high performance. The VN0 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN0 if they fail. This counts the = number of times a VN0 credit was used. Note that a single VN0 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN0 will only count a single credit even though it may use multiple= buffers.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA credit Acquisitions", + "Counter": "0,1", + "EventCode": "0x33", + "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED", + "PerPkg": "1", + "PublicDescription": "Number of QPI VNA Credit acquisitions. This= event can be used in conjunction with the VNA In-Use Accumulator to calcul= ate the average lifetime of a credit holder. VNA credits are used by all m= essage classes in order to communicate across QPI. If a packet is unable t= o acquire credits, it will then attempt to use credts from the VN0 pool. N= ote that a single packet may require multiple flit buffers (i.e. when data = is being transfered). Therefore, this event will increment by the number o= f credits acquired in each cycle. Filtering based on message class is not = provided. One can count the number of packets transfered in a given messag= e class using an qfclk event.", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; DRS Message Class", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions = that were rejected because the VNA credit pool was full (or almost full). = It is possible to filter this event by message class. Some packets use mor= e than one flit buffer, and therefore must acquire multiple credits. There= fore, one could get a reject even if the VNA credits were not fully used up= . The VNA pool is generally used to provide the bulk of the QPI bandwidth = (as opposed to the VN0 pool which is used to guarantee forward progress). = VNA credits can run out if the flit buffer on the receiving side starts to = queue up substantially. This can happen if the rest of the uncore is unabl= e to drain the requests fast enough.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; HOM Message Class", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions = that were rejected because the VNA credit pool was full (or almost full). = It is possible to filter this event by message class. Some packets use mor= e than one flit buffer, and therefore must acquire multiple credits. There= fore, one could get a reject even if the VNA credits were not fully used up= . The VNA pool is generally used to provide the bulk of the QPI bandwidth = (as opposed to the VN0 pool which is used to guarantee forward progress). = VNA credits can run out if the flit buffer on the receiving side starts to = queue up substantially. This can happen if the rest of the uncore is unabl= e to drain the requests fast enough.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; NCB Message Class", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions = that were rejected because the VNA credit pool was full (or almost full). = It is possible to filter this event by message class. Some packets use mor= e than one flit buffer, and therefore must acquire multiple credits. There= fore, one could get a reject even if the VNA credits were not fully used up= . The VNA pool is generally used to provide the bulk of the QPI bandwidth = (as opposed to the VN0 pool which is used to guarantee forward progress). = VNA credits can run out if the flit buffer on the receiving side starts to = queue up substantially. This can happen if the rest of the uncore is unabl= e to drain the requests fast enough.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; NCS Message Class", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCS", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions = that were rejected because the VNA credit pool was full (or almost full). = It is possible to filter this event by message class. Some packets use mor= e than one flit buffer, and therefore must acquire multiple credits. There= fore, one could get a reject even if the VNA credits were not fully used up= . The VNA pool is generally used to provide the bulk of the QPI bandwidth = (as opposed to the VN0 pool which is used to guarantee forward progress). = VNA credits can run out if the flit buffer on the receiving side starts to = queue up substantially. This can happen if the rest of the uncore is unabl= e to drain the requests fast enough.", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; NDR Message Class", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions = that were rejected because the VNA credit pool was full (or almost full). = It is possible to filter this event by message class. Some packets use mor= e than one flit buffer, and therefore must acquire multiple credits. There= fore, one could get a reject even if the VNA credits were not fully used up= . The VNA pool is generally used to provide the bulk of the QPI bandwidth = (as opposed to the VN0 pool which is used to guarantee forward progress). = VNA credits can run out if the flit buffer on the receiving side starts to = queue up substantially. This can happen if the rest of the uncore is unabl= e to drain the requests fast enough.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; SNP Message Class", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions = that were rejected because the VNA credit pool was full (or almost full). = It is possible to filter this event by message class. Some packets use mor= e than one flit buffer, and therefore must acquire multiple credits. There= fore, one could get a reject even if the VNA credits were not fully used up= . The VNA pool is generally used to provide the bulk of the QPI bandwidth = (as opposed to the VN0 pool which is used to guarantee forward progress). = VNA credits can run out if the flit buffer on the receiving side starts to = queue up substantially. This can happen if the rest of the uncore is unabl= e to drain the requests fast enough.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Cycles with no VNA credits available", + "Counter": "0,1", + "EventCode": "0x31", + "EventName": "UNC_R3_VNA_CREDIT_CYCLES_OUT", + "PerPkg": "1", + "PublicDescription": "Number of QPI uclk cycles when the transmitt= ed has no VNA credits available and therefore cannot send any requests on t= his channel. Note that this does not mean that no flits can be transmitted= , as those holding VN0 credits will still (potentially) be able to transmit= . Generally it is the goal of the uncore that VNA credits should not run o= ut, as this can substantially throttle back useful QPI bandwidth.", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Cycles with 1 or more VNA credits in use", + "Counter": "0,1", + "EventCode": "0x32", + "EventName": "UNC_R3_VNA_CREDIT_CYCLES_USED", + "PerPkg": "1", + "PublicDescription": "Number of QPI uclk cycles with one or more V= NA credits in use. This event can be used in conjunction with the VNA In-U= se Accumulator to calculate the average number of used VNA credits.", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VLW Received", + "Counter": "0,1", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were r= eceived from Uncore. Specify the thread to filter on using NCUPMONCTRLGLC= TR.ThreadID.", + "UMask": "0x8", + "Unit": "UBOX" + }, + { + "BriefDescription": "VLW Received", + "Counter": "0,1", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.INT_PRIO", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were r= eceived from Uncore. Specify the thread to filter on using NCUPMONCTRLGLC= TR.ThreadID.", + "UMask": "0x10", + "Unit": "UBOX" + }, + { + "BriefDescription": "VLW Received", + "Counter": "0,1", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.IPI_RCVD", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were r= eceived from Uncore. Specify the thread to filter on using NCUPMONCTRLGLC= TR.ThreadID.", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "VLW Received", + "Counter": "0,1", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were r= eceived from Uncore. Specify the thread to filter on using NCUPMONCTRLGLC= TR.ThreadID.", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "VLW Received", + "Counter": "0,1", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.VLW_RCVD", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were r= eceived from Uncore. Specify the thread to filter on using NCUPMONCTRLGLC= TR.ThreadID.", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "Filter Match", + "Counter": "0,1", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.DISABLE", + "PerPkg": "1", + "PublicDescription": "Filter match per thread (w/ or w/o Filter En= able). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "Filter Match", + "Counter": "0,1", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.ENABLE", + "Filter": "UBoxFilter[3:0]", + "PerPkg": "1", + "PublicDescription": "Filter match per thread (w/ or w/o Filter En= able). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "Filter Match", + "Counter": "0,1", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE", + "PerPkg": "1", + "PublicDescription": "Filter match per thread (w/ or w/o Filter En= able). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x8", + "Unit": "UBOX" + }, + { + "BriefDescription": "Filter Match", + "Counter": "0,1", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE", + "Filter": "UBoxFilter[3:0]", + "PerPkg": "1", + "PublicDescription": "Filter match per thread (w/ or w/o Filter En= able). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "IDI Lock/SplitLock Cycles", + "Counter": "0,1", + "EventCode": "0x44", + "EventName": "UNC_U_LOCK_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of times an IDI Lock/SplitLock sequen= ce was started", + "Unit": "UBOX" + }, + { + "BriefDescription": "MsgCh Requests by Size; 4B Requests", + "Counter": "0,1", + "EventCode": "0x47", + "EventName": "UNC_U_MSG_CHNL_SIZE_COUNT.4B", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of transactions on the message channe= l filtered by request size. This includes both reads and writes.", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "MsgCh Requests by Size; 8B Requests", + "Counter": "0,1", + "EventCode": "0x47", + "EventName": "UNC_U_MSG_CHNL_SIZE_COUNT.8B", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Number of transactions on the message channe= l filtered by request size. This includes both reads and writes.", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "Cycles PHOLD Assert to Ack; ACK to Deassert", + "Counter": "0,1", + "EventCode": "0x45", + "EventName": "UNC_U_PHOLD_CYCLES.ACK_TO_DEASSERT", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "PHOLD cycles. Filter from source CoreID.", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK", + "Counter": "0,1", + "EventCode": "0x45", + "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "PHOLD cycles. Filter from source CoreID.", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "RACU Request", + "Counter": "0,1", + "EventCode": "0x46", + "EventName": "UNC_U_RACU_REQUESTS.COUNT", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Correctable Machine Check= ", + "Counter": "0,1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.CMC", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one= or all cores", + "UMask": "0x10", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Livelock", + "Counter": "0,1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.LIVELOCK", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one= or all cores", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; LTError", + "Counter": "0,1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.LTERROR", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one= or all cores", + "UMask": "0x8", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Monitor T0", + "Counter": "0,1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one= or all cores", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Monitor T1", + "Counter": "0,1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one= or all cores", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Other", + "Counter": "0,1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.OTHER", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one= or all cores", + "UMask": "0x80", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Trap", + "Counter": "0,1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.TRAP", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one= or all cores", + "UMask": "0x40", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Che= ck", + "Counter": "0,1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.UMC", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one= or all cores", + "UMask": "0x20", + "Unit": "UBOX" + } +] diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-power.json b/to= ols/perf/pmu-events/arch/x86/jaketown/uncore-power.json index 8755693d86c6..04228344cb9c 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-power.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-power.json @@ -1,272 +1,372 @@ [ { - "BriefDescription": "PCU clock ticks. Use to get percentages of PC= U cycles events", + "BriefDescription": "pclk Cycles", "Counter": "0,1,2,3", "EventName": "UNC_P_CLOCKTICKS", "PerPkg": "1", + "PublicDescription": "The PCU runs off a fixed 800 MHz clock. Thi= s event counts the number of pclk cycles measured while the counter was ena= bled. The pclk, like the Memory Controller's dclk, counts at a constant ra= te making it a good measure of actual wall time.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles that the uncore w= as running at a frequency greater than or equal to the frequency that is co= nfigured in the filter. (filter_band0=3DXXX with XXX in 100Mhz units). One= can also use inversion (filter_inv=3D1) to track cycles when we were less = than the configured frequency", + "BriefDescription": "Core C State Transition Cycles", "Counter": "0,1,2,3", - "EventCode": "0xb", - "EventName": "UNC_P_FREQ_BAND0_CYCLES", - "MetricExpr": "(UNC_P_FREQ_BAND0_CYCLES / UNC_P_CLOCKTICKS) * 100.= ", - "MetricName": "freq_band0_cycles %", + "EventCode": "0x3", + "EventName": "UNC_P_CORE0_TRANSITION_CYCLES", + "ExtSel": "1", "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles that the uncore w= as running at a frequency greater than or equal to the frequency that is co= nfigured in the filter. (filter_band1=3DXXX with XXX in 100Mhz units). One= can also use inversion (filter_inv=3D1) to track cycles when we were less = than the configured frequency", + "BriefDescription": "Core C State Transition Cycles", "Counter": "0,1,2,3", - "EventCode": "0xc", - "EventName": "UNC_P_FREQ_BAND1_CYCLES", - "MetricExpr": "(UNC_P_FREQ_BAND1_CYCLES / UNC_P_CLOCKTICKS) * 100.= ", - "MetricName": "freq_band1_cycles %", + "EventCode": "0x4", + "EventName": "UNC_P_CORE1_TRANSITION_CYCLES", + "ExtSel": "1", "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles that the uncore w= as running at a frequency greater than or equal to the frequency that is co= nfigured in the filter. (filter_band2=3DXXX with XXX in 100Mhz units). One= can also use inversion (filter_inv=3D1) to track cycles when we were less = than the configured frequency", + "BriefDescription": "Core C State Transition Cycles", "Counter": "0,1,2,3", - "EventCode": "0xd", - "EventName": "UNC_P_FREQ_BAND2_CYCLES", - "MetricExpr": "(UNC_P_FREQ_BAND2_CYCLES / UNC_P_CLOCKTICKS) * 100.= ", - "MetricName": "freq_band2_cycles %", + "EventCode": "0x5", + "EventName": "UNC_P_CORE2_TRANSITION_CYCLES", + "ExtSel": "1", "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles that the uncore w= as running at a frequency greater than or equal to the frequency that is co= nfigured in the filter. (filter_band3=3DXXX, with XXX in 100Mhz units). On= e can also use inversion (filter_inv=3D1) to track cycles when we were less= than the configured frequency", + "BriefDescription": "Core C State Transition Cycles", "Counter": "0,1,2,3", - "EventCode": "0xe", - "EventName": "UNC_P_FREQ_BAND3_CYCLES", - "MetricExpr": "(UNC_P_FREQ_BAND3_CYCLES / UNC_P_CLOCKTICKS) * 100.= ", - "MetricName": "freq_band3_cycles %", + "EventCode": "0x6", + "EventName": "UNC_P_CORE3_TRANSITION_CYCLES", + "ExtSel": "1", "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of times that the uncore tr= ansitioned a frequency greater than or equal to the frequency that is confi= gured in the filter. (filter_band0=3DXXX with XXX in 100Mhz units). One ca= n also use inversion (filter_inv=3D1) to track cycles when we were less tha= n the configured frequency. Derived from unc_p_freq_band0_cycles", + "BriefDescription": "Core C State Transition Cycles", "Counter": "0,1,2,3", - "EventCode": "0xb", - "EventName": "UNC_P_FREQ_BAND0_TRANSITIONS", - "Filter": "edge=3D1", - "MetricExpr": "(UNC_P_FREQ_BAND0_CYCLES / UNC_P_CLOCKTICKS) * 100.= ", - "MetricName": "freq_band0_cycles %", + "EventCode": "0x7", + "EventName": "UNC_P_CORE4_TRANSITION_CYCLES", + "ExtSel": "1", "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of times that the uncore tr= ansistioned to a frequency greater than or equal to the frequency that is c= onfigured in the filter. (filter_band1=3DXXX with XXX in 100Mhz units). On= e can also use inversion (filter_inv=3D1) to track cycles when we were less= than the configured frequency. Derived from unc_p_freq_band1_cycles", + "BriefDescription": "Core C State Transition Cycles", "Counter": "0,1,2,3", - "EventCode": "0xc", - "EventName": "UNC_P_FREQ_BAND1_TRANSITIONS", - "Filter": "edge=3D1", - "MetricExpr": "(UNC_P_FREQ_BAND1_CYCLES / UNC_P_CLOCKTICKS) * 100.= ", - "MetricName": "freq_band1_cycles %", + "EventCode": "0x8", + "EventName": "UNC_P_CORE5_TRANSITION_CYCLES", + "ExtSel": "1", "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles that the uncore t= ransitioned to a frequency greater than or equal to the frequency that is c= onfigured in the filter. (filter_band2=3DXXX with XXX in 100Mhz units). On= e can also use inversion (filter_inv=3D1) to track cycles when we were less= than the configured frequency. Derived from unc_p_freq_band2_cycles", + "BriefDescription": "Core C State Transition Cycles", "Counter": "0,1,2,3", - "EventCode": "0xd", - "EventName": "UNC_P_FREQ_BAND2_TRANSITIONS", - "Filter": "edge=3D1", - "MetricExpr": "(UNC_P_FREQ_BAND2_CYCLES / UNC_P_CLOCKTICKS) * 100.= ", - "MetricName": "freq_band2_cycles %", + "EventCode": "0x9", + "EventName": "UNC_P_CORE6_TRANSITION_CYCLES", + "ExtSel": "1", "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles that the uncore t= ransitioned to a frequency greater than or equal to the frequency that is c= onfigured in the filter. (filter_band3=3DXXX, with XXX in 100Mhz units). O= ne can also use inversion (filter_inv=3D1) to track cycles when we were les= s than the configured frequency. Derived from unc_p_freq_band3_cycles", + "BriefDescription": "Core C State Transition Cycles", "Counter": "0,1,2,3", - "EventCode": "0xe", - "EventName": "UNC_P_FREQ_BAND3_TRANSITIONS", - "Filter": "edge=3D1", - "MetricExpr": "(UNC_P_FREQ_BAND3_CYCLES / UNC_P_CLOCKTICKS) * 100.= ", - "MetricName": "freq_band3_cycles %", + "EventCode": "0xa", + "EventName": "UNC_P_CORE7_TRANSITION_CYCLES", + "ExtSel": "1", "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions. There is one event per core.", "Unit": "PCU" }, { - "BriefDescription": "This is an occupancy event that tracks the nu= mber of cores that are in C0. It can be used by itself to get the average = number of cores in C0, with threshholding to generate histograms, or with o= ther PCU events and occupancy triggering to capture other details", + "BriefDescription": "Core C State Demotions", "Counter": "0,1,2,3", - "EventCode": "0x80", - "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", - "Filter": "occ_sel=3D1", - "MetricExpr": "(UNC_P_POWER_STATE_OCCUPANCY.CORES_C0 / UNC_P_CLOCK= TICKS) * 100.", - "MetricName": "power_state_occupancy.cores_c0 %", + "EventCode": "0x1e", + "EventName": "UNC_P_DEMOTIONS_CORE0", + "Filter": "PCUFilter[7:0]", "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", "Unit": "PCU" }, { - "BriefDescription": "This is an occupancy event that tracks the nu= mber of cores that are in C3. It can be used by itself to get the average = number of cores in C0, with threshholding to generate histograms, or with o= ther PCU events and occupancy triggering to capture other details", + "BriefDescription": "Core C State Demotions", "Counter": "0,1,2,3", - "EventCode": "0x80", - "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", - "Filter": "occ_sel=3D2", - "MetricExpr": "(UNC_P_POWER_STATE_OCCUPANCY.CORES_C3 / UNC_P_CLOCK= TICKS) * 100.", - "MetricName": "power_state_occupancy.cores_c3 %", + "EventCode": "0x1f", + "EventName": "UNC_P_DEMOTIONS_CORE1", + "Filter": "PCUFilter[7:0]", "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", "Unit": "PCU" }, { - "BriefDescription": "This is an occupancy event that tracks the nu= mber of cores that are in C6. It can be used by itself to get the average = number of cores in C0, with threshholding to generate histograms, or with o= ther PCU events ", + "BriefDescription": "Core C State Demotions", "Counter": "0,1,2,3", - "EventCode": "0x80", - "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", - "Filter": "occ_sel=3D3", - "MetricExpr": "(UNC_P_POWER_STATE_OCCUPANCY.CORES_C6 / UNC_P_CLOCK= TICKS) * 100.", - "MetricName": "power_state_occupancy.cores_c6 %", + "EventCode": "0x20", + "EventName": "UNC_P_DEMOTIONS_CORE2", "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles that we are in ex= ternal PROCHOT mode. This mode is triggered when a sensor off the die dete= rmines that something off-die (like DRAM) is too hot and must throttle to a= void damaging the chip", + "BriefDescription": "Core C State Demotions", "Counter": "0,1,2,3", - "EventCode": "0xa", - "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES", - "MetricExpr": "(UNC_P_PROCHOT_EXTERNAL_CYCLES / UNC_P_CLOCKTICKS) = * 100.", - "MetricName": "prochot_external_cycles %", + "EventCode": "0x21", + "EventName": "UNC_P_DEMOTIONS_CORE3", + "Filter": "PCUFilter[7:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_P_DEMOTIONS_CORE4", + "Filter": "PCUFilter[7:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_P_DEMOTIONS_CORE5", + "Filter": "PCUFilter[7:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_P_DEMOTIONS_CORE6", + "Filter": "PCUFilter[7:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x25", + "EventName": "UNC_P_DEMOTIONS_CORE7", + "Filter": "PCUFilter[7:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a configurab= le cores had a C-state demotion", + "Unit": "PCU" + }, + { + "BriefDescription": "Frequency Residency", + "Counter": "0,1,2,3", + "EventCode": "0xb", + "EventName": "UNC_P_FREQ_BAND0_CYCLES", + "Filter": "PCUFilter[7:0]", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the uncore = was running at a frequency greater than or equal to the frequency that is c= onfigured in the filter. One can use all four counters with this event, so= it is possible to track up to 4 configurable bands. One can use edge dete= ct in conjunction with this event to track the number of times that we tran= sitioned into a frequency greater than or equal to the configurable frequen= cy. One can also use inversion to track cycles when we were less than the c= onfigured frequency.", + "Unit": "PCU" + }, + { + "BriefDescription": "Frequency Residency", + "Counter": "0,1,2,3", + "EventCode": "0xc", + "EventName": "UNC_P_FREQ_BAND1_CYCLES", + "Filter": "PCUFilter[15:8]", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the uncore = was running at a frequency greater than or equal to the frequency that is c= onfigured in the filter. One can use all four counters with this event, so= it is possible to track up to 4 configurable bands. One can use edge dete= ct in conjunction with this event to track the number of times that we tran= sitioned into a frequency greater than or equal to the configurable frequen= cy. One can also use inversion to track cycles when we were less than the c= onfigured frequency.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles when temperature = is the upper limit on frequency", + "BriefDescription": "Frequency Residency", + "Counter": "0,1,2,3", + "EventCode": "0xd", + "EventName": "UNC_P_FREQ_BAND2_CYCLES", + "Filter": "PCUFilter[23:16]", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the uncore = was running at a frequency greater than or equal to the frequency that is c= onfigured in the filter. One can use all four counters with this event, so= it is possible to track up to 4 configurable bands. One can use edge dete= ct in conjunction with this event to track the number of times that we tran= sitioned into a frequency greater than or equal to the configurable frequen= cy. One can also use inversion to track cycles when we were less than the c= onfigured frequency.", + "Unit": "PCU" + }, + { + "BriefDescription": "Frequency Residency", + "Counter": "0,1,2,3", + "EventCode": "0xe", + "EventName": "UNC_P_FREQ_BAND3_CYCLES", + "Filter": "PCUFilter[31:24]", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the uncore = was running at a frequency greater than or equal to the frequency that is c= onfigured in the filter. One can use all four counters with this event, so= it is possible to track up to 4 configurable bands. One can use edge dete= ct in conjunction with this event to track the number of times that we tran= sitioned into a frequency greater than or equal to the configurable frequen= cy. One can also use inversion to track cycles when we were less than the c= onfigured frequency.", + "Unit": "PCU" + }, + { + "BriefDescription": "Current Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_P_FREQ_MAX_CURRENT_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when current is = the upper limit on frequency.", + "Unit": "PCU" + }, + { + "BriefDescription": "Thermal Strongest Upper Limit Cycles", "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES", - "MetricExpr": "(UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES / UNC_P_CLOCKT= ICKS) * 100.", - "MetricName": "freq_max_limit_thermal_cycles %", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when thermal con= ditions are the upper limit on frequency. This is related to the THERMAL_T= HROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are abo= ve the thermal temperature. This event (STRONGEST_UPPER_LIMIT) is sampled = at the output of the algorithm that determines the actual frequency, while = THERMAL_THROTTLE looks at the input.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles when the OS is th= e upper limit on frequency", + "BriefDescription": "OS Strongest Upper Limit Cycles", "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_P_FREQ_MAX_OS_CYCLES", - "MetricExpr": "(UNC_P_FREQ_MAX_OS_CYCLES / UNC_P_CLOCKTICKS) * 100= .", - "MetricName": "freq_max_os_cycles %", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the OS is t= he upper limit on frequency.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles when power is the= upper limit on frequency", + "BriefDescription": "Power Strongest Upper Limit Cycles", "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES", - "MetricExpr": "(UNC_P_FREQ_MAX_POWER_CYCLES / UNC_P_CLOCKTICKS) * = 100.", - "MetricName": "freq_max_power_cycles %", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when power is th= e upper limit on frequency.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles when current is t= he upper limit on frequency", + "BriefDescription": "IO P Limit Strongest Lower Limit Cycles", "Counter": "0,1,2,3", - "EventCode": "0x7", - "EventName": "UNC_P_FREQ_MAX_CURRENT_CYCLES", - "MetricExpr": "(UNC_P_FREQ_MAX_CURRENT_CYCLES / UNC_P_CLOCKTICKS) = * 100.", - "MetricName": "freq_max_current_cycles %", + "EventCode": "0x1", + "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES", + "ExtSel": "1", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when IO P Limit = is preventing us from dropping the frequency lower. This algorithm monitor= s the needs to the IO subsystem on both local and remote sockets and will m= aintain a frequency high enough to maintain good IO BW. This is necessary = for when all the IA cores on a socket are idle but a user still would like = to maintain high IO Bandwidth.", + "Unit": "PCU" + }, + { + "BriefDescription": "Perf P Limit Strongest Lower Limit Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_P_FREQ_MIN_PERF_P_CYCLES", + "ExtSel": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when Perf P Limi= t is preventing us from dropping the frequency lower. Perf P Limit is an a= lgorithm that takes input from remote sockets when determining if a socket = should drop it's frequency down. This is largely to minimize increases in = snoop and remote read latencies.", "Unit": "PCU" }, { "BriefDescription": "Cycles spent changing Frequency", "Counter": "0,1,2,3", "EventName": "UNC_P_FREQ_TRANS_CYCLES", - "MetricExpr": "(UNC_P_FREQ_TRANS_CYCLES / UNC_P_CLOCKTICKS) * 100.= ", - "MetricName": "freq_trans_cycles %", + "ExtSel": "1", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the system = is changing frequency. This can not be filtered by thread ID. One can als= o use it with the occupancy counter that monitors number of threads in C0 t= o estimate the performance impact that frequency transitions had on the sys= tem.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles that the uncore w= as running at a frequency greater than or equal to 1.2Ghz. Derived from unc= _p_freq_band0_cycles", + "BriefDescription": "Memory Phase Shedding Cycles", "Counter": "0,1,2,3", - "EventCode": "0xb", - "EventName": "UNC_P_FREQ_GE_1200MHZ_CYCLES", - "Filter": "filter_band0=3D12", - "MetricExpr": "(UNC_P_FREQ_GE_1200MHZ_CYCLES / UNC_P_CLOCKTICKS) *= 100.", - "MetricName": "freq_ge_1200mhz_cycles %", + "EventCode": "0x2f", + "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the PCU has= triggered memory phase shedding. This is a mode that can be run in the iM= C physicals that saves power at the expense of additional latency.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles that the uncore w= as running at a frequency greater than or equal to 2Ghz. Derived from unc_p= _freq_band1_cycles", + "BriefDescription": "Number of cores in C0", "Counter": "0,1,2,3", - "EventCode": "0xc", - "EventName": "UNC_P_FREQ_GE_2000MHZ_CYCLES", - "Filter": "filter_band1=3D20", - "MetricExpr": "(UNC_P_FREQ_GE_2000MHZ_CYCLES / UNC_P_CLOCKTICKS) *= 100.", - "MetricName": "freq_ge_2000mhz_cycles %", + "EventCode": "0x80", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", "PerPkg": "1", + "PublicDescription": "This is an occupancy event that tracks the n= umber of cores that are in C0. It can be used by itself to get the average= number of cores in C0, with threshholding to generate histograms, or with = other PCU events and occupancy triggering to capture other details.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles that the uncore w= as running at a frequency greater than or equal to 3Ghz. Derived from unc_p= _freq_band2_cycles", + "BriefDescription": "Number of cores in C0", "Counter": "0,1,2,3", - "EventCode": "0xd", - "EventName": "UNC_P_FREQ_GE_3000MHZ_CYCLES", - "Filter": "filter_band2=3D30", - "MetricExpr": "(UNC_P_FREQ_GE_3000MHZ_CYCLES / UNC_P_CLOCKTICKS) *= 100.", - "MetricName": "freq_ge_3000mhz_cycles %", + "EventCode": "0x80", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", "PerPkg": "1", + "PublicDescription": "This is an occupancy event that tracks the n= umber of cores that are in C0. It can be used by itself to get the average= number of cores in C0, with threshholding to generate histograms, or with = other PCU events and occupancy triggering to capture other details.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles that the uncore w= as running at a frequency greater than or equal to 4Ghz. Derived from unc_p= _freq_band3_cycles", + "BriefDescription": "Number of cores in C0", "Counter": "0,1,2,3", - "EventCode": "0xe", - "EventName": "UNC_P_FREQ_GE_4000MHZ_CYCLES", - "Filter": "filter_band3=3D40", - "MetricExpr": "(UNC_P_FREQ_GE_4000MHZ_CYCLES / UNC_P_CLOCKTICKS) *= 100.", - "MetricName": "freq_ge_4000mhz_cycles %", + "EventCode": "0x80", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", "PerPkg": "1", + "PublicDescription": "This is an occupancy event that tracks the n= umber of cores that are in C0. It can be used by itself to get the average= number of cores in C0, with threshholding to generate histograms, or with = other PCU events and occupancy triggering to capture other details.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of times that the uncore tr= ansitioned to a frequency greater than or equal to 1.2Ghz. Derived from unc= _p_freq_band0_cycles", + "BriefDescription": "External Prochot", + "Counter": "0,1,2,3", + "EventCode": "0xa", + "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that we are in e= xternal PROCHOT mode. This mode is triggered when a sensor off the die det= ermines that something off-die (like DRAM) is too hot and must throttle to = avoid damaging the chip.", + "Unit": "PCU" + }, + { + "BriefDescription": "Internal Prochot", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that we are in I= nteral PROCHOT mode. This mode is triggered when a sensor on the die deter= mines that we are too hot and must throttle to avoid damaging the chip.", + "Unit": "PCU" + }, + { + "BriefDescription": "Total Core C State Transition Cycles", "Counter": "0,1,2,3", "EventCode": "0xb", - "EventName": "UNC_P_FREQ_GE_1200MHZ_TRANSITIONS", - "Filter": "edge=3D1,filter_band0=3D12", - "MetricExpr": "(UNC_P_FREQ_GE_1200MHZ_CYCLES / UNC_P_CLOCKTICKS) *= 100.", - "MetricName": "freq_ge_1200mhz_cycles %", + "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES", + "ExtSel": "1", "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions across all cores.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of times that the uncore tr= ansitioned to a frequency greater than or equal to 2Ghz. Derived from unc_p= _freq_band1_cycles", + "BriefDescription": "Cycles Changing Voltage", "Counter": "0,1,2,3", - "EventCode": "0xc", - "EventName": "UNC_P_FREQ_GE_2000MHZ_TRANSITIONS", - "Filter": "edge=3D1,filter_band1=3D20", - "MetricExpr": "(UNC_P_FREQ_GE_2000MHZ_CYCLES / UNC_P_CLOCKTICKS) *= 100.", - "MetricName": "freq_ge_2000mhz_cycles %", + "EventCode": "0x3", + "EventName": "UNC_P_VOLT_TRANS_CYCLES_CHANGE", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the system = is changing voltage. There is no filtering supported with this event. One= can use it as a simple event, or use it conjunction with the occupancy eve= nts to monitor the number of cores or threads that were impacted by the tra= nsition. This event is calculated by or'ing together the increasing and de= creasing events.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles that the uncore t= ransitioned to a frequency greater than or equal to 3Ghz. Derived from unc_= p_freq_band2_cycles", + "BriefDescription": "Cycles Decreasing Voltage", "Counter": "0,1,2,3", - "EventCode": "0xd", - "EventName": "UNC_P_FREQ_GE_3000MHZ_TRANSITIONS", - "Filter": "edge=3D1,filter_band2=3D30", - "MetricExpr": "(UNC_P_FREQ_GE_3000MHZ_CYCLES / UNC_P_CLOCKTICKS) *= 100.", - "MetricName": "freq_ge_3000mhz_cycles %", + "EventCode": "0x2", + "EventName": "UNC_P_VOLT_TRANS_CYCLES_DECREASE", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the system = is decreasing voltage. There is no filtering supported with this event. O= ne can use it as a simple event, or use it conjunction with the occupancy e= vents to monitor the number of cores or threads that were impacted by the t= ransition.", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles that the uncore t= ransitioned to a frequency greater than or equal to 4Ghz. Derived from unc_= p_freq_band3_cycles", + "BriefDescription": "Cycles Increasing Voltage", "Counter": "0,1,2,3", - "EventCode": "0xe", - "EventName": "UNC_P_FREQ_GE_4000MHZ_TRANSITIONS", - "Filter": "edge=3D1,filter_band3=3D40", - "MetricExpr": "(UNC_P_FREQ_GE_4000MHZ_CYCLES / UNC_P_CLOCKTICKS) *= 100.", - "MetricName": "freq_ge_4000mhz_cycles %", + "EventCode": "0x1", + "EventName": "UNC_P_VOLT_TRANS_CYCLES_INCREASE", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the system = is increasing voltage. There is no filtering supported with this event. O= ne can use it as a simple event, or use it conjunction with the occupancy e= vents to monitor the number of cores or threads that were impacted by the t= ransition.", + "Unit": "PCU" + }, + { + "BriefDescription": "VR Hot", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_P_VR_HOT_CYCLES", "PerPkg": "1", "Unit": "PCU" } diff --git a/tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json b/= tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json index 4dd136d00a10..98362abba1a7 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json @@ -146,4 +146,4 @@ "SampleAfterValue": "100007", "UMask": "0x20" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 4b8e248d6588..370106fe2076 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -14,7 +14,7 @@ GenuineIntel-6-(7D|7E|A7),v1.14,icelake,core GenuineIntel-6-6[AC],v1.15,icelakex,core GenuineIntel-6-3A,v22,ivybridge,core GenuineIntel-6-3E,v21,ivytown,core -GenuineIntel-6-2D,v20,jaketown,core +GenuineIntel-6-2D,v21,jaketown,core GenuineIntel-6-57,v9,knightslanding,core GenuineIntel-6-85,v9,knightslanding,core GenuineIntel-6-1E,v2,nehalemep,core --=20 2.37.1.359.gd136c6c3e2-goog From nobody Wed Apr 15 05:45:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8AE34C04A68 for ; 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Wed, 27 Jul 2022 15:09:29 -0700 (PDT) Date: Wed, 27 Jul 2022 15:08:19 -0700 In-Reply-To: <20220727220832.2865794-1-irogers@google.com> Message-Id: <20220727220832.2865794-18-irogers@google.com> Mime-Version: 1.0 References: <20220727220832.2865794-1-irogers@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH v3 17/30] perf vendor events: Update Intel knightslanding From: Ian Rogers To: perry.taylor@intel.com, caleb.biggers@intel.com, kshipra.bopardikar@intel.com, Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Sedat Dilek Cc: Stephane Eranian , Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Update to v9, the metrics are based on TMA 4.4 full. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/downloa= d_and_gen.py to download and generate the latest events and metrics. Manually copy the knightslanding files into perf and update mapfile.csv. Tested on a non-knightslanding with 'perf test': 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok Note: uncore-memory has become uncore-other as the topic was determined this way in the conversion scripts. For simplicity the scripts naming is maintained. Signed-off-by: Ian Rogers --- .../arch/x86/knightslanding/cache.json | 2 +- .../x86/knightslanding/floating-point.json | 2 +- .../arch/x86/knightslanding/frontend.json | 2 +- .../arch/x86/knightslanding/memory.json | 2 +- .../arch/x86/knightslanding/pipeline.json | 2 +- .../x86/knightslanding/uncore-memory.json | 42 - .../arch/x86/knightslanding/uncore-other.json | 3890 +++++++++++++++++ .../x86/knightslanding/virtual-memory.json | 2 +- tools/perf/pmu-events/arch/x86/mapfile.csv | 3 +- 9 files changed, 3897 insertions(+), 50 deletions(-) delete mode 100644 tools/perf/pmu-events/arch/x86/knightslanding/uncore-me= mory.json create mode 100644 tools/perf/pmu-events/arch/x86/knightslanding/uncore-ot= her.json diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/cache.json b/too= ls/perf/pmu-events/arch/x86/knightslanding/cache.json index 1bd50b186e93..5e10eabda300 100644 --- a/tools/perf/pmu-events/arch/x86/knightslanding/cache.json +++ b/tools/perf/pmu-events/arch/x86/knightslanding/cache.json @@ -2300,4 +2300,4 @@ "SampleAfterValue": "100007", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/floating-point.j= son b/tools/perf/pmu-events/arch/x86/knightslanding/floating-point.json index 5fce5020efa1..ff5db600e420 100644 --- a/tools/perf/pmu-events/arch/x86/knightslanding/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/knightslanding/floating-point.json @@ -26,4 +26,4 @@ "SampleAfterValue": "200003", "UMask": "0x20" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json b/= tools/perf/pmu-events/arch/x86/knightslanding/frontend.json index d075ab594d75..63343a0d1e86 100644 --- a/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json +++ b/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json @@ -55,4 +55,4 @@ "SampleAfterValue": "200003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/memory.json b/to= ols/perf/pmu-events/arch/x86/knightslanding/memory.json index 5e6ca6896af1..2611defaeaa2 100644 --- a/tools/perf/pmu-events/arch/x86/knightslanding/memory.json +++ b/tools/perf/pmu-events/arch/x86/knightslanding/memory.json @@ -1107,4 +1107,4 @@ "SampleAfterValue": "100007", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json b/= tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json index 8f4213e5fbfd..1f13bc2686cb 100644 --- a/tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json @@ -374,4 +374,4 @@ "SampleAfterValue": "2000003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-memory.js= on b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-memory.json deleted file mode 100644 index e3bcd86c4f56..000000000000 --- a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-memory.json +++ /dev/null @@ -1,42 +0,0 @@ -[ - { - "BriefDescription": "ddr bandwidth read (CPU traffic only) (MB/sec= ). ", - "Counter": "0,1,2,3", - "EventCode": "0x03", - "EventName": "UNC_M_CAS_COUNT.RD", - "PerPkg": "1", - "ScaleUnit": "6.4e-05MiB", - "UMask": "0x01", - "Unit": "imc" - }, - { - "BriefDescription": "ddr bandwidth write (CPU traffic only) (MB/se= c). ", - "Counter": "0,1,2,3", - "EventCode": "0x03", - "EventName": "UNC_M_CAS_COUNT.WR", - "PerPkg": "1", - "ScaleUnit": "6.4e-05MiB", - "UMask": "0x02", - "Unit": "imc" - }, - { - "BriefDescription": "mcdram bandwidth read (CPU traffic only) (MB/= sec). ", - "Counter": "0,1,2,3", - "EventCode": "0x01", - "EventName": "UNC_E_RPQ_INSERTS", - "PerPkg": "1", - "ScaleUnit": "6.4e-05MiB", - "UMask": "0x01", - "Unit": "edc_eclk" - }, - { - "BriefDescription": "mcdram bandwidth write (CPU traffic only) (MB= /sec). ", - "Counter": "0,1,2,3", - "EventCode": "0x02", - "EventName": "UNC_E_WPQ_INSERTS", - "PerPkg": "1", - "ScaleUnit": "6.4e-05MiB", - "UMask": "0x01", - "Unit": "edc_eclk" - } -] diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.jso= n b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json new file mode 100644 index 000000000000..a87d7431ef45 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json @@ -0,0 +1,3890 @@ +[ + { + "BriefDescription": "Counts the number of read requests and stream= ing stores that hit in MCDRAM cache and the data in MCDRAM is clean with re= spect to DDR. This event is only valid in cache and hybrid memory mode.", + "Counter": "0,1,2,3", + "EventCode": "0x02", + "EventName": "UNC_E_EDC_ACCESS.HIT_CLEAN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "EDC_UCLK" + }, + { + "BriefDescription": "Counts the number of read requests and stream= ing stores that hit in MCDRAM cache and the data in MCDRAM is dirty with re= spect to DDR. This event is only valid in cache and hybrid memory mode. ", + "Counter": "0,1,2,3", + "EventCode": "0x02", + "EventName": "UNC_E_EDC_ACCESS.HIT_DIRTY", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "EDC_UCLK" + }, + { + "BriefDescription": "Counts the number of read requests and stream= ing stores that miss in MCDRAM cache and the data evicted from the MCDRAM i= s clean with respect to DDR. This event is only valid in cache and hybrid m= emory mode.", + "Counter": "0,1,2,3", + "EventCode": "0x02", + "EventName": "UNC_E_EDC_ACCESS.MISS_CLEAN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "EDC_UCLK" + }, + { + "BriefDescription": "Counts the number of read requests and stream= ing stores that miss in MCDRAM cache and the data evicted from the MCDRAM i= s dirty with respect to DDR. This event is only valid in cache and hybrid m= emory mode.", + "Counter": "0,1,2,3", + "EventCode": "0x02", + "EventName": "UNC_E_EDC_ACCESS.MISS_DIRTY", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "EDC_UCLK" + }, + { + "BriefDescription": "Number of EDC Hits or Misses. Miss I", + "Counter": "0,1,2,3", + "EventCode": "0x02", + "EventName": "UNC_E_EDC_ACCESS.MISS_INVALID", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "EDC_UCLK" + }, + { + "BriefDescription": "ECLK count", + "Counter": "0,1,2,3", + "EventName": "UNC_E_E_CLOCKTICKS", + "PerPkg": "1", + "Unit": "EDC_ECLK" + }, + { + "BriefDescription": "Counts the number of read requests received b= y the MCDRAM controller. This event is valid in all three memory modes: fla= t, cache and hybrid. In cache and hybrid memory mode, this event counts all= read requests as well as streaming stores that hit or miss in the MCDRAM c= ache. ", + "Counter": "0,1,2,3", + "EventCode": "0x01", + "EventName": "UNC_E_RPQ_INSERTS", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "EDC_ECLK" + }, + { + "BriefDescription": "UCLK count", + "Counter": "0,1,2,3", + "EventName": "UNC_E_U_CLOCKTICKS", + "PerPkg": "1", + "Unit": "EDC_UCLK" + }, + { + "BriefDescription": "Counts the number of write requests received = by the MCDRAM controller. This event is valid in all three memory modes: fl= at, cache and hybrid. In cache and hybrid memory mode, this event counts al= l streaming stores, writebacks and, read requests that miss in MCDRAM cache= .", + "Counter": "0,1,2,3", + "EventCode": "0x02", + "EventName": "UNC_E_WPQ_INSERTS", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "EDC_ECLK" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress= 0", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress= 1", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress= 2", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress= 3", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress= 4", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress= 5", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress= 6", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress= 7", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress= 0-7", + "Counter": "0,1,2,3", + "EventCode": "0x81", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED_EXT.ANY_OF_TGR0_THRU_TGR7", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress= 8", + "Counter": "0,1,2,3", + "EventCode": "0x81", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED_EXT.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgres= s 0", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgres= s 1", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgres= s 2", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgres= s 3", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgres= s 4", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgres= s 5", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgres= s 6", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgres= s 7", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgres= s 0-7", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY_EXT.ANY_OF_TGR0_THRU_TGR7= ", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgres= s 8", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY_EXT.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress= 0", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress= 1", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress= 2", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress= 3", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress= 4", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress= 5", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress= 6", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress= 7", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress= 0-7", + "Counter": "0,1,2,3", + "EventCode": "0x89", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED_EXT.ANY_OF_TGR0_THRU_TGR7", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress= 8", + "Counter": "0,1,2,3", + "EventCode": "0x89", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED_EXT.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgres= s 0", + "Counter": "0,1,2,3", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgres= s 1", + "Counter": "0,1,2,3", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgres= s 2", + "Counter": "0,1,2,3", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgres= s 3", + "Counter": "0,1,2,3", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgres= s 4", + "Counter": "0,1,2,3", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgres= s 5", + "Counter": "0,1,2,3", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgres= s 6", + "Counter": "0,1,2,3", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgres= s 7", + "Counter": "0,1,2,3", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgres= s 0-7", + "Counter": "0,1,2,3", + "EventCode": "0x8B", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY_EXT.ANY_OF_TGR0_THRU_TGR7= ", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgres= s 8", + "Counter": "0,1,2,3", + "EventCode": "0x8B", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY_EXT.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 0", + "Counter": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 1", + "Counter": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 2", + "Counter": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 3", + "Counter": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 4", + "Counter": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 5", + "Counter": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 6", + "Counter": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 7", + "Counter": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 0-7", + "Counter": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD_EXT.ANY_OF_TGR= 0_THRU_TGR7", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 8", + "Counter": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD_EXT.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 0", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 1", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 2", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 3", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 4", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 5", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 6", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 7", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 0-7", + "Counter": "0,1,2,3", + "EventCode": "0xD5", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL_EXT.ANY_OF_TGR= 0_THRU_TGR7", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 8", + "Counter": "0,1,2,3", + "EventCode": "0xD5", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL_EXT.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress= 0", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress= 1", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress= 2", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress= 3", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress= 4", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress= 5", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress= 6", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress= 7", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress= 0-7", + "Counter": "0,1,2,3", + "EventCode": "0x85", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED_EXT.ANY_OF_TGR0_THRU_TGR7", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress= 8", + "Counter": "0,1,2,3", + "EventCode": "0x85", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED_EXT.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgres= s 0", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgres= s 1", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgres= s 2", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgres= s 3", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgres= s 4", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgres= s 5", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgres= s 6", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgres= s 7", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgres= s 0-7", + "Counter": "0,1,2,3", + "EventCode": "0x87", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY_EXT.ANY_OF_TGR0_THRU_TGR7= ", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgres= s 8", + "Counter": "0,1,2,3", + "EventCode": "0x87", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY_EXT.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress= 0", + "Counter": "0,1,2,3", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress= 1", + "Counter": "0,1,2,3", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress= 2", + "Counter": "0,1,2,3", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress= 3", + "Counter": "0,1,2,3", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress= 4", + "Counter": "0,1,2,3", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress= 5", + "Counter": "0,1,2,3", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress= 6", + "Counter": "0,1,2,3", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress= 7", + "Counter": "0,1,2,3", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress= 0-7", + "Counter": "0,1,2,3", + "EventCode": "0x8D", + "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED_EXT.ANY_OF_TGR0_THRU_TGR7", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress= 8", + "Counter": "0,1,2,3", + "EventCode": "0x8D", + "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED_EXT.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgres= s 0", + "Counter": "0,1,2,3", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgres= s 1", + "Counter": "0,1,2,3", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgres= s 2", + "Counter": "0,1,2,3", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgres= s 3", + "Counter": "0,1,2,3", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgres= s 4", + "Counter": "0,1,2,3", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgres= s 5", + "Counter": "0,1,2,3", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgres= s 6", + "Counter": "0,1,2,3", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgres= s 7", + "Counter": "0,1,2,3", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgres= s 0-7", + "Counter": "0,1,2,3", + "EventCode": "0x8F", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY_EXT.ANY_OF_TGR0_THRU_TGR7= ", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgres= s 8", + "Counter": "0,1,2,3", + "EventCode": "0x8F", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY_EXT.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 0", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 1", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 2", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 3", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 4", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 5", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 6", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 7", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 0-7", + "Counter": "0,1,2,3", + "EventCode": "0xD3", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD_EXT.ANY_OF_TGR= 0_THRU_TGR7", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 8", + "Counter": "0,1,2,3", + "EventCode": "0xD3", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD_EXT.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 0", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 1", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 2", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 3", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 4", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 5", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 6", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 7", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 0-7", + "Counter": "0,1,2,3", + "EventCode": "0xD7", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL_EXT.ANY_OF_TGR= 0_THRU_TGR7", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 8", + "Counter": "0,1,2,3", + "EventCode": "0xD7", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL_EXT.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups. Counts the number of times the= LLC was accessed. Writeback transactions from L2 to the LLC This includes= all write transactions -- both Cachable and UC.", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_H_CACHE_LINES_VICTIMIZED.E_STATE", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups. Counts the number of times the= LLC was accessed. Filters for any transaction originating from the IPQ or = IRQ. This does not include lookups originating from the ISMQ.", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_H_CACHE_LINES_VICTIMIZED.F_STATE", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized that Match NID", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_H_CACHE_LINES_VICTIMIZED.LOCAL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups. Counts the number of times the= LLC was accessed. Read transactions", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_H_CACHE_LINES_VICTIMIZED.M_STATE", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized that Does Not Match NID", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_H_CACHE_LINES_VICTIMIZED.REMOTE", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups. Counts the number of times the= LLC was accessed. Filters for only snoop requests coming from the remote s= ocket(s) through the IPQ.", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_H_CACHE_LINES_VICTIMIZED.S_STATE", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Uncore Clocks", + "Counter": "0,1,2,3", + "EventCode": "0xC0", + "EventName": "UNC_H_CLOCK", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used", + "Counter": "0,1,2,3", + "EventCode": "0x9D", + "EventName": "UNC_H_EGRESS_HORZ_ADS_USED.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used", + "Counter": "0,1,2,3", + "EventCode": "0x9D", + "EventName": "UNC_H_EGRESS_HORZ_ADS_USED.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used", + "Counter": "0,1,2,3", + "EventCode": "0x9D", + "EventName": "UNC_H_EGRESS_HORZ_ADS_USED.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Bypass. AD ring", + "Counter": "0,1,2,3", + "EventCode": "0x9F", + "EventName": "UNC_H_EGRESS_HORZ_BYPASS.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Bypass. AK ring", + "Counter": "0,1,2,3", + "EventCode": "0x9F", + "EventName": "UNC_H_EGRESS_HORZ_BYPASS.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Bypass. BL ring", + "Counter": "0,1,2,3", + "EventCode": "0x9F", + "EventName": "UNC_H_EGRESS_HORZ_BYPASS.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Bypass. IV ring", + "Counter": "0,1,2,3", + "EventCode": "0x9F", + "EventName": "UNC_H_EGRESS_HORZ_BYPASS.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full AD= ", + "Counter": "0,1,2,3", + "EventCode": "0x96", + "EventName": "UNC_H_EGRESS_HORZ_CYCLES_FULL.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full AK= ", + "Counter": "0,1,2,3", + "EventCode": "0x96", + "EventName": "UNC_H_EGRESS_HORZ_CYCLES_FULL.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full BL= ", + "Counter": "0,1,2,3", + "EventCode": "0x96", + "EventName": "UNC_H_EGRESS_HORZ_CYCLES_FULL.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full IV= ", + "Counter": "0,1,2,3", + "EventCode": "0x96", + "EventName": "UNC_H_EGRESS_HORZ_CYCLES_FULL.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty AD", + "Counter": "0,1,2,3", + "EventCode": "0x97", + "EventName": "UNC_H_EGRESS_HORZ_CYCLES_NE.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty AK", + "Counter": "0,1,2,3", + "EventCode": "0x97", + "EventName": "UNC_H_EGRESS_HORZ_CYCLES_NE.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty BL", + "Counter": "0,1,2,3", + "EventCode": "0x97", + "EventName": "UNC_H_EGRESS_HORZ_CYCLES_NE.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty IV", + "Counter": "0,1,2,3", + "EventCode": "0x97", + "EventName": "UNC_H_EGRESS_HORZ_CYCLES_NE.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts AD", + "Counter": "0,1,2,3", + "EventCode": "0x95", + "EventName": "UNC_H_EGRESS_HORZ_INSERTS.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts AK", + "Counter": "0,1,2,3", + "EventCode": "0x95", + "EventName": "UNC_H_EGRESS_HORZ_INSERTS.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts BL", + "Counter": "0,1,2,3", + "EventCode": "0x95", + "EventName": "UNC_H_EGRESS_HORZ_INSERTS.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts IV", + "Counter": "0,1,2,3", + "EventCode": "0x95", + "EventName": "UNC_H_EGRESS_HORZ_INSERTS.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs", + "Counter": "0,1,2,3", + "EventCode": "0x99", + "EventName": "UNC_H_EGRESS_HORZ_NACK.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs", + "Counter": "0,1,2,3", + "EventCode": "0x99", + "EventName": "UNC_H_EGRESS_HORZ_NACK.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs", + "Counter": "0,1,2,3", + "EventCode": "0x99", + "EventName": "UNC_H_EGRESS_HORZ_NACK.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs", + "Counter": "0,1,2,3", + "EventCode": "0x99", + "EventName": "UNC_H_EGRESS_HORZ_NACK.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy AD", + "Counter": "0,1,2,3", + "EventCode": "0x94", + "EventName": "UNC_H_EGRESS_HORZ_OCCUPANCY.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy AK", + "Counter": "0,1,2,3", + "EventCode": "0x94", + "EventName": "UNC_H_EGRESS_HORZ_OCCUPANCY.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy BL", + "Counter": "0,1,2,3", + "EventCode": "0x94", + "EventName": "UNC_H_EGRESS_HORZ_OCCUPANCY.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy IV", + "Counter": "0,1,2,3", + "EventCode": "0x94", + "EventName": "UNC_H_EGRESS_HORZ_OCCUPANCY.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation", + "Counter": "0,1,2,3", + "EventCode": "0x9B", + "EventName": "UNC_H_EGRESS_HORZ_STARVED.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation", + "Counter": "0,1,2,3", + "EventCode": "0x9B", + "EventName": "UNC_H_EGRESS_HORZ_STARVED.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation", + "Counter": "0,1,2,3", + "EventCode": "0x9B", + "EventName": "UNC_H_EGRESS_HORZ_STARVED.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation", + "Counter": "0,1,2,3", + "EventCode": "0x9B", + "EventName": "UNC_H_EGRESS_HORZ_STARVED.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts number of cycles IV was blocked in the= TGR Egress due to SNP/GO Ordering requirements", + "Counter": "0,1,2,3", + "EventCode": "0xAE", + "EventName": "UNC_H_EGRESS_ORDERING.IV_SNP_GO_DN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts number of cycles IV was blocked in the= TGR Egress due to SNP/GO Ordering requirements", + "Counter": "0,1,2,3", + "EventCode": "0xAE", + "EventName": "UNC_H_EGRESS_ORDERING.IV_SNP_GO_UP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used", + "Counter": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "UNC_H_EGRESS_VERT_ADS_USED.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used", + "Counter": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "UNC_H_EGRESS_VERT_ADS_USED.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used", + "Counter": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "UNC_H_EGRESS_VERT_ADS_USED.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used", + "Counter": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "UNC_H_EGRESS_VERT_ADS_USED.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used", + "Counter": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "UNC_H_EGRESS_VERT_ADS_USED.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used", + "Counter": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "UNC_H_EGRESS_VERT_ADS_USED.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Bypass. AD ring agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_H_EGRESS_VERT_BYPASS.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Bypass. AD ring agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_H_EGRESS_VERT_BYPASS.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Bypass. AK ring agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_H_EGRESS_VERT_BYPASS.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Bypass. AK ring agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_H_EGRESS_VERT_BYPASS.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Bypass. BL ring agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_H_EGRESS_VERT_BYPASS.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Bypass. BL ring agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_H_EGRESS_VERT_BYPASS.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Bypass. IV ring agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_H_EGRESS_VERT_BYPASS.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full AD -= Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full AD -= Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full AK -= Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full AK -= Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full BL -= Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full BL -= Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full IV -= Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.IV_AG0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= IV - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.IV_AG0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_H_EGRESS_VERT_INSERTS.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_H_EGRESS_VERT_INSERTS.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_H_EGRESS_VERT_INSERTS.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_H_EGRESS_VERT_INSERTS.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_H_EGRESS_VERT_INSERTS.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_H_EGRESS_VERT_INSERTS.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations IV - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_H_EGRESS_VERT_INSERTS.IV_AG0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_H_EGRESS_VERT_NACK.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_H_EGRESS_VERT_NACK.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs Onto AK Ring", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_H_EGRESS_VERT_NACK.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_H_EGRESS_VERT_NACK.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs Onto BL Ring", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_H_EGRESS_VERT_NACK.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_H_EGRESS_VERT_NACK.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_H_EGRESS_VERT_NACK.IV_AG0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy IV - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.IV_AG0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_H_EGRESS_VERT_STARVED.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_H_EGRESS_VERT_STARVED.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation Onto= AK Ring", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_H_EGRESS_VERT_STARVED.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_H_EGRESS_VERT_STARVED.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation Onto= BL Ring", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_H_EGRESS_VERT_STARVED.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_H_EGRESS_VERT_STARVED.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_H_EGRESS_VERT_STARVED.IV_AG0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts cycles source throttling is adderted -= horizontal", + "Counter": "0,1,2,3", + "EventCode": "0xA5", + "EventName": "UNC_H_FAST_ASSERTED.HORZ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts cycles source throttling is adderted -= vertical", + "Counter": "0,1,2,3", + "EventCode": "0xA5", + "EventName": "UNC_H_FAST_ASSERTED.VERT", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Horizont= al AD ring is being used at this ring stop - Left and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA7", + "EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Horizont= al AD ring is being used at this ring stop - Left and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA7", + "EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Horizont= al AD ring is being used at this ring stop - Right and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA7", + "EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Horizont= al AD ring is being used at this ring stop - Right and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA7", + "EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Horizont= al AK ring is being used at this ring stop - Left and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA9", + "EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Horizont= al AK ring is being used at this ring stop - Left and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA9", + "EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Horizont= al AK ring is being used at this ring stop - Right and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA9", + "EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Horizont= al AK ring is being used at this ring stop - Right and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA9", + "EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Horizont= al BL ring is being used at this ring stop - Left and Even", + "Counter": "0,1,2,3", + "EventCode": "0xAB", + "EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Horizont= al BL ring is being used at this ring stop - Left and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xAB", + "EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Horizont= al BL ring is being used at this ring stop - Right and Even", + "Counter": "0,1,2,3", + "EventCode": "0xAB", + "EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Horizont= al BL ring is being used at this ring stop - Right and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xAB", + "EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Horizont= al IV ring is being used at this ring stop - Left", + "Counter": "0,1,2,3", + "EventCode": "0xAD", + "EventName": "UNC_H_HORZ_RING_IV_IN_USE.LEFT", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Horizont= al IV ring is being used at this ring stop - Right", + "Counter": "0,1,2,3", + "EventCode": "0xAD", + "EventName": "UNC_H_HORZ_RING_IV_IN_USE.RIGHT", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Allocations. Counts number of allocat= ions per cycle into the specified Ingress queue. - IPQ", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_H_INGRESS_INSERTS.IPQ", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Allocations. Counts number of allocat= ions per cycle into the specified Ingress queue. - IRQ", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_H_INGRESS_INSERTS.IRQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Allocations. Counts number of allocat= ions per cycle into the specified Ingress queue. - IRQ Rejected", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_H_INGRESS_INSERTS.IRQ_REJ", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Allocations. Counts number of allocat= ions per cycle into the specified Ingress queue. - PRQ", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_H_INGRESS_INSERTS.PRQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Allocations. Counts number of allocat= ions per cycle into the specified Ingress queue. - PRQ Rejected", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_H_INGRESS_INSERTS.PRQ_REJ", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles with the IPQ in Internal Starvation.", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_H_INGRESS_INT_STARVED.IPQ", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles with the IRQ in Internal Starvation.", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_H_INGRESS_INT_STARVED.IRQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles with the ISMQ in Internal Starvation.", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_H_INGRESS_INT_STARVED.ISMQ", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress internal starvation cycles. Counts cy= cles in internal starvation. This occurs when one or more of the entries in= the ingress queue are being starved out by other entries in the queue.", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_H_INGRESS_INT_STARVED.PRQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Occupancy. Counts number of entries i= n the specified Ingress queue in each cycle. - IPQ", + "EventCode": "0x11", + "EventName": "UNC_H_INGRESS_OCCUPANCY.IPQ", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Occupancy. Counts number of entries i= n the specified Ingress queue in each cycle. - IRQ", + "EventCode": "0x11", + "EventName": "UNC_H_INGRESS_OCCUPANCY.IRQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Occupancy. Counts number of entries i= n the specified Ingress queue in each cycle. - IRQ Rejected", + "EventCode": "0x11", + "EventName": "UNC_H_INGRESS_OCCUPANCY.IRQ_REJ", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Occupancy. Counts number of entries i= n the specified Ingress queue in each cycle. - PRQ", + "EventCode": "0x11", + "EventName": "UNC_H_INGRESS_OCCUPANCY.PRQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Occupancy. Counts number of entries i= n the specified Ingress queue in each cycle. - PRQ Rejected", + "EventCode": "0x11", + "EventName": "UNC_H_INGRESS_OCCUPANCY.PRQ_REJ", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.ANY_REJECT_IPQ0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.ANY_REJECT_IRQ0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Queue Retries", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Queue Retries", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Queue Retries", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Queue Retries", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Queue Retries", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Queue Retries", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Queue Retries", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Queue Retries", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Queue Retries", + "Counter": "0,1,2,3", + "EventCode": "0x2F", + "EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Queue Retries", + "Counter": "0,1,2,3", + "EventCode": "0x2F", + "EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.ANY_REJECT_IRQ0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Queue Retries", + "Counter": "0,1,2,3", + "EventCode": "0x2F", + "EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Queue Retries", + "Counter": "0,1,2,3", + "EventCode": "0x2F", + "EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Queue Retries", + "Counter": "0,1,2,3", + "EventCode": "0x2F", + "EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.ANY_REJECT_IRQ0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ= (everything except for ISMQ)", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ= (everything except for ISMQ)", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ= (everything except for ISMQ)", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ= (everything except for ISMQ)", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ= (everything except for ISMQ)", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ= (everything except for ISMQ)", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ= (everything except for ISMQ)", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ= (everything except for ISMQ)", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ= (everything except for ISMQ)", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ= (everything except for ISMQ)", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.ANY_REJECT_IRQ0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ= (everything except for ISMQ)", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ= (everything except for ISMQ)", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ= (everything except for ISMQ)", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Miscellaneous events in the Cbo. CV0 Prefetch= Miss", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_H_MISC.CV0_PREF_MISS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Miscellaneous events in the Cbo. CV0 Prefetch= Victim", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_H_MISC.CV0_PREF_VIC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Miscellaneous events in the Cbo. RFO HitS", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_H_MISC.RFO_HIT_S", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Miscellaneous events in the Cbo. Silent Snoop= Eviction", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_H_MISC.RSPI_WAS_FSE", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Miscellaneous events in the Cbo. Write Combin= ing Aliasing", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_H_MISC.WC_ALIASING", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Number of incoming messages from the Horizont= al ring that were bounced, by ring type.", + "Counter": "0,1,2,3", + "EventCode": "0xA1", + "EventName": "UNC_H_RING_BOUNCES_HORZ.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Number of incoming messages from the Horizont= al ring that were bounced, by ring type - Acknowledgements to core", + "Counter": "0,1,2,3", + "EventCode": "0xA1", + "EventName": "UNC_H_RING_BOUNCES_HORZ.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Number of incoming messages from the Horizont= al ring that were bounced, by ring type - Data Responses to core.", + "Counter": "0,1,2,3", + "EventCode": "0xA1", + "EventName": "UNC_H_RING_BOUNCES_HORZ.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Number of incoming messages from the Horizont= al ring that were bounced, by ring type - Snoops of processor's cache.", + "Counter": "0,1,2,3", + "EventCode": "0xA1", + "EventName": "UNC_H_RING_BOUNCES_HORZ.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Number of incoming messages from the Vertical= ring that were bounced, by ring type.", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_H_RING_BOUNCES_VERT.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Number of incoming messages from the Vertical= ring that were bounced, by ring type - Acknowledgements to core", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_H_RING_BOUNCES_VERT.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Number of incoming messages from the Vertical= ring that were bounced, by ring type - Data Responses to core.", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_H_RING_BOUNCES_VERT.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Number of incoming messages from the Vertical= ring that were bounced, by ring type - Snoops of processor's cache.", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_H_RING_BOUNCES_VERT.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal ring sink starvation count - AD ri= ng", + "Counter": "0,1,2,3", + "EventCode": "0xA3", + "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal ring sink starvation count - AK ri= ng", + "Counter": "0,1,2,3", + "EventCode": "0xA3", + "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal ring sink starvation count - BL ri= ng", + "Counter": "0,1,2,3", + "EventCode": "0xA3", + "EventName": "UNC_H_RING_SINK_STARVED_HORZ.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal ring sink starvation count - IV ri= ng", + "Counter": "0,1,2,3", + "EventCode": "0xA3", + "EventName": "UNC_H_RING_SINK_STARVED_HORZ.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical ring sink starvation count - AD ring= ", + "Counter": "0,1,2,3", + "EventCode": "0xA2", + "EventName": "UNC_H_RING_SINK_STARVED_VERT.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical ring sink starvation count - AK ring= ", + "Counter": "0,1,2,3", + "EventCode": "0xA2", + "EventName": "UNC_H_RING_SINK_STARVED_VERT.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical ring sink starvation count - BL ring= ", + "Counter": "0,1,2,3", + "EventCode": "0xA2", + "EventName": "UNC_H_RING_SINK_STARVED_VERT.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical ring sink starvation count - IV ring= ", + "Counter": "0,1,2,3", + "EventCode": "0xA2", + "EventName": "UNC_H_RING_SINK_STARVED_VERT.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts cycles in throttle mode.", + "Counter": "0,1,2,3", + "EventCode": "0xA4", + "EventName": "UNC_H_RING_SRC_THRTL", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups. Counts the number of times the= LLC was accessed. Filters for any transaction originating from the IPQ or = IRQ. This does not include lookups originating from the ISMQ.", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_H_SF_LOOKUP.ANY", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups. Counts the number of times the= LLC was accessed. Read transactions", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_H_SF_LOOKUP.DATA_READ", + "PerPkg": "1", + "UMask": "0x03", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups. Counts the number of times the= LLC was accessed. Filters for only snoop requests coming from the remote s= ocket(s) through the IPQ.", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_H_SF_LOOKUP.REMOTE_SNOOP", + "PerPkg": "1", + "UMask": "0x09", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups. Counts the number of times the= LLC was accessed. Writeback transactions from L2 to the LLC This includes= all write transactions -- both Cachable and UC.", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_H_SF_LOOKUP.WRITE", + "PerPkg": "1", + "UMask": "0x05", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation. Counts cycle= s under injection starvation mode. This starvation is triggered when the C= MS Ingress cannot send a transaction onto the mesh for a long period of tim= e. In this case, because a message from the other queue has higher priorit= y", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_H_TG_INGRESS_BUSY_STARVED.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation. Counts cycle= s under injection starvation mode. This starvation is triggered when the C= MS Ingress cannot send a transaction onto the mesh for a long period of tim= e. In this case, because a message from the other queue has higher priorit= y", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_H_TG_INGRESS_BUSY_STARVED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation. Counts cycle= s under injection starvation mode. This starvation is triggered when the C= MS Ingress cannot send a transaction onto the mesh for a long period of tim= e. In this case, because a message from the other queue has higher priorit= y", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_H_TG_INGRESS_BUSY_STARVED.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation. Counts cycle= s under injection starvation mode. This starvation is triggered when the C= MS Ingress cannot send a transaction onto the mesh for a long period of tim= e. In this case, because a message from the other queue has higher priorit= y", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_H_TG_INGRESS_BUSY_STARVED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass. Number of packets = bypassing the CMS Ingress .", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_H_TG_INGRESS_BYPASS.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass. Number of packets = bypassing the CMS Ingress .", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_H_TG_INGRESS_BYPASS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass. Number of packets = bypassing the CMS Ingress .", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_H_TG_INGRESS_BYPASS.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass. Number of packets = bypassing the CMS Ingress .", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_H_TG_INGRESS_BYPASS.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass. Number of packets = bypassing the CMS Ingress .", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_H_TG_INGRESS_BYPASS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass. Number of packets = bypassing the CMS Ingress .", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_H_TG_INGRESS_BYPASS.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation. Counts cycle= s under injection starvation mode. This starvation is triggered when the C= MS Ingress cannot send a transaction onto the mesh for a long period of tim= e. In this case, the Ingress is unable to forward to the Egress due to a l= ack of credit.", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation. Counts cycle= s under injection starvation mode. This starvation is triggered when the C= MS Ingress cannot send a transaction onto the mesh for a long period of tim= e. In this case, the Ingress is unable to forward to the Egress due to a l= ack of credit.", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation. Counts cycle= s under injection starvation mode. This starvation is triggered when the C= MS Ingress cannot send a transaction onto the mesh for a long period of tim= e. In this case, the Ingress is unable to forward to the Egress due to a l= ack of credit.", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation. Counts cycle= s under injection starvation mode. This starvation is triggered when the C= MS Ingress cannot send a transaction onto the mesh for a long period of tim= e. In this case, the Ingress is unable to forward to the Egress due to a l= ack of credit.", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation. Counts cycle= s under injection starvation mode. This starvation is triggered when the C= MS Ingress cannot send a transaction onto the mesh for a long period of tim= e. In this case, the Ingress is unable to forward to the Egress due to a l= ack of credit.", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation. Counts cycle= s under injection starvation mode. This starvation is triggered when the C= MS Ingress cannot send a transaction onto the mesh for a long period of tim= e. In this case, the Ingress is unable to forward to the Egress due to a l= ack of credit.", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.IFV", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation. Counts cycle= s under injection starvation mode. This starvation is triggered when the C= MS Ingress cannot send a transaction onto the mesh for a long period of tim= e. In this case, the Ingress is unable to forward to the Egress due to a l= ack of credit.", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations. Number of all= ocations into the CMS Ingress The Ingress is used to queue up requests rec= eived from the mesh", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_H_TG_INGRESS_INSERTS.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations. Number of all= ocations into the CMS Ingress The Ingress is used to queue up requests rec= eived from the mesh", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_H_TG_INGRESS_INSERTS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations. Number of all= ocations into the CMS Ingress The Ingress is used to queue up requests rec= eived from the mesh", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_H_TG_INGRESS_INSERTS.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations. Number of all= ocations into the CMS Ingress The Ingress is used to queue up requests rec= eived from the mesh", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_H_TG_INGRESS_INSERTS.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations. Number of all= ocations into the CMS Ingress The Ingress is used to queue up requests rec= eived from the mesh", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_H_TG_INGRESS_INSERTS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations. Number of all= ocations into the CMS Ingress The Ingress is used to queue up requests rec= eived from the mesh", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_H_TG_INGRESS_INSERTS.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy. Occupancy event= for the Ingress buffers in the CMS The Ingress is used to queue up reques= ts received from the mesh", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_H_TG_INGRESS_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy. Occupancy event= for the Ingress buffers in the CMS The Ingress is used to queue up reques= ts received from the mesh", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_H_TG_INGRESS_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy. Occupancy event= for the Ingress buffers in the CMS The Ingress is used to queue up reques= ts received from the mesh", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_H_TG_INGRESS_OCCUPANCY.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy. Occupancy event= for the Ingress buffers in the CMS The Ingress is used to queue up reques= ts received from the mesh", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_H_TG_INGRESS_OCCUPANCY.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy. Occupancy event= for the Ingress buffers in the CMS The Ingress is used to queue up reques= ts received from the mesh", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_H_TG_INGRESS_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy. Occupancy event= for the Ingress buffers in the CMS The Ingress is used to queue up reques= ts received from the mesh", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_H_TG_INGRESS_OCCUPANCY.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Uncore Clocks", + "Counter": "0,1,2,3", + "EventName": "UNC_H_U_CLOCKTICKS", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Vertical= AD ring is being used at this ring stop - Down and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA6", + "EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Vertical= AD ring is being used at this ring stop - Down and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA6", + "EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Vertical= AD ring is being used at this ring stop - Up and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA6", + "EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Vertical= AD ring is being used at this ring stop - Up and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA6", + "EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Vertical= AK ring is being used at this ring stop - Down and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA8", + "EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Vertical= AK ring is being used at this ring stop - Down and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA8", + "EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Vertical= AK ring is being used at this ring stop - Up and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA8", + "EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Vertical= AK ring is being used at this ring stop - Up and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA8", + "EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Vertical= BL ring is being used at this ring stop - Down and Even", + "Counter": "0,1,2,3", + "EventCode": "0xAA", + "EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Vertical= BL ring is being used at this ring stop - Down and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xAA", + "EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Vertical= BL ring is being used at this ring stop - Up and Even", + "Counter": "0,1,2,3", + "EventCode": "0xAA", + "EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Vertical= BL ring is being used at this ring stop - Up and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xAA", + "EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Vertical= IV ring is being used at this ring stop - Down", + "Counter": "0,1,2,3", + "EventCode": "0xAC", + "EventName": "UNC_H_VERT_RING_IV_IN_USE.DN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Vertical= IV ring is being used at this ring stop - Up", + "Counter": "0,1,2,3", + "EventCode": "0xAC", + "EventName": "UNC_H_VERT_RING_IV_IN_USE.UP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full. Counts the numbe= r of cycles when the M2PCIe Egress is full. AD_0", + "Counter": "0,1,2,3", + "EventCode": "0x25", + "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AD_0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full. Counts the numbe= r of cycles when the M2PCIe Egress is full. AD_1", + "Counter": "0,1,2,3", + "EventCode": "0x25", + "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AD_1", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full. Counts the numbe= r of cycles when the M2PCIe Egress is full. AK_0", + "Counter": "0,1,2,3", + "EventCode": "0x25", + "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AK_0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full. Counts the numbe= r of cycles when the M2PCIe Egress is full. AK_1", + "Counter": "0,1,2,3", + "EventCode": "0x25", + "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AK_1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full. Counts the numbe= r of cycles when the M2PCIe Egress is full. BL_0", + "Counter": "0,1,2,3", + "EventCode": "0x25", + "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.BL_0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full. Counts the numbe= r of cycles when the M2PCIe Egress is full. BL_1", + "Counter": "0,1,2,3", + "EventCode": "0x25", + "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.BL_1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the = number of cycles when the M2PCIe Egress is not empty. AD_0", + "Counter": "0,1", + "EventCode": "0x23", + "EventName": "UNC_M2P_EGRESS_CYCLES_NE.AD_0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the = number of cycles when the M2PCIe Egress is not empty. AD_1", + "Counter": "0,1", + "EventCode": "0x23", + "EventName": "UNC_M2P_EGRESS_CYCLES_NE.AD_1", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the = number of cycles when the M2PCIe Egress is not empty. AK_0", + "Counter": "0,1", + "EventCode": "0x23", + "EventName": "UNC_M2P_EGRESS_CYCLES_NE.AK_0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the = number of cycles when the M2PCIe Egress is not empty. AK_1", + "Counter": "0,1", + "EventCode": "0x23", + "EventName": "UNC_M2P_EGRESS_CYCLES_NE.AK_1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the = number of cycles when the M2PCIe Egress is not empty. BL_0", + "Counter": "0,1", + "EventCode": "0x23", + "EventName": "UNC_M2P_EGRESS_CYCLES_NE.BL_0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the = number of cycles when the M2PCIe Egress is not empty. BL_1", + "Counter": "0,1", + "EventCode": "0x23", + "EventName": "UNC_M2P_EGRESS_CYCLES_NE.BL_1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress. Counts the number of= number of messages inserted into the the M2PCIe Egress queue. AD_0", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_M2P_EGRESS_INSERTS.AD_0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress. Counts the number of= number of messages inserted into the the M2PCIe Egress queue. AD_1", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_M2P_EGRESS_INSERTS.AD_1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress. Counts the number of= number of messages inserted into the the M2PCIe Egress queue. AK_0", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_M2P_EGRESS_INSERTS.AK_0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress. Counts the number of= number of messages inserted into the the M2PCIe Egress queue. AK_1", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_M2P_EGRESS_INSERTS.AK_1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress. Counts the number of= number of messages inserted into the the M2PCIe Egress queue. AK_CRD_0", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_M2P_EGRESS_INSERTS.AK_CRD_0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress. Counts the number of= number of messages inserted into the the M2PCIe Egress queue. AK_CRD_1", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_M2P_EGRESS_INSERTS.AK_CRD_1", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress. Counts the number of= number of messages inserted into the the M2PCIe Egress queue. BL_0", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_M2P_EGRESS_INSERTS.BL_0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress. Counts the number of= number of messages inserted into the the M2PCIe Egress queue. BL_1", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_M2P_EGRESS_INSERTS.BL_1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress Queue Cycles Not Empty. Counts the nu= mber of cycles when the M2PCIe Ingress is not empty.ALL", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "UNC_M2P_INGRESS_CYCLES_NE.ALL", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress Queue Cycles Not Empty. Counts the nu= mber of cycles when the M2PCIe Ingress is not empty.CBO_IDI", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "UNC_M2P_INGRESS_CYCLES_NE.CBO_IDI", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress Queue Cycles Not Empty. Counts the nu= mber of cycles when the M2PCIe Ingress is not empty.CBO_NCB", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "UNC_M2P_INGRESS_CYCLES_NE.CBO_NCB", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress Queue Cycles Not Empty. Counts the nu= mber of cycles when the M2PCIe Ingress is not empty.CBO_NCS", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "UNC_M2P_INGRESS_CYCLES_NE.CBO_NCS", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CAS All", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "UNC_M_CAS_COUNT.ALL", + "PerPkg": "1", + "UMask": "0x03", + "Unit": "iMC_DCLK" + }, + { + "BriefDescription": "CAS Reads", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "UNC_M_CAS_COUNT.RD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "iMC_DCLK" + }, + { + "BriefDescription": "CAS Writes", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "UNC_M_CAS_COUNT.WR", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "iMC_DCLK" + }, + { + "BriefDescription": "DCLK count", + "Counter": "0,1,2,3", + "EventName": "UNC_M_D_CLOCKTICKS", + "PerPkg": "1", + "Unit": "iMC_DCLK" + }, + { + "BriefDescription": "UCLK count", + "Counter": "0,1,2,3", + "EventName": "UNC_M_U_CLOCKTICKS", + "PerPkg": "1", + "Unit": "iMC_UCLK" + } +] diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.j= son b/tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.json index eda299ef5ff8..821cdd44a12f 100644 --- a/tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.json @@ -62,4 +62,4 @@ "SampleAfterValue": "100003", "UMask": "0x3" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 370106fe2076..cc42946cacd3 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -15,8 +15,7 @@ GenuineIntel-6-6[AC],v1.15,icelakex,core GenuineIntel-6-3A,v22,ivybridge,core GenuineIntel-6-3E,v21,ivytown,core GenuineIntel-6-2D,v21,jaketown,core -GenuineIntel-6-57,v9,knightslanding,core -GenuineIntel-6-85,v9,knightslanding,core +GenuineIntel-6-(57|85),v9,knightslanding,core GenuineIntel-6-1E,v2,nehalemep,core GenuineIntel-6-1F,v2,nehalemep,core GenuineIntel-6-1A,v2,nehalemep,core --=20 2.37.1.359.gd136c6c3e2-goog From nobody Wed Apr 15 05:45:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00B0EC04A68 for ; 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charset="utf-8" Events are v1.00, there are no metrics yet. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/downloa= d_and_gen.py to download and generate the events and metrics. Manually copy the meteorlake files into perf and update mapfile.csv. Tested on a non-meteorlake with 'perf test': 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok Signed-off-by: Ian Rogers --- tools/perf/pmu-events/arch/x86/mapfile.csv | 1 + .../pmu-events/arch/x86/meteorlake/cache.json | 262 ++++++++++++++++++ .../arch/x86/meteorlake/frontend.json | 24 ++ .../arch/x86/meteorlake/memory.json | 185 +++++++++++++ .../pmu-events/arch/x86/meteorlake/other.json | 46 +++ .../arch/x86/meteorlake/pipeline.json | 254 +++++++++++++++++ .../arch/x86/meteorlake/virtual-memory.json | 46 +++ 7 files changed, 818 insertions(+) create mode 100644 tools/perf/pmu-events/arch/x86/meteorlake/cache.json create mode 100644 tools/perf/pmu-events/arch/x86/meteorlake/frontend.json create mode 100644 tools/perf/pmu-events/arch/x86/meteorlake/memory.json create mode 100644 tools/perf/pmu-events/arch/x86/meteorlake/other.json create mode 100644 tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json create mode 100644 tools/perf/pmu-events/arch/x86/meteorlake/virtual-memor= y.json diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index cc42946cacd3..52e4d063ca6b 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -16,6 +16,7 @@ GenuineIntel-6-3A,v22,ivybridge,core GenuineIntel-6-3E,v21,ivytown,core GenuineIntel-6-2D,v21,jaketown,core GenuineIntel-6-(57|85),v9,knightslanding,core +GenuineIntel-6-AA,v1.00,meteorlake,core GenuineIntel-6-1E,v2,nehalemep,core GenuineIntel-6-1F,v2,nehalemep,core GenuineIntel-6-1A,v2,nehalemep,core diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/cache.json b/tools/p= erf/pmu-events/arch/x86/meteorlake/cache.json new file mode 100644 index 000000000000..32b2aa9b1475 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/meteorlake/cache.json @@ -0,0 +1,262 @@ +[ + { + "BriefDescription": "Counts the number of cacheable memory request= s that miss in the LLC. Counts on a per core basis.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x2e", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "UMask": "0x41", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of cacheable memory request= s that access the LLC. Counts on a per core basis.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x2e", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "UMask": "0x4f", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of load ops retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "UMask": "0x81", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of store ops retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "UMask": "0x82", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "CollectPEBSRecord": "3", + "Counter": "0,1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "TakenAlone": "1", + "UMask": "0x5", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "CollectPEBSRecord": "3", + "Counter": "0,1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "TakenAlone": "1", + "UMask": "0x5", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "CollectPEBSRecord": "3", + "Counter": "0,1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "TakenAlone": "1", + "UMask": "0x5", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "CollectPEBSRecord": "3", + "Counter": "0,1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "TakenAlone": "1", + "UMask": "0x5", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "CollectPEBSRecord": "3", + "Counter": "0,1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "TakenAlone": "1", + "UMask": "0x5", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "CollectPEBSRecord": "3", + "Counter": "0,1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "TakenAlone": "1", + "UMask": "0x5", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "CollectPEBSRecord": "3", + "Counter": "0,1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "TakenAlone": "1", + "UMask": "0x5", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "CollectPEBSRecord": "3", + "Counter": "0,1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "TakenAlone": "1", + "UMask": "0x5", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of stores uops retired sam= e as MEM_UOPS_RETIRED.ALL_STORES", + "CollectPEBSRecord": "3", + "Counter": "0,1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "UMask": "0x6", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "L2 code requests", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xe4", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Demand Data Read access L2 cache", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xe1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Core-originated cacheable requests that misse= d L3 (Except hardware prefetches to the L3)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x2e", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "UMask": "0x41", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Core-originated cacheable requests that refer= to L3 (Except hardware prefetches to the L3)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x2e", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "UMask": "0x4f", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired load instructions.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.ALL_LOADS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x81", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired store instructions.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.ALL_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x82", + "Unit": "cpu_core" + } +] diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/frontend.json b/tool= s/perf/pmu-events/arch/x86/meteorlake/frontend.json new file mode 100644 index 000000000000..9657768fc95a --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/meteorlake/frontend.json @@ -0,0 +1,24 @@ +[ + { + "BriefDescription": "Counts every time the code stream enters into= a new cache line by walking sequential from the previous line or being red= irected by a jump.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.ACCESSES", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "UMask": "0x3", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts every time the code stream enters into= a new cache line by walking sequential from the previous line or being red= irected by a jump and the instruction cache registers bytes are not present= . -", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "UMask": "0x2", + "Unit": "cpu_atom" + } +] diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/memory.json b/tools/= perf/pmu-events/arch/x86/meteorlake/memory.json new file mode 100644 index 000000000000..15b2294a8ae7 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/meteorlake/memory.json @@ -0,0 +1,185 @@ +[ + { + "BriefDescription": "Counts cacheable demand data reads were not s= upplied by the L3 cache.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00001", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts demand reads for ownership, including = SWPREFETCHW which is an RFO were not supplied by the L3 cache.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_RFO.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00002", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 128 cycles.", + "CollectPEBSRecord": "2", + "Counter": "1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "1009", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 16 cycles.", + "CollectPEBSRecord": "2", + "Counter": "1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "20011", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 256 cycles.", + "CollectPEBSRecord": "2", + "Counter": "1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "503", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 32 cycles.", + "CollectPEBSRecord": "2", + "Counter": "1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 4 cycles.", + "CollectPEBSRecord": "2", + "Counter": "1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 512 cycles.", + "CollectPEBSRecord": "2", + "Counter": "1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "101", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 64 cycles.", + "CollectPEBSRecord": "2", + "Counter": "1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "2003", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 8 cycles.", + "CollectPEBSRecord": "2", + "Counter": "1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "50021", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired memory store access operations. A PDi= st event for PEBS Store Latency Facility.", + "CollectPEBSRecord": "2", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE", + "PEBS": "2", + "SampleAfterValue": "1000003", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts demand data reads that were not suppli= ed by the L3 cache.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00001", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts demand read for ownership (RFO) reques= ts and software prefetches for exclusive ownership (PREFETCHW) that were no= t supplied by the L3 cache.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.DEMAND_RFO.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00002", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_core" + } +] diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/other.json b/tools/p= erf/pmu-events/arch/x86/meteorlake/other.json new file mode 100644 index 000000000000..14273ac54d2c --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/meteorlake/other.json @@ -0,0 +1,46 @@ +[ + { + "BriefDescription": "Counts cacheable demand data reads Catch all = value for any response types - this includes response types not define in t= he OCR. If this is set all other response types will be ignored", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10001", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts demand reads for ownership, including = SWPREFETCHW which is an RFO Catch all value for any response types - this i= ncludes response types not define in the OCR. If this is set all other res= ponse types will be ignored", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10002", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts demand data reads that have any type o= f response.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10001", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts demand read for ownership (RFO) reques= ts and software prefetches for exclusive ownership (PREFETCHW) that have an= y type of response.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10002", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_core" + } +] diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json b/tool= s/perf/pmu-events/arch/x86/meteorlake/pipeline.json new file mode 100644 index 000000000000..0a7981675b6c --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json @@ -0,0 +1,254 @@ +[ + { + "BriefDescription": "Counts the total number of branch instruction= s retired for all branch types.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the total number of mispredicted branc= h instructions retired for all branch types.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Fixed Counter: Counts the number of unhalted = core clock cycles", + "CollectPEBSRecord": "2", + "Counter": "33", + "EventName": "CPU_CLK_UNHALTED.CORE", + "PEBScounters": "33", + "SampleAfterValue": "2000003", + "UMask": "0x2", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of unhalted core clock cycl= es[This event is alias to CPU_CLK_UNHALTED.THREAD_P]", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x3c", + "EventName": "CPU_CLK_UNHALTED.CORE_P", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Fixed Counter: Counts the number of unhalted = reference clock cycles", + "CollectPEBSRecord": "2", + "Counter": "34", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PEBScounters": "34", + "SampleAfterValue": "2000003", + "UMask": "0x3", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Fixed Counter: Counts the number of unhalted = core clock cycles", + "CollectPEBSRecord": "2", + "Counter": "33", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PEBScounters": "33", + "SampleAfterValue": "2000003", + "UMask": "0x2", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of unhalted core clock cycl= es[This event is alias to CPU_CLK_UNHALTED.CORE_P]", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x3c", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Fixed Counter: Counts the number of instructi= ons retired", + "CollectPEBSRecord": "2", + "Counter": "32", + "EventName": "INST_RETIRED.ANY", + "PEBS": "1", + "PEBScounters": "32", + "SampleAfterValue": "2000003", + "UMask": "0x1", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of instructions retired", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc0", + "EventName": "INST_RETIRED.ANY_P", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend because allocation is stalled due to a mispredict= ed jump or a machine clear.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.ALL", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of retirement slots not con= sumed due to backend stalls", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.ALL", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of retirement slots not con= sumed due to front end stalls", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.ALL", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of consumed retirement slot= s. Similar to UOPS_RETIRED.ALL", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x72", + "EventName": "TOPDOWN_RETIRING.ALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "All branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "Unit": "cpu_core" + }, + { + "BriefDescription": "All mispredicted branch instructions retired.= ", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Reference cycles when the core is not in halt= state.", + "CollectPEBSRecord": "2", + "Counter": "34", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PEBScounters": "34", + "SampleAfterValue": "2000003", + "UMask": "0x3", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Reference cycles when the core is not in halt= state.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x3c", + "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Core cycles when the thread is not in halt st= ate", + "CollectPEBSRecord": "2", + "Counter": "33", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PEBScounters": "33", + "SampleAfterValue": "2000003", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Thread cycles when thread is not in halt stat= e", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x3c", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Number of instructions retired. Fixed Counter= - architectural event", + "CollectPEBSRecord": "2", + "Counter": "32", + "EventName": "INST_RETIRED.ANY", + "PEBS": "1", + "PEBScounters": "32", + "SampleAfterValue": "2000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Number of instructions retired. General Count= er - architectural event", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc0", + "EventName": "INST_RETIRED.ANY_P", + "PEBS": "1", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Loads blocked due to overlapping with a prece= ding store that cannot be forwarded.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x82", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TMA slots available for an unhalted logical p= rocessor. Fixed counter - architectural event", + "CollectPEBSRecord": "2", + "Counter": "35", + "EventName": "TOPDOWN.SLOTS", + "PEBScounters": "35", + "SampleAfterValue": "10000003", + "UMask": "0x4", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TMA slots available for an unhalted logical p= rocessor. General counter - architectural event", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa4", + "EventName": "TOPDOWN.SLOTS_P", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "10000003", + "UMask": "0x1", + "Unit": "cpu_core" + } +] diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/virtual-memory.json = b/tools/perf/pmu-events/arch/x86/meteorlake/virtual-memory.json new file mode 100644 index 000000000000..3087730cca7b --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/meteorlake/virtual-memory.json @@ -0,0 +1,46 @@ +[ + { + "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to any page size.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "UMask": "0xe", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (All page sizes)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0xe", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Store misses in all TLB levels causes a page = walk that completes. (All page sizes)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0xe", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (All page sizes)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0xe", + "Unit": "cpu_core" + } +] --=20 2.37.1.359.gd136c6c3e2-goog From nobody Wed Apr 15 05:45:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9456DC04A68 for ; Wed, 27 Jul 2022 22:11:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232845AbiG0WLY (ORCPT ); Wed, 27 Jul 2022 18:11:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52062 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233423AbiG0WKP (ORCPT ); Wed, 27 Jul 2022 18:10:15 -0400 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 979B25F98E for ; Wed, 27 Jul 2022 15:09:35 -0700 (PDT) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-317f6128c86so777697b3.22 for ; Wed, 27 Jul 2022 15:09:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=QK3ShdNa0rI6xddT9IjDfF/1fuI9KTuI6MjArajlZ3g=; b=RYQgdV32UKgIHVVGkPVMlKyyE2lzxe54JtXNdgzXM4KAh5m722x6iC6Y2Y2mJ8GzCg FjUP2lOzETy6FtGSF36Yw8X0lTCtubikEbOyEqTZPhzoUzq3g2debZo3x1chAEcSQ66T 4UtV9hUjvf4cM+qY1q0u7Nju5KgW4heSML0ornaPG8/6Myf61ZCuuBDpll/Wvxk9Hdr0 t2FJ9mXTmo5jP04EsrkR146pA4Jn4eJfcaKRSPf759sq2pYZY3roEM2NbQMPLA53a+jL Ep9Xw9WVnp7l9fYAukSaaamzqGv7Dm4o2TzFBonB5mZx2iSiiwDbaH4arp1WdJb4KDwz w0OQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=QK3ShdNa0rI6xddT9IjDfF/1fuI9KTuI6MjArajlZ3g=; b=j1BLZJPQnu0DtQ9kUxKz/w3WE8HaWRmDtXZQol+BjAmGAkCHHNvjo2ELAulKy/Nh6g pmMkEQboR42qyTqnU7FZbdjPExk0BxM9qgRZBQs1zOmnWVFZMiE6k2ONc8mcW4UtGPlA rvWZhdPPtw9shk9Z2Y69A3LWSLaHzm2bRj66gGM8V8MXAvt4qJAk614k0ptVfRfV1C83 G1u86s05FlEWl3j2AtQRbh9ALshcXAxGZvMEIkR1nfOLJfyi3sHMSkSw6e3ggqJJti+m fyJtvIuIutuBSxJeXD2vcPVpctJ1hbKYoWpbZmKhJ5u1Pja84SYRu18LInz1wJA07VRc zlhw== X-Gm-Message-State: AJIora8Oh20RjWwKzL9vFpzg15w/QzBVkTiUs2nMPRbwp/yS7RqMXTTq aUdq2da2IQSUNiUHEzd6xyW5l1QH2RKQ X-Google-Smtp-Source: AGRyM1t0pOHP4lSvxoHVy7o1puENJFiEYen43msokDWuAwzs90kVh5ZPY7F0YMRRrZaFjY/AkApAippddNQY X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:882a:af57:8cb6:6f9e]) (user=irogers job=sendgmr) by 2002:a81:6503:0:b0:31d:6463:bf1a with SMTP id z3-20020a816503000000b0031d6463bf1amr19771913ywb.178.1658959775099; Wed, 27 Jul 2022 15:09:35 -0700 (PDT) Date: Wed, 27 Jul 2022 15:08:21 -0700 In-Reply-To: <20220727220832.2865794-1-irogers@google.com> Message-Id: <20220727220832.2865794-20-irogers@google.com> Mime-Version: 1.0 References: <20220727220832.2865794-1-irogers@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH v3 19/30] perf vendor events: Update Intel nehalemep From: Ian Rogers To: perry.taylor@intel.com, caleb.biggers@intel.com, kshipra.bopardikar@intel.com, Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Sedat Dilek Cc: Stephane Eranian , Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update to v3, the are no TMA metrics for nehalemep. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/downloa= d_and_gen.py to download and generate the latest events and metrics. Manually copy the nehalemep files into perf and update mapfile.csv. Tested on a non-nehalemep with 'perf test': 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok Signed-off-by: Ian Rogers --- tools/perf/pmu-events/arch/x86/mapfile.csv | 4 +--- .../perf/pmu-events/arch/x86/nehalemep/cache.json | 14 +++++++------- .../arch/x86/nehalemep/floating-point.json | 2 +- .../pmu-events/arch/x86/nehalemep/frontend.json | 2 +- .../perf/pmu-events/arch/x86/nehalemep/memory.json | 6 +++--- .../arch/x86/nehalemep/virtual-memory.json | 2 +- 6 files changed, 14 insertions(+), 16 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 52e4d063ca6b..b9066dceee8d 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -17,9 +17,7 @@ GenuineIntel-6-3E,v21,ivytown,core GenuineIntel-6-2D,v21,jaketown,core GenuineIntel-6-(57|85),v9,knightslanding,core GenuineIntel-6-AA,v1.00,meteorlake,core -GenuineIntel-6-1E,v2,nehalemep,core -GenuineIntel-6-1F,v2,nehalemep,core -GenuineIntel-6-1A,v2,nehalemep,core +GenuineIntel-6-1[AEF],v3,nehalemep,core GenuineIntel-6-2E,v2,nehalemex,core GenuineIntel-6-[4589]E,v24,skylake,core GenuineIntel-6-A[56],v24,skylake,core diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/cache.json b/tools/pe= rf/pmu-events/arch/x86/nehalemep/cache.json index bcf74d793ae2..1ee91300baf9 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemep/cache.json +++ b/tools/perf/pmu-events/arch/x86/nehalemep/cache.json @@ -1773,7 +1773,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Offcore data reads, RFO's and prefetches sati= sfied by the IO, CSR, MMIO unit", + "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the IO, CSR, MMIO unit", "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", @@ -1784,7 +1784,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Offcore data reads, RFO's and prefetches stat= isfied by the LLC and not found in a sibling core", + "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the LLC and not found in a sibling core", "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", @@ -1795,7 +1795,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Offcore data reads, RFO's and prefetches sati= sfied by the LLC and HIT in a sibling core", + "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the LLC and HIT in a sibling core", "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", @@ -1806,7 +1806,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Offcore data reads, RFO's and prefetches sati= sfied by the LLC and HITM in a sibling core", + "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the LLC and HITM in a sibling core", "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", @@ -1861,7 +1861,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Offcore data reads, RFO's and prefetches that= HIT in a remote cache", + "BriefDescription": "Offcore data reads, RFOs, and prefetches that= HIT in a remote cache", "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT", @@ -1872,7 +1872,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Offcore data reads, RFO's and prefetches that= HITM in a remote cache", + "BriefDescription": "Offcore data reads, RFOs, and prefetches that= HITM in a remote cache", "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", @@ -3226,4 +3226,4 @@ "SampleAfterValue": "200000", "UMask": "0x8" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/floating-point.json b= /tools/perf/pmu-events/arch/x86/nehalemep/floating-point.json index 39af1329224a..666e466d351c 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemep/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/nehalemep/floating-point.json @@ -226,4 +226,4 @@ "SampleAfterValue": "200000", "UMask": "0x8" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/frontend.json b/tools= /perf/pmu-events/arch/x86/nehalemep/frontend.json index 8ac5c24888c5..c561ac24d91d 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemep/frontend.json +++ b/tools/perf/pmu-events/arch/x86/nehalemep/frontend.json @@ -23,4 +23,4 @@ "SampleAfterValue": "2000000", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/memory.json b/tools/p= erf/pmu-events/arch/x86/nehalemep/memory.json index 26138ae639f4..6e95de3f3409 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemep/memory.json +++ b/tools/perf/pmu-events/arch/x86/nehalemep/memory.json @@ -286,7 +286,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Offcore data reads, RFO's and prefetches stat= isfied by the local DRAM.", + "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the local DRAM.", "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM", @@ -297,7 +297,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Offcore data reads, RFO's and prefetches stat= isfied by the remote DRAM", + "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the remote DRAM", "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM", @@ -736,4 +736,4 @@ "SampleAfterValue": "100000", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/virtual-memory.json b= /tools/perf/pmu-events/arch/x86/nehalemep/virtual-memory.json index 6d3247c55bcd..e88c0802e679 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemep/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/nehalemep/virtual-memory.json @@ -106,4 +106,4 @@ "SampleAfterValue": "200000", "UMask": "0x1" } -] \ No newline at end of file +] --=20 2.37.1.359.gd136c6c3e2-goog From nobody Wed Apr 15 05:45:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13EBFC04A68 for ; Wed, 27 Jul 2022 22:12:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237275AbiG0WMW (ORCPT ); Wed, 27 Jul 2022 18:12:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54616 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234096AbiG0WK5 (ORCPT ); Wed, 27 Jul 2022 18:10:57 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 379D65FAC2 for ; Wed, 27 Jul 2022 15:09:38 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id bu13-20020a056902090d00b00671743601f1so282008ybb.0 for ; Wed, 27 Jul 2022 15:09:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=zK/zxjikkKaQz9Vn4oqJJgZb9wtOPZRS0BsyJ3kYLiY=; b=gqYdAhST78rbXDy4loBktw+Daq2ghr3mHnioi3ymsgIYox2TqFtPIKjjR7HehUBcTJ oo1Sfoz3sfGK7jy7Q3p4AUNhhgvF5vx8jqdodVlXvsq2m6HjbUogwYDY9409T6o+r2N9 sexVv8FzANbY+PQ/NVwkoLMjz669UPZvp8EgoxWkMXRg5b9R09iAw1fZLe7V4AKd44ED P148SY2d7mRwvgEj5LMHwl4PRl3VvSawCVxS0Hlq4/gPXQDcGOholhZQc0TQntw9AK2k 0Mnkaudiyg6WmhGI5Wc5iSVYh1Ybj7W/mbnFxaRGJMYCiGh0fX8Cprd9XZw5zEW83YlN +g2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=zK/zxjikkKaQz9Vn4oqJJgZb9wtOPZRS0BsyJ3kYLiY=; b=eCIhhorCp2T5ygSffFU4VoCXMIQTGgPOKd7Hw3w78V3ZZs1pYdpD691j4HKOxLmRRW grbZns8nwlN5n73ruoYoynCErAfYwRYfZ2ubDaCRSvQpZbFqe4g4W2EBJub99GsH5aRJ VjN6b5kkV8lpd7PozwdFgsPCIGVQoDqk8PR5Dnzcf5Tbrp+AhXrLjo7c4Dyj2MseAgdO /BhWUtgAIbyLlWE1LS9Zw1Xrh53e1T5CRPSlsm3TgWbj22DiDdZ7eg6pZiH1t999bpFB 4doFvAOB5MDmZ1a8phYNUof4LmZ2qpNU/4RbMxl/8FWvp4KPKYgv4yvVieyC+mg0IrB3 exHg== X-Gm-Message-State: AJIora+FBRQBzGxfnXq7PETDl940xk7rjs6oaww8eVtlRNwV28FEIkyY kfsmObcpOTHS/8A876uz3oebgqggvCNT X-Google-Smtp-Source: AGRyM1vmq0JoAEdESXyxgFejesWns0jydO1mAAIV35begPISSSgczq8b4jhqqBzsOTBe+t/EsQBEYDVwdS64 X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:882a:af57:8cb6:6f9e]) (user=irogers job=sendgmr) by 2002:a25:4bc2:0:b0:66f:31d:f5b5 with SMTP id y185-20020a254bc2000000b0066f031df5b5mr19478920yba.328.1658959777869; Wed, 27 Jul 2022 15:09:37 -0700 (PDT) Date: Wed, 27 Jul 2022 15:08:22 -0700 In-Reply-To: <20220727220832.2865794-1-irogers@google.com> Message-Id: <20220727220832.2865794-21-irogers@google.com> Mime-Version: 1.0 References: <20220727220832.2865794-1-irogers@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH v3 20/30] perf vendor events: Update Intel nehalemex From: Ian Rogers To: perry.taylor@intel.com, caleb.biggers@intel.com, kshipra.bopardikar@intel.com, Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Sedat Dilek Cc: Stephane Eranian , Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update to v3, there are no TMA metrics for nehalemex. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/downloa= d_and_gen.py to download and generate the latest events and metrics. Manually copy the nehalemex files into perf and update mapfile.csv. Tested on a non-nehalemex with 'perf test': 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok Note: most of this change is just sorting the keys in the json dictionaries. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- .../pmu-events/arch/x86/nehalemex/cache.json | 2974 ++++++++--------- .../arch/x86/nehalemex/floating-point.json | 182 +- .../arch/x86/nehalemex/frontend.json | 20 +- .../pmu-events/arch/x86/nehalemex/memory.json | 672 ++-- .../pmu-events/arch/x86/nehalemex/other.json | 170 +- .../arch/x86/nehalemex/pipeline.json | 830 ++--- .../arch/x86/nehalemex/virtual-memory.json | 92 +- 8 files changed, 2471 insertions(+), 2471 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index b9066dceee8d..2f9419ee2d29 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -18,7 +18,7 @@ GenuineIntel-6-2D,v21,jaketown,core GenuineIntel-6-(57|85),v9,knightslanding,core GenuineIntel-6-AA,v1.00,meteorlake,core GenuineIntel-6-1[AEF],v3,nehalemep,core -GenuineIntel-6-2E,v2,nehalemex,core +GenuineIntel-6-2E,v3,nehalemex,core GenuineIntel-6-[4589]E,v24,skylake,core GenuineIntel-6-A[56],v24,skylake,core GenuineIntel-6-37,v13,silvermont,core diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/cache.json b/tools/pe= rf/pmu-events/arch/x86/nehalemex/cache.json index 21a0f8fd057e..01542c4ea678 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemex/cache.json +++ b/tools/perf/pmu-events/arch/x86/nehalemex/cache.json @@ -1,3184 +1,3184 @@ [ { - "EventCode": "0x63", + "BriefDescription": "Cycles L1D locked", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles L1D locked" + "UMask": "0x2" }, { - "EventCode": "0x63", + "BriefDescription": "Cycles L1D and L2 locked", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D_L2", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles L1D and L2 locked" + "UMask": "0x1" }, { - "EventCode": "0x51", + "BriefDescription": "L1D cache lines replaced in M state", "Counter": "0,1", - "UMask": "0x4", + "EventCode": "0x51", "EventName": "L1D.M_EVICT", "SampleAfterValue": "2000000", - "BriefDescription": "L1D cache lines replaced in M state" + "UMask": "0x4" }, { - "EventCode": "0x51", + "BriefDescription": "L1D cache lines allocated in the M state", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x51", "EventName": "L1D.M_REPL", "SampleAfterValue": "2000000", - "BriefDescription": "L1D cache lines allocated in the M state" + "UMask": "0x2" }, { - "EventCode": "0x51", + "BriefDescription": "L1D snoop eviction of cache lines in M state", "Counter": "0,1", - "UMask": "0x8", + "EventCode": "0x51", "EventName": "L1D.M_SNOOP_EVICT", "SampleAfterValue": "2000000", - "BriefDescription": "L1D snoop eviction of cache lines in M state" + "UMask": "0x8" }, { - "EventCode": "0x51", + "BriefDescription": "L1 data cache lines allocated", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x51", "EventName": "L1D.REPL", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache lines allocated" + "UMask": "0x1" }, { - "EventCode": "0x43", + "BriefDescription": "All references to the L1 data cache", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x43", "EventName": "L1D_ALL_REF.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "All references to the L1 data cache" + "UMask": "0x1" }, { - "EventCode": "0x43", + "BriefDescription": "L1 data cacheable reads and writes", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x43", "EventName": "L1D_ALL_REF.CACHEABLE", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cacheable reads and writes" + "UMask": "0x2" }, { - "EventCode": "0x40", + "BriefDescription": "L1 data cache read in E state", "Counter": "0,1", - "UMask": "0x4", + "EventCode": "0x40", "EventName": "L1D_CACHE_LD.E_STATE", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache read in E state" + "UMask": "0x4" }, { - "EventCode": "0x40", + "BriefDescription": "L1 data cache read in I state (misses)", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x40", "EventName": "L1D_CACHE_LD.I_STATE", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache read in I state (misses)" + "UMask": "0x1" }, { - "EventCode": "0x40", + "BriefDescription": "L1 data cache reads", "Counter": "0,1", - "UMask": "0x8", - "EventName": "L1D_CACHE_LD.M_STATE", + "EventCode": "0x40", + "EventName": "L1D_CACHE_LD.MESI", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache read in M state" + "UMask": "0xf" }, { - "EventCode": "0x40", + "BriefDescription": "L1 data cache read in M state", "Counter": "0,1", - "UMask": "0xf", - "EventName": "L1D_CACHE_LD.MESI", + "EventCode": "0x40", + "EventName": "L1D_CACHE_LD.M_STATE", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache reads" + "UMask": "0x8" }, { - "EventCode": "0x40", + "BriefDescription": "L1 data cache read in S state", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x40", "EventName": "L1D_CACHE_LD.S_STATE", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache read in S state" + "UMask": "0x2" }, { - "EventCode": "0x42", + "BriefDescription": "L1 data cache load locks in E state", "Counter": "0,1", - "UMask": "0x4", + "EventCode": "0x42", "EventName": "L1D_CACHE_LOCK.E_STATE", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache load locks in E state" + "UMask": "0x4" }, { - "EventCode": "0x42", + "BriefDescription": "L1 data cache load lock hits", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x42", "EventName": "L1D_CACHE_LOCK.HIT", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache load lock hits" + "UMask": "0x1" }, { - "EventCode": "0x42", + "BriefDescription": "L1 data cache load locks in M state", "Counter": "0,1", - "UMask": "0x8", + "EventCode": "0x42", "EventName": "L1D_CACHE_LOCK.M_STATE", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache load locks in M state" + "UMask": "0x8" }, { - "EventCode": "0x42", + "BriefDescription": "L1 data cache load locks in S state", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x42", "EventName": "L1D_CACHE_LOCK.S_STATE", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache load locks in S state" + "UMask": "0x2" }, { - "EventCode": "0x53", + "BriefDescription": "L1D load lock accepted in fill buffer", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x53", "EventName": "L1D_CACHE_LOCK_FB_HIT", "SampleAfterValue": "2000000", - "BriefDescription": "L1D load lock accepted in fill buffer" + "UMask": "0x1" }, { - "EventCode": "0x52", + "BriefDescription": "L1D prefetch load lock accepted in fill buffe= r", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x52", "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", "SampleAfterValue": "2000000", - "BriefDescription": "L1D prefetch load lock accepted in fill buffe= r" + "UMask": "0x1" }, { - "EventCode": "0x41", + "BriefDescription": "L1 data cache stores in E state", "Counter": "0,1", - "UMask": "0x4", + "EventCode": "0x41", "EventName": "L1D_CACHE_ST.E_STATE", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache stores in E state" + "UMask": "0x4" }, { - "EventCode": "0x41", + "BriefDescription": "L1 data cache stores in M state", "Counter": "0,1", - "UMask": "0x8", + "EventCode": "0x41", "EventName": "L1D_CACHE_ST.M_STATE", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache stores in M state" + "UMask": "0x8" }, { - "EventCode": "0x41", + "BriefDescription": "L1 data cache stores in S state", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x41", "EventName": "L1D_CACHE_ST.S_STATE", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache stores in S state" + "UMask": "0x2" }, { - "EventCode": "0x4E", + "BriefDescription": "L1D hardware prefetch misses", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x4E", "EventName": "L1D_PREFETCH.MISS", "SampleAfterValue": "200000", - "BriefDescription": "L1D hardware prefetch misses" + "UMask": "0x2" }, { - "EventCode": "0x4E", + "BriefDescription": "L1D hardware prefetch requests", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x4E", "EventName": "L1D_PREFETCH.REQUESTS", "SampleAfterValue": "200000", - "BriefDescription": "L1D hardware prefetch requests" + "UMask": "0x1" }, { - "EventCode": "0x4E", + "BriefDescription": "L1D hardware prefetch requests triggered", "Counter": "0,1", - "UMask": "0x4", + "EventCode": "0x4E", "EventName": "L1D_PREFETCH.TRIGGERS", "SampleAfterValue": "200000", - "BriefDescription": "L1D hardware prefetch requests triggered" + "UMask": "0x4" }, { - "EventCode": "0x28", + "BriefDescription": "L1 writebacks to L2 in E state", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x28", "EventName": "L1D_WB_L2.E_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in E state" + "UMask": "0x4" }, { - "EventCode": "0x28", + "BriefDescription": "L1 writebacks to L2 in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x28", "EventName": "L1D_WB_L2.I_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in I state (misses)" + "UMask": "0x1" }, { - "EventCode": "0x28", + "BriefDescription": "All L1 writebacks to L2", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L1D_WB_L2.M_STATE", + "EventCode": "0x28", + "EventName": "L1D_WB_L2.MESI", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in M state" + "UMask": "0xf" }, { - "EventCode": "0x28", + "BriefDescription": "L1 writebacks to L2 in M state", "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L1D_WB_L2.MESI", + "EventCode": "0x28", + "EventName": "L1D_WB_L2.M_STATE", "SampleAfterValue": "100000", - "BriefDescription": "All L1 writebacks to L2" + "UMask": "0x8" }, { - "EventCode": "0x28", + "BriefDescription": "L1 writebacks to L2 in S state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x28", "EventName": "L1D_WB_L2.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in S state" + "UMask": "0x2" }, { - "EventCode": "0x26", + "BriefDescription": "All L2 data requests", "Counter": "0,1,2,3", - "UMask": "0xff", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.ANY", "SampleAfterValue": "200000", - "BriefDescription": "All L2 data requests" + "UMask": "0xff" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand loads in E state", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in E state" + "UMask": "0x4" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand loads in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in I state (misses)" + "UMask": "0x1" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand requests", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", + "EventCode": "0x26", + "EventName": "L2_DATA_RQSTS.DEMAND.MESI", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in M state" + "UMask": "0xf" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand loads in M state", "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L2_DATA_RQSTS.DEMAND.MESI", + "EventCode": "0x26", + "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand requests" + "UMask": "0x8" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand loads in S state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in S state" + "UMask": "0x2" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data prefetches in E state", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in E state" + "UMask": "0x40" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data prefetches in the I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in the I state (misses)" + "UMask": "0x10" }, { - "EventCode": "0x26", + "BriefDescription": "All L2 data prefetches", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", + "EventCode": "0x26", + "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in M state" + "UMask": "0xf0" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data prefetches in M state", "Counter": "0,1,2,3", - "UMask": "0xf0", - "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", + "EventCode": "0x26", + "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", "SampleAfterValue": "200000", - "BriefDescription": "All L2 data prefetches" + "UMask": "0x80" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data prefetches in the S state", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in the S state" + "UMask": "0x20" }, { - "EventCode": "0xF1", + "BriefDescription": "L2 lines alloacated", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0xF1", "EventName": "L2_LINES_IN.ANY", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines alloacated" + "UMask": "0x7" }, { - "EventCode": "0xF1", + "BriefDescription": "L2 lines allocated in the E state", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF1", "EventName": "L2_LINES_IN.E_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines allocated in the E state" + "UMask": "0x4" }, { - "EventCode": "0xF1", + "BriefDescription": "L2 lines allocated in the S state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF1", "EventName": "L2_LINES_IN.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines allocated in the S state" + "UMask": "0x2" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 lines evicted", "Counter": "0,1,2,3", - "UMask": "0xf", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.ANY", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines evicted" + "UMask": "0xf" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 lines evicted by a demand request", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines evicted by a demand request" + "UMask": "0x1" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 modified lines evicted by a demand request= ", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_DIRTY", "SampleAfterValue": "100000", - "BriefDescription": "L2 modified lines evicted by a demand request" + "UMask": "0x2" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 lines evicted by a prefetch request", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines evicted by a prefetch request" + "UMask": "0x4" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 modified lines evicted by a prefetch reque= st", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", "SampleAfterValue": "100000", - "BriefDescription": "L2 modified lines evicted by a prefetch reque= st" + "UMask": "0x8" }, { - "EventCode": "0x24", + "BriefDescription": "L2 instruction fetches", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_RQSTS.IFETCH_HIT", + "EventCode": "0x24", + "EventName": "L2_RQSTS.IFETCHES", "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetch hits" + "UMask": "0x30" }, { - "EventCode": "0x24", + "BriefDescription": "L2 instruction fetch hits", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_RQSTS.IFETCH_MISS", + "EventCode": "0x24", + "EventName": "L2_RQSTS.IFETCH_HIT", "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetch misses" + "UMask": "0x10" }, { - "EventCode": "0x24", + "BriefDescription": "L2 instruction fetch misses", "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "L2_RQSTS.IFETCHES", + "EventCode": "0x24", + "EventName": "L2_RQSTS.IFETCH_MISS", "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetches" + "UMask": "0x20" }, { - "EventCode": "0x24", + "BriefDescription": "L2 load hits", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x24", "EventName": "L2_RQSTS.LD_HIT", "SampleAfterValue": "200000", - "BriefDescription": "L2 load hits" + "UMask": "0x1" }, { - "EventCode": "0x24", + "BriefDescription": "L2 load misses", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x24", "EventName": "L2_RQSTS.LD_MISS", "SampleAfterValue": "200000", - "BriefDescription": "L2 load misses" + "UMask": "0x2" }, { - "EventCode": "0x24", + "BriefDescription": "L2 requests", "Counter": "0,1,2,3", - "UMask": "0x3", + "EventCode": "0x24", "EventName": "L2_RQSTS.LOADS", "SampleAfterValue": "200000", - "BriefDescription": "L2 requests" + "UMask": "0x3" }, { - "EventCode": "0x24", + "BriefDescription": "All L2 misses", "Counter": "0,1,2,3", - "UMask": "0xaa", + "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "SampleAfterValue": "200000", - "BriefDescription": "All L2 misses" + "UMask": "0xaa" }, { + "BriefDescription": "All L2 prefetches", + "Counter": "0,1,2,3", "EventCode": "0x24", + "EventName": "L2_RQSTS.PREFETCHES", + "SampleAfterValue": "200000", + "UMask": "0xc0" + }, + { + "BriefDescription": "L2 prefetch hits", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCH_HIT", "SampleAfterValue": "200000", - "BriefDescription": "L2 prefetch hits" + "UMask": "0x40" }, { - "EventCode": "0x24", + "BriefDescription": "L2 prefetch misses", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCH_MISS", "SampleAfterValue": "200000", - "BriefDescription": "L2 prefetch misses" + "UMask": "0x80" }, { - "EventCode": "0x24", + "BriefDescription": "All L2 requests", "Counter": "0,1,2,3", - "UMask": "0xc0", - "EventName": "L2_RQSTS.PREFETCHES", + "EventCode": "0x24", + "EventName": "L2_RQSTS.REFERENCES", "SampleAfterValue": "200000", - "BriefDescription": "All L2 prefetches" + "UMask": "0xff" }, { - "EventCode": "0x24", + "BriefDescription": "L2 RFO requests", "Counter": "0,1,2,3", - "UMask": "0xff", - "EventName": "L2_RQSTS.REFERENCES", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFOS", "SampleAfterValue": "200000", - "BriefDescription": "All L2 requests" + "UMask": "0xc" }, { - "EventCode": "0x24", + "BriefDescription": "L2 RFO hits", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO hits" + "UMask": "0x4" }, { - "EventCode": "0x24", + "BriefDescription": "L2 RFO misses", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO misses" + "UMask": "0x8" }, { - "EventCode": "0x24", + "BriefDescription": "All L2 transactions", "Counter": "0,1,2,3", - "UMask": "0xc", - "EventName": "L2_RQSTS.RFOS", - "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO requests" - }, - { "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x80", "EventName": "L2_TRANSACTIONS.ANY", "SampleAfterValue": "200000", - "BriefDescription": "All L2 transactions" + "UMask": "0x80" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 fill transactions", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.FILL", "SampleAfterValue": "200000", - "BriefDescription": "L2 fill transactions" + "UMask": "0x20" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 instruction fetch transactions", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.IFETCH", "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetch transactions" + "UMask": "0x4" }, { - "EventCode": "0xF0", + "BriefDescription": "L1D writeback to L2 transactions", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.L1D_WB", "SampleAfterValue": "200000", - "BriefDescription": "L1D writeback to L2 transactions" + "UMask": "0x10" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 Load transactions", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.LOAD", "SampleAfterValue": "200000", - "BriefDescription": "L2 Load transactions" + "UMask": "0x1" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 prefetch transactions", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.PREFETCH", "SampleAfterValue": "200000", - "BriefDescription": "L2 prefetch transactions" + "UMask": "0x8" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 RFO transactions", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.RFO", "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO transactions" + "UMask": "0x2" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 writeback to LLC transactions", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.WB", "SampleAfterValue": "200000", - "BriefDescription": "L2 writeback to LLC transactions" + "UMask": "0x40" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand lock RFOs in E state", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.E_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in E state" + "UMask": "0x40" }, { - "EventCode": "0x27", + "BriefDescription": "All demand L2 lock RFOs that hit the cache", "Counter": "0,1,2,3", - "UMask": "0xe0", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.HIT", "SampleAfterValue": "100000", - "BriefDescription": "All demand L2 lock RFOs that hit the cache" + "UMask": "0xe0" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand lock RFOs in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.I_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in I state (misses)" + "UMask": "0x10" }, { - "EventCode": "0x27", + "BriefDescription": "All demand L2 lock RFOs", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_WRITE.LOCK.M_STATE", + "EventCode": "0x27", + "EventName": "L2_WRITE.LOCK.MESI", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in M state" + "UMask": "0xf0" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand lock RFOs in M state", "Counter": "0,1,2,3", - "UMask": "0xf0", - "EventName": "L2_WRITE.LOCK.MESI", + "EventCode": "0x27", + "EventName": "L2_WRITE.LOCK.M_STATE", "SampleAfterValue": "100000", - "BriefDescription": "All demand L2 lock RFOs" + "UMask": "0x80" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand lock RFOs in S state", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in S state" + "UMask": "0x20" }, { - "EventCode": "0x27", + "BriefDescription": "All L2 demand store RFOs that hit the cache", "Counter": "0,1,2,3", - "UMask": "0xe", + "EventCode": "0x27", "EventName": "L2_WRITE.RFO.HIT", "SampleAfterValue": "100000", - "BriefDescription": "All L2 demand store RFOs that hit the cache" + "UMask": "0xe" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand store RFOs in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x27", "EventName": "L2_WRITE.RFO.I_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand store RFOs in I state (misses)" + "UMask": "0x1" }, { - "EventCode": "0x27", + "BriefDescription": "All L2 demand store RFOs", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_WRITE.RFO.M_STATE", + "EventCode": "0x27", + "EventName": "L2_WRITE.RFO.MESI", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand store RFOs in M state" + "UMask": "0xf" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand store RFOs in M state", "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L2_WRITE.RFO.MESI", + "EventCode": "0x27", + "EventName": "L2_WRITE.RFO.M_STATE", "SampleAfterValue": "100000", - "BriefDescription": "All L2 demand store RFOs" + "UMask": "0x8" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand store RFOs in S state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x27", "EventName": "L2_WRITE.RFO.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand store RFOs in S state" + "UMask": "0x2" }, { - "EventCode": "0x2E", + "BriefDescription": "Longest latency cache miss", "Counter": "0,1,2,3", - "UMask": "0x41", + "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "SampleAfterValue": "100000", - "BriefDescription": "Longest latency cache miss" + "UMask": "0x41" }, { - "EventCode": "0x2E", + "BriefDescription": "Longest latency cache reference", "Counter": "0,1,2,3", - "UMask": "0x4f", + "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "SampleAfterValue": "200000", - "BriefDescription": "Longest latency cache reference" + "UMask": "0x4f" }, { - "PEBS": "1", + "BriefDescription": "Memory instructions retired above 0 clocks (P= recise Event)", + "Counter": "3", "EventCode": "0xB", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_INST_RETIRED.LOADS", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", + "MSRIndex": "0x3F6", + "MSRValue": "0x0", + "PEBS": "2", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired which contains a load (P= recise Event)" + "UMask": "0x10" }, { - "PEBS": "1", + "BriefDescription": "Memory instructions retired above 1024 clocks= (Precise Event)", + "Counter": "3", "EventCode": "0xB", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_INST_RETIRED.STORES", - "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired which contains a store (= Precise Event)" + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", + "MSRIndex": "0x3F6", + "MSRValue": "0x400", + "PEBS": "2", + "SampleAfterValue": "100", + "UMask": "0x10" }, { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "MEM_LOAD_RETIRED.HIT_LFB", - "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that miss L1D and hit an previo= usly allocated LFB (Precise Event)" + "BriefDescription": "Memory instructions retired above 128 clocks = (Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "SampleAfterValue": "1000", + "UMask": "0x10" }, { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_LOAD_RETIRED.L1D_HIT", - "SampleAfterValue": "2000000", - "BriefDescription": "Retired loads that hit the L1 data cache (Pre= cise Event)" + "BriefDescription": "Memory instructions retired above 16 clocks (= Precise Event)", + "Counter": "3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "SampleAfterValue": "10000", + "UMask": "0x10" }, { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_LOAD_RETIRED.L2_HIT", - "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that hit the L2 cache (Precise = Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "MEM_LOAD_RETIRED.LLC_MISS", - "SampleAfterValue": "10000", - "BriefDescription": "Retired loads that miss the LLC cache (Precis= e Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", - "SampleAfterValue": "40000", - "BriefDescription": "Retired loads that hit valid versions in the = LLC cache (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", - "SampleAfterValue": "40000", - "BriefDescription": "Retired loads that hit sibling core's L2 in m= odified or unmodified states (Precise Event)" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore L1 data cache writebacks" - }, - { - "EventCode": "0xB2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_SQ_FULL", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests blocked due to Super Queue f= ull" - }, - { - "EventCode": "0xF4", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "SQ_MISC.SPLIT_LOCK", - "SampleAfterValue": "2000000", - "BriefDescription": "Super Queue lock splits across a cache line" - }, - { - "EventCode": "0x6", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "STORE_BLOCKS.AT_RET", - "SampleAfterValue": "200000", - "BriefDescription": "Loads delayed with at-Retirement block code" - }, - { - "EventCode": "0x6", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "STORE_BLOCKS.L1D_BLOCK", - "SampleAfterValue": "200000", - "BriefDescription": "Cacheable loads delayed with L1D block code" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x0", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", - "MSRIndex": "0x3F6", - "SampleAfterValue": "2000000", - "BriefDescription": "Memory instructions retired above 0 clocks (P= recise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x400", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", - "MSRIndex": "0x3F6", - "SampleAfterValue": "100", - "BriefDescription": "Memory instructions retired above 1024 clocks= (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x80", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", - "MSRIndex": "0x3F6", - "SampleAfterValue": "1000", - "BriefDescription": "Memory instructions retired above 128 clocks = (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x10", + "BriefDescription": "Memory instructions retired above 16384 clock= s (Precise Event)", "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", - "MSRIndex": "0x3F6", - "SampleAfterValue": "10000", - "BriefDescription": "Memory instructions retired above 16 clocks (= Precise Event)" - }, - { - "PEBS": "2", "EventCode": "0xB", - "MSRValue": "0x4000", - "Counter": "3", - "UMask": "0x10", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", "MSRIndex": "0x3F6", + "MSRValue": "0x4000", + "PEBS": "2", "SampleAfterValue": "5", - "BriefDescription": "Memory instructions retired above 16384 clock= s (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x800", + "BriefDescription": "Memory instructions retired above 2048 clocks= (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", "MSRIndex": "0x3F6", + "MSRValue": "0x800", + "PEBS": "2", "SampleAfterValue": "50", - "BriefDescription": "Memory instructions retired above 2048 clocks= (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x100", + "BriefDescription": "Memory instructions retired above 256 clocks = (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", "SampleAfterValue": "500", - "BriefDescription": "Memory instructions retired above 256 clocks = (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x20", + "BriefDescription": "Memory instructions retired above 32 clocks (= Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", "SampleAfterValue": "5000", - "BriefDescription": "Memory instructions retired above 32 clocks (= Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x8000", + "BriefDescription": "Memory instructions retired above 32768 clock= s (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", "MSRIndex": "0x3F6", + "MSRValue": "0x8000", + "PEBS": "2", "SampleAfterValue": "3", - "BriefDescription": "Memory instructions retired above 32768 clock= s (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x4", + "BriefDescription": "Memory instructions retired above 4 clocks (P= recise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", "SampleAfterValue": "50000", - "BriefDescription": "Memory instructions retired above 4 clocks (P= recise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x1000", + "BriefDescription": "Memory instructions retired above 4096 clocks= (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", "MSRIndex": "0x3F6", + "MSRValue": "0x1000", + "PEBS": "2", "SampleAfterValue": "20", - "BriefDescription": "Memory instructions retired above 4096 clocks= (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x200", + "BriefDescription": "Memory instructions retired above 512 clocks = (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", "SampleAfterValue": "200", - "BriefDescription": "Memory instructions retired above 512 clocks = (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x40", + "BriefDescription": "Memory instructions retired above 64 clocks (= Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", "SampleAfterValue": "2000", - "BriefDescription": "Memory instructions retired above 64 clocks (= Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x8", + "BriefDescription": "Memory instructions retired above 8 clocks (P= recise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", "SampleAfterValue": "20000", - "BriefDescription": "Memory instructions retired above 8 clocks (P= recise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x2000", + "BriefDescription": "Memory instructions retired above 8192 clocks= (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", "MSRIndex": "0x3F6", + "MSRValue": "0x2000", + "PEBS": "2", "SampleAfterValue": "10", - "BriefDescription": "Memory instructions retired above 8192 clocks= (Precise Event)" + "UMask": "0x10" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F11", + "BriefDescription": "Instructions retired which contains a load (P= recise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LOADS", + "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Instructions retired which contains a store (= Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.STORES", + "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired loads that miss L1D and hit an previo= usly allocated LFB (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.HIT_LFB", + "PEBS": "1", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "Retired loads that hit the L1 data cache (Pre= cise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.L1D_HIT", + "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired loads that hit the L2 cache (Precise = Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.L2_HIT", + "PEBS": "1", + "SampleAfterValue": "200000", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired loads that miss the LLC cache (Precis= e Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.LLC_MISS", + "PEBS": "1", + "SampleAfterValue": "10000", + "UMask": "0x10" + }, + { + "BriefDescription": "Retired loads that hit valid versions in the = LLC cache (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", + "PEBS": "1", + "SampleAfterValue": "40000", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired loads that hit sibling core's L2 in m= odified or unmodified states (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", + "PEBS": "1", + "SampleAfterValue": "40000", + "UMask": "0x8" + }, + { + "BriefDescription": "Offcore L1 data cache writebacks", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", + "SampleAfterValue": "100000", + "UMask": "0x40" + }, + { + "BriefDescription": "Offcore requests blocked due to Super Queue f= ull", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "OFFCORE_REQUESTS_SQ_FULL", + "SampleAfterValue": "100000", + "UMask": "0x1" + }, + { + "BriefDescription": "Offcore data reads satisfied by any cache or = DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F11", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by any cache or = DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF11", + "BriefDescription": "All offcore data reads", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF11", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore data reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8011", + "BriefDescription": "Offcore data reads satisfied by the IO, CSR, = MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the IO, CSR, = MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x111", + "BriefDescription": "Offcore data reads satisfied by the LLC and n= ot found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x111", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC and n= ot found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x211", + "BriefDescription": "Offcore data reads satisfied by the LLC and H= IT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x211", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC and H= IT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x411", + "BriefDescription": "Offcore data reads satisfied by the LLC and = HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x411", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC and = HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x711", + "BriefDescription": "Offcore data reads satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x711", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4711", + "BriefDescription": "Offcore data reads satisfied by the LLC or lo= cal DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4711", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC or lo= cal DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1811", + "BriefDescription": "Offcore data reads satisfied by a remote cach= e", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1811", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by a remote cach= e", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3811", + "BriefDescription": "Offcore data reads satisfied by a remote cach= e or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3811", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by a remote cach= e or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1011", + "BriefDescription": "Offcore data reads that HIT in a remote cache= ", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads that HIT in a remote cache= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x811", + "BriefDescription": "Offcore data reads that HITM in a remote cach= e", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x811", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads that HITM in a remote cach= e", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F44", + "BriefDescription": "Offcore code reads satisfied by any cache or = DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F44", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by any cache or = DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF44", + "BriefDescription": "All offcore code reads", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF44", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore code reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8044", + "BriefDescription": "Offcore code reads satisfied by the IO, CSR, = MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the IO, CSR, = MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x144", + "BriefDescription": "Offcore code reads satisfied by the LLC and n= ot found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x144", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC and n= ot found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x244", + "BriefDescription": "Offcore code reads satisfied by the LLC and H= IT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x244", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC and H= IT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x444", + "BriefDescription": "Offcore code reads satisfied by the LLC and = HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x444", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC and = HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x744", + "BriefDescription": "Offcore code reads satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x744", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4744", + "BriefDescription": "Offcore code reads satisfied by the LLC or lo= cal DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4744", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC or lo= cal DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1844", + "BriefDescription": "Offcore code reads satisfied by a remote cach= e", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1844", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by a remote cach= e", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3844", + "BriefDescription": "Offcore code reads satisfied by a remote cach= e or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3844", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by a remote cach= e or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1044", + "BriefDescription": "Offcore code reads that HIT in a remote cache= ", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads that HIT in a remote cache= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x844", + "BriefDescription": "Offcore code reads that HITM in a remote cach= e", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x844", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads that HITM in a remote cach= e", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7FFF", + "BriefDescription": "Offcore requests satisfied by any cache or DR= AM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7FFF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by any cache or DR= AM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFFFF", + "BriefDescription": "All offcore requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFFFF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x80FF", + "BriefDescription": "Offcore requests satisfied by the IO, CSR, MM= IO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x80FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the IO, CSR, MM= IO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1FF", + "BriefDescription": "Offcore requests satisfied by the LLC and not= found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x1FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC and not= found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2FF", + "BriefDescription": "Offcore requests satisfied by the LLC and HIT= in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x2FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC and HIT= in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4FF", + "BriefDescription": "Offcore requests satisfied by the LLC and HI= TM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM= ", "MSRIndex": "0x1A6", + "MSRValue": "0x4FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC and HI= TM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7FF", + "BriefDescription": "Offcore requests satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x7FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x47FF", + "BriefDescription": "Offcore requests satisfied by the LLC or loca= l DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x47FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC or loca= l DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x18FF", + "BriefDescription": "Offcore requests satisfied by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x18FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x38FF", + "BriefDescription": "Offcore requests satisfied by a remote cache = or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x38FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by a remote cache = or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x10FF", + "BriefDescription": "Offcore requests that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x10FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8FF", + "BriefDescription": "Offcore requests that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x8FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F22", + "BriefDescription": "Offcore RFO requests satisfied by any cache o= r DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F22", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by any cache o= r DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF22", + "BriefDescription": "All offcore RFO requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF22", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore RFO requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8022", + "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR= , MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR= , MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x122", + "BriefDescription": "Offcore RFO requests satisfied by the LLC and= not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x122", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC and= not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x222", + "BriefDescription": "Offcore RFO requests satisfied by the LLC and= HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x222", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC and= HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x422", + "BriefDescription": "Offcore RFO requests satisfied by the LLC an= d HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x422", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC an= d HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x722", + "BriefDescription": "Offcore RFO requests satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x722", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4722", + "BriefDescription": "Offcore RFO requests satisfied by the LLC or = local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4722", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC or = local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1822", + "BriefDescription": "Offcore RFO requests satisfied by a remote ca= che", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1822", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by a remote ca= che", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3822", + "BriefDescription": "Offcore RFO requests satisfied by a remote ca= che or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3822", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by a remote ca= che or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1022", + "BriefDescription": "Offcore RFO requests that HIT in a remote cac= he", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests that HIT in a remote cac= he", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x822", + "BriefDescription": "Offcore RFO requests that HITM in a remote ca= che", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x822", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests that HITM in a remote ca= che", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F08", + "BriefDescription": "Offcore writebacks to any cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F08", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF08", + "BriefDescription": "All offcore writebacks", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF08", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore writebacks", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8008", + "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.= ", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x108", + "BriefDescription": "Offcore writebacks to the LLC and not found i= n a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x108", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the LLC and not found i= n a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x408", + "BriefDescription": "Offcore writebacks to the LLC and HITM in a = sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x408", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the LLC and HITM in a = sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x708", + "BriefDescription": "Offcore writebacks to the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x708", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4708", + "BriefDescription": "Offcore writebacks to the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4708", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1808", + "BriefDescription": "Offcore writebacks to a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1808", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3808", + "BriefDescription": "Offcore writebacks to a remote cache or remot= e DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3808", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to a remote cache or remot= e DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1008", + "BriefDescription": "Offcore writebacks that HIT in a remote cache= ", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks that HIT in a remote cache= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x808", + "BriefDescription": "Offcore writebacks that HITM in a remote cach= e", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x808", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks that HITM in a remote cach= e", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F77", + "BriefDescription": "Offcore code or data read requests satisfied = by any cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F77", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF77", + "BriefDescription": "All offcore code or data read requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF77", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore code or data read requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8077", + "BriefDescription": "Offcore code or data read requests satisfied = by the IO, CSR, MMIO unit.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by the IO, CSR, MMIO unit.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x177", + "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x177", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x277", + "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x277", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x477", + "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM= ", "MSRIndex": "0x1A6", + "MSRValue": "0x477", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x777", + "BriefDescription": "Offcore code or data read requests satisfied = by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x777", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4777", + "BriefDescription": "Offcore code or data read requests satisfied = by the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4777", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1877", + "BriefDescription": "Offcore code or data read requests satisfied = by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1877", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3877", + "BriefDescription": "Offcore code or data read requests satisfied = by a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3877", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1077", + "BriefDescription": "Offcore code or data read requests that HIT i= n a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests that HIT i= n a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x877", + "BriefDescription": "Offcore code or data read requests that HITM = in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x877", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests that HITM = in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F33", + "BriefDescription": "Offcore request =3D all data, response =3D an= y cache_dram", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F33", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request =3D all data, response =3D an= y cache_dram", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF33", + "BriefDescription": "Offcore request =3D all data, response =3D an= y location", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF33", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request =3D all data, response =3D an= y location", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8033", + "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches sati= sfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x133", + "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x133", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches stat= isfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x233", + "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x233", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches sati= sfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x433", + "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x433", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches sati= sfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x733", + "BriefDescription": "Offcore request =3D all data, response =3D lo= cal cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x733", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request =3D all data, response =3D lo= cal cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4733", + "BriefDescription": "Offcore request =3D all data, response =3D lo= cal cache or dram", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4733", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request =3D all data, response =3D lo= cal cache or dram", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1833", + "BriefDescription": "Offcore request =3D all data, response =3D re= mote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1833", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request =3D all data, response =3D re= mote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3833", + "BriefDescription": "Offcore request =3D all data, response =3D re= mote cache or dram", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3833", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request =3D all data, response =3D re= mote cache or dram", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1033", + "BriefDescription": "Offcore data reads, RFOs, and prefetches that= HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches that= HIT in a remote cache ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x833", + "BriefDescription": "Offcore data reads, RFOs, and prefetches that= HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x833", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches that= HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F03", + "BriefDescription": "Offcore demand data requests satisfied by any= cache or DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F03", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by any= cache or DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF03", + "BriefDescription": "All offcore demand data requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF03", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore demand data requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8003", + "BriefDescription": "Offcore demand data requests satisfied by the= IO, CSR, MMIO unit.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the= IO, CSR, MMIO unit.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x103", + "BriefDescription": "Offcore demand data requests satisfied by the= LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x103", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the= LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x203", + "BriefDescription": "Offcore demand data requests satisfied by the= LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x203", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the= LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x403", + "BriefDescription": "Offcore demand data requests satisfied by the= LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM= ", "MSRIndex": "0x1A6", + "MSRValue": "0x403", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the= LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x703", + "BriefDescription": "Offcore demand data requests satisfied by the= LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x703", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the= LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4703", + "BriefDescription": "Offcore demand data requests satisfied by the= LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4703", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the= LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1803", + "BriefDescription": "Offcore demand data requests satisfied by a r= emote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1803", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by a r= emote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3803", + "BriefDescription": "Offcore demand data requests satisfied by a r= emote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3803", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by a r= emote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1003", + "BriefDescription": "Offcore demand data requests that HIT in a re= mote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests that HIT in a re= mote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x803", + "BriefDescription": "Offcore demand data requests that HITM in a r= emote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x803", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests that HITM in a r= emote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F01", + "BriefDescription": "Offcore demand data reads satisfied by any ca= che or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F01", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by any ca= che or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF01", + "BriefDescription": "All offcore demand data reads", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF01", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore demand data reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8001", + "BriefDescription": "Offcore demand data reads satisfied by the IO= , CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the IO= , CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x101", + "BriefDescription": "Offcore demand data reads satisfied by the LL= C and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_COR= E", "MSRIndex": "0x1A6", + "MSRValue": "0x101", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LL= C and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x201", + "BriefDescription": "Offcore demand data reads satisfied by the LL= C and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_H= IT", "MSRIndex": "0x1A6", + "MSRValue": "0x201", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LL= C and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x401", + "BriefDescription": "Offcore demand data reads satisfied by the LL= C and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_H= ITM", "MSRIndex": "0x1A6", + "MSRValue": "0x401", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LL= C and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x701", + "BriefDescription": "Offcore demand data reads satisfied by the LL= C", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x701", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LL= C", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4701", + "BriefDescription": "Offcore demand data reads satisfied by the LL= C or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4701", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LL= C or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1801", + "BriefDescription": "Offcore demand data reads satisfied by a remo= te cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1801", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by a remo= te cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3801", + "BriefDescription": "Offcore demand data reads satisfied by a remo= te cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3801", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by a remo= te cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1001", + "BriefDescription": "Offcore demand data reads that HIT in a remot= e cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads that HIT in a remot= e cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x801", + "BriefDescription": "Offcore demand data reads that HITM in a remo= te cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x801", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads that HITM in a remo= te cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F04", + "BriefDescription": "Offcore demand code reads satisfied by any ca= che or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F04", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by any ca= che or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF04", + "BriefDescription": "All offcore demand code reads", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF04", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore demand code reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8004", + "BriefDescription": "Offcore demand code reads satisfied by the IO= , CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the IO= , CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x104", + "BriefDescription": "Offcore demand code reads satisfied by the LL= C and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE= ", "MSRIndex": "0x1A6", + "MSRValue": "0x104", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LL= C and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x204", + "BriefDescription": "Offcore demand code reads satisfied by the LL= C and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HI= T", "MSRIndex": "0x1A6", + "MSRValue": "0x204", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LL= C and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x404", + "BriefDescription": "Offcore demand code reads satisfied by the LL= C and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HI= TM", "MSRIndex": "0x1A6", + "MSRValue": "0x404", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LL= C and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x704", + "BriefDescription": "Offcore demand code reads satisfied by the LL= C", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x704", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LL= C", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4704", + "BriefDescription": "Offcore demand code reads satisfied by the LL= C or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4704", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LL= C or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1804", + "BriefDescription": "Offcore demand code reads satisfied by a remo= te cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1804", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by a remo= te cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3804", + "BriefDescription": "Offcore demand code reads satisfied by a remo= te cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3804", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by a remo= te cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1004", + "BriefDescription": "Offcore demand code reads that HIT in a remot= e cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads that HIT in a remot= e cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x804", + "BriefDescription": "Offcore demand code reads that HITM in a remo= te cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x804", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads that HITM in a remo= te cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F02", + "BriefDescription": "Offcore demand RFO requests satisfied by any = cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F02", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by any = cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF02", + "BriefDescription": "All offcore demand RFO requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF02", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore demand RFO requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8002", + "BriefDescription": "Offcore demand RFO requests satisfied by the = IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the = IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x102", + "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x102", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x202", + "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x202", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x402", + "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x402", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x702", + "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x702", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4702", + "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4702", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1802", + "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1802", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3802", + "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3802", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1002", + "BriefDescription": "Offcore demand RFO requests that HIT in a rem= ote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests that HIT in a rem= ote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x802", + "BriefDescription": "Offcore demand RFO requests that HITM in a re= mote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x802", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests that HITM in a re= mote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F80", + "BriefDescription": "Offcore other requests satisfied by any cache= or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F80", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by any cache= or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF80", + "BriefDescription": "All offcore other requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF80", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore other requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8080", + "BriefDescription": "Offcore other requests satisfied by the IO, C= SR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the IO, C= SR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x180", + "BriefDescription": "Offcore other requests satisfied by the LLC a= nd not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x180", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC a= nd not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x280", + "BriefDescription": "Offcore other requests satisfied by the LLC a= nd HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x280", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC a= nd HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x480", + "BriefDescription": "Offcore other requests satisfied by the LLC = and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x480", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC = and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x780", + "BriefDescription": "Offcore other requests satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x780", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4780", + "BriefDescription": "Offcore other requests satisfied by the LLC o= r local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4780", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC o= r local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1880", + "BriefDescription": "Offcore other requests satisfied by a remote = cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1880", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by a remote = cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3880", + "BriefDescription": "Offcore other requests satisfied by a remote = cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3880", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by a remote = cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1080", + "BriefDescription": "Offcore other requests that HIT in a remote c= ache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests that HIT in a remote c= ache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x880", + "BriefDescription": "Offcore other requests that HITM in a remote = cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x880", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests that HITM in a remote = cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F30", + "BriefDescription": "Offcore prefetch data requests satisfied by a= ny cache or DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F30", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by a= ny cache or DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF30", + "BriefDescription": "All offcore prefetch data requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF30", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch data requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8030", + "BriefDescription": "Offcore prefetch data requests satisfied by t= he IO, CSR, MMIO unit.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8030", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by t= he IO, CSR, MMIO unit.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x130", + "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x130", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x230", + "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x230", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x430", + "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x430", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x730", + "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x730", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4730", + "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4730", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1830", + "BriefDescription": "Offcore prefetch data requests satisfied by a= remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1830", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by a= remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3830", + "BriefDescription": "Offcore prefetch data requests satisfied by a= remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3830", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by a= remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1030", + "BriefDescription": "Offcore prefetch data requests that HIT in a = remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1030", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests that HIT in a = remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x830", + "BriefDescription": "Offcore prefetch data requests that HITM in a= remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x830", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests that HITM in a= remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F10", + "BriefDescription": "Offcore prefetch data reads satisfied by any = cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F10", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by any = cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF10", + "BriefDescription": "All offcore prefetch data reads", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF10", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch data reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8010", + "BriefDescription": "Offcore prefetch data reads satisfied by the = IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the = IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x110", + "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x110", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x210", + "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x210", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x410", + "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x410", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x710", + "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x710", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4710", + "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4710", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1810", + "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1810", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3810", + "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3810", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1010", + "BriefDescription": "Offcore prefetch data reads that HIT in a rem= ote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads that HIT in a rem= ote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x810", + "BriefDescription": "Offcore prefetch data reads that HITM in a re= mote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x810", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads that HITM in a re= mote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F40", + "BriefDescription": "Offcore prefetch code reads satisfied by any = cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F40", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by any = cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF40", + "BriefDescription": "All offcore prefetch code reads", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF40", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch code reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8040", + "BriefDescription": "Offcore prefetch code reads satisfied by the = IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the = IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x140", + "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x140", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x240", + "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x240", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x440", + "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x440", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x740", + "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x740", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4740", + "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4740", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1840", + "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1840", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3840", + "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3840", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1040", + "BriefDescription": "Offcore prefetch code reads that HIT in a rem= ote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads that HIT in a rem= ote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x840", + "BriefDescription": "Offcore prefetch code reads that HITM in a re= mote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x840", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads that HITM in a re= mote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F20", + "BriefDescription": "Offcore prefetch RFO requests satisfied by an= y cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F20", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by an= y cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF20", + "BriefDescription": "All offcore prefetch RFO requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF20", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch RFO requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8020", + "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x120", + "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x120", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x220", + "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x220", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x420", + "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x420", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x720", + "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x720", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4720", + "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4720", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1820", + "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1820", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3820", + "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3820", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1020", + "BriefDescription": "Offcore prefetch RFO requests that HIT in a r= emote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests that HIT in a r= emote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x820", + "BriefDescription": "Offcore prefetch RFO requests that HITM in a = remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x820", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests that HITM in a = remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F70", + "BriefDescription": "Offcore prefetch requests satisfied by any ca= che or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F70", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by any ca= che or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF70", + "BriefDescription": "All offcore prefetch requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF70", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8070", + "BriefDescription": "Offcore prefetch requests satisfied by the IO= , CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the IO= , CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x170", + "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x170", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x270", + "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x270", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x470", + "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x470", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x770", + "BriefDescription": "Offcore prefetch requests satisfied by the LL= C", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x770", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LL= C", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4770", + "BriefDescription": "Offcore prefetch requests satisfied by the LL= C or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4770", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LL= C or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1870", + "BriefDescription": "Offcore prefetch requests satisfied by a remo= te cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1870", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by a remo= te cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3870", + "BriefDescription": "Offcore prefetch requests satisfied by a remo= te cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3870", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by a remo= te cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1070", + "BriefDescription": "Offcore prefetch requests that HIT in a remot= e cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests that HIT in a remot= e cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x870", + "BriefDescription": "Offcore prefetch requests that HITM in a remo= te cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x870", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests that HITM in a remo= te cache", - "Offcore": "1" + "UMask": "0x1" + }, + { + "BriefDescription": "Super Queue lock splits across a cache line", + "Counter": "0,1,2,3", + "EventCode": "0xF4", + "EventName": "SQ_MISC.SPLIT_LOCK", + "SampleAfterValue": "2000000", + "UMask": "0x10" + }, + { + "BriefDescription": "Loads delayed with at-Retirement block code", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "STORE_BLOCKS.AT_RET", + "SampleAfterValue": "200000", + "UMask": "0x4" + }, + { + "BriefDescription": "Cacheable loads delayed with L1D block code", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "STORE_BLOCKS.L1D_BLOCK", + "SampleAfterValue": "200000", + "UMask": "0x8" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/floating-point.json b= /tools/perf/pmu-events/arch/x86/nehalemex/floating-point.json index 7d2f71a9dee3..666e466d351c 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemex/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/nehalemex/floating-point.json @@ -1,229 +1,229 @@ [ { - "PEBS": "1", - "EventCode": "0xF7", + "BriefDescription": "X87 Floating point assists (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xF7", "EventName": "FP_ASSIST.ALL", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "X87 Floating point assists (Precise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xF7", + "BriefDescription": "X87 Floating poiint assists for invalid input= value (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF7", "EventName": "FP_ASSIST.INPUT", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "X87 Floating poiint assists for invalid input= value (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xF7", + "BriefDescription": "X87 Floating point assists for invalid output= value (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF7", "EventName": "FP_ASSIST.OUTPUT", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "X87 Floating point assists for invalid output= value (Precise Event)" + "UMask": "0x2" }, { - "EventCode": "0x10", + "BriefDescription": "MMX Uops", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.MMX", "SampleAfterValue": "2000000", - "BriefDescription": "MMX Uops" + "UMask": "0x2" }, { + "BriefDescription": "SSE2 integer Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER", + "SampleAfterValue": "2000000", + "UMask": "0x8" + }, + { + "BriefDescription": "SSE* FP double precision Uops", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", "SampleAfterValue": "2000000", - "BriefDescription": "SSE* FP double precision Uops" + "UMask": "0x80" }, { - "EventCode": "0x10", + "BriefDescription": "SSE and SSE2 FP Uops", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP", "SampleAfterValue": "2000000", - "BriefDescription": "SSE and SSE2 FP Uops" + "UMask": "0x4" }, { - "EventCode": "0x10", + "BriefDescription": "SSE FP packed Uops", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED", "SampleAfterValue": "2000000", - "BriefDescription": "SSE FP packed Uops" + "UMask": "0x10" }, { - "EventCode": "0x10", + "BriefDescription": "SSE FP scalar Uops", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR", "SampleAfterValue": "2000000", - "BriefDescription": "SSE FP scalar Uops" + "UMask": "0x20" }, { - "EventCode": "0x10", + "BriefDescription": "SSE* FP single precision Uops", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", "SampleAfterValue": "2000000", - "BriefDescription": "SSE* FP single precision Uops" + "UMask": "0x40" }, { - "EventCode": "0x10", + "BriefDescription": "Computational floating-point operations execu= ted", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER", - "SampleAfterValue": "2000000", - "BriefDescription": "SSE2 integer Uops" - }, - { "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "FP_COMP_OPS_EXE.X87", "SampleAfterValue": "2000000", - "BriefDescription": "Computational floating-point operations execu= ted" + "UMask": "0x1" }, { - "EventCode": "0xCC", + "BriefDescription": "All Floating Point to and from MMX transition= s", "Counter": "0,1,2,3", - "UMask": "0x3", + "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "All Floating Point to and from MMX transition= s" + "UMask": "0x3" }, { - "EventCode": "0xCC", + "BriefDescription": "Transitions from MMX to Floating Point instru= ctions", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.TO_FP", "SampleAfterValue": "2000000", - "BriefDescription": "Transitions from MMX to Floating Point instru= ctions" + "UMask": "0x1" }, { - "EventCode": "0xCC", + "BriefDescription": "Transitions from Floating Point to MMX instru= ctions", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.TO_MMX", "SampleAfterValue": "2000000", - "BriefDescription": "Transitions from Floating Point to MMX instru= ctions" + "UMask": "0x2" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer pack operations", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACK", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer pack operations" + "UMask": "0x4" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer arithmetic operations", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_ARITH", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer arithmetic operations" + "UMask": "0x20" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer logical operations", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_LOGICAL", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer logical operations" + "UMask": "0x10" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer multiply operations", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_MPY", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer multiply operations" + "UMask": "0x1" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer shift operations", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_SHIFT", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer shift operations" + "UMask": "0x2" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer shuffle/move operations", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x12", "EventName": "SIMD_INT_128.SHUFFLE_MOVE", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer shuffle/move operations" + "UMask": "0x40" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer unpack operations", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x12", "EventName": "SIMD_INT_128.UNPACK", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer unpack operations" + "UMask": "0x8" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit pack operations", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACK", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit pack operations" + "UMask": "0x4" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit arithmetic operations", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_ARITH", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit arithmetic operations" + "UMask": "0x20" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit logical operations", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_LOGICAL", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit logical operations" + "UMask": "0x10" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit packed multiply operation= s", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_MPY", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit packed multiply operation= s" + "UMask": "0x1" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit shift operations", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_SHIFT", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit shift operations" + "UMask": "0x2" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit shuffle/move operations", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.SHUFFLE_MOVE", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit shuffle/move operations" + "UMask": "0x40" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit unpack operations", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.UNPACK", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit unpack operations" + "UMask": "0x8" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/frontend.json b/tools= /perf/pmu-events/arch/x86/nehalemex/frontend.json index e5e21e03444d..c561ac24d91d 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemex/frontend.json +++ b/tools/perf/pmu-events/arch/x86/nehalemex/frontend.json @@ -1,26 +1,26 @@ [ { - "EventCode": "0xD0", + "BriefDescription": "Instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD0", "EventName": "MACRO_INSTS.DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions decoded" + "UMask": "0x1" }, { - "EventCode": "0xA6", + "BriefDescription": "Macro-fused instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xA6", "EventName": "MACRO_INSTS.FUSIONS_DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Macro-fused instructions decoded" + "UMask": "0x1" }, { - "EventCode": "0x19", + "BriefDescription": "Two Uop instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x19", "EventName": "TWO_UOP_INSTS_DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Two Uop instructions decoded" + "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/memory.json b/tools/p= erf/pmu-events/arch/x86/nehalemex/memory.json index f914a4525b65..6e95de3f3409 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemex/memory.json +++ b/tools/perf/pmu-events/arch/x86/nehalemex/memory.json @@ -1,739 +1,739 @@ [ { - "EventCode": "0xB7", - "MSRValue": "0x6011", + "BriefDescription": "Offcore data reads satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF811", + "BriefDescription": "Offcore data reads that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF811", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4011", + "BriefDescription": "Offcore data reads satisfied by the local DRA= M", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the local DRA= M", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2011", + "BriefDescription": "Offcore data reads satisfied by a remote DRAM= ", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by a remote DRAM= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6044", + "BriefDescription": "Offcore code reads satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF844", + "BriefDescription": "Offcore code reads that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF844", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4044", + "BriefDescription": "Offcore code reads satisfied by the local DRA= M", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the local DRA= M", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2044", + "BriefDescription": "Offcore code reads satisfied by a remote DRAM= ", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by a remote DRAM= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x60FF", + "BriefDescription": "Offcore requests satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x60FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF8FF", + "BriefDescription": "Offcore requests that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF8FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x40FF", + "BriefDescription": "Offcore requests satisfied by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x40FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x20FF", + "BriefDescription": "Offcore requests satisfied by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x20FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6022", + "BriefDescription": "Offcore RFO requests satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF822", + "BriefDescription": "Offcore RFO requests that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF822", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4022", + "BriefDescription": "Offcore RFO requests satisfied by the local D= RAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the local D= RAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2022", + "BriefDescription": "Offcore RFO requests satisfied by a remote DR= AM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by a remote DR= AM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6008", + "BriefDescription": "Offcore writebacks to any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF808", + "BriefDescription": "Offcore writebacks that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF808", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4008", + "BriefDescription": "Offcore writebacks to the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2008", + "BriefDescription": "Offcore writebacks to a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6077", + "BriefDescription": "Offcore code or data read requests satisfied = by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF877", + "BriefDescription": "Offcore code or data read requests that misse= d the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF877", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests that misse= d the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4077", + "BriefDescription": "Offcore code or data read requests satisfied = by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2077", + "BriefDescription": "Offcore code or data read requests satisfied = by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied = by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6033", + "BriefDescription": "Offcore request =3D all data, response =3D an= y DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request =3D all data, response =3D an= y DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF833", + "BriefDescription": "Offcore request =3D all data, response =3D an= y LLC miss", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF833", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request =3D all data, response =3D an= y LLC miss", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4033", + "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the local DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches stat= isfied by the local DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2033", + "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches stat= isfied by the remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6003", + "BriefDescription": "Offcore demand data requests satisfied by any= DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by any= DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF803", + "BriefDescription": "Offcore demand data requests that missed the = LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF803", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests that missed the = LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4003", + "BriefDescription": "Offcore demand data requests satisfied by the= local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the= local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2003", + "BriefDescription": "Offcore demand data requests satisfied by a r= emote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by a r= emote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6001", + "BriefDescription": "Offcore demand data reads satisfied by any DR= AM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by any DR= AM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF801", + "BriefDescription": "Offcore demand data reads that missed the LLC= ", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF801", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads that missed the LLC= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4001", + "BriefDescription": "Offcore demand data reads satisfied by the lo= cal DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the lo= cal DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2001", + "BriefDescription": "Offcore demand data reads satisfied by a remo= te DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by a remo= te DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6004", + "BriefDescription": "Offcore demand code reads satisfied by any DR= AM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by any DR= AM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF804", + "BriefDescription": "Offcore demand code reads that missed the LLC= ", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF804", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads that missed the LLC= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4004", + "BriefDescription": "Offcore demand code reads satisfied by the lo= cal DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the lo= cal DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2004", + "BriefDescription": "Offcore demand code reads satisfied by a remo= te DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by a remo= te DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6002", + "BriefDescription": "Offcore demand RFO requests satisfied by any = DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by any = DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF802", + "BriefDescription": "Offcore demand RFO requests that missed the L= LC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF802", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests that missed the L= LC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4002", + "BriefDescription": "Offcore demand RFO requests satisfied by the = local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the = local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2002", + "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6080", + "BriefDescription": "Offcore other requests satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF880", + "BriefDescription": "Offcore other requests that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF880", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2080", + "BriefDescription": "Offcore other requests satisfied by a remote = DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by a remote = DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6030", + "BriefDescription": "Offcore prefetch data requests satisfied by a= ny DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6030", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by a= ny DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF830", + "BriefDescription": "Offcore prefetch data requests that missed th= e LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF830", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests that missed th= e LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4030", + "BriefDescription": "Offcore prefetch data requests satisfied by t= he local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4030", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by t= he local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2030", + "BriefDescription": "Offcore prefetch data requests satisfied by a= remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2030", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by a= remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6010", + "BriefDescription": "Offcore prefetch data reads satisfied by any = DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by any = DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF810", + "BriefDescription": "Offcore prefetch data reads that missed the L= LC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF810", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads that missed the L= LC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4010", + "BriefDescription": "Offcore prefetch data reads satisfied by the = local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the = local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2010", + "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6040", + "BriefDescription": "Offcore prefetch code reads satisfied by any = DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by any = DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF840", + "BriefDescription": "Offcore prefetch code reads that missed the L= LC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF840", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads that missed the L= LC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4040", + "BriefDescription": "Offcore prefetch code reads satisfied by the = local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the = local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2040", + "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6020", + "BriefDescription": "Offcore prefetch RFO requests satisfied by an= y DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by an= y DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF820", + "BriefDescription": "Offcore prefetch RFO requests that missed the= LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF820", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests that missed the= LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4020", + "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2020", + "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6070", + "BriefDescription": "Offcore prefetch requests satisfied by any DR= AM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by any DR= AM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF870", + "BriefDescription": "Offcore prefetch requests that missed the LLC= ", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF870", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests that missed the LLC= ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4070", + "BriefDescription": "Offcore prefetch requests satisfied by the lo= cal DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the lo= cal DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2070", + "BriefDescription": "Offcore prefetch requests satisfied by a remo= te DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by a remo= te DRAM", - "Offcore": "1" + "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/other.json b/tools/pe= rf/pmu-events/arch/x86/nehalemex/other.json index af0860622445..f6887b234b0e 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemex/other.json +++ b/tools/perf/pmu-events/arch/x86/nehalemex/other.json @@ -1,210 +1,146 @@ [ { - "EventCode": "0xE8", + "BriefDescription": "ES segment renames", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BPU_CLEARS.EARLY", - "SampleAfterValue": "2000000", - "BriefDescription": "Early Branch Prediciton Unit clears" - }, - { - "EventCode": "0xE8", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BPU_CLEARS.LATE", - "SampleAfterValue": "2000000", - "BriefDescription": "Late Branch Prediction Unit clears" - }, - { - "EventCode": "0xE5", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BPU_MISSED_CALL_RET", - "SampleAfterValue": "2000000", - "BriefDescription": "Branch prediction unit missed call or return" - }, - { "EventCode": "0xD5", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "ES_REG_RENAMES", "SampleAfterValue": "2000000", - "BriefDescription": "ES segment renames" + "UMask": "0x1" }, { - "EventCode": "0x6C", + "BriefDescription": "I/O transactions", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x6C", "EventName": "IO_TRANSACTIONS", "SampleAfterValue": "2000000", - "BriefDescription": "I/O transactions" + "UMask": "0x1" }, { - "EventCode": "0x80", + "BriefDescription": "L1I instruction fetch stall cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x80", "EventName": "L1I.CYCLES_STALLED", "SampleAfterValue": "2000000", - "BriefDescription": "L1I instruction fetch stall cycles" + "UMask": "0x4" }, { - "EventCode": "0x80", + "BriefDescription": "L1I instruction fetch hits", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x80", "EventName": "L1I.HITS", "SampleAfterValue": "2000000", - "BriefDescription": "L1I instruction fetch hits" + "UMask": "0x1" }, { - "EventCode": "0x80", + "BriefDescription": "L1I instruction fetch misses", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x80", "EventName": "L1I.MISSES", "SampleAfterValue": "2000000", - "BriefDescription": "L1I instruction fetch misses" + "UMask": "0x2" }, { - "EventCode": "0x80", + "BriefDescription": "L1I Instruction fetches", "Counter": "0,1,2,3", - "UMask": "0x3", + "EventCode": "0x80", "EventName": "L1I.READS", "SampleAfterValue": "2000000", - "BriefDescription": "L1I Instruction fetches" + "UMask": "0x3" }, { - "EventCode": "0x82", + "BriefDescription": "Large ITLB hit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x82", "EventName": "LARGE_ITLB.HIT", "SampleAfterValue": "200000", - "BriefDescription": "Large ITLB hit" + "UMask": "0x1" }, { - "EventCode": "0x13", + "BriefDescription": "All loads dispatched", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "All loads dispatched" + "UMask": "0x7" }, { - "EventCode": "0x13", + "BriefDescription": "Loads dispatched from the MOB", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.MOB", "SampleAfterValue": "2000000", - "BriefDescription": "Loads dispatched from the MOB" + "UMask": "0x4" }, { - "EventCode": "0x13", + "BriefDescription": "Loads dispatched that bypass the MOB", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.RS", "SampleAfterValue": "2000000", - "BriefDescription": "Loads dispatched that bypass the MOB" + "UMask": "0x1" }, { - "EventCode": "0x13", + "BriefDescription": "Loads dispatched from stage 305", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.RS_DELAYED", "SampleAfterValue": "2000000", - "BriefDescription": "Loads dispatched from stage 305" + "UMask": "0x2" }, { - "EventCode": "0x7", + "BriefDescription": "False dependencies due to partial address ali= asing", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x7", "EventName": "PARTIAL_ADDRESS_ALIAS", "SampleAfterValue": "200000", - "BriefDescription": "False dependencies due to partial address ali= asing" - }, - { - "EventCode": "0xD2", - "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "RAT_STALLS.ANY", - "SampleAfterValue": "2000000", - "BriefDescription": "All RAT stall cycles" - }, - { - "EventCode": "0xD2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "RAT_STALLS.FLAGS", - "SampleAfterValue": "2000000", - "BriefDescription": "Flag stall cycles" - }, - { - "EventCode": "0xD2", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "RAT_STALLS.REGISTERS", - "SampleAfterValue": "2000000", - "BriefDescription": "Partial register stall cycles" - }, - { - "EventCode": "0xD2", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "RAT_STALLS.ROB_READ_PORT", - "SampleAfterValue": "2000000", - "BriefDescription": "ROB read port stalls cycles" + "UMask": "0x1" }, { - "EventCode": "0xD2", + "BriefDescription": "All Store buffer stall cycles", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "RAT_STALLS.SCOREBOARD", - "SampleAfterValue": "2000000", - "BriefDescription": "Scoreboard stall cycles" - }, - { "EventCode": "0x4", - "Counter": "0,1,2,3", - "UMask": "0x7", "EventName": "SB_DRAIN.ANY", "SampleAfterValue": "200000", - "BriefDescription": "All Store buffer stall cycles" + "UMask": "0x7" }, { - "EventCode": "0xD4", + "BriefDescription": "Segment rename stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD4", "EventName": "SEG_RENAME_STALLS", "SampleAfterValue": "2000000", - "BriefDescription": "Segment rename stall cycles" + "UMask": "0x1" }, { - "EventCode": "0xB8", + "BriefDescription": "Thread responded HIT to snoop", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB8", "EventName": "SNOOP_RESPONSE.HIT", "SampleAfterValue": "100000", - "BriefDescription": "Thread responded HIT to snoop" + "UMask": "0x1" }, { - "EventCode": "0xB8", + "BriefDescription": "Thread responded HITE to snoop", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xB8", "EventName": "SNOOP_RESPONSE.HITE", "SampleAfterValue": "100000", - "BriefDescription": "Thread responded HITE to snoop" + "UMask": "0x2" }, { - "EventCode": "0xB8", + "BriefDescription": "Thread responded HITM to snoop", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xB8", "EventName": "SNOOP_RESPONSE.HITM", "SampleAfterValue": "100000", - "BriefDescription": "Thread responded HITM to snoop" + "UMask": "0x4" }, { - "EventCode": "0xF6", + "BriefDescription": "Super Queue full stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xF6", "EventName": "SQ_FULL_STALL_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Super Queue full stall cycles" + "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/pipeline.json b/tools= /perf/pmu-events/arch/x86/nehalemex/pipeline.json index 41006ddcd893..6fc1a6efd8e8 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemex/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/nehalemex/pipeline.json @@ -1,881 +1,945 @@ [ { - "EventCode": "0x14", + "BriefDescription": "Cycles the divider is busy", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x14", "EventName": "ARITH.CYCLES_DIV_BUSY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles the divider is busy" + "UMask": "0x1" }, { - "EventCode": "0x14", - "Invert": "1", + "BriefDescription": "Divide Operations executed", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x14", "EventName": "ARITH.DIV", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Divide Operations executed", - "CounterMask": "1", - "EdgeDetect": "1" + "UMask": "0x1" }, { - "EventCode": "0x14", + "BriefDescription": "Multiply operations executed", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x14", "EventName": "ARITH.MUL", "SampleAfterValue": "2000000", - "BriefDescription": "Multiply operations executed" + "UMask": "0x2" }, { - "EventCode": "0xE6", + "BriefDescription": "BACLEAR asserted with bad target address", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xE6", "EventName": "BACLEAR.BAD_TARGET", "SampleAfterValue": "2000000", - "BriefDescription": "BACLEAR asserted with bad target address" + "UMask": "0x2" }, { - "EventCode": "0xE6", + "BriefDescription": "BACLEAR asserted, regardless of cause", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE6", "EventName": "BACLEAR.CLEAR", "SampleAfterValue": "2000000", - "BriefDescription": "BACLEAR asserted, regardless of cause " + "UMask": "0x1" }, { - "EventCode": "0xA7", + "BriefDescription": "Instruction queue forced BACLEAR", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xA7", "EventName": "BACLEAR_FORCE_IQ", "SampleAfterValue": "2000000", - "BriefDescription": "Instruction queue forced BACLEAR" + "UMask": "0x1" }, { - "EventCode": "0xE0", + "BriefDescription": "Early Branch Prediciton Unit clears", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE8", + "EventName": "BPU_CLEARS.EARLY", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Late Branch Prediction Unit clears", + "Counter": "0,1,2,3", + "EventCode": "0xE8", + "EventName": "BPU_CLEARS.LATE", + "SampleAfterValue": "2000000", + "UMask": "0x2" + }, + { + "BriefDescription": "Branch prediction unit missed call or return", + "Counter": "0,1,2,3", + "EventCode": "0xE5", + "EventName": "BPU_MISSED_CALL_RET", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Branch instructions decoded", + "Counter": "0,1,2,3", + "EventCode": "0xE0", "EventName": "BR_INST_DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Branch instructions decoded" + "UMask": "0x1" }, { - "EventCode": "0x88", + "BriefDescription": "Branch instructions executed", "Counter": "0,1,2,3", - "UMask": "0x7f", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.ANY", "SampleAfterValue": "200000", - "BriefDescription": "Branch instructions executed" + "UMask": "0x7f" }, { - "EventCode": "0x88", + "BriefDescription": "Conditional branch instructions executed", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.COND", "SampleAfterValue": "200000", - "BriefDescription": "Conditional branch instructions executed" + "UMask": "0x1" }, { - "EventCode": "0x88", + "BriefDescription": "Unconditional branches executed", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT", "SampleAfterValue": "200000", - "BriefDescription": "Unconditional branches executed" + "UMask": "0x2" }, { - "EventCode": "0x88", + "BriefDescription": "Unconditional call branches executed", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "20000", - "BriefDescription": "Unconditional call branches executed" + "UMask": "0x10" }, { - "EventCode": "0x88", + "BriefDescription": "Indirect call branches executed", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "20000", - "BriefDescription": "Indirect call branches executed" + "UMask": "0x20" }, { - "EventCode": "0x88", + "BriefDescription": "Indirect non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "20000", - "BriefDescription": "Indirect non call branches executed" + "UMask": "0x4" }, { - "EventCode": "0x88", + "BriefDescription": "Call branches executed", "Counter": "0,1,2,3", - "UMask": "0x30", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.NEAR_CALLS", "SampleAfterValue": "20000", - "BriefDescription": "Call branches executed" + "UMask": "0x30" }, { - "EventCode": "0x88", + "BriefDescription": "All non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.NON_CALLS", "SampleAfterValue": "200000", - "BriefDescription": "All non call branches executed" + "UMask": "0x7" }, { - "EventCode": "0x88", + "BriefDescription": "Indirect return branches executed", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.RETURN_NEAR", "SampleAfterValue": "20000", - "BriefDescription": "Indirect return branches executed" + "UMask": "0x8" }, { - "EventCode": "0x88", + "BriefDescription": "Taken branches executed", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN", "SampleAfterValue": "200000", - "BriefDescription": "Taken branches executed" + "UMask": "0x40" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Retired branch instructions (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired branch instructions (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Retired conditional branch instructions (Prec= ise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired conditional branch instructions (Prec= ise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Retired near call instructions (Precise Event= )", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "Retired near call instructions (Precise Event= )" + "UMask": "0x2" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted branches executed", "Counter": "0,1,2,3", - "UMask": "0x7f", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ANY", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted branches executed" + "UMask": "0x7f" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted conditional branches executed", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.COND", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted conditional branches executed" + "UMask": "0x1" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted unconditional branches executed", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted unconditional branches executed" + "UMask": "0x2" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted non call branches executed" + "UMask": "0x10" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted indirect call branches executed", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted indirect call branches executed" + "UMask": "0x20" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted indirect non call branches execu= ted", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted indirect non call branches execu= ted" + "UMask": "0x4" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted call branches executed", "Counter": "0,1,2,3", - "UMask": "0x30", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NEAR_CALLS", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted call branches executed" + "UMask": "0x30" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NON_CALLS", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted non call branches executed" + "UMask": "0x7" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted return branches executed", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.RETURN_NEAR", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted return branches executed" + "UMask": "0x8" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted taken branches executed", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted taken branches executed" + "UMask": "0x40" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Mispredicted near retired calls (Precise Even= t)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_CALL", + "PEBS": "1", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted near retired calls (Precise Even= t)" + "UMask": "0x2" }, { - "EventCode": "0x0", + "BriefDescription": "Reference cycles when thread is not halted (f= ixed counter)", "Counter": "Fixed counter 3", - "UMask": "0x0", + "EventCode": "0x0", "EventName": "CPU_CLK_UNHALTED.REF", "SampleAfterValue": "2000000", - "BriefDescription": "Reference cycles when thread is not halted (f= ixed counter)" + "UMask": "0x0" }, { - "EventCode": "0x3C", + "BriefDescription": "Reference base clock (133 Mhz) cycles when th= read is not halted (programmable counter)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_P", "SampleAfterValue": "100000", - "BriefDescription": "Reference base clock (133 Mhz) cycles when th= read is not halted (programmable counter)" + "UMask": "0x1" }, { - "EventCode": "0x0", + "BriefDescription": "Cycles when thread is not halted (fixed count= er)", "Counter": "Fixed counter 2", - "UMask": "0x0", + "EventCode": "0x0", "EventName": "CPU_CLK_UNHALTED.THREAD", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles when thread is not halted (fixed count= er)" + "UMask": "0x0" }, { - "EventCode": "0x3C", + "BriefDescription": "Cycles when thread is not halted (programmabl= e counter)", "Counter": "0,1,2,3", - "UMask": "0x0", + "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles when thread is not halted (programmabl= e counter)" + "UMask": "0x0" }, { - "EventCode": "0x3C", - "Invert": "1", + "BriefDescription": "Total CPU cycles", "Counter": "0,1,2,3", - "UMask": "0x0", + "CounterMask": "2", + "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Total CPU cycles", - "CounterMask": "2" + "UMask": "0x0" }, { - "EventCode": "0x87", + "BriefDescription": "Any Instruction Length Decoder stall cycles", "Counter": "0,1,2,3", - "UMask": "0xf", + "EventCode": "0x87", "EventName": "ILD_STALL.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Any Instruction Length Decoder stall cycles" + "UMask": "0xf" }, { - "EventCode": "0x87", + "BriefDescription": "Instruction Queue full stall cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x87", "EventName": "ILD_STALL.IQ_FULL", "SampleAfterValue": "2000000", - "BriefDescription": "Instruction Queue full stall cycles" + "UMask": "0x4" }, { - "EventCode": "0x87", + "BriefDescription": "Length Change Prefix stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "SampleAfterValue": "2000000", - "BriefDescription": "Length Change Prefix stall cycles" + "UMask": "0x1" }, { - "EventCode": "0x87", + "BriefDescription": "Stall cycles due to BPU MRU bypass", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x87", "EventName": "ILD_STALL.MRU", "SampleAfterValue": "2000000", - "BriefDescription": "Stall cycles due to BPU MRU bypass" + "UMask": "0x2" }, { - "EventCode": "0x87", + "BriefDescription": "Regen stall cycles", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x87", "EventName": "ILD_STALL.REGEN", "SampleAfterValue": "2000000", - "BriefDescription": "Regen stall cycles" + "UMask": "0x8" }, { - "EventCode": "0x18", + "BriefDescription": "Instructions that must be decoded by decoder = 0", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x18", "EventName": "INST_DECODED.DEC0", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions that must be decoded by decoder = 0" + "UMask": "0x1" }, { - "EventCode": "0x1E", + "BriefDescription": "Instructions written to instruction queue.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INST_QUEUE_WRITE_CYCLES", + "EventCode": "0x17", + "EventName": "INST_QUEUE_WRITES", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles instructions are written to the instru= ction queue" + "UMask": "0x1" }, { - "EventCode": "0x17", + "BriefDescription": "Cycles instructions are written to the instru= ction queue", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INST_QUEUE_WRITES", + "EventCode": "0x1E", + "EventName": "INST_QUEUE_WRITE_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions written to instruction queue." + "UMask": "0x1" }, { - "EventCode": "0x0", + "BriefDescription": "Instructions retired (fixed counter)", "Counter": "Fixed counter 1", - "UMask": "0x0", + "EventCode": "0x0", "EventName": "INST_RETIRED.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired (fixed counter)" + "UMask": "0x0" }, { - "PEBS": "1", - "EventCode": "0xC0", + "BriefDescription": "Instructions retired (Programmable counter an= d Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired (Programmable counter an= d Precise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC0", + "BriefDescription": "Retired MMX instructions (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC0", "EventName": "INST_RETIRED.MMX", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Retired MMX instructions (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC0", - "Invert": "1", + "BriefDescription": "Total cycles (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "16", + "EventCode": "0xC0", "EventName": "INST_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Total cycles (Precise Event)", - "CounterMask": "16" + "UMask": "0x1" }, { - "PEBS": "1", + "BriefDescription": "Total cycles (Precise Event)", + "Counter": "0,1,2,3", + "CounterMask": "16", "EventCode": "0xC0", + "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", + "Invert": "1", + "PEBS": "2", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired floating-point operations (Precise Ev= ent)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC0", "EventName": "INST_RETIRED.X87", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Retired floating-point operations (Precise Ev= ent)" + "UMask": "0x2" }, { - "EventCode": "0x4C", + "BriefDescription": "Load operations conflicting with software pre= fetches", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x4C", "EventName": "LOAD_HIT_PRE", "SampleAfterValue": "200000", - "BriefDescription": "Load operations conflicting with software pre= fetches" + "UMask": "0x1" }, { - "EventCode": "0xA8", + "BriefDescription": "Cycles when uops were delivered by the LSD", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xA8", "EventName": "LSD.ACTIVE", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles when uops were delivered by the LSD", - "CounterMask": "1" + "UMask": "0x1" }, { - "EventCode": "0xA8", - "Invert": "1", + "BriefDescription": "Cycles no uops were delivered by the LSD", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xA8", "EventName": "LSD.INACTIVE", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no uops were delivered by the LSD", - "CounterMask": "1" + "UMask": "0x1" }, { - "EventCode": "0x20", + "BriefDescription": "Loops that can't stream from the instruction = queue", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x20", "EventName": "LSD_OVERFLOW", "SampleAfterValue": "2000000", - "BriefDescription": "Loops that can't stream from the instruction = queue" + "UMask": "0x1" }, { - "EventCode": "0xC3", + "BriefDescription": "Cycles machine clear asserted", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.CYCLES", "SampleAfterValue": "20000", - "BriefDescription": "Cycles machine clear asserted" + "UMask": "0x1" }, { - "EventCode": "0xC3", + "BriefDescription": "Execution pipeline restart due to Memory orde= ring conflicts", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEM_ORDER", "SampleAfterValue": "20000", - "BriefDescription": "Execution pipeline restart due to Memory orde= ring conflicts" + "UMask": "0x2" }, { - "EventCode": "0xC3", + "BriefDescription": "Self-Modifying Code detected", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "SampleAfterValue": "20000", - "BriefDescription": "Self-Modifying Code detected" + "UMask": "0x4" }, { - "EventCode": "0xA2", + "BriefDescription": "All RAT stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "RESOURCE_STALLS.ANY", + "EventCode": "0xD2", + "EventName": "RAT_STALLS.ANY", + "SampleAfterValue": "2000000", + "UMask": "0xf" + }, + { + "BriefDescription": "Flag stall cycles", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "RAT_STALLS.FLAGS", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Partial register stall cycles", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "RAT_STALLS.REGISTERS", + "SampleAfterValue": "2000000", + "UMask": "0x2" + }, + { + "BriefDescription": "ROB read port stalls cycles", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "RAT_STALLS.ROB_READ_PORT", + "SampleAfterValue": "2000000", + "UMask": "0x4" + }, + { + "BriefDescription": "Scoreboard stall cycles", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "RAT_STALLS.SCOREBOARD", "SampleAfterValue": "2000000", - "BriefDescription": "Resource related stall cycles" + "UMask": "0x8" }, { + "BriefDescription": "Resource related stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ANY", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "FPU control word write stall cycles", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.FPCW", "SampleAfterValue": "2000000", - "BriefDescription": "FPU control word write stall cycles" + "UMask": "0x20" }, { - "EventCode": "0xA2", + "BriefDescription": "Load buffer stall cycles", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.LOAD", "SampleAfterValue": "2000000", - "BriefDescription": "Load buffer stall cycles" + "UMask": "0x2" }, { - "EventCode": "0xA2", + "BriefDescription": "MXCSR rename stall cycles", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.MXCSR", "SampleAfterValue": "2000000", - "BriefDescription": "MXCSR rename stall cycles" + "UMask": "0x40" }, { - "EventCode": "0xA2", + "BriefDescription": "Other Resource related stall cycles", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.OTHER", "SampleAfterValue": "2000000", - "BriefDescription": "Other Resource related stall cycles" + "UMask": "0x80" }, { - "EventCode": "0xA2", + "BriefDescription": "ROB full stall cycles", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ROB_FULL", "SampleAfterValue": "2000000", - "BriefDescription": "ROB full stall cycles" + "UMask": "0x10" }, { - "EventCode": "0xA2", + "BriefDescription": "Reservation Station full stall cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.RS_FULL", "SampleAfterValue": "2000000", - "BriefDescription": "Reservation Station full stall cycles" + "UMask": "0x4" }, { - "EventCode": "0xA2", + "BriefDescription": "Store buffer stall cycles", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.STORE", "SampleAfterValue": "2000000", - "BriefDescription": "Store buffer stall cycles" + "UMask": "0x8" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Packed-Double Uops retired (Precise Even= t)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Packed-Double Uops retired (Precise Even= t)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Packed-Single Uops retired (Precise Even= t)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Packed-Single Uops retired (Precise Even= t)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Even= t)", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Even= t)" + "UMask": "0x8" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Even= t)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Even= t)" + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Vector Integer Uops retired (Precise Eve= nt)", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Vector Integer Uops retired (Precise Eve= nt)" + "UMask": "0x10" }, { - "EventCode": "0xDB", + "BriefDescription": "Stack pointer instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOP_UNFUSION", - "SampleAfterValue": "2000000", - "BriefDescription": "Uop unfusions due to FP exceptions" - }, - { "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x4", "EventName": "UOPS_DECODED.ESP_FOLDING", "SampleAfterValue": "2000000", - "BriefDescription": "Stack pointer instructions decoded" + "UMask": "0x4" }, { - "EventCode": "0xD1", + "BriefDescription": "Stack pointer sync operations", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xD1", "EventName": "UOPS_DECODED.ESP_SYNC", "SampleAfterValue": "2000000", - "BriefDescription": "Stack pointer sync operations" + "UMask": "0x8" }, { - "EventCode": "0xD1", + "BriefDescription": "Uops decoded by Microcode Sequencer", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterMask": "1", + "EventCode": "0xD1", "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops decoded by Microcode Sequencer", - "CounterMask": "1" + "UMask": "0x2" }, { - "EventCode": "0xD1", - "Invert": "1", + "BriefDescription": "Cycles no Uops are decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xD1", "EventName": "UOPS_DECODED.STALL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops are decoded", - "CounterMask": "1" + "UMask": "0x1" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x3f", "AnyThread": "1", + "BriefDescription": "Cycles Uops executed on any port (core count)= ", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops executed on any port (core count)= ", - "CounterMask": "1" + "UMask": "0x3f" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1f", "AnyThread": "1", + "BriefDescription": "Cycles Uops executed on ports 0-4 (core count= )", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops executed on ports 0-4 (core count= )", - "CounterMask": "1" + "UMask": "0x1f" }, { - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x3f", "AnyThread": "1", - "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT", - "SampleAfterValue": "2000000", "BriefDescription": "Uops executed on any port (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", - "EdgeDetect": "1" - }, - { + "EdgeDetect": "1", "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT", "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1f", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on ports 0-4 (core count)", - "CounterMask": "1", - "EdgeDetect": "1" + "UMask": "0x3f" }, { + "AnyThread": "1", + "BriefDescription": "Uops executed on ports 0-4 (core count)", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EdgeDetect": "1", "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5", "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x3f", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops issued on any port (core count= )", - "CounterMask": "1" + "UMask": "0x1f" }, { + "AnyThread": "1", + "BriefDescription": "Cycles no Uops issued on any port (core count= )", + "Counter": "0,1,2,3", + "CounterMask": "1", "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES", "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1f", + "SampleAfterValue": "2000000", + "UMask": "0x3f" + }, + { "AnyThread": "1", + "BriefDescription": "Cycles no Uops issued on ports 0-4 (core coun= t)", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops issued on ports 0-4 (core coun= t)", - "CounterMask": "1" + "UMask": "0x1f" }, { - "EventCode": "0xB1", + "BriefDescription": "Uops executed on port 0", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT0", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 0" + "UMask": "0x1" }, { - "EventCode": "0xB1", + "BriefDescription": "Uops issued on ports 0, 1 or 5", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT015", "SampleAfterValue": "2000000", - "BriefDescription": "Uops issued on ports 0, 1 or 5" + "UMask": "0x40" }, { - "EventCode": "0xB1", - "Invert": "1", + "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5", "Counter": "0,1,2,3", - "UMask": "0x40", + "CounterMask": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5", - "CounterMask": "1" + "UMask": "0x40" }, { - "EventCode": "0xB1", + "BriefDescription": "Uops executed on port 1", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT1", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 1" + "UMask": "0x2" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x4", "AnyThread": "1", - "EventName": "UOPS_EXECUTED.PORT2_CORE", + "BriefDescription": "Uops issued on ports 2, 3 or 4", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.PORT234_CORE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 2 (core count)" + "UMask": "0x80" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x80", "AnyThread": "1", - "EventName": "UOPS_EXECUTED.PORT234_CORE", + "BriefDescription": "Uops executed on port 2 (core count)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.PORT2_CORE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops issued on ports 2, 3 or 4" + "UMask": "0x4" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x8", "AnyThread": "1", + "BriefDescription": "Uops executed on port 3 (core count)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT3_CORE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 3 (core count)" + "UMask": "0x8" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x10", "AnyThread": "1", + "BriefDescription": "Uops executed on port 4 (core count)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT4_CORE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 4 (core count)" + "UMask": "0x10" }, { - "EventCode": "0xB1", + "BriefDescription": "Uops executed on port 5", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT5", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 5" + "UMask": "0x20" }, { - "EventCode": "0xE", + "BriefDescription": "Uops issued", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Uops issued" + "UMask": "0x1" }, { - "EventCode": "0xE", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", "AnyThread": "1", + "BriefDescription": "Cycles no Uops were issued on any thread", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops were issued on any thread", - "CounterMask": "1" + "UMask": "0x1" }, { - "EventCode": "0xE", - "Counter": "0,1,2,3", - "UMask": "0x1", "AnyThread": "1", + "BriefDescription": "Cycles Uops were issued on either thread", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops were issued on either thread", - "CounterMask": "1" + "UMask": "0x1" }, { - "EventCode": "0xE", + "BriefDescription": "Fused Uops issued", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.FUSED", "SampleAfterValue": "2000000", - "BriefDescription": "Fused Uops issued" + "UMask": "0x2" }, { - "EventCode": "0xE", - "Invert": "1", + "BriefDescription": "Cycles no Uops were issued", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops were issued", - "CounterMask": "1" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Cycles Uops are being retired", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ACTIVE_CYCLES", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops are being retired", - "CounterMask": "1" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ANY", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Uops retired (Precise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Macro-fused Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.MACRO_FUSED", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Macro-fused Uops retired (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Retirement slots used (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Retirement slots used (Precise Event)" + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xC2", - "Invert": "1", + "BriefDescription": "Cycles Uops are not retiring (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.STALL_CYCLES", + "Invert": "1", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops are not retiring (Precise Event)", - "CounterMask": "1" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC2", - "Invert": "1", + "BriefDescription": "Total cycles using precise uop retired event = (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "16", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Total cycles using precise uop retired event = (Precise Event)", - "CounterMask": "16" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xC0", - "Invert": "1", + "BriefDescription": "Uop unfusions due to FP exceptions", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", + "EventCode": "0xDB", + "EventName": "UOP_UNFUSION", "SampleAfterValue": "2000000", - "BriefDescription": "Total cycles (Precise Event)", - "CounterMask": "16" + "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/virtual-memory.json b= /tools/perf/pmu-events/arch/x86/nehalemex/virtual-memory.json index 0596094e0ee9..e88c0802e679 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemex/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/nehalemex/virtual-memory.json @@ -1,109 +1,109 @@ [ { - "EventCode": "0x8", + "BriefDescription": "DTLB load misses", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.ANY", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load misses" + "UMask": "0x1" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB load miss caused by low part of address", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.PDE_MISS", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss caused by low part of address" + "UMask": "0x20" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB second level hit", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "2000000", - "BriefDescription": "DTLB second level hit" + "UMask": "0x10" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB load miss page walks complete", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss page walks complete" + "UMask": "0x2" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB misses", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x49", "EventName": "DTLB_MISSES.ANY", "SampleAfterValue": "200000", - "BriefDescription": "DTLB misses" + "UMask": "0x1" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB first level misses but second level hit", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x49", "EventName": "DTLB_MISSES.STLB_HIT", "SampleAfterValue": "200000", - "BriefDescription": "DTLB first level misses but second level hit" + "UMask": "0x10" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB miss page walks", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x49", "EventName": "DTLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "DTLB miss page walks" + "UMask": "0x2" }, { - "EventCode": "0xAE", + "BriefDescription": "ITLB flushes", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xAE", "EventName": "ITLB_FLUSH", "SampleAfterValue": "2000000", - "BriefDescription": "ITLB flushes" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC8", + "BriefDescription": "ITLB miss", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "ITLB_MISS_RETIRED", - "SampleAfterValue": "200000", - "BriefDescription": "Retired instructions that missed the ITLB (Pr= ecise Event)" - }, - { "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "ITLB_MISSES.ANY", "SampleAfterValue": "200000", - "BriefDescription": "ITLB miss" + "UMask": "0x1" }, { - "EventCode": "0x85", + "BriefDescription": "ITLB miss page walks", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "ITLB miss page walks" + "UMask": "0x2" }, { + "BriefDescription": "Retired instructions that missed the ITLB (Pr= ecise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xC8", + "EventName": "ITLB_MISS_RETIRED", "PEBS": "1", - "EventCode": "0xCB", + "SampleAfterValue": "200000", + "UMask": "0x20" + }, + { + "BriefDescription": "Retired loads that miss the DTLB (Precise Eve= nt)", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that miss the DTLB (Precise Eve= nt)" + "UMask": "0x80" }, { - "PEBS": "1", - "EventCode": "0xC", + "BriefDescription": "Retired stores that miss the DTLB (Precise Ev= ent)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC", "EventName": "MEM_STORE_RETIRED.DTLB_MISS", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired stores that miss the DTLB (Precise Ev= ent)" + "UMask": "0x1" } -] \ No newline at end of file +] --=20 2.37.1.359.gd136c6c3e2-goog From nobody Wed Apr 15 05:45:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA3B7C19F2B for ; Wed, 27 Jul 2022 22:12:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234657AbiG0WM0 (ORCPT ); Wed, 27 Jul 2022 18:12:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54674 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234589AbiG0WLA (ORCPT ); Wed, 27 Jul 2022 18:11:00 -0400 Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4D4ED6050B for ; Wed, 27 Jul 2022 15:09:41 -0700 (PDT) Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-31ea3f0e357so909227b3.16 for ; Wed, 27 Jul 2022 15:09:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc:content-transfer-encoding; bh=9Gc2w15QpXr70RCVVUOr9rn9w+unlgQvLTkvIDXXoOo=; b=SrEQAFOqB7f32wvWb7ZhymAbrJTFjQF6fgdOjnLcn9FUGZWrhogkXeqVjOQuicgbNO rS4flrgM8J1wWmax5gvuY6NUT/Po6Yf38EsSxdj9i6ovJelmAdutDJrvyBbtqHptWFd6 1sudT3QQWj0MbkvZy/JeMRNGC8/Ic71mQmHKFiyQy5Eurogdi0SeSZmBHbVax0kFsmGd +LmCcfO9YMSjoLmDe9BM24zSyvfkV0w4epyxBgEL7a5OfOExVzsL9S5NI1pRbnsGSOIh caU69LDa2lsT0arl+BFhuilV0GpWxGHXadyysa5T5RnfZ+Wd+poNVXHZgNz9Cxe3OK6R Ky7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc:content-transfer-encoding; bh=9Gc2w15QpXr70RCVVUOr9rn9w+unlgQvLTkvIDXXoOo=; b=RHQJjDimObgGWalzhu8JGqusa0PiwuzDnaa3Rblzqke4n90YcHJFdQhreelP5B0pU/ 6Q+yuE6cGjCMos6hLTvsUEwjM31krAppywPWGo9g6+pByfmuBtyBns/MromG3XcE+t8C FryGtPgU2OcMQEcuF7sQHQJvfixquuwkwJCEGBrV5PKp5kp43/SIGoFKTlIgsJzJRhHr CkR5d1Hx8HWk2cg1fAuEfSVBizjS+bXxr8EE+HNWSNWR34LsJ5WeBBJuLWVJ1xqig8qK p9Pic9qPtCLCSGuo4hMO57BLo+0qcIxBhu2nZeoLQoRlEgSykDI03+hDtF69EuZ24yZp ChEw== X-Gm-Message-State: AJIora8n3quz5gJ5OBGYcmiXdIPA8cr4bM/Ky0QbckGBmArz1VjH+rYP RUK9rnmdOiZRCJbB4BuGmz0++RBI8ZQu X-Google-Smtp-Source: AGRyM1vxhp1kwEareI7JfTulz8twIP2TkoCgly5FajyKFvIcXmhDp7ZtArzkKoH6kD82u1gwj90Ak5IfMrYy X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:882a:af57:8cb6:6f9e]) (user=irogers job=sendgmr) by 2002:a81:6c94:0:b0:31f:517e:c6ef with SMTP id h142-20020a816c94000000b0031f517ec6efmr7944742ywc.165.1658959780468; Wed, 27 Jul 2022 15:09:40 -0700 (PDT) Date: Wed, 27 Jul 2022 15:08:23 -0700 In-Reply-To: <20220727220832.2865794-1-irogers@google.com> Message-Id: <20220727220832.2865794-22-irogers@google.com> Mime-Version: 1.0 References: <20220727220832.2865794-1-irogers@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH v3 21/30] perf vendor events: Update Intel sandybridge From: Ian Rogers To: perry.taylor@intel.com, caleb.biggers@intel.com, kshipra.bopardikar@intel.com, Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Sedat Dilek Cc: Stephane Eranian , Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Update to v17, the metrics are based on TMA 4.4 full. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/downloa= d_and_gen.py to download and generate the latest events and metrics. Manually copy the sandybridge files into perf and update mapfile.csv. Tested on a non-sandybridge with 'perf test': 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok Signed-off-by: Ian Rogers --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- tools/perf/pmu-events/arch/x86/sandybridge/cache.json | 2 +- .../arch/x86/sandybridge/floating-point.json | 2 +- .../pmu-events/arch/x86/sandybridge/frontend.json | 4 ++-- .../perf/pmu-events/arch/x86/sandybridge/memory.json | 2 +- tools/perf/pmu-events/arch/x86/sandybridge/other.json | 2 +- .../pmu-events/arch/x86/sandybridge/pipeline.json | 10 +++++----- .../pmu-events/arch/x86/sandybridge/snb-metrics.json | 11 +++++++++-- .../pmu-events/arch/x86/sandybridge/uncore-other.json | 2 +- .../arch/x86/sandybridge/virtual-memory.json | 2 +- 10 files changed, 23 insertions(+), 16 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 2f9419ee2d29..0b56c4a8a3a8 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -19,12 +19,12 @@ GenuineIntel-6-(57|85),v9,knightslanding,core GenuineIntel-6-AA,v1.00,meteorlake,core GenuineIntel-6-1[AEF],v3,nehalemep,core GenuineIntel-6-2E,v3,nehalemex,core +GenuineIntel-6-2A,v17,sandybridge,core GenuineIntel-6-[4589]E,v24,skylake,core GenuineIntel-6-A[56],v24,skylake,core GenuineIntel-6-37,v13,silvermont,core GenuineIntel-6-4D,v13,silvermont,core GenuineIntel-6-4C,v13,silvermont,core -GenuineIntel-6-2A,v15,sandybridge,core GenuineIntel-6-2C,v2,westmereep-dp,core GenuineIntel-6-25,v2,westmereep-sp,core GenuineIntel-6-2F,v2,westmereex,core diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/cache.json b/tools/= perf/pmu-events/arch/x86/sandybridge/cache.json index 92a7269eb444..a1d622352131 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/cache.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/cache.json @@ -1876,4 +1876,4 @@ "SampleAfterValue": "100003", "UMask": "0x10" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json= b/tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json index 713878fd062b..eb2ff2cfdf6b 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json @@ -135,4 +135,4 @@ "SampleAfterValue": "2000003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/frontend.json b/too= ls/perf/pmu-events/arch/x86/sandybridge/frontend.json index fa22f9463b66..e2c82e43a2de 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/frontend.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/frontend.json @@ -176,7 +176,7 @@ "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_CYCLES", - "PublicDescription": "This event counts cycles during which the mi= crocode sequencer assisted the front-end in delivering uops. Microcode ass= ists are used for complex instructions or scenarios that can't be handled b= y the standard decoder. Using other instructions, if possible, will usuall= y improve performance. See the Intel 64 and IA-32 Architectures Optimizati= on Reference Manual for more information.", + "PublicDescription": "This event counts cycles during which the mi= crocode sequencer assisted the front-end in delivering uops. Microcode ass= ists are used for complex instructions or scenarios that can't be handled b= y the standard decoder. Using other instructions, if possible, will usuall= y improve performance. See the Intel(R) 64 and IA-32 Architectures Optimiz= ation Reference Manual for more information.", "SampleAfterValue": "2000003", "UMask": "0x30" }, @@ -311,4 +311,4 @@ "SampleAfterValue": "2000003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/memory.json b/tools= /perf/pmu-events/arch/x86/sandybridge/memory.json index 931892d34076..3c283ca309f3 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/memory.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/memory.json @@ -442,4 +442,4 @@ "SampleAfterValue": "100003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/other.json b/tools/= perf/pmu-events/arch/x86/sandybridge/other.json index e251f535ec09..2f873ab14156 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/other.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/other.json @@ -55,4 +55,4 @@ "SampleAfterValue": "2000003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json b/too= ls/perf/pmu-events/arch/x86/sandybridge/pipeline.json index b9a3f194a00a..2c3b6c92aa6b 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json @@ -609,7 +609,7 @@ "UMask": "0x3" }, { - "BriefDescription": "Number of occurences waiting for the checkpoi= nts in Resource Allocation Table (RAT) to be recovered after Nuke due to al= l other cases except JEClear (e.g. whenever a ucode assist is needed like S= SE exception, memory disambiguation, etc...).", + "BriefDescription": "Number of occurrences waiting for the checkpo= ints in Resource Allocation Table (RAT) to be recovered after Nuke due to a= ll other cases except JEClear (e.g. whenever a ucode assist is needed like = SSE exception, memory disambiguation, etc...).", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", @@ -652,7 +652,7 @@ "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", - "PublicDescription": "This event counts loads that followed a stor= e to the same address, where the data could not be forwarded inside the pip= eline from the store to the load. The most common reason why store forward= ing would be blocked is when a load's address range overlaps with a preceed= ing smaller uncompleted store. See the table of not supported store forwar= ds in the Intel 64 and IA-32 Architectures Optimization Reference Manual. = The penalty for blocked store forwarding is that the load must wait for the= store to complete before it can be issued.", + "PublicDescription": "This event counts loads that followed a stor= e to the same address, where the data could not be forwarded inside the pip= eline from the store to the load. The most common reason why store forward= ing would be blocked is when a load's address range overlaps with a preceed= ing smaller uncompleted store. See the table of not supported store forwar= ds in the Intel(R) 64 and IA-32 Architectures Optimization Reference Manual= . The penalty for blocked store forwarding is that the load must wait for = the store to complete before it can be issued.", "SampleAfterValue": "100003", "UMask": "0x2" }, @@ -778,7 +778,7 @@ "CounterMask": "1", "EventCode": "0x59", "EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP_CYCLES", - "PublicDescription": "This event counts the number of cycles spent= executing performance-sensitive flags-merging uops. For example, shift CL = (merge_arith_flags). For more details, See the Intel 64 and IA-32 Architect= ures Optimization Reference Manual.", + "PublicDescription": "This event counts the number of cycles spent= executing performance-sensitive flags-merging uops. For example, shift CL = (merge_arith_flags). For more details, See the Intel(R) 64 and IA-32 Archit= ectures Optimization Reference Manual.", "SampleAfterValue": "2000003", "UMask": "0x20" }, @@ -797,7 +797,7 @@ "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x59", "EventName": "PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW", - "PublicDescription": "This event counts the number of cycles with = at least one slow LEA uop being allocated. A uop is generally considered as= slow LEA if it has three sources (for example, two sources and immediate) = regardless of whether it is a result of LEA instruction or not. Examples of= the slow LEA uop are or uops with base, index, and offset source operands = using base and index reqisters, where base is EBR/RBP/R13, using RIP relati= ve or 16-bit addressing modes. See the Intel 64 and IA-32 Architectures Opt= imization Reference Manual for more details about slow LEA instructions.", + "PublicDescription": "This event counts the number of cycles with = at least one slow LEA uop being allocated. A uop is generally considered as= slow LEA if it has three sources (for example, two sources and immediate) = regardless of whether it is a result of LEA instruction or not. Examples of= the slow LEA uop are or uops with base, index, and offset source operands = using base and index reqisters, where base is EBR/RBP/R13, using RIP relati= ve or 16-bit addressing modes. See the Intel(R) 64 and IA-32 Architectures = Optimization Reference Manual for more details about slow LEA instructions.= ", "SampleAfterValue": "2000003", "UMask": "0x40" }, @@ -1209,4 +1209,4 @@ "SampleAfterValue": "2000003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json b/= tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json index c8e7050d9c26..ae7ed267b2a2 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json @@ -124,7 +124,7 @@ "MetricName": "FLOPc_SMT" }, { - "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is at least 1 uop executed)", + "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per-core", "MetricExpr": "UOPS_DISPATCHED.THREAD / (( cpu@UOPS_DISPATCHED.COR= E\\,cmask\\=3D1@ / 2 ) if #SMT_on else cpu@UOPS_DISPATCHED.CORE\\,cmask\\= =3D1@)", "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" @@ -141,6 +141,12 @@ "MetricGroup": "Summary;TmaL1", "MetricName": "Instructions" }, + { + "BriefDescription": "Average number of Uops retired in cycles wher= e at least one uop has retired.", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE= _SLOTS\\,cmask\\=3D1@", + "MetricGroup": "Pipeline;Ret", + "MetricName": "Retire" + }, { "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MIT= E_UOPS + IDQ.MS_UOPS ) )", @@ -163,7 +169,8 @@ "BriefDescription": "Giga Floating Point Operations Per Second", "MetricExpr": "( ( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_CO= MP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 = * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * S= IMD_FP_256.PACKED_SINGLE ) / 1000000000 ) / duration_time", "MetricGroup": "Cor;Flops;HPC", - "MetricName": "GFLOPs" + "MetricName": "GFLOPs", + "PublicDescription": "Giga Floating Point Operations Per Second. A= ggregate across all supported options of: FP precisions, scalar and vector = instructions, vector-width and AMX engine." }, { "BriefDescription": "Average Frequency Utilization relative nomina= l frequency", diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/uncore-other.json b= /tools/perf/pmu-events/arch/x86/sandybridge/uncore-other.json index 6278068908cf..88f1e326205f 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/uncore-other.json @@ -82,10 +82,10 @@ { "BriefDescription": "This 48-bit fixed counter counts the UCLK cyc= les.", "Counter": "Fixed", + "EventCode": "0xff", "EventName": "UNC_CLOCK.SOCKET", "PerPkg": "1", "PublicDescription": "This 48-bit fixed counter counts the UCLK cy= cles.", - "UMask": "0x01", "Unit": "ARB" } ] diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json= b/tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json index 4dd136d00a10..98362abba1a7 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json @@ -146,4 +146,4 @@ "SampleAfterValue": "100007", "UMask": "0x20" } -] \ No newline at end of file +] --=20 2.37.1.359.gd136c6c3e2-goog From nobody Wed Apr 15 05:45:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 661C7C04A68 for ; Wed, 27 Jul 2022 22:12:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237400AbiG0WMn (ORCPT ); Wed, 27 Jul 2022 18:12:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54800 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236038AbiG0WLF (ORCPT ); Wed, 27 Jul 2022 18:11:05 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5386E60534 for ; Wed, 27 Jul 2022 15:09:44 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id a11-20020a5b090b000000b00672acbe13c1so257884ybq.2 for ; Wed, 27 Jul 2022 15:09:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc:content-transfer-encoding; bh=q5I7cSh1hZ5hUaG9oP/hKj02fl7BLkhlrzGqrEd6Zk4=; b=nJjfXSPz9aDkS8Gzy13fCPAHs9P4SlqbTVPQ2mCYQupdphP0riZo47ZrQ/rXSlZRIk Bi6q8QUdWF1URVxJo65jMNtEcqsGQBlDLRosp5xeC1i5KUdn+x1+MFDQc3v/td3ukTSd NHSLoYqKtzoPs/vXhvI/3TzoJdGdd70NYEMB5XC7OlxmUpyUnJrCEihT4IHYrSY2I+0t HhELsjNKqK42eKrF3w22TvXt/YTT4kYjZO09XY5tkcTo/lhLL9VqtEnDatZqiWDOj2zB mIir4QMkpA7QVOiuM2+5cxJGMO+Ko+8eH1nPb7zZ0c0z2VmK/+U9fZyq6rRvBmuVlBxb XbEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc:content-transfer-encoding; bh=q5I7cSh1hZ5hUaG9oP/hKj02fl7BLkhlrzGqrEd6Zk4=; b=LR5T6yOATY6YarZvZmdaNr1EGWuZlwhuhpKxJlZ22Nbc5LkF6vpfLn4s+C4UN6HMiL uN0R3//f1ZNVk20BpIACX8L6vCjBEcQPpALE0o/fNPR07XV86eW+YMByz+S+4GXiKMjm hthJSEmJiMb8ERnqqpTJpCDR3lnLSEZhO67zPmM98G29ufoKrn3rp+0VROlwM5aTyL3S KslUdXx+0XQnpo760Cd8mYHhgJ4sj2ZxENCrNYKNGsO36Eicg0fVAUimiRUVW3b+eZKR 6s+Q+C7kuEp0cBhlr98cJLvmSB4MxpKigIv2mnYNNYlaQTQNMwlYGzKhOhpx6IVXop1r GR8A== X-Gm-Message-State: AJIora+V7XaHTcST7/1UvtiLEh0LG79MuomJJXsiwTI/Mrm6L26jWDFy C3ileL9zcESkktpZmt2VKAlazHHAHhES X-Google-Smtp-Source: AGRyM1sV3mtDliYqRx5llWVgk0fSsdQWJQnogV327eU583NLLuFz9TfYMV6GF51m/L1vdeQfJGJo2UEbt78N X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:882a:af57:8cb6:6f9e]) (user=irogers job=sendgmr) by 2002:a05:6902:3c4:b0:670:6a54:dbc2 with SMTP id g4-20020a05690203c400b006706a54dbc2mr18617548ybs.576.1658959783369; Wed, 27 Jul 2022 15:09:43 -0700 (PDT) Date: Wed, 27 Jul 2022 15:08:24 -0700 In-Reply-To: <20220727220832.2865794-1-irogers@google.com> Message-Id: <20220727220832.2865794-23-irogers@google.com> Mime-Version: 1.0 References: <20220727220832.2865794-1-irogers@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH v3 22/30] perf vendor events: Update Intel sapphirerapids From: Ian Rogers To: perry.taylor@intel.com, caleb.biggers@intel.com, kshipra.bopardikar@intel.com, Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Sedat Dilek Cc: Stephane Eranian , Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Update to v1.04, the metrics are based on TMA 4.4 full. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/downloa= d_and_gen.py to download and generate the latest events and metrics. Manually copy the sapphirerapids files into perf and update mapfile.csv. Tested on a non-sapphirerapids with 'perf test': 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok Signed-off-by: Ian Rogers --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- .../arch/x86/sapphirerapids/cache.json | 46 +- .../arch/x86/sapphirerapids/memory.json | 11 + .../arch/x86/sapphirerapids/other.json | 64 +- .../arch/x86/sapphirerapids/pipeline.json | 18 +- .../arch/x86/sapphirerapids/spr-metrics.json | 566 +++++++++++++++++- .../arch/x86/sapphirerapids/uncore-other.json | 9 - 7 files changed, 691 insertions(+), 25 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 0b56c4a8a3a8..317ae526e376 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -20,6 +20,7 @@ GenuineIntel-6-AA,v1.00,meteorlake,core GenuineIntel-6-1[AEF],v3,nehalemep,core GenuineIntel-6-2E,v3,nehalemex,core GenuineIntel-6-2A,v17,sandybridge,core +GenuineIntel-6-8F,v1.04,sapphirerapids,core GenuineIntel-6-[4589]E,v24,skylake,core GenuineIntel-6-A[56],v24,skylake,core GenuineIntel-6-37,v13,silvermont,core @@ -31,7 +32,6 @@ GenuineIntel-6-2F,v2,westmereex,core GenuineIntel-6-55-[01234],v1,skylakex,core GenuineIntel-6-8[CD],v1,tigerlake,core GenuineIntel-6-86,v1,snowridgex,core -GenuineIntel-6-8F,v1,sapphirerapids,core AuthenticAMD-23-([12][0-9A-F]|[0-9A-F]),v2,amdzen1,core AuthenticAMD-23-[[:xdigit:]]+,v1,amdzen2,core AuthenticAMD-25-[[:xdigit:]]+,v1,amdzen3,core diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/cache.json b/too= ls/perf/pmu-events/arch/x86/sapphirerapids/cache.json index 92c55ef996aa..348476ce8107 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/cache.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/cache.json @@ -131,6 +131,18 @@ "Speculative": "1", "UMask": "0x1" }, + { + "BriefDescription": "Cache lines that have been L2 hardware prefet= ched but not used by demand accesses", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x26", + "EventName": "L2_LINES_OUT.USELESS_HWPF", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of cache lines that have b= een prefetched by the L2 hardware prefetcher but not used by demand access = when evicted from the L2 cache", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x4" + }, { "BriefDescription": "All accesses to L2 cache[This event is alias = to L2_RQSTS.REFERENCES]", "CollectPEBSRecord": "2", @@ -358,18 +370,31 @@ "UMask": "0x28" }, { - "BriefDescription": "LONGEST_LAT_CACHE.MISS", + "BriefDescription": "Core-originated cacheable requests that misse= d L3 (Except hardware prefetches to the L3)", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.MISS", "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts core-originated cacheable requests th= at miss the L3 cache (Longest Latency cache). Requests include data and cod= e reads, Reads-for-Ownership (RFOs), speculative accesses and hardware pref= etches to the L1 and L2. It does not include hardware prefetches to the L3= , and may not count other types of requests to the L3.", "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x41" }, { - "BriefDescription": "All retired load instructions.", + "BriefDescription": "Core-originated cacheable requests that refer= to L3 (Except hardware prefetches to the L3)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x2e", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts core-originated cacheable requests to= the L3 cache (Longest Latency cache). Requests include data and code reads= , Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches = to the L1 and L2. It does not include hardware prefetches to the L3, and m= ay not count other types of requests to the L3.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x4f" + }, + { + "BriefDescription": "Retired load instructions.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", @@ -377,12 +402,12 @@ "EventName": "MEM_INST_RETIRED.ALL_LOADS", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts all retired load instructions. This e= vent accounts for SW prefetch instructions for loads.", + "PublicDescription": "Counts all retired load instructions. This e= vent accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2= or PREFETCHW.", "SampleAfterValue": "1000003", "UMask": "0x81" }, { - "BriefDescription": "All retired store instructions.", + "BriefDescription": "Retired store instructions.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", @@ -391,7 +416,7 @@ "L1_Hit_Indication": "1", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts all retired store instructions. This = event account for SW prefetch instructions and PREFETCHW instruction for st= ores.", + "PublicDescription": "Counts all retired store instructions.", "SampleAfterValue": "1000003", "UMask": "0x82" }, @@ -1013,6 +1038,17 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts demand reads for ownership (RFO), hard= ware prefetch RFOs (which bring data to L2), and software prefetches for ex= clusive ownership (PREFETCHW) that hit to a (M)odified cacheline in the L3 = or snoop filter.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.RFO_TO_CORE.L3_HIT_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F80040022", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts streaming stores that hit in the L3 or= were snooped from another core's caches on the same socket.", "Counter": "0,1,2,3", diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/memory.json b/to= ols/perf/pmu-events/arch/x86/sapphirerapids/memory.json index cb861211b7bc..6e761b628ca4 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/memory.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/memory.json @@ -276,6 +276,17 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were not supplied by the local socket's L1, L2, or L3 caches and t= he cacheline is homed locally.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F04C04477", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that missed the L3 Cache and were supplied by the local socket (DRAM or= PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PM= M or DRAM accesses that are controlled by the close or distant SNC Cluster.= It does not count misses to the L3 which go to Local CXL Type 2 Memory or= Local Non DRAM.", "Counter": "0,1,2,3", diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/other.json b/too= ls/perf/pmu-events/arch/x86/sapphirerapids/other.json index acef4a2b8968..95dbef8ae80a 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/other.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/other.json @@ -174,6 +174,17 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts data load hardware prefetch requests t= o the L1 data cache that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.HWPF_L1D.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10400", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts hardware prefetches (which bring data = to L2) that have any type of response.", "Counter": "0,1,2,3", @@ -207,6 +218,17 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts writebacks of modified cachelines and = streaming stores that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.MODIFIED_WRITE.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10808", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that have any type of response.", "Counter": "0,1,2,3", @@ -344,9 +366,49 @@ "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa5", + "EventName": "RS.EMPTY", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts cycles during which the reservation s= tation (RS) is empty for this logical processor. This is usually caused whe= n the front-end pipeline runs into starvation periods (e.g. branch mispredi= ctions or i-cache misses)", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x7" + }, + { + "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xa5", + "EventName": "RS.EMPTY_COUNT", + "Invert": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts end of periods where the Reservation = Station (RS) was empty. Could be useful to closely sample on front-end late= ncy issues (see the FRONTEND_RETIRED event of designated precise events)", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x7" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = RS.EMPTY_COUNT", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xa5", + "EventName": "RS_EMPTY.COUNT", + "Invert": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x7" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = RS.EMPTY", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa5", "EventName": "RS_EMPTY.CYCLES", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles during which the reservation s= tation (RS) is empty for this logical processor.", "SampleAfterValue": "1000003", "Speculative": "1", "UMask": "0x7" diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/pipeline.json b/= tools/perf/pmu-events/arch/x86/sapphirerapids/pipeline.json index bceea0304620..df4f3d714e6e 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/pipeline.json @@ -57,7 +57,6 @@ "EventCode": "0xb0", "EventName": "ARITH.IDIV_ACTIVE", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "ARITH.IDIV_ACTIVE", "SampleAfterValue": "1000003", "Speculative": "1", "UMask": "0x8" @@ -229,7 +228,7 @@ "UMask": "0x10" }, { - "BriefDescription": "number of branch instructions retired that we= re mispredicted and taken. Non PEBS", + "BriefDescription": "number of branch instructions retired that we= re mispredicted and taken.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", @@ -393,6 +392,18 @@ "Speculative": "1", "UMask": "0x3" }, + { + "BriefDescription": "Reference cycles when the core is not in halt= state.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x3c", + "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of reference cycles when t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction or the MWAIT instruction. This event is not affe= cted by core frequency changes (for example, P states, TM2 transitions) but= has the same incrementing frequency as the time stamp counter. This event = can approximate elapsed time while the core was not in a halt state. It is = counted on a dedicated fixed counter, leaving the four (eight when Hyperthr= eading is disabled) programmable counters available for other events. Note:= On all current platforms this event stops counting during 'throttling (TM)= ' states duty off periods the processor is 'halted'. The counter update is= done at a lower clock rate then the core clock the overflow status bit for= this counter may appear 'sticky'. After the counter has overflowed and so= ftware clears the overflow status bit and resets the counter to less than M= AX. The reset value to the counter is not clocked immediately so the overfl= ow status bit will flip 'high (1)' and generate another PMI (if enabled) af= ter which the reset value gets clocked into the counter. Therefore, softwar= e will get the interrupt, read the overflow status bit '1 for bit 34 while = the counter value is less than MAX. Software should ignore this case.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x1" + }, { "BriefDescription": "Core cycles when the thread is not in halt st= ate", "CollectPEBSRecord": "2", @@ -617,12 +628,13 @@ "UMask": "0x10" }, { - "BriefDescription": "Number of all retired NOP instructions.", + "BriefDescription": "Retired NOP instructions.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", "EventName": "INST_RETIRED.NOP", "PEBScounters": "1,2,3,4,5,6,7", + "PublicDescription": "Counts all retired NOP or ENDBR32/64 instruc= tions", "SampleAfterValue": "2000003", "UMask": "0x2" }, diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json= b/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json index 8f9497838bd4..b9adef1fb72e 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json @@ -11,12 +11,6 @@ "MetricGroup": "Ret;Summary", "MetricName": "IPC" }, - { - "BriefDescription": "Cycles Per Instruction (per Logical Processor= )", - "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", - "MetricGroup": "Pipeline;Mem", - "MetricName": "CPI" - }, { "BriefDescription": "Per-Logical Processor actual clocks when the = Logical Processor is active.", "MetricExpr": "CPU_CLK_UNHALTED.THREAD", @@ -526,5 +520,565 @@ "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C6_Pkg_Residency" + }, + { + "BriefDescription": "Percentage of time spent in the active CPU po= wer state C0", + "MetricExpr": "100 * CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricGroup": "", + "MetricName": "cpu_utilization_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "CPU operating frequency (in GHz)", + "MetricExpr": "(( CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_T= SC * #SYSTEM_TSC_FREQ ) / 1000000000) / duration_time", + "MetricGroup": "", + "MetricName": "cpu_operating_frequency", + "ScaleUnit": "1GHz" + }, + { + "BriefDescription": "Cycles per instruction retired; indicating ho= w much time each executed instruction took; in units of cycles.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "cpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "The ratio of number of completed memory load = instructions to the total number completed instructions", + "MetricExpr": "MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "loads_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "The ratio of number of completed memory store= instructions to the total number completed instructions", + "MetricExpr": "MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "stores_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of requests missing L1 data c= ache (includes data+rfo w/ prefetches) to the total number of completed ins= tructions", + "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l1d_mpi_includes_data_plus_rfo_with_prefetches", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of demand load requests hitti= ng in L1 data cache to the total number of completed instructions ", + "MetricExpr": "MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l1d_demand_data_read_hits_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read requests missing= in L1 instruction cache (includes prefetches) to the total number of compl= eted instructions", + "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed demand load requ= ests hitting in L2 cache to the total number of completed instructions ", + "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l2_demand_data_read_hits_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of requests missing L2 cache = (includes code+data+rfo w/ prefetches) to the total number of completed ins= tructions", + "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l2_mpi_includes_code_plus_data_plus_rfo_with_prefet= ches", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed data read reques= t missing L2 cache to the total number of completed instructions", + "MetricExpr": "MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l2_demand_data_read_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read request missing = L2 cache to the total number of completed instructions", + "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l2_demand_code_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of data read requests missing= last level core cache (includes demand w/ prefetches) to the total number = of completed instructions", + "MetricExpr": "( UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA + UNC_CHA= _TOR_INSERTS.IA_MISS_DRD + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF ) / INST_RE= TIRED.ANY", + "MetricGroup": "", + "MetricName": "llc_data_read_mpi_demand_plus_prefetch", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read requests missing= last level core cache (includes demand w/ prefetches) to the total number = of completed instructions", + "MetricExpr": "( UNC_CHA_TOR_INSERTS.IA_MISS_CRD ) / INST_RETIRED.= ANY", + "MetricGroup": "", + "MetricName": "llc_code_read_mpi_demand_plus_prefetch", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) d= emand data read miss (read memory access) in nano seconds", + "MetricExpr": "( ( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DR= D / UNC_CHA_TOR_INSERTS.IA_MISS_DRD ) / ( UNC_CHA_CLOCKTICKS / ( source_cou= nt(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD) * #num_packages ) ) ) * duration_time= )", + "MetricGroup": "", + "MetricName": "llc_demand_data_read_miss_latency", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) d= emand data read miss (read memory access) addressed to local memory in nano= seconds", + "MetricExpr": "( ( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DR= D_LOCAL / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL ) / ( UNC_CHA_CLOCKTICKS / = ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL) * #num_packages ) )= ) * duration_time )", + "MetricGroup": "", + "MetricName": "llc_demand_data_read_miss_latency_for_local_request= s", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) d= emand data read miss (read memory access) addressed to remote memory in nan= o seconds", + "MetricExpr": "( ( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DR= D_REMOTE / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE ) / ( UNC_CHA_CLOCKTICKS = / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE) * #num_packages = ) ) ) * duration_time )", + "MetricGroup": "", + "MetricName": "llc_demand_data_read_miss_latency_for_remote_reques= ts", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) d= emand data read miss (read memory access) addressed to Intel(R) Optane(TM) = Persistent Memory(PMEM) in nano seconds", + "MetricExpr": "( ( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DR= D_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM ) / ( UNC_CHA_CLOCKTICKS / ( so= urce_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM) * #num_packages ) ) ) * d= uration_time )", + "MetricGroup": "", + "MetricName": "llc_demand_data_read_miss_to_pmem_latency", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) d= emand data read miss (read memory access) addressed to DRAM in nano seconds= ", + "MetricExpr": "( ( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DR= D_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR ) / ( UNC_CHA_CLOCKTICKS / ( so= urce_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR) * #num_packages ) ) ) * d= uration_time )", + "MetricGroup": "", + "MetricName": "llc_demand_data_read_miss_to_dram_latency", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = all page sizes) caused by a code fetch to the total number of completed ins= tructions. This implies it missed in the ITLB (Instruction TLB) and further= levels of TLB.", + "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "itlb_2nd_level_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total n= umber of completed instructions. This implies it missed in the Instruction = Translation Lookaside Buffer (ITLB) and further levels of TLB.", + "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY= ", + "MetricGroup": "", + "MetricName": "itlb_2nd_level_large_page_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = all page sizes) caused by demand data loads to the total number of complete= d instructions. This implies it missed in the DTLB and further levels of TL= B.", + "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "dtlb_2nd_level_load_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = 2 megabyte page sizes) caused by demand data loads to the total number of c= ompleted instructions. This implies it missed in the Data Translation Looka= side Buffer (DTLB) and further levels of TLB.", + "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRE= D.ANY", + "MetricGroup": "", + "MetricName": "dtlb_2nd_level_2mb_large_page_load_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = all page sizes) caused by demand data stores to the total number of complet= ed instructions. This implies it missed in the DTLB and further levels of T= LB.", + "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY= ", + "MetricGroup": "", + "MetricName": "dtlb_2nd_level_store_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Memory read that miss the last level cache (L= LC) addressed to local DRAM as a percentage of total memory read accesses, = does not include LLC prefetches.", + "MetricExpr": "100 * ( UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC= _CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL ) / ( UNC_CHA_TOR_INSERTS.IA_MISS_D= RD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS= .IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE )", + "MetricGroup": "", + "MetricName": "numa_percent_reads_addressed_to_local_dram", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Memory reads that miss the last level cache (= LLC) addressed to remote DRAM as a percentage of total memory read accesses= , does not include LLC prefetches.", + "MetricExpr": "100 * ( UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UN= C_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE ) / ( UNC_CHA_TOR_INSERTS.IA_MISS= _DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSER= TS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE )", + "MetricGroup": "", + "MetricName": "numa_percent_reads_addressed_to_remote_dram", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Uncore operating frequency in GHz", + "MetricExpr": "( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_CLOCK= TICKS) * #num_packages ) / 1000000000) / duration_time", + "MetricGroup": "", + "MetricName": "uncore_frequency", + "ScaleUnit": "1GHz" + }, + { + "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data t= ransmit bandwidth (MB/sec)", + "MetricExpr": "( UNC_UPI_TxL_FLITS.ALL_DATA * (64 / 9.0) / 1000000= ) / duration_time", + "MetricGroup": "", + "MetricName": "upi_data_transmit_bw_only_data", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "DDR memory read bandwidth (MB/sec)", + "MetricExpr": "( UNC_M_CAS_COUNT.RD * 64 / 1000000) / duration_tim= e", + "MetricGroup": "", + "MetricName": "memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "DDR memory write bandwidth (MB/sec)", + "MetricExpr": "( UNC_M_CAS_COUNT.WR * 64 / 1000000) / duration_tim= e", + "MetricGroup": "", + "MetricName": "memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "DDR memory bandwidth (MB/sec)", + "MetricExpr": "(( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) * 64 /= 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "memory_bandwidth_total", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) m= emory read bandwidth (MB/sec)", + "MetricExpr": "( UNC_M_PMM_RPQ_INSERTS * 64 / 1000000) / duration_= time", + "MetricGroup": "", + "MetricName": "pmem_memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) m= emory write bandwidth (MB/sec)", + "MetricExpr": "( UNC_M_PMM_WPQ_INSERTS * 64 / 1000000) / duration_= time", + "MetricGroup": "", + "MetricName": "pmem_memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) m= emory bandwidth (MB/sec)", + "MetricExpr": "(( UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS ) = * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "pmem_memory_bandwidth_total", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO reads that are initiated by e= nd device controllers that are requesting memory from the CPU.", + "MetricExpr": "( UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1000000) /= duration_time", + "MetricGroup": "", + "MetricName": "io_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO writes that are initiated by = end device controllers that are writing memory to the CPU.", + "MetricExpr": "(( UNC_CHA_TOR_INSERTS.IO_ITOM + UNC_CHA_TOR_INSERT= S.IO_ITOMCACHENEAR ) * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "io_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Uops delivered from decoded instruction cache= (decoded stream buffer or DSB) as a percent of total uops delivered to Ins= truction Decode Queue", + "MetricExpr": "100 * ( IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UO= PS + IDQ.MS_UOPS + LSD.UOPS ) )", + "MetricGroup": "", + "MetricName": "percent_uops_delivered_from_decoded_icache_dsb", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Uops delivered from legacy decode pipeline (M= icro-instruction Translation Engine or MITE) as a percent of total uops del= ivered to Instruction Decode Queue", + "MetricExpr": "100 * ( IDQ.MITE_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_U= OPS + IDQ.MS_UOPS + LSD.UOPS ) )", + "MetricGroup": "", + "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline_= mite", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Uops delivered from microcode sequencer (MS) = as a percent of total uops delivered to Instruction Decode Queue", + "MetricExpr": "100 * ( IDQ.MS_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOP= S + IDQ.MS_UOPS + LSD.UOPS ) )", + "MetricGroup": "", + "MetricName": "percent_uops_delivered_from_microcode_sequencer_ms", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Bandwidth (MB/sec) of read requests that miss= the last level cache (LLC) and go to local memory.", + "MetricExpr": "( UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1000000) / du= ration_time", + "MetricGroup": "", + "MetricName": "llc_miss_local_memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth (MB/sec) of write requests that mis= s the last level cache (LLC) and go to local memory.", + "MetricExpr": "( UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1000000) / d= uration_time", + "MetricGroup": "", + "MetricName": "llc_miss_local_memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth (MB/sec) of read requests that miss= the last level cache (LLC) and go to remote memory.", + "MetricExpr": "( UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1000000) / d= uration_time", + "MetricGroup": "", + "MetricName": "llc_miss_remote_memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth (MB/sec) of write requests that mis= s the last level cache (LLC) and go to remote memory.", + "MetricExpr": "( UNC_CHA_REQUESTS.WRITES_REMOTE * 64 / 1000000) / = duration_time", + "MetricGroup": "", + "MetricName": "llc_miss_remote_memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend. Frontend denotes th= e first part of the processor core responsible to fetch operations that are= executed later on by the Backend part. Within the Frontend; a branch predi= ctor predicts the next address to fetch; cache-lines are fetched from the m= emory subsystem; parsed into instructions; and lastly decoded into micro-op= erations (uops). Ideally the Frontend can issue Machine_Width uops every cy= cle to the Backend. Frontend Bound denotes unutilized issue-slots when ther= e is no Backend stall; i.e. bubbles where Frontend delivered no uops while = Backend could have accepted them. For example; stalls due to instruction-ca= che misses would be categorized under Frontend Bound.", + "MetricExpr": "100 * ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bou= nd + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - I= NT_MISC.UOP_DROPPING / ( slots ) )", + "MetricGroup": "TmaL1;PGO", + "MetricName": "tma_frontend_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = CPU was stalled due to Frontend latency issues. For example; instruction-c= ache misses; iTLB misses or fetch stalls after a branch misprediction are c= ategorized under Frontend Latency. In such cases; the Frontend eventually d= elivers no uops for some period.", + "MetricExpr": "100 * ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-= bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) = - INT_MISC.UOP_DROPPING / ( slots ) ) )", + "MetricGroup": "Frontend;TmaL2;m_tma_frontend_bound_percent", + "MetricName": "tma_fetch_latency_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to instruction cache misses.", + "MetricExpr": "100 * ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THR= EAD ) )", + "MetricGroup": "BigFoot;FetchLat;IcMiss;TmaL3;m_tma_fetch_latency_= percent", + "MetricName": "tma_icache_misses_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Instruction TLB (ITLB) misses.", + "MetricExpr": "100 * ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THRE= AD ) )", + "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TmaL3;m_tma_fetch_laten= cy_percent", + "MetricName": "tma_itlb_misses_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Branch Resteers. Branch Resteers estimates the Fron= tend delay in fetching operations from corrected path; following all sorts = of miss-predicted branches. For example; branchy code with lots of miss-pre= dictions might get categorized under Branch Resteers. Note the value of thi= s node may overlap with its siblings.", + "MetricExpr": "100 * ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_U= NHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.TH= READ ) ) )", + "MetricGroup": "FetchLat;TmaL3;m_tma_fetch_latency_percent", + "MetricName": "tma_branch_resteers_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decod= ed i-cache) is a Uop Cache where the front-end directly delivers Uops (micr= o operations) avoiding heavy x86 decoding. The DSB pipeline has shorter lat= ency and delivered higher bandwidth than the MITE (legacy instruction decod= e pipeline). Switching between the two pipelines can cause penalties hence = this metric measures the exposed penalty.", + "MetricExpr": "100 * ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CL= K_UNHALTED.THREAD ) )", + "MetricGroup": "DSBmiss;FetchLat;TmaL3;m_tma_fetch_latency_percent= ", + "MetricName": "tma_dsb_switches_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU= was stalled due to Length Changing Prefixes (LCPs). Using proper compiler = flags or Intel Compiler by default will certainly avoid this. #Link: Optimi= zation Guide about LCP BKMs.", + "MetricExpr": "100 * ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "FetchLat;TmaL3;m_tma_fetch_latency_percent", + "MetricName": "tma_lcp_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates the fraction of cycles = when the CPU was stalled due to switches of uop delivery to the Microcode S= equencer (MS). Commonly used instructions are optimized for delivery by the= DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certa= in operations cannot be handled natively by the execution pipeline; and mus= t be performed by microcode (small programs injected into the execution str= eam). Switching to the MS too often can negatively impact performance. The = MS is designated to deliver long uop flows required by CISC instructions li= ke CPUID; or uncommon conditions like Floating Point Assists when dealing w= ith Denormals.", + "MetricExpr": "100 * ( ( 3 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTE= D.THREAD ) )", + "MetricGroup": "FetchLat;MicroSeq;TmaL3;m_tma_fetch_latency_percen= t", + "MetricName": "tma_ms_switches_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = CPU was stalled due to Frontend bandwidth issues. For example; inefficienc= ies at the instruction decoders; or restrictions for caching in the DSB (de= coded uops cache) are categorized under Fetch Bandwidth. In such cases; the= Frontend typically delivers suboptimal amount of uops to the Backend.", + "MetricExpr": "100 * ( max( 0 , ( topdown\\-fe\\-bound / ( topdown= \\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-= bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) - ( ( topdown\\-fetch\\-lat /= ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdo= wn\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) ) )", + "MetricGroup": "FetchBW;Frontend;TmaL2;m_tma_frontend_bound_percen= t", + "MetricName": "tma_fetch_bandwidth_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycle= s in which CPU was likely limited due to the MITE pipeline (the legacy deco= de pipeline). This pipeline is used for code that was not pre-cached in the= DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of= long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", + "MetricExpr": "100 * ( ( IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK = ) / ( CPU_CLK_UNHALTED.DISTRIBUTED ) / 2 )", + "MetricGroup": "DSBmiss;FetchBW;TmaL3;m_tma_fetch_bandwidth_percen= t", + "MetricName": "tma_mite_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycle= s in which CPU was likely limited due to DSB (decoded uop cache) fetch pipe= line. For example; inefficient utilization of the DSB cache structure or b= ank conflict when reading from it; are categorized here.", + "MetricExpr": "100 * ( ( IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK ) = / ( CPU_CLK_UNHALTED.DISTRIBUTED ) / 2 )", + "MetricGroup": "DSB;FetchBW;TmaL3;m_tma_fetch_bandwidth_percent", + "MetricName": "tma_dsb_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This category represents fraction of slots wa= sted due to incorrect speculations. This include slots used to issue uops t= hat do not eventually get retired and slots for which the issue-pipeline wa= s blocked due to recovery from earlier incorrect speculation. For example; = wasted work due to miss-predicted branches are categorized under Bad Specul= ation category. Incorrect data speculation followed by Memory Ordering Nuke= s is another example.", + "MetricExpr": "100 * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdo= wn\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\= \-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / = ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdow= n\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdow= n\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) )", + "MetricGroup": "TmaL1", + "MetricName": "tma_bad_speculation_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Branch Misprediction. These slots are either wasted = by uops fetched from an incorrectly speculated program path; or stalls when= the out-of-order part of the machine needs to recover its state from a spe= culative path.", + "MetricExpr": "( 100 * ( topdown\\-br\\-mispredict / ( topdown\\-f= e\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-boun= d ) ) ) + ( 0 * slots )", + "MetricGroup": "BadSpec;BrMispredicts;TmaL2;m_tma_bad_speculation_= percent", + "MetricName": "tma_branch_mispredicts_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Machine Clears. These slots are either wasted by uop= s fetched prior to the clear; or stalls the out-of-order portion of the mac= hine needs to recover its state after the clear. For example; this can happ= en due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modify= ing-Code (SMC) nukes.", + "MetricExpr": "100 * ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-boun= d / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + to= pdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be= \\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiri= ng + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bou= nd + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) )= , 0 ) ) - ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\= -bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) )", + "MetricGroup": "BadSpec;MachineClears;TmaL2;m_tma_bad_speculation_= percent", + "MetricName": "tma_machine_clears_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend. Backend is the portion of the processor cor= e where the out-of-order scheduler dispatches ready uops into their respect= ive execution units; and once completed these uops get retired according to= program order. For example; stalls due to data-cache misses or stalls due = to the divider unit being overloaded are both categorized under Backend Bou= nd. Backend Bound is further divided into two main categories: Memory Bound= and Core Bound.", + "MetricExpr": "( 100 * ( topdown\\-be\\-bound / ( topdown\\-fe\\-b= ound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) )= ) + ( 0 * slots )", + "MetricGroup": "TmaL1", + "MetricName": "tma_backend_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = Memory subsystem within the Backend was a bottleneck. Memory Bound estimat= es fraction of slots where pipeline is likely stalled due to demand load or= store instructions. This accounts mainly for (1) non-completed in-flight m= emory demand loads which coincides with execution units starvation; in addi= tion to (2) cases where stores could impose backpressure on the pipeline wh= en many of them get buffered at the same time (less common out of the two).= ", + "MetricExpr": "( 100 * ( topdown\\-mem\\-bound / ( topdown\\-fe\\-= bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) = ) ) + ( 0 * slots )", + "MetricGroup": "Backend;TmaL2;m_tma_backend_bound_percent", + "MetricName": "tma_memory_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was s= talled without loads missing the L1 data cache. The L1 data cache typicall= y has the shortest latency. However; in certain cases like loads blocked o= n older stores; a load might suffer due to high latency even though it is b= eing satisfied by the L1. Another example is loads who miss in the TLB. The= se cases are characterized by execution unit stalls; while some non-complet= ed demand load lives in the machine without having that demand load missing= the L1 cache.", + "MetricExpr": "100 * ( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY= _ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) )", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TmaL3;m_tma_memor= y_bound_percent", + "MetricName": "tma_l1_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was s= talled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 m= isses/L2 hits) can improve the latency and increase performance.", + "MetricExpr": "100 * ( ( MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_= ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TmaL3;m_tma_memor= y_bound_percent", + "MetricName": "tma_l2_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was s= talled due to loads accesses to L3 cache or contended with a sibling Core. = Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and= increase performance.", + "MetricExpr": "100 * ( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_A= CTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TmaL3;m_tma_memor= y_bound_percent", + "MetricName": "tma_l3_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was s= talled on accesses to external memory (DRAM) by loads. Better caching can i= mprove the latency and increase performance.", + "MetricExpr": "100 * ( min( ( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS /= ( CPU_CLK_UNHALTED.THREAD ) ) - ( min( ( ( ( ( 1 - ( ( ( 19 * ( MEM_LOAD_L= 3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_R= ETIRED.L1_MISS ) ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1= + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) + ( MEM_L= OAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LO= AD_RETIRED.L1_MISS ) ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 += ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) / ( ( 1= 9 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HI= T / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.= LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS )= ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.F= B_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REM= OTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) )= ) ) ) ) + ( 25 * ( ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED= .FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + 33 * ( ( MEM_LOAD_L3_MISS_= RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L= 1_MISS ) ) ) ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_U= NHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_P= MM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) ,= ( 1 ) ) ) ) ) , ( 1 ) ) )", + "MetricGroup": "MemoryBound;TmaL3mem;TmaL3;m_tma_memory_bound_perc= ent", + "MetricName": "tma_dram_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric roughly estimates (based on idle = latencies) how often the CPU was stalled on accesses to external 3D-Xpoint = (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memo= ry Module. ", + "MetricExpr": "100 * ( min( ( ( ( ( 1 - ( ( ( 19 * ( MEM_LOAD_L3_M= ISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETI= RED.L1_MISS ) ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + = ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) + ( MEM_LOAD= _L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_= RETIRED.L1_MISS ) ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( = MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) / ( ( 19 *= ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT /= ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOC= AL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) = ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_H= IT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE= _HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) = ) ) ) + ( 25 * ( ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB= _HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + 33 * ( ( MEM_LOAD_L3_MISS_RET= IRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_M= ISS ) ) ) ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHA= LTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM = + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( = 1 ) ) )", + "MetricGroup": "MemoryBound;Server;TmaL3mem;TmaL3;m_tma_memory_bou= nd_percent", + "MetricName": "tma_pmm_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates how often CPU was stall= ed due to RFO store memory accesses; RFO store issue a read-for-ownership = request before the write. Even though store accesses do not typically stall= out-of-order CPUs; there are few cases where stores can lead to actual sta= lls. This metric will be flagged should RFO stores be a bottleneck.", + "MetricExpr": "100 * ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UN= HALTED.THREAD ) )", + "MetricGroup": "MemoryBound;TmaL3mem;TmaL3;m_tma_memory_bound_perc= ent", + "MetricName": "tma_store_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e Core non-memory issues were of a bottleneck. Shortage in hardware comput= e resources; or dependencies in software's instructions are both categorize= d under Core Bound. Hence it may indicate the machine ran out of an out-of-= order resource; certain execution units are overloaded or dependencies in p= rogram's data- or instruction-flow are limiting the performance (e.g. FP-ch= ained long-latency arithmetic operations).", + "MetricExpr": "( 100 * ( max( 0 , ( topdown\\-be\\-bound / ( topdo= wn\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\= \-bound ) ) - ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-= bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) ) + ( 0 * sl= ots )", + "MetricGroup": "Backend;TmaL2;Compute;m_tma_backend_bound_percent", + "MetricName": "tma_core_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles whe= re the Divider unit was active. Divide and square root instructions are per= formed by the Divider unit and can take considerably longer latency than in= teger or Floating Point addition; subtraction; or multiplication.", + "MetricExpr": "100 * ( ARITH.DIVIDER_ACTIVE / ( CPU_CLK_UNHALTED.T= HREAD ) )", + "MetricGroup": "TmaL3;m_tma_core_bound_percent", + "MetricName": "tma_divider_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles the = CPU performance was potentially limited due to Core computation issues (non= divider-related). Two distinct categories can be attributed into this met= ric: (1) heavy data-dependency among contiguous instructions would manifest= in this metric - such cases are often referred to as low Instruction Level= Parallelism (ILP). (2) Contention on some hardware execution unit other th= an Divider. For example; when there are too many multiply operations.", + "MetricExpr": "( 100 * ( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( EXE_= ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + top= down\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE= _ACTIVITY.2_PORTS_UTIL\\,umask\\=3D0xc@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) i= f ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOU= ND_ON_LOADS ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / (= topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown= \\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=3D0xc@ ) / ( CP= U_CLK_UNHALTED.THREAD ) ) ) + ( 0 * slots )", + "MetricGroup": "PortsUtil;TmaL3;m_tma_core_bound_percent", + "MetricName": "tma_ports_utilization_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired. Ideally= ; all pipeline slots would be attributed to the Retiring category. Retirin= g of 100% would indicate the maximum Pipeline_Width throughput was achieved= . Maximizing Retiring typically increases the Instructions-per-cycle (see = IPC metric). Note that a high Retiring value does not necessary mean there = is no room for more performance. For example; Heavy-operations or Microcod= e Assists are categorized under Retiring. They often indicate suboptimal pe= rformance and can often be optimized or avoided. ", + "MetricExpr": "( 100 * ( topdown\\-retiring / ( topdown\\-fe\\-bou= nd + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) )= + ( 0 * slots )", + "MetricGroup": "TmaL1", + "MetricName": "tma_retiring_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring light-weight operations -- instructions that require= no more than one uop (micro-operation). This correlates with total number = of instructions used by the program. A uops-per-instruction (see UPI metric= ) ratio of 1 or less should be expected for decently optimized software run= ning on Intel Core/Xeon products. While this often indicates efficient X86 = instructions were executed; high value does not necessarily mean better per= formance cannot be achieved.", + "MetricExpr": "( 100 * ( max( 0 , ( topdown\\-retiring / ( topdown= \\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-= bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-ba= d\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) ) + ( 0 * slot= s )", + "MetricGroup": "Retire;TmaL2;m_tma_retiring_percent", + "MetricName": "tma_light_operations_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents overall arithmetic flo= ating-point (FP) operations fraction the CPU has executed (retired). Note t= his metric's value may exceed its parent due to use of \"Uops\" CountDomain= and FMA double-counting.", + "MetricExpr": "100 * ( ( ( topdown\\-retiring / ( topdown\\-fe\\-b= ound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) )= * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD ) + ( ( FP_ARITH_INST_RETIRED.S= CALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + FP_ARITH_INST_RETIRED2= .SCALAR ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad= \\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + (= min( ( ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.= 128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_IN= ST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + = FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.VECTOR ) = / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + = topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1 ) ) ) += ( cpu@AMX_OPS_RETIRED.BF16\\,cmask\\=3D0x1@ / ( ( topdown\\-retiring / ( t= opdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\= -be\\-bound ) ) * ( slots ) ) ) )", + "MetricGroup": "HPC;TmaL3;m_tma_light_operations_percent", + "MetricName": "tma_fp_arith_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents overall Integer (Int) = select operations fraction the CPU has executed (retired). Vector/Matrix In= t operations and shuffles are counted. Note this metric's value may exceed = its parent due to use of \"Uops\" CountDomain.", + "MetricExpr": "100 * ( ( ( INT_VEC_RETIRED.ADD_128 + INT_VEC_RETIR= ED.VNNI_128 ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\= -bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )= + ( ( INT_VEC_RETIRED.ADD_256 + INT_VEC_RETIRED.MUL_256 + INT_VEC_RETIRED.= VNNI_256 ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-ba= d\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + = ( INT_VEC_RETIRED.SHUFFLES / ( ( topdown\\-retiring / ( topdown\\-fe\\-boun= d + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * = ( slots ) ) ) )", + "MetricGroup": "Pipeline;TmaL3;m_tma_light_operations_percent", + "MetricName": "tma_int_operations_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring memory operations -- uops for memory load or store a= ccesses.", + "MetricExpr": "100 * ( ( max( 0 , ( topdown\\-retiring / ( topdown= \\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-= bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-ba= d\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * MEM_UOP_RETI= RED.ANY / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\= -spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", + "MetricGroup": "Pipeline;TmaL3;m_tma_light_operations_percent", + "MetricName": "tma_memory_operations_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring fused instructions -- where one uop can represent mu= ltiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC= are commonly used examples.", + "MetricExpr": "100 * ( ( max( 0 , ( topdown\\-retiring / ( topdown= \\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-= bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-ba= d\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * INST_RETIRED= .MACRO_FUSED / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-= bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", + "MetricGroup": "Pipeline;TmaL3;m_tma_light_operations_percent", + "MetricName": "tma_fused_instructions_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring branch instructions that were not fused. Non-conditi= onal branches like direct JMP or CALL would count here. Can be used to exam= ine fusible conditional jumps that were not fused.", + "MetricExpr": "100 * ( ( max( 0 , ( topdown\\-retiring / ( topdown= \\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-= bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-ba= d\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( BR_INST_RE= TIRED.ALL_BRANCHES - INST_RETIRED.MACRO_FUSED ) / ( ( topdown\\-retiring / = ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdow= n\\-be\\-bound ) ) * ( slots ) ) )", + "MetricGroup": "Pipeline;TmaL3;m_tma_light_operations_percent", + "MetricName": "tma_non_fused_branches_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring NOP (no op) instructions. Compilers often use NOPs f= or certain address alignments - e.g. start address of a function or loop bo= dy.", + "MetricExpr": "100 * ( ( max( 0 , ( topdown\\-retiring / ( topdown= \\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-= bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-ba= d\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * INST_RETIRED= .NOP / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-sp= ec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", + "MetricGroup": "Pipeline;TmaL3;m_tma_light_operations_percent", + "MetricName": "tma_nop_instructions_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents the remaining light uo= ps fraction the CPU has executed - remaining means not covered by other sib= ling nodes. May undercount due to FMA double counting", + "MetricExpr": "100 * ( max( 0 , ( max( 0 , ( topdown\\-retiring / = ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdow= n\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + top= down\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) - ( (= ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + t= opdown\\-retiring + topdown\\-be\\-bound ) ) * UOPS_EXECUTED.X87 / UOPS_EXE= CUTED.THREAD ) + ( ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RE= TIRED.SCALAR_DOUBLE + FP_ARITH_INST_RETIRED2.SCALAR ) / ( ( topdown\\-retir= ing / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + = topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( min( ( ( FP_ARITH_INST_RETIRED= .128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_I= NST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE += FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACK= ED_SINGLE + FP_ARITH_INST_RETIRED2.VECTOR ) / ( ( topdown\\-retiring / ( to= pdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-= be\\-bound ) ) * ( slots ) ) ) , ( 1 ) ) ) + ( cpu@AMX_OPS_RETIRED.BF16\\,c= mask\\=3D0x1@ / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\= -bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )= ) + ( ( ( INT_VEC_RETIRED.ADD_128 + INT_VEC_RETIRED.VNNI_128 ) / ( ( topdo= wn\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-r= etiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( ( INT_VEC_RETIRED.AD= D_256 + INT_VEC_RETIRED.MUL_256 + INT_VEC_RETIRED.VNNI_256 ) / ( ( topdown\= \-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-reti= ring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( INT_VEC_RETIRED.SHUFFLE= S / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec = + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) ) + ( ( max= ( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec = + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops /= ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdo= wn\\-be\\-bound ) ) ) ) * MEM_UOP_RETIRED.ANY / ( ( topdown\\-retiring / ( = topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\= \-be\\-bound ) ) * ( slots ) ) ) + ( ( max( 0 , ( topdown\\-retiring / ( to= pdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-= be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown= \\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * INST_RE= TIRED.MACRO_FUSED / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdo= wn\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots )= ) ) + ( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown= \\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\= -heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-re= tiring + topdown\\-be\\-bound ) ) ) ) * ( BR_INST_RETIRED.ALL_BRANCHES - IN= ST_RETIRED.MACRO_FUSED ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound = + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( = slots ) ) ) + ( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + = topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( to= pdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdo= wn\\-retiring + topdown\\-be\\-bound ) ) ) ) * INST_RETIRED.NOP / ( ( topdo= wn\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-r= etiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) ) ) )", + "MetricGroup": "Pipeline;TmaL3;m_tma_light_operations_percent", + "MetricName": "tma_other_light_ops_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring heavy-weight operations -- instructions that require= two or more uops or microcoded sequences. This highly-correlates with the = uop length of these instructions/sequences.", + "MetricExpr": "( 100 * ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-= bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) = ) ) + ( 0 * slots )", + "MetricGroup": "Retire;TmaL2;m_tma_retiring_percent", + "MetricName": "tma_heavy_operations_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring instructions that that are decoder into two or up to= ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of= uops in such instructions.", + "MetricExpr": "100 * ( ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-= bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) = ) - ( UOPS_RETIRED.MS / ( slots ) ) )", + "MetricGroup": "TmaL3;m_tma_heavy_operations_percent", + "MetricName": "tma_few_uops_instructions_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS= is used for CISC instructions not supported by the default decoders (like = repeat move strings; or CPUID); or by microcode assists used to address som= e operation modes (like in Floating Point assists). These cases can often b= e avoided.", + "MetricExpr": "100 * ( UOPS_RETIRED.MS / ( slots ) )", + "MetricGroup": "MicroSeq;TmaL3;m_tma_heavy_operations_percent", + "MetricName": "tma_microcode_sequencer_percent", + "ScaleUnit": "1%" } ] diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-other.jso= n b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-other.json index 9b8664c50213..495ceee21071 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-other.json @@ -20,15 +20,6 @@ "UMaskExt": "0x00000000", "Unit": "UPI LL" }, - { - "BriefDescription": "Clockticks in the UBOX using a dedicated 48-b= it Fixed Counter", - "Counter": "FIXED", - "CounterType": "FIXED", - "EventCode": "0xff", - "EventName": "UNC_U_CLOCKTICKS", - "PerPkg": "1", - "Unit": "UBOX" - }, { "BriefDescription": "IRP Clockticks", "Counter": "0,1", --=20 2.37.1.359.gd136c6c3e2-goog From nobody Wed Apr 15 05:45:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5AD4C04A68 for ; Wed, 27 Jul 2022 22:12:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236731AbiG0WMt (ORCPT ); Wed, 27 Jul 2022 18:12:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54828 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236269AbiG0WLG (ORCPT ); Wed, 27 Jul 2022 18:11:06 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4EF5D606A2 for ; Wed, 27 Jul 2022 15:09:46 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id r64-20020a254443000000b006707b7c2baeso220990yba.16 for ; Wed, 27 Jul 2022 15:09:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=5e6HWfs1SkPqYIQUoHpxkfHvDU0TH9v/J1FBs30MsCg=; b=dmCKrRvLxDgfDOA7gJDXPRREKyRR+6V8Cpy3dG5OdYlMWRVWzh/iFO6AfDmGLvOW6o IhDhhYw1LqXbP22Cf0O1t2Do/clsrR+Iw1f0RyYKXSVwVEHN+fqvNv03wsjCpoq68RUg 1XoA5MYMoLdfrw9ur7HY1Y17wIRRozzW4h44owbMJpfTcB0eK3ZUxFPNt5WDhyUCVL68 f521ap9Y0ut3CyDcovudXoH38MTSeqaHtL8eoQOk3X5zSqVnwfXLg3Clx/vznCQo59aU kBzCJza6AuRIYPFEi1uso20e57KOsjNnjLU8e4Ocr9R15MVXEbim32t7qWFlxx/zQ/Co VCdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=5e6HWfs1SkPqYIQUoHpxkfHvDU0TH9v/J1FBs30MsCg=; b=3zs00lavPLYc9Smgqf0Cb3OZEHyAtNxX4xe/fcvzrv8+nkuqjCRMkmVALFs11iE9XD 3kPMrX8OfN81urr5yvUocj/krfcsDT8YhwaR5sV16yKLUOKeuF+unk03jhlhqOHGFhvJ XVWGNUBBScfVUpsDSbiafYC1fd9/AHLCmuTzXRuOsk14Le12vo3Kpe7m/1EMgEUEunPt FoVbsXkhcPbTLIkb9yElzRhcI+TS+YrTdYauhwkugNaAd5xYe58PVDVW1hzWMWa1Yx8r q4bPJSGe11wLITkorMLHcfx0nrHzkUA0Q53zl0kGJT/RCGC32Gkm3UgJRVWDX1aFhFch 7VpQ== X-Gm-Message-State: AJIora8UWVisMjQTj/t+TG69znZK7XGr//ZMmeB/LJIoR6dPp3s5ffEY H7RCyUjthU4HnaVM8g5Kz1qfR6AUbWFV X-Google-Smtp-Source: AGRyM1scfzyD/SGvx7bEmSdZVscFfZVfwFGGgNxe3iHhQd2TG/zjQpKe48mhRc1wxSgqYTeL6aurRyGAr1XX X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:882a:af57:8cb6:6f9e]) (user=irogers job=sendgmr) by 2002:a81:6e02:0:b0:321:cce0:b268 with SMTP id j2-20020a816e02000000b00321cce0b268mr1964112ywc.233.1658959785901; Wed, 27 Jul 2022 15:09:45 -0700 (PDT) Date: Wed, 27 Jul 2022 15:08:25 -0700 In-Reply-To: <20220727220832.2865794-1-irogers@google.com> Message-Id: <20220727220832.2865794-24-irogers@google.com> Mime-Version: 1.0 References: <20220727220832.2865794-1-irogers@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH v3 23/30] perf vendor events: Update Intel silvermont From: Ian Rogers To: perry.taylor@intel.com, caleb.biggers@intel.com, kshipra.bopardikar@intel.com, Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Sedat Dilek Cc: Stephane Eranian , Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update to v14, the metrics are based on TMA 4.4 full. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/downloa= d_and_gen.py to download and generate the latest events and metrics. Manually copy the silvermont files into perf and update mapfile.csv. Other than aligning whitespace this change just folds the mapfile.csv entries for silvertmont onto one line. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/arch/x86/mapfile.csv | 4 +--- tools/perf/pmu-events/arch/x86/silvermont/cache.json | 2 +- tools/perf/pmu-events/arch/x86/silvermont/floating-point.json | 2 +- tools/perf/pmu-events/arch/x86/silvermont/frontend.json | 2 +- tools/perf/pmu-events/arch/x86/silvermont/memory.json | 2 +- tools/perf/pmu-events/arch/x86/silvermont/other.json | 2 +- tools/perf/pmu-events/arch/x86/silvermont/pipeline.json | 2 +- tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json | 2 +- 8 files changed, 8 insertions(+), 10 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 317ae526e376..2dc86cf445f9 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -21,11 +21,9 @@ GenuineIntel-6-1[AEF],v3,nehalemep,core GenuineIntel-6-2E,v3,nehalemex,core GenuineIntel-6-2A,v17,sandybridge,core GenuineIntel-6-8F,v1.04,sapphirerapids,core +GenuineIntel-6-(37|4C|4D),v14,silvermont,core GenuineIntel-6-[4589]E,v24,skylake,core GenuineIntel-6-A[56],v24,skylake,core -GenuineIntel-6-37,v13,silvermont,core -GenuineIntel-6-4D,v13,silvermont,core -GenuineIntel-6-4C,v13,silvermont,core GenuineIntel-6-2C,v2,westmereep-dp,core GenuineIntel-6-25,v2,westmereep-sp,core GenuineIntel-6-2F,v2,westmereex,core diff --git a/tools/perf/pmu-events/arch/x86/silvermont/cache.json b/tools/p= erf/pmu-events/arch/x86/silvermont/cache.json index e16e1d910e4a..7959504dff29 100644 --- a/tools/perf/pmu-events/arch/x86/silvermont/cache.json +++ b/tools/perf/pmu-events/arch/x86/silvermont/cache.json @@ -807,4 +807,4 @@ "SampleAfterValue": "200003", "UMask": "0x4" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/silvermont/floating-point.json = b/tools/perf/pmu-events/arch/x86/silvermont/floating-point.json index 1d75b35694ac..aa4faf110512 100644 --- a/tools/perf/pmu-events/arch/x86/silvermont/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/silvermont/floating-point.json @@ -8,4 +8,4 @@ "SampleAfterValue": "200003", "UMask": "0x4" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/silvermont/frontend.json b/tool= s/perf/pmu-events/arch/x86/silvermont/frontend.json index a4c98e43f677..43e5e48f7212 100644 --- a/tools/perf/pmu-events/arch/x86/silvermont/frontend.json +++ b/tools/perf/pmu-events/arch/x86/silvermont/frontend.json @@ -71,4 +71,4 @@ "SampleAfterValue": "200003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/silvermont/memory.json b/tools/= perf/pmu-events/arch/x86/silvermont/memory.json index 5e21fc3fd078..0f5fba43da4c 100644 --- a/tools/perf/pmu-events/arch/x86/silvermont/memory.json +++ b/tools/perf/pmu-events/arch/x86/silvermont/memory.json @@ -8,4 +8,4 @@ "SampleAfterValue": "200003", "UMask": "0x2" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/silvermont/other.json b/tools/p= erf/pmu-events/arch/x86/silvermont/other.json index 16d16a1ce6de..4db59d84c144 100644 --- a/tools/perf/pmu-events/arch/x86/silvermont/other.json +++ b/tools/perf/pmu-events/arch/x86/silvermont/other.json @@ -17,4 +17,4 @@ "SampleAfterValue": "200003", "UMask": "0x2" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/silvermont/pipeline.json b/tool= s/perf/pmu-events/arch/x86/silvermont/pipeline.json index 03a4c7f26698..e42a37eabc17 100644 --- a/tools/perf/pmu-events/arch/x86/silvermont/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/silvermont/pipeline.json @@ -313,4 +313,4 @@ "SampleAfterValue": "2000003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json = b/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json index f4b8a1ef48f6..b50cee3a5e4c 100644 --- a/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json @@ -66,4 +66,4 @@ "SampleAfterValue": "100003", "UMask": "0x3" } -] \ No newline at end of file +] --=20 2.37.1.359.gd136c6c3e2-goog From nobody Wed Apr 15 05:45:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9264C04A68 for ; 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Wed, 27 Jul 2022 15:09:48 -0700 (PDT) Date: Wed, 27 Jul 2022 15:08:26 -0700 In-Reply-To: <20220727220832.2865794-1-irogers@google.com> Message-Id: <20220727220832.2865794-25-irogers@google.com> Mime-Version: 1.0 References: <20220727220832.2865794-1-irogers@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH v3 24/30] perf vendor events: Update Intel skylake From: Ian Rogers To: perry.taylor@intel.com, caleb.biggers@intel.com, kshipra.bopardikar@intel.com, Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Sedat Dilek Cc: Stephane Eranian , Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Update to v53, the metrics are based on TMA 4.4 full. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/downloa= d_and_gen.py to download and generate the latest events and metrics. Manually copy the skylake files into perf and update mapfile.csv. Tested on a non-skylake with 'perf test': 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok Signed-off-by: Ian Rogers --- tools/perf/pmu-events/arch/x86/mapfile.csv | 3 +- .../arch/x86/skylake/floating-point.json | 2 +- .../pmu-events/arch/x86/skylake/frontend.json | 2 +- .../pmu-events/arch/x86/skylake/other.json | 2 +- .../arch/x86/skylake/skl-metrics.json | 178 ++++++++---- .../arch/x86/skylake/uncore-cache.json | 142 ++++++++++ .../arch/x86/skylake/uncore-other.json | 79 ++++++ .../pmu-events/arch/x86/skylake/uncore.json | 254 ------------------ .../arch/x86/skylake/virtual-memory.json | 2 +- 9 files changed, 345 insertions(+), 319 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/skylake/uncore-cache.json create mode 100644 tools/perf/pmu-events/arch/x86/skylake/uncore-other.json delete mode 100644 tools/perf/pmu-events/arch/x86/skylake/uncore.json diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 2dc86cf445f9..78552ef68482 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -22,8 +22,7 @@ GenuineIntel-6-2E,v3,nehalemex,core GenuineIntel-6-2A,v17,sandybridge,core GenuineIntel-6-8F,v1.04,sapphirerapids,core GenuineIntel-6-(37|4C|4D),v14,silvermont,core -GenuineIntel-6-[4589]E,v24,skylake,core -GenuineIntel-6-A[56],v24,skylake,core +GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v53,skylake,core GenuineIntel-6-2C,v2,westmereep-dp,core GenuineIntel-6-25,v2,westmereep-sp,core GenuineIntel-6-2F,v2,westmereex,core diff --git a/tools/perf/pmu-events/arch/x86/skylake/floating-point.json b/t= ools/perf/pmu-events/arch/x86/skylake/floating-point.json index 73cfb2a39722..d6cee5ae4402 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/skylake/floating-point.json @@ -70,4 +70,4 @@ "SampleAfterValue": "100003", "UMask": "0x1e" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/skylake/frontend.json b/tools/p= erf/pmu-events/arch/x86/skylake/frontend.json index ecce4273ae52..8633ee406813 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/frontend.json +++ b/tools/perf/pmu-events/arch/x86/skylake/frontend.json @@ -527,4 +527,4 @@ "SampleAfterValue": "2000003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/skylake/other.json b/tools/perf= /pmu-events/arch/x86/skylake/other.json index 4f4839024915..8f4bc8892c47 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/other.json +++ b/tools/perf/pmu-events/arch/x86/skylake/other.json @@ -17,4 +17,4 @@ "SampleAfterValue": "2000003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json b/tool= s/perf/pmu-events/arch/x86/skylake/skl-metrics.json index defbca9a6038..73fa72d3dcb1 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json @@ -95,13 +95,13 @@ { "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIV= ITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORT= S_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_= ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NO= T_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 *= INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) * ( ( (max( (= CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK= _UNHALTED.THREAD , 0 )) / ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.= BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UT= IL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTI= VITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DE= LIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT= _MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (min( 9 * c= pu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=3D1@ + DTLB_LOAD_MISSES.WALK_ACTIVE = , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 )= ) / CPU_CLK_UNHALTED.THREAD) / (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYC= LE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) + ( (EXE_A= CTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.ST= ALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTA= L + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_= UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STOR= ES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) -= ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED= .THREAD))) ) * ( (( 9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=3D1@ + DTL= B_STORE_MISSES.WALK_ACTIVE ) / CPU_CLK_UNHALTED.THREAD) / #(EXE_ACTIVITY.BO= UND_ON_STORES / CPU_CLK_UNHALTED.THREAD) ) ) ", - "MetricGroup": "Mem;MemoryTLB", + "MetricGroup": "Mem;MemoryTLB;Offcore", "MetricName": "Memory_Data_TLBs" }, { "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIV= ITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORT= S_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 = ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) = ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (I= DQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 += CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( U= OPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) )))) * ( ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - = CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / ((( CYC= LE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVI= TY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS /= (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD= _ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EX= E_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( (= CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE /= CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOV= ERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU= _CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (m= in( 9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=3D1@ + DTLB_LOAD_MISSES.WAL= K_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_M= ISS , 0 ) ) / CPU_CLK_UNHALTED.THREAD) / (max( ( CYCLE_ACTIVITY.STALLS_MEM_= ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) += ( (EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_AC= TIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.ST= ALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 *= ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTI= VE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACT= IVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_C= YCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_= UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (( 9 * = cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=3D1@ + DTLB_STORE_MISSES.WALK_ACTI= VE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREA= D_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / #(EXE_ACTIVITY.BOUND_ON_STORES = / CPU_CLK_UNHALTED.THREAD) ) ) ", - "MetricGroup": "Mem;MemoryTLB;_SMT", + "MetricGroup": "Mem;MemoryTLB;Offcore_SMT", "MetricName": "Memory_Data_TLBs_SMT" }, { @@ -214,42 +214,36 @@ "MetricName": "FLOPc_SMT" }, { - "BriefDescription": "Actual per-core usage of the Floating Point e= xecution units (regardless of the vector width)", + "BriefDescription": "Actual per-core usage of the Floating Point n= on-X87 execution units (regardless of precision or vector-width)", "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_I= NST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP= _ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_= DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * CPU_CLK_UNHALT= ED.THREAD )", "MetricGroup": "Cor;Flops;HPC", "MetricName": "FP_Arith_Utilization", - "PublicDescription": "Actual per-core usage of the Floating Point = execution units (regardless of the vector width). Values > 1 are possible d= ue to Fused-Multiply Add (FMA) counting." + "PublicDescription": "Actual per-core usage of the Floating Point = non-X87 execution units (regardless of precision or vector-width). Values >= 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; = [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less commo= n)." }, { - "BriefDescription": "Actual per-core usage of the Floating Point e= xecution units (regardless of the vector width). SMT version; use when SMT = is enabled and measuring per logical CPU.", + "BriefDescription": "Actual per-core usage of the Floating Point n= on-X87 execution units (regardless of precision or vector-width). SMT versi= on; use when SMT is enabled and measuring per logical CPU.", "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_I= NST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP= _ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_= DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * ( ( CPU_CLK_UN= HALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UN= HALTED.REF_XCLK ) ) )", "MetricGroup": "Cor;Flops;HPC_SMT", "MetricName": "FP_Arith_Utilization_SMT", - "PublicDescription": "Actual per-core usage of the Floating Point = execution units (regardless of the vector width). Values > 1 are possible d= ue to Fused-Multiply Add (FMA) counting. SMT version; use when SMT is enabl= ed and measuring per logical CPU." + "PublicDescription": "Actual per-core usage of the Floating Point = non-X87 execution units (regardless of precision or vector-width). Values >= 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; = [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less commo= n). SMT version; use when SMT is enabled and measuring per logical CPU." }, { - "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is at least 1 uop executed)", + "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per-core", "MetricExpr": "UOPS_EXECUTED.THREAD / (( UOPS_EXECUTED.CORE_CYCLES= _GE_1 / 2 ) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, { - "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIR= ED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.TH= READ))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_C= LK_UNHALTED.THREAD)) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.A= LL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU= _CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CO= RE / (4 * CPU_CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_= MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BrMispredicts", - "MetricName": "Branch_Misprediction_Cost" - }, - { - "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIR= ED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU= _CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU= _CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_D= ELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED= .ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ((BR_MISP_RETIRED.AL= L_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT= _MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_= DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 )= * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )= )) ) * (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_= THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCH= ES", - "MetricGroup": "Bad;BrMispredicts_SMT", - "MetricName": "Branch_Misprediction_Cost_SMT" + "BriefDescription": "Probability of Core Bound bottleneck hidden b= y SMT-profiling artifacts", + "MetricExpr": "( 1 - ((1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU= _CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES )= / (4 * CPU_CLK_UNHALTED.THREAD)) - ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE= _ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.= 1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) = * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_U= OPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY= + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)))) / ((EX= E_ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.R= ETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL)) = / CPU_CLK_UNHALTED.THREAD if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STAL= LS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else (EXE_ACTIVITY.1_PORTS_UTI= L + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIV= ITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD) if ((1 - (IDQ_UOPS_NOT_DELIVER= ED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC= .RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)) - ((( CYCLE_ACTIVITY.ST= ALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTA= L + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_= UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STOR= ES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) -= ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED= .THREAD)))) < ((EXE_ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACTIVITY.1_PORTS_UTIL= + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVI= TY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD if ( ARITH.DIVIDER_ACTIVE < ( C= YCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else (EXE_AC= TIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.TH= READ)) * EXE_ACTIVITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD) else 1 ) if = 0 > 0.5 else 0", + "MetricGroup": "Cor;SMT", + "MetricName": "Core_Bound_Likely" }, { - "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear)", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "IpMispredict" + "BriefDescription": "Probability of Core Bound bottleneck hidden b= y SMT-profiling artifacts", + "MetricExpr": "( 1 - ((1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( (= CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE /= CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOV= ERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU= _CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ((( CYC= LE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVI= TY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS /= (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD= _ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EX= E_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( (= CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE /= CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOV= ERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU= _CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))))) / ((EXE= _ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RE= TIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTE= D.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORT= S_UTIL)) / CPU_CLK_UNHALTED.THREAD if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTI= VITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else (EXE_ACTIVITY.1_= PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD = / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCL= K ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD) if ((1 - (I= DQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 += CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( U= OPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) ))) - ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIV= ITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORT= S_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 = ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) = ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (I= DQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 += CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( U= OPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) ))))) < ((EXE_ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACT= IVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED= .THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED= .REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD if = ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STA= LLS_MEM_ANY ) ) else (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOT= S / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THR= EAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) /= CPU_CLK_UNHALTED.THREAD) else 1 ) if (1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTI= VE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 )) > 0.5 else 0", + "MetricGroup": "Cor;SMT_SMT", + "MetricName": "Core_Bound_Likely_SMT" }, { "BriefDescription": "Core actual clocks when any Logical Processor= is active on the Physical Core", @@ -334,12 +328,30 @@ "MetricName": "IpArith_AVX256", "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit = instruction (lower number means higher occurrence rate). May undercount due= to FMA double counting." }, + { + "BriefDescription": "Instructions per Software prefetch instructio= n (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrenc= e rate)", + "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umas= k\\=3D0xF@", + "MetricGroup": "Prefetches", + "MetricName": "IpSWPF" + }, { "BriefDescription": "Total number of retired Instructions, Sample = with: INST_RETIRED.PREC_DIST", "MetricExpr": "INST_RETIRED.ANY", "MetricGroup": "Summary;TmaL1", "MetricName": "Instructions" }, + { + "BriefDescription": "Average number of Uops retired in cycles wher= e at least one uop has retired.", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE= _SLOTS\\,cmask\\=3D1@", + "MetricGroup": "Pipeline;Ret", + "MetricName": "Retire" + }, + { + "BriefDescription": "", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,c= mask\\=3D1@", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", + "MetricName": "Execute" + }, { "BriefDescription": "Average number of Uops issued by front-end wh= en it issued something", "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=3D1= @", @@ -353,23 +365,47 @@ "MetricName": "DSB_Coverage" }, { - "BriefDescription": "Total penalty related to DSB (uop cache) miss= es - subset/see of/the Instruction_Fetch_BW Bottleneck.", - "MetricExpr": "(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.COR= E / (4 * CPU_CLK_UNHALTED.THREAD)) * (DSB2MITE_SWITCHES.PENALTY_CYCLES / CP= U_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.C= ORE / (4 * CPU_CLK_UNHALTED.THREAD)) + ((IDQ_UOPS_NOT_DELIVERED.CORE / (4 *= CPU_CLK_UNHALTED.THREAD)) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELI= V.CORE / (4 * CPU_CLK_UNHALTED.THREAD))) * (( IDQ.ALL_MITE_CYCLES_ANY_UOPS = - IDQ.ALL_MITE_CYCLES_4_UOPS ) / CPU_CLK_UNHALTED.THREAD / 2) / #((IDQ_UOPS= _NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - (4 * IDQ_UOPS_NOT_DE= LIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)))", + "BriefDescription": "Average number of cycles of a switch from the= DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details= .", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / DSB2MITE_SWITCHE= S.COUNT", + "MetricGroup": "DSBmiss", + "MetricName": "DSB_Switch_Cost" + }, + { + "BriefDescription": "Total penalty related to DSB (uop cache) miss= es - subset of the Instruction_Fetch_BW Bottleneck.", + "MetricExpr": "100 * ( (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_D= ELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * (DSB2MITE_SWITCHES.PENALTY_CYC= LES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS= _DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) + ((IDQ_UOPS_NOT_DELIVERED.COR= E / (4 * CPU_CLK_UNHALTED.THREAD)) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_U= OPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD))) * (( IDQ.ALL_MITE_CYCLES_A= NY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS ) / CPU_CLK_UNHALTED.THREAD / 2) / #((= IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - (4 * IDQ_UOP= S_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD))) = )", "MetricGroup": "DSBmiss;Fed", - "MetricName": "DSB_Misses_Cost" + "MetricName": "DSB_Misses" }, { - "BriefDescription": "Total penalty related to DSB (uop cache) miss= es - subset/see of/the Instruction_Fetch_BW Bottleneck.", - "MetricExpr": "(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.COR= E / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THR= EAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (DSB2MITE_SWITCHES.PENALTY_C= YCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UO= PS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHA= LTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + ((IDQ_UOPS_NOT_D= ELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHA= LTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ_UOPS_NO= T_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2= ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK )= )))) * (( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS ) / ( = ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE = / CPU_CLK_UNHALTED.REF_XCLK ) ) / 2) / #((IDQ_UOPS_NOT_DELIVERED.CORE / (4 = * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACT= IVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_= 0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_= UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))))", + "BriefDescription": "Total penalty related to DSB (uop cache) miss= es - subset of the Instruction_Fetch_BW Bottleneck.", + "MetricExpr": "100 * ( (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_D= ELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED= .ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (DSB2MITE_SWITCHES.P= ENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYC= LES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_= CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + ((IDQ_UO= PS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_= CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ= _UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.TH= READ / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.RE= F_XCLK ) )))) * (( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOP= S ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD= _ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) / 2) / #((IDQ_UOPS_NOT_DELIVERED.CO= RE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_TH= READ_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ_UOPS_NOT_DELIVERED= .CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + = CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) )", "MetricGroup": "DSBmiss;Fed_SMT", - "MetricName": "DSB_Misses_Cost_SMT" + "MetricName": "DSB_Misses_SMT" }, { - "BriefDescription": "Number of Instructions per non-speculative DS= B miss", + "BriefDescription": "Number of Instructions per non-speculative DS= B miss (lower number means higher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", "MetricGroup": "DSBmiss;Fed", "MetricName": "IpDSB_Miss_Ret" }, + { + "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "IpMispredict" + }, + { + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIR= ED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.TH= READ))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_C= LK_UNHALTED.THREAD)) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.A= LL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU= _CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CO= RE / (4 * CPU_CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_= MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "Branch_Misprediction_Cost" + }, + { + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIR= ED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU= _CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU= _CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_D= ELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED= .ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ((BR_MISP_RETIRED.AL= L_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT= _MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_= DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 )= * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )= )) ) * (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_= THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCH= ES", + "MetricGroup": "Bad;BrMispredicts_SMT", + "MetricName": "Branch_Misprediction_Cost_SMT" + }, { "BriefDescription": "Fraction of branches that are non-taken condi= tionals", "MetricExpr": "BR_INST_RETIRED.NOT_TAKEN / BR_INST_RETIRED.ALL_BRA= NCHES", @@ -395,11 +431,10 @@ "MetricName": "Jump" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load instructions (in core cycles)", + "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load operations (in core cycles)", "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS = + MEM_LOAD_RETIRED.FB_HIT )", "MetricGroup": "Mem;MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency", - "PublicDescription": "Actual Average Latency for L1 data-cache mis= s demand load instructions (in core cycles). Latency may be overestimated f= or multi-load instructions - e.g. repeat strings." + "MetricName": "Load_Miss_Real_Latency" }, { "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", @@ -407,30 +442,6 @@ "MetricGroup": "Mem;MemoryBound;MemoryBW", "MetricName": "MLP" }, - { - "BriefDescription": "Average data fill bandwidth to the L1 data ca= che [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW" - }, - { - "BriefDescription": "Average data fill bandwidth to the L2 cache [= GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW" - }, - { - "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW" - }, - { - "BriefDescription": "Average per-core data access bandwidth to the= L3 cache [GB / sec]", - "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / d= uration_time", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "L3_Cache_Access_BW" - }, { "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", @@ -450,13 +461,13 @@ "MetricName": "L2MPKI" }, { - "BriefDescription": "L2 cache misses per kilo instruction for all = request types (including speculative)", + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instru= ction for all request types (including speculative)", "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", "MetricGroup": "Mem;CacheMisses;Offcore", "MetricName": "L2MPKI_All" }, { - "BriefDescription": "L2 cache misses per kilo instruction for all = demand loads (including speculative)", + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instru= ction for all demand loads (including speculative)", "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.= ANY", "MetricGroup": "Mem;CacheMisses", "MetricName": "L2MPKI_Load" @@ -480,7 +491,7 @@ "MetricName": "L3MPKI" }, { - "BriefDescription": "Fill Buffer (FB) true hits per kilo instructi= ons for retired demand loads", + "BriefDescription": "Fill Buffer (FB) hits per kilo instructions f= or retired demand loads (L1D misses that merge into ongoing miss-handling e= ntries)", "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", "MetricGroup": "Mem;CacheMisses", "MetricName": "FB_HPKI" @@ -498,6 +509,54 @@ "MetricGroup": "Mem;MemoryTLB_SMT", "MetricName": "Page_Walks_Utilization_SMT" }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", + "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L1D_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 2 cache [GB / sec]", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L2_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L3_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-core data access bandwidth to the= L3 cache [GB / sec]", + "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / d= uration_time", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "L3_Cache_Access_BW" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L1 data cache [GB / sec]", + "MetricExpr": "(64 * L1D.REPLACEMENT / 1000000000 / duration_time)= ", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L1D_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L2 cache [GB / sec]", + "MetricExpr": "(64 * L2_LINES_IN.ALL / 1000000000 / duration_time)= ", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L2_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L3 cache [GB / sec]", + "MetricExpr": "(64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duratio= n_time)", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L3_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data access bandwidth to t= he L3 cache [GB / sec]", + "MetricExpr": "(64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / = duration_time)", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "L3_Cache_Access_BW_1T" + }, { "BriefDescription": "Average CPU Utilization", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", @@ -514,7 +573,8 @@ "BriefDescription": "Giga Floating Point Operations Per Second", "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_= ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_= DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RET= IRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) = / 1000000000 ) / duration_time", "MetricGroup": "Cor;Flops;HPC", - "MetricName": "GFLOPs" + "MetricName": "GFLOPs", + "PublicDescription": "Giga Floating Point Operations Per Second. A= ggregate across all supported options of: FP precisions, scalar and vector = instructions, vector-width and AMX engine." }, { "BriefDescription": "Average Frequency Utilization relative nomina= l frequency", diff --git a/tools/perf/pmu-events/arch/x86/skylake/uncore-cache.json b/too= ls/perf/pmu-events/arch/x86/skylake/uncore-cache.json new file mode 100644 index 000000000000..edb1014bee0f --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/skylake/uncore-cache.json @@ -0,0 +1,142 @@ +[ + { + "BriefDescription": "L3 Lookup any request that access cache and f= ound line in E or S-state", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES", + "PerPkg": "1", + "PublicDescription": "L3 Lookup any request that access cache and = found line in E or S-state.", + "UMask": "0x86", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup any request that access cache and f= ound line in I-state", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I", + "PerPkg": "1", + "PublicDescription": "L3 Lookup any request that access cache and = found line in I-state.", + "UMask": "0x88", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup any request that access cache and f= ound line in M-state", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M", + "PerPkg": "1", + "PublicDescription": "L3 Lookup any request that access cache and = found line in M-state.", + "UMask": "0x81", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup any request that access cache and f= ound line in MESI-state", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI", + "PerPkg": "1", + "PublicDescription": "L3 Lookup any request that access cache and = found line in MESI-state.", + "UMask": "0x8f", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup read request that access cache and = found line in E or S-state", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES", + "PerPkg": "1", + "PublicDescription": "L3 Lookup read request that access cache and= found line in E or S-state.", + "UMask": "0x16", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup read request that access cache and = found line in I-state", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I", + "PerPkg": "1", + "PublicDescription": "L3 Lookup read request that access cache and= found line in I-state.", + "UMask": "0x18", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup read request that access cache and = found line in any MESI-state", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI", + "PerPkg": "1", + "PublicDescription": "L3 Lookup read request that access cache and= found line in any MESI-state.", + "UMask": "0x1f", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup write request that access cache and= found line in E or S-state", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES", + "PerPkg": "1", + "PublicDescription": "L3 Lookup write request that access cache an= d found line in E or S-state.", + "UMask": "0x26", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup write request that access cache and= found line in M-state", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M", + "PerPkg": "1", + "PublicDescription": "L3 Lookup write request that access cache an= d found line in M-state.", + "UMask": "0x21", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup write request that access cache and= found line in MESI-state", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI", + "PerPkg": "1", + "PublicDescription": "L3 Lookup write request that access cache an= d found line in MESI-state.", + "UMask": "0x2f", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop initiated by this Cbox due= to processor core memory request which hits a modified line in some proces= sor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop initiated by this Cbox du= e to processor core memory request which hits a modified line in some proce= ssor core.", + "UMask": "0x48", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop initiated by this Cbox due= to processor core memory request which hits a non-modified line in some pr= ocessor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop initiated by this Cbox du= e to processor core memory request which hits a non-modified line in some p= rocessor core.", + "UMask": "0x44", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop resulted from L3 Eviction = which misses in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop resulted from L3 Eviction= which misses in some processor core.", + "UMask": "0x81", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop initiated by this Cbox due= to processor core memory request which misses in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop initiated by this Cbox du= e to processor core memory request which misses in some processor core.", + "UMask": "0x41", + "Unit": "CBO" + } +] diff --git a/tools/perf/pmu-events/arch/x86/skylake/uncore-other.json b/too= ls/perf/pmu-events/arch/x86/skylake/uncore-other.json new file mode 100644 index 000000000000..bf5d4acdd6b8 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/skylake/uncore-other.json @@ -0,0 +1,79 @@ +[ + { + "BriefDescription": "Number of entries allocated. Account for Any = type: e.g. Snoop, Core aperture, etc.", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", + "PerPkg": "1", + "PublicDescription": "Number of entries allocated. Account for Any= type: e.g. Snoop, Core aperture, etc.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of all Core entries outstanding for th= e memory controller. The outstanding interval starts after LLC miss till re= turn of first data chunk. Accounts for Coherent and non-coherent traffic.", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", + "PerPkg": "1", + "PublicDescription": "Number of all Core entries outstanding for t= he memory controller. The outstanding interval starts after LLC miss till r= eturn of first data chunk. Accounts for Coherent and non-coherent traffic.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Cycles with at least one request outstanding = is waiting for data return from memory controller. Account for coherent and= non-coherent requests initiated by IA Cores, Processor Graphics Unit, or L= LC.", + "CounterMask": "1", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", + "PerPkg": "1", + "PublicDescription": "Cycles with at least one request outstanding= is waiting for data return from memory controller. Account for coherent an= d non-coherent requests initiated by IA Cores, Processor Graphics Unit, or = LLC.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of Core Data Read entries outstanding = for the memory controller. The outstanding interval starts after LLC miss t= ill return of first data chunk.", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.DATA_READ", + "PerPkg": "1", + "PublicDescription": "Number of Core Data Read entries outstanding= for the memory controller. The outstanding interval starts after LLC miss = till return of first data chunk.", + "UMask": "0x02", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of Core coherent Data Read requests se= nt to memory controller whose data is returned directly to requesting agent= .", + "Counter": "0,1", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.DATA_READ", + "PerPkg": "1", + "PublicDescription": "Number of Core coherent Data Read requests s= ent to memory controller whose data is returned directly to requesting agen= t.", + "UMask": "0x02", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of Core coherent Data Read requests se= nt to memory controller whose data is returned directly to requesting agent= .", + "Counter": "0,1", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT", + "PerPkg": "1", + "PublicDescription": "Number of Core coherent Data Read requests s= ent to memory controller whose data is returned directly to requesting agen= t.", + "UMask": "0x02", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of Writes allocated - any write transa= ctions: full/partials writes and evictions.", + "Counter": "0,1", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", + "PerPkg": "1", + "PublicDescription": "Number of Writes allocated - any write trans= actions: full/partials writes and evictions.", + "UMask": "0x20", + "Unit": "ARB" + }, + { + "BriefDescription": "This 48-bit fixed counter counts the UCLK cyc= les", + "Counter": "FIXED", + "EventCode": "0xff", + "EventName": "UNC_CLOCK.SOCKET", + "PerPkg": "1", + "PublicDescription": "This 48-bit fixed counter counts the UCLK cy= cles.", + "Unit": "CLOCK" + } +] diff --git a/tools/perf/pmu-events/arch/x86/skylake/uncore.json b/tools/per= f/pmu-events/arch/x86/skylake/uncore.json deleted file mode 100644 index dbc193252fb3..000000000000 --- a/tools/perf/pmu-events/arch/x86/skylake/uncore.json +++ /dev/null @@ -1,254 +0,0 @@ -[ - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x41", - "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE", - "BriefDescription": "A cross-core snoop initiated by this Cbox due to = processor core memory request which misses in some processor core.", - "PublicDescription": "A cross-core snoop initiated by this Cbox due to= processor core memory request which misses in some processor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x81", - "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION", - "BriefDescription": "A cross-core snoop resulted from L3 Eviction whic= h misses in some processor core.", - "PublicDescription": "A cross-core snoop resulted from L3 Eviction whi= ch misses in some processor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x44", - "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE", - "BriefDescription": "A cross-core snoop initiated by this Cbox due to = processor core memory request which hits a non-modified line in some proces= sor core.", - "PublicDescription": "A cross-core snoop initiated by this Cbox due to= processor core memory request which hits a non-modified line in some proce= ssor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x48", - "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE", - "BriefDescription": "A cross-core snoop initiated by this Cbox due to = processor core memory request which hits a modified line in some processor = core.", - "PublicDescription": "A cross-core snoop initiated by this Cbox due to= processor core memory request which hits a modified line in some processor= core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x21", - "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M", - "BriefDescription": "L3 Lookup write request that access cache and fou= nd line in M-state", - "PublicDescription": "L3 Lookup write request that access cache and fo= und line in M-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x81", - "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M", - "BriefDescription": "L3 Lookup any request that access cache and found= line in M-state", - "PublicDescription": "L3 Lookup any request that access cache and foun= d line in M-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x18", - "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I", - "BriefDescription": "L3 Lookup read request that access cache and foun= d line in I-state", - "PublicDescription": "L3 Lookup read request that access cache and fou= nd line in I-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x88", - "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I", - "BriefDescription": "L3 Lookup any request that access cache and found= line in I-state", - "PublicDescription": "L3 Lookup any request that access cache and foun= d line in I-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x1f", - "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI", - "BriefDescription": "L3 Lookup read request that access cache and foun= d line in any MESI-state", - "PublicDescription": "L3 Lookup read request that access cache and fou= nd line in any MESI-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x2f", - "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI", - "BriefDescription": "L3 Lookup write request that access cache and fou= nd line in MESI-state", - "PublicDescription": "L3 Lookup write request that access cache and fo= und line in MESI-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x8f", - "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI", - "BriefDescription": "L3 Lookup any request that access cache and found= line in MESI-state", - "PublicDescription": "L3 Lookup any request that access cache and foun= d line in MESI-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x86", - "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES", - "BriefDescription": "L3 Lookup any request that access cache and found= line in E or S-state", - "PublicDescription": "L3 Lookup any request that access cache and foun= d line in E or S-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x16", - "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES", - "BriefDescription": "L3 Lookup read request that access cache and foun= d line in E or S-state", - "PublicDescription": "L3 Lookup read request that access cache and fou= nd line in E or S-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x26", - "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES", - "BriefDescription": "L3 Lookup write request that access cache and fou= nd line in E or S-state", - "PublicDescription": "L3 Lookup write request that access cache and fo= und line in E or S-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "iMPH-U", - "EventCode": "0x80", - "UMask": "0x01", - "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", - "BriefDescription": "Each cycle count number of all Core outgoing vali= d entries. Such entry is defined as valid from its allocation till first of= IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent = traffic.", - "PublicDescription": "Each cycle count number of all Core outgoing val= id entries. Such entry is defined as valid from its allocation till first o= f IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent= traffic.", - "Counter": "0", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "iMPH-U", - "EventCode": "0x81", - "UMask": "0x01", - "EventName": "UNC_ARB_TRK_REQUESTS.ALL", - "BriefDescription": "Total number of Core outgoing entries allocated. = Accounts for Coherent and non-coherent traffic.", - "PublicDescription": "Total number of Core outgoing entries allocated.= Accounts for Coherent and non-coherent traffic.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "iMPH-U", - "EventCode": "0x81", - "UMask": "0x02", - "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT", - "BriefDescription": "Number of Core coherent Data Read entries allocat= ed in DirectData mode", - "PublicDescription": "Number of Core coherent Data Read entries alloca= ted in DirectData mode.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "iMPH-U", - "EventCode": "0x81", - "UMask": "0x20", - "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", - "BriefDescription": "Number of Writes allocated - any write transactio= ns: full/partials writes and evictions.", - "PublicDescription": "Number of Writes allocated - any write transacti= ons: full/partials writes and evictions.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "iMPH-U", - "EventCode": "0x84", - "UMask": "0x01", - "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", - "BriefDescription": "Number of entries allocated. Account for Any type= : e.g. Snoop, Core aperture, etc.", - "PublicDescription": "Number of entries allocated. Account for Any typ= e: e.g. Snoop, Core aperture, etc.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "iMPH-U", - "EventCode": "0x80", - "UMask": "0x01", - "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", - "BriefDescription": "Cycles with at least one request outstanding is w= aiting for data return from memory controller. Account for coherent and non= -coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.;= ", - "PublicDescription": "Cycles with at least one request outstanding is = waiting for data return from memory controller. Account for coherent and no= n-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.= ", - "Counter": "0", - "CounterMask": "1", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "NCU", - "EventCode": "0x0", - "UMask": "0x01", - "EventName": "UNC_CLOCK.SOCKET", - "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles", - "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles= .", - "Counter": "FIXED", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - } -] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/skylake/virtual-memory.json b/t= ools/perf/pmu-events/arch/x86/skylake/virtual-memory.json index 792ca39f013a..dd334b416c57 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/skylake/virtual-memory.json @@ -281,4 +281,4 @@ "SampleAfterValue": "100007", "UMask": "0x20" } -] \ No newline at end of file +] --=20 2.37.1.359.gd136c6c3e2-goog From nobody Wed Apr 15 05:45:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4065DC04A68 for ; Wed, 27 Jul 2022 22:13:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237337AbiG0WN0 (ORCPT ); Wed, 27 Jul 2022 18:13:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51324 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237338AbiG0WMk (ORCPT ); Wed, 27 Jul 2022 18:12:40 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8040BB67 for ; Wed, 27 Jul 2022 15:10:07 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id a11-20020a5b090b000000b00672acbe13c1so258080ybq.2 for ; Wed, 27 Jul 2022 15:10:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc:content-transfer-encoding; bh=V8b4c+TTEHGi8RlCaFmiNPaQkWj/mS+6d391P4KEKN0=; b=SZHDUxvVPCmbVyJ7GkTNxK2oJ8e1i1RjF2sd6NxXGufbHCX6VwYDYSrKbMVLtkLQpr tXvOfRDLTAq0xfwvnbUSpDLvuKQfgCAG1GwgKqpp0SlnGkPkKF0ngA+fWNW6hWPGLjnA QBr+OkAfU6ITRNFSAhHEVQFaszX8Fe+naXvrMEsOavL9f0LUKqmVQh3f/nlfGXJgTkCv D8Rgw1bgbk0PMNusUfdL3e6JYaV4hrifH8zCWdIqYwJul190kOIO926YhRm1KMo052oy s5p76Ki4tlgChMnogFBwTaF8ZAjAkIxzcWN4WoN5IWsShBsixODb0I3Lfac2H5MysR82 UJxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc:content-transfer-encoding; bh=V8b4c+TTEHGi8RlCaFmiNPaQkWj/mS+6d391P4KEKN0=; b=zAZ7wHnv903E514dCeen1yyMMO9YswholAl+wuJ2eD4s4Le6MvqVz9/UHIInItCsst ALiogrXvu0pWa4zNFurDaUEVMnCNekvZPOEGCOUB/jwpd6dGGS1QIhl19YRxlsSoQlPD 2cqgnNasnWFyrm2ZHDPLySdWNYHYZuKUSgEvpweizdq+j/BMHv0STTIe/BNb1IoAAfXr Dag28EfF0dePd5tPKU2ht2tldTlD8hZTKj8B4F8DMxDUrXppzjjhTwdl6QqACryEELd9 QVsVk7D5j2HS19VQtc1WN0+2MB36514QUE0AGS0RJI/HWi0+1ivI67xU8VSxTEN2zCBP Gt/A== X-Gm-Message-State: AJIora92ruCRNqokgPW6kPkvf/MEJIRbWCZ/Jt3/hkeMRdKxPTAP3/vp +gm+oH0hw9QJ0Jd6MynDW5isRqj7PLQN X-Google-Smtp-Source: AGRyM1ukoDPf7VJHe0qhdulPyh4xvhQi3AjzU28BxM5VuTNy0G+DTkFaJiLwjaDJCtvkoI4HTA/IBK52eiwj X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:882a:af57:8cb6:6f9e]) (user=irogers job=sendgmr) by 2002:a05:6902:38a:b0:670:aa12:8908 with SMTP id f10-20020a056902038a00b00670aa128908mr18475385ybs.446.1658959791300; Wed, 27 Jul 2022 15:09:51 -0700 (PDT) Date: Wed, 27 Jul 2022 15:08:27 -0700 In-Reply-To: <20220727220832.2865794-1-irogers@google.com> Message-Id: <20220727220832.2865794-26-irogers@google.com> Mime-Version: 1.0 References: <20220727220832.2865794-1-irogers@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH v3 25/30] perf vendor events: Update Intel skylakex From: Ian Rogers To: perry.taylor@intel.com, caleb.biggers@intel.com, kshipra.bopardikar@intel.com, Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Sedat Dilek Cc: Stephane Eranian , Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Update to v1.28, the metrics are based on TMA 4.4 full. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/downloa= d_and_gen.py to download and generate the latest events and metrics. Manually copy the skylakex files into perf and update mapfile.csv. Tested with 'perf test': 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok 90: perf all metricgroups test : Ok 91: perf all metrics test : Skip 93: perf all PMU test : Ok Signed-off-by: Ian Rogers --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- .../arch/x86/skylakex/floating-point.json | 2 +- .../arch/x86/skylakex/frontend.json | 2 +- .../pmu-events/arch/x86/skylakex/other.json | 66 +- .../arch/x86/skylakex/pipeline.json | 11 + .../arch/x86/skylakex/skx-metrics.json | 667 ++++++++++++++-- .../arch/x86/skylakex/uncore-memory.json | 9 + .../arch/x86/skylakex/uncore-other.json | 730 +++++++++++++++++- .../arch/x86/skylakex/virtual-memory.json | 2 +- 9 files changed, 1414 insertions(+), 77 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 78552ef68482..14b1707cf8ab 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -23,10 +23,10 @@ GenuineIntel-6-2A,v17,sandybridge,core GenuineIntel-6-8F,v1.04,sapphirerapids,core GenuineIntel-6-(37|4C|4D),v14,silvermont,core GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v53,skylake,core +GenuineIntel-6-55-[01234],v1.28,skylakex,core GenuineIntel-6-2C,v2,westmereep-dp,core GenuineIntel-6-25,v2,westmereep-sp,core GenuineIntel-6-2F,v2,westmereex,core -GenuineIntel-6-55-[01234],v1,skylakex,core GenuineIntel-6-8[CD],v1,tigerlake,core GenuineIntel-6-86,v1,snowridgex,core AuthenticAMD-23-([12][0-9A-F]|[0-9A-F]),v2,amdzen1,core diff --git a/tools/perf/pmu-events/arch/x86/skylakex/floating-point.json b/= tools/perf/pmu-events/arch/x86/skylakex/floating-point.json index 9e873ab22450..09810e3d688c 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/floating-point.json @@ -90,4 +90,4 @@ "SampleAfterValue": "100003", "UMask": "0x1e" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/skylakex/frontend.json b/tools/= perf/pmu-events/arch/x86/skylakex/frontend.json index ecce4273ae52..8633ee406813 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/frontend.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/frontend.json @@ -527,4 +527,4 @@ "SampleAfterValue": "2000003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/skylakex/other.json b/tools/per= f/pmu-events/arch/x86/skylakex/other.json index 779654e62d97..403805e7e581 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/other.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/other.json @@ -39,6 +39,69 @@ "SampleAfterValue": "200003", "UMask": "0x40" }, + { + "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDFE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xEF", + "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDFE", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDM", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xEF", + "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDM", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITFSE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xEF", + "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITFSE", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITI", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xEF", + "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITI", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDFE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xEF", + "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDFE", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDM", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xEF", + "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDM", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SHITFSE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xEF", + "EventName": "CORE_SNOOP_RESPONSE.RSP_SHITFSE", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, { "BriefDescription": "Number of hardware interrupts received by the= processor.", "Counter": "0,1,2,3", @@ -70,6 +133,7 @@ "UMask": "0x2" }, { + "BriefDescription": "MEMORY_DISAMBIGUATION.HISTORY_RESET", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x09", @@ -77,4 +141,4 @@ "SampleAfterValue": "2000003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/skylakex/pipeline.json b/tools/= perf/pmu-events/arch/x86/skylakex/pipeline.json index 79fda10ec4bb..f085b9145952 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/pipeline.json @@ -165,6 +165,17 @@ "SampleAfterValue": "400009", "UMask": "0x20" }, + { + "BriefDescription": "This event counts the number of mispredicted = ret instructions retired. Non PEBS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.RET", + "PEBS": "1", + "PublicDescription": "This is a non-precise version (that is, does= not use PEBS) of the event that counts mispredicted return instructions re= tired.", + "SampleAfterValue": "100007", + "UMask": "0x8" + }, { "BriefDescription": "Core crystal clock cycles when this thread is= unhalted and the other thread is halted.", "Counter": "0,1,2,3", diff --git a/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json b/too= ls/perf/pmu-events/arch/x86/skylakex/skx-metrics.json index b016f7d1ff3d..d65420bda04f 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json @@ -95,13 +95,13 @@ { "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIV= ITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORT= S_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_= ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NO= T_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 *= INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) * ( ( (max( (= CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK= _UNHALTED.THREAD , 0 )) / ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.= BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UT= IL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTI= VITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DE= LIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT= _MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (min( 9 * c= pu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=3D1@ + DTLB_LOAD_MISSES.WALK_ACTIVE = , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 )= ) / CPU_CLK_UNHALTED.THREAD) / (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYC= LE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) + ( (EXE_A= CTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.ST= ALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTA= L + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_= UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STOR= ES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) -= ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED= .THREAD))) ) * ( (( 9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=3D1@ + DTL= B_STORE_MISSES.WALK_ACTIVE ) / CPU_CLK_UNHALTED.THREAD) / #(EXE_ACTIVITY.BO= UND_ON_STORES / CPU_CLK_UNHALTED.THREAD) ) ) ", - "MetricGroup": "Mem;MemoryTLB", + "MetricGroup": "Mem;MemoryTLB;Offcore", "MetricName": "Memory_Data_TLBs" }, { "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIV= ITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORT= S_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 = ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) = ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (I= DQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 += CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( U= OPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) )))) * ( ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - = CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / ((( CYC= LE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVI= TY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS /= (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD= _ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EX= E_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( (= CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE /= CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOV= ERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU= _CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (m= in( 9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=3D1@ + DTLB_LOAD_MISSES.WAL= K_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_M= ISS , 0 ) ) / CPU_CLK_UNHALTED.THREAD) / (max( ( CYCLE_ACTIVITY.STALLS_MEM_= ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) += ( (EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_AC= TIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.ST= ALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 *= ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTI= VE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACT= IVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_C= YCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_= UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (( 9 * = cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=3D1@ + DTLB_STORE_MISSES.WALK_ACTI= VE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREA= D_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / #(EXE_ACTIVITY.BOUND_ON_STORES = / CPU_CLK_UNHALTED.THREAD) ) ) ", - "MetricGroup": "Mem;MemoryTLB;_SMT", + "MetricGroup": "Mem;MemoryTLB;Offcore_SMT", "MetricName": "Memory_Data_TLBs_SMT" }, { @@ -158,12 +158,6 @@ "MetricGroup": "Branches;Fed;FetchBW", "MetricName": "UpTB" }, - { - "BriefDescription": "Cycles Per Instruction (per Logical Processor= )", - "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", - "MetricGroup": "Pipeline;Mem", - "MetricName": "CPI" - }, { "BriefDescription": "Per-Logical Processor actual clocks when the = Logical Processor is active.", "MetricExpr": "CPU_CLK_UNHALTED.THREAD", @@ -214,42 +208,36 @@ "MetricName": "FLOPc_SMT" }, { - "BriefDescription": "Actual per-core usage of the Floating Point e= xecution units (regardless of the vector width)", + "BriefDescription": "Actual per-core usage of the Floating Point n= on-X87 execution units (regardless of precision or vector-width)", "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_I= NST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP= _ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_= DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.5= 12B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) ) / ( 2 * CPU= _CLK_UNHALTED.THREAD )", "MetricGroup": "Cor;Flops;HPC", "MetricName": "FP_Arith_Utilization", - "PublicDescription": "Actual per-core usage of the Floating Point = execution units (regardless of the vector width). Values > 1 are possible d= ue to Fused-Multiply Add (FMA) counting." + "PublicDescription": "Actual per-core usage of the Floating Point = non-X87 execution units (regardless of precision or vector-width). Values >= 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; = [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less commo= n)." }, { - "BriefDescription": "Actual per-core usage of the Floating Point e= xecution units (regardless of the vector width). SMT version; use when SMT = is enabled and measuring per logical CPU.", + "BriefDescription": "Actual per-core usage of the Floating Point n= on-X87 execution units (regardless of precision or vector-width). SMT versi= on; use when SMT is enabled and measuring per logical CPU.", "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_I= NST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP= _ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_= DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.5= 12B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) ) / ( 2 * ( (= CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE /= CPU_CLK_UNHALTED.REF_XCLK ) ) )", "MetricGroup": "Cor;Flops;HPC_SMT", "MetricName": "FP_Arith_Utilization_SMT", - "PublicDescription": "Actual per-core usage of the Floating Point = execution units (regardless of the vector width). Values > 1 are possible d= ue to Fused-Multiply Add (FMA) counting. SMT version; use when SMT is enabl= ed and measuring per logical CPU." + "PublicDescription": "Actual per-core usage of the Floating Point = non-X87 execution units (regardless of precision or vector-width). Values >= 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; = [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less commo= n). SMT version; use when SMT is enabled and measuring per logical CPU." }, { - "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is at least 1 uop executed)", + "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per-core", "MetricExpr": "UOPS_EXECUTED.THREAD / (( UOPS_EXECUTED.CORE_CYCLES= _GE_1 / 2 ) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, { - "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIR= ED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.TH= READ))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_C= LK_UNHALTED.THREAD)) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.A= LL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU= _CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CO= RE / (4 * CPU_CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_= MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BrMispredicts", - "MetricName": "Branch_Misprediction_Cost" + "BriefDescription": "Probability of Core Bound bottleneck hidden b= y SMT-profiling artifacts", + "MetricExpr": "( 1 - ((1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU= _CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES )= / (4 * CPU_CLK_UNHALTED.THREAD)) - ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE= _ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.= 1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) = * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_U= OPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY= + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)))) / ((EX= E_ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.R= ETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL)) = / CPU_CLK_UNHALTED.THREAD if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STAL= LS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else (EXE_ACTIVITY.1_PORTS_UTI= L + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIV= ITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD) if ((1 - (IDQ_UOPS_NOT_DELIVER= ED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC= .RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)) - ((( CYCLE_ACTIVITY.ST= ALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTA= L + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_= UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STOR= ES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) -= ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED= .THREAD)))) < ((EXE_ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACTIVITY.1_PORTS_UTIL= + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVI= TY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD if ( ARITH.DIVIDER_ACTIVE < ( C= YCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else (EXE_AC= TIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.TH= READ)) * EXE_ACTIVITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD) else 1 ) if = 0 > 0.5 else 0", + "MetricGroup": "Cor;SMT", + "MetricName": "Core_Bound_Likely" }, { - "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIR= ED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU= _CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU= _CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_D= ELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED= .ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ((BR_MISP_RETIRED.AL= L_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT= _MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_= DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 )= * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )= )) ) * (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_= THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCH= ES", - "MetricGroup": "Bad;BrMispredicts_SMT", - "MetricName": "Branch_Misprediction_Cost_SMT" - }, - { - "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear)", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "IpMispredict" + "BriefDescription": "Probability of Core Bound bottleneck hidden b= y SMT-profiling artifacts", + "MetricExpr": "( 1 - ((1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( (= CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE /= CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOV= ERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU= _CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ((( CYC= LE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVI= TY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS /= (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD= _ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EX= E_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( (= CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE /= CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOV= ERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU= _CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))))) / ((EXE= _ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RE= TIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTE= D.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORT= S_UTIL)) / CPU_CLK_UNHALTED.THREAD if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTI= VITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else (EXE_ACTIVITY.1_= PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD = / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCL= K ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD) if ((1 - (I= DQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 += CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( U= OPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) ))) - ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIV= ITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORT= S_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 = ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) = ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (I= DQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 += CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( U= OPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_= CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_= CLK_UNHALTED.REF_XCLK ) ))))) < ((EXE_ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACT= IVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED= .THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED= .REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD if = ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STA= LLS_MEM_ANY ) ) else (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOT= S / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THR= EAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) /= CPU_CLK_UNHALTED.THREAD) else 1 ) if (1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTI= VE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 )) > 0.5 else 0", + "MetricGroup": "Cor;SMT_SMT", + "MetricName": "Core_Bound_Likely_SMT" }, { "BriefDescription": "Core actual clocks when any Logical Processor= is active on the Physical Core", @@ -341,12 +329,30 @@ "MetricName": "IpArith_AVX512", "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit i= nstruction (lower number means higher occurrence rate). May undercount due = to FMA double counting." }, + { + "BriefDescription": "Instructions per Software prefetch instructio= n (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrenc= e rate)", + "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umas= k\\=3D0xF@", + "MetricGroup": "Prefetches", + "MetricName": "IpSWPF" + }, { "BriefDescription": "Total number of retired Instructions, Sample = with: INST_RETIRED.PREC_DIST", "MetricExpr": "INST_RETIRED.ANY", "MetricGroup": "Summary;TmaL1", "MetricName": "Instructions" }, + { + "BriefDescription": "Average number of Uops retired in cycles wher= e at least one uop has retired.", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE= _SLOTS\\,cmask\\=3D1@", + "MetricGroup": "Pipeline;Ret", + "MetricName": "Retire" + }, + { + "BriefDescription": "", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,c= mask\\=3D1@", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", + "MetricName": "Execute" + }, { "BriefDescription": "Average number of Uops issued by front-end wh= en it issued something", "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=3D1= @", @@ -360,23 +366,47 @@ "MetricName": "DSB_Coverage" }, { - "BriefDescription": "Total penalty related to DSB (uop cache) miss= es - subset/see of/the Instruction_Fetch_BW Bottleneck.", - "MetricExpr": "(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.COR= E / (4 * CPU_CLK_UNHALTED.THREAD)) * (DSB2MITE_SWITCHES.PENALTY_CYCLES / CP= U_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.C= ORE / (4 * CPU_CLK_UNHALTED.THREAD)) + ((IDQ_UOPS_NOT_DELIVERED.CORE / (4 *= CPU_CLK_UNHALTED.THREAD)) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELI= V.CORE / (4 * CPU_CLK_UNHALTED.THREAD))) * (( IDQ.ALL_MITE_CYCLES_ANY_UOPS = - IDQ.ALL_MITE_CYCLES_4_UOPS ) / CPU_CLK_UNHALTED.THREAD / 2) / #((IDQ_UOPS= _NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - (4 * IDQ_UOPS_NOT_DE= LIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)))", + "BriefDescription": "Average number of cycles of a switch from the= DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details= .", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / DSB2MITE_SWITCHE= S.COUNT", + "MetricGroup": "DSBmiss", + "MetricName": "DSB_Switch_Cost" + }, + { + "BriefDescription": "Total penalty related to DSB (uop cache) miss= es - subset of the Instruction_Fetch_BW Bottleneck.", + "MetricExpr": "100 * ( (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_D= ELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * (DSB2MITE_SWITCHES.PENALTY_CYC= LES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS= _DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) + ((IDQ_UOPS_NOT_DELIVERED.COR= E / (4 * CPU_CLK_UNHALTED.THREAD)) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_U= OPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD))) * (( IDQ.ALL_MITE_CYCLES_A= NY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS ) / CPU_CLK_UNHALTED.THREAD / 2) / #((= IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - (4 * IDQ_UOP= S_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD))) = )", "MetricGroup": "DSBmiss;Fed", - "MetricName": "DSB_Misses_Cost" + "MetricName": "DSB_Misses" }, { - "BriefDescription": "Total penalty related to DSB (uop cache) miss= es - subset/see of/the Instruction_Fetch_BW Bottleneck.", - "MetricExpr": "(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.COR= E / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THR= EAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (DSB2MITE_SWITCHES.PENALTY_C= YCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UO= PS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHA= LTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + ((IDQ_UOPS_NOT_D= ELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHA= LTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ_UOPS_NO= T_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2= ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK )= )))) * (( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS ) / ( = ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE = / CPU_CLK_UNHALTED.REF_XCLK ) ) / 2) / #((IDQ_UOPS_NOT_DELIVERED.CORE / (4 = * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACT= IVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_= 0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_= UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))))", + "BriefDescription": "Total penalty related to DSB (uop cache) miss= es - subset of the Instruction_Fetch_BW Bottleneck.", + "MetricExpr": "100 * ( (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_D= ELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED= .ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (DSB2MITE_SWITCHES.P= ENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYC= LES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_= CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + ((IDQ_UO= PS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_= CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ= _UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.TH= READ / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.RE= F_XCLK ) )))) * (( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOP= S ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD= _ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) / 2) / #((IDQ_UOPS_NOT_DELIVERED.CO= RE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_TH= READ_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ_UOPS_NOT_DELIVERED= .CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + = CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) )", "MetricGroup": "DSBmiss;Fed_SMT", - "MetricName": "DSB_Misses_Cost_SMT" + "MetricName": "DSB_Misses_SMT" }, { - "BriefDescription": "Number of Instructions per non-speculative DS= B miss", + "BriefDescription": "Number of Instructions per non-speculative DS= B miss (lower number means higher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", "MetricGroup": "DSBmiss;Fed", "MetricName": "IpDSB_Miss_Ret" }, + { + "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "IpMispredict" + }, + { + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIR= ED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.TH= READ))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_C= LK_UNHALTED.THREAD)) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.A= LL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU= _CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CO= RE / (4 * CPU_CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_= MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "Branch_Misprediction_Cost" + }, + { + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIR= ED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU= _CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU= _CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_D= ELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED= .ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ((BR_MISP_RETIRED.AL= L_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT= _MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_= DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 )= * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )= )) ) * (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_= THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCH= ES", + "MetricGroup": "Bad;BrMispredicts_SMT", + "MetricName": "Branch_Misprediction_Cost_SMT" + }, { "BriefDescription": "Fraction of branches that are non-taken condi= tionals", "MetricExpr": "BR_INST_RETIRED.NOT_TAKEN / BR_INST_RETIRED.ALL_BRA= NCHES", @@ -402,11 +432,10 @@ "MetricName": "Jump" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load instructions (in core cycles)", + "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load operations (in core cycles)", "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS = + MEM_LOAD_RETIRED.FB_HIT )", "MetricGroup": "Mem;MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency", - "PublicDescription": "Actual Average Latency for L1 data-cache mis= s demand load instructions (in core cycles). Latency may be overestimated f= or multi-load instructions - e.g. repeat strings." + "MetricName": "Load_Miss_Real_Latency" }, { "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", @@ -414,30 +443,6 @@ "MetricGroup": "Mem;MemoryBound;MemoryBW", "MetricName": "MLP" }, - { - "BriefDescription": "Average data fill bandwidth to the L1 data ca= che [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW" - }, - { - "BriefDescription": "Average data fill bandwidth to the L2 cache [= GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW" - }, - { - "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW" - }, - { - "BriefDescription": "Average per-core data access bandwidth to the= L3 cache [GB / sec]", - "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / d= uration_time", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "L3_Cache_Access_BW" - }, { "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", @@ -457,13 +462,13 @@ "MetricName": "L2MPKI" }, { - "BriefDescription": "L2 cache misses per kilo instruction for all = request types (including speculative)", + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instru= ction for all request types (including speculative)", "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", "MetricGroup": "Mem;CacheMisses;Offcore", "MetricName": "L2MPKI_All" }, { - "BriefDescription": "L2 cache misses per kilo instruction for all = demand loads (including speculative)", + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instru= ction for all demand loads (including speculative)", "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.= ANY", "MetricGroup": "Mem;CacheMisses", "MetricName": "L2MPKI_Load" @@ -487,7 +492,7 @@ "MetricName": "L3MPKI" }, { - "BriefDescription": "Fill Buffer (FB) true hits per kilo instructi= ons for retired demand loads", + "BriefDescription": "Fill Buffer (FB) hits per kilo instructions f= or retired demand loads (L1D misses that merge into ongoing miss-handling e= ntries)", "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", "MetricGroup": "Mem;CacheMisses", "MetricName": "FB_HPKI" @@ -505,6 +510,30 @@ "MetricGroup": "Mem;MemoryTLB_SMT", "MetricName": "Page_Walks_Utilization_SMT" }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", + "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L1D_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 2 cache [GB / sec]", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L2_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L3_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-core data access bandwidth to the= L3 cache [GB / sec]", + "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / d= uration_time", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "L3_Cache_Access_BW" + }, { "BriefDescription": "Rate of silent evictions from the L2 cache pe= r Kilo instruction where the evicted lines are dropped (no writeback to L3 = or memory)", "MetricExpr": "1000 * L2_LINES_OUT.SILENT / INST_RETIRED.ANY", @@ -517,6 +546,30 @@ "MetricGroup": "L2Evicts;Mem;Server", "MetricName": "L2_Evictions_NonSilent_PKI" }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L1 data cache [GB / sec]", + "MetricExpr": "(64 * L1D.REPLACEMENT / 1000000000 / duration_time)= ", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L1D_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L2 cache [GB / sec]", + "MetricExpr": "(64 * L2_LINES_IN.ALL / 1000000000 / duration_time)= ", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L2_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L3 cache [GB / sec]", + "MetricExpr": "(64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duratio= n_time)", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L3_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data access bandwidth to t= he L3 cache [GB / sec]", + "MetricExpr": "(64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / = duration_time)", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "L3_Cache_Access_BW_1T" + }, { "BriefDescription": "Average CPU Utilization", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", @@ -533,7 +586,8 @@ "BriefDescription": "Giga Floating Point Operations Per Second", "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_= ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_= DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RET= IRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE = + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.5= 12B_PACKED_SINGLE ) / 1000000000 ) / duration_time", "MetricGroup": "Cor;Flops;HPC", - "MetricName": "GFLOPs" + "MetricName": "GFLOPs", + "PublicDescription": "Giga Floating Point Operations Per Second. A= ggregate across all supported options of: FP precisions, scalar and vector = instructions, vector-width and AMX engine." }, { "BriefDescription": "Average Frequency Utilization relative nomina= l frequency", @@ -690,5 +744,488 @@ "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C7_Pkg_Residency" + }, + { + "BriefDescription": "Percentage of time spent in the active CPU po= wer state C0", + "MetricExpr": "100 * CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricGroup": "", + "MetricName": "cpu_utilization_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "CPU operating frequency (in GHz)", + "MetricExpr": "(( CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_T= SC * #SYSTEM_TSC_FREQ ) / 1000000000) / duration_time", + "MetricGroup": "", + "MetricName": "cpu_operating_frequency", + "ScaleUnit": "1GHz" + }, + { + "BriefDescription": "Cycles per instruction retired; indicating ho= w much time each executed instruction took; in units of cycles.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "cpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "The ratio of number of completed memory load = instructions to the total number completed instructions", + "MetricExpr": "MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "loads_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "The ratio of number of completed memory store= instructions to the total number completed instructions", + "MetricExpr": "MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "stores_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of requests missing L1 data c= ache (includes data+rfo w/ prefetches) to the total number of completed ins= tructions", + "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l1d_mpi_includes_data_plus_rfo_with_prefetches", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of demand load requests hitti= ng in L1 data cache to the total number of completed instructions ", + "MetricExpr": "MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l1d_demand_data_read_hits_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read requests missing= in L1 instruction cache (includes prefetches) to the total number of compl= eted instructions", + "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed demand load requ= ests hitting in L2 cache to the total number of completed instructions ", + "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l2_demand_data_read_hits_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of requests missing L2 cache = (includes code+data+rfo w/ prefetches) to the total number of completed ins= tructions", + "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l2_mpi_includes_code_plus_data_plus_rfo_with_prefet= ches", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed data read reques= t missing L2 cache to the total number of completed instructions", + "MetricExpr": "MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l2_demand_data_read_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read request missing = L2 cache to the total number of completed instructions", + "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l2_demand_code_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of data read requests missing= last level core cache (includes demand w/ prefetches) to the total number = of completed instructions", + "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=3D0x12D= 4043300000000@ / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "llc_data_read_mpi_demand_plus_prefetch", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read requests missing= last level core cache (includes demand w/ prefetches) to the total number = of completed instructions", + "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=3D0x12C= C023300000000@ / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "llc_code_read_mpi_demand_plus_prefetch", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = all page sizes) caused by a code fetch to the total number of completed ins= tructions. This implies it missed in the ITLB (Instruction TLB) and further= levels of TLB.", + "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "itlb_2nd_level_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total n= umber of completed instructions. This implies it missed in the Instruction = Translation Lookaside Buffer (ITLB) and further levels of TLB.", + "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY= ", + "MetricGroup": "", + "MetricName": "itlb_2nd_level_large_page_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = all page sizes) caused by demand data loads to the total number of complete= d instructions. This implies it missed in the DTLB and further levels of TL= B.", + "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "dtlb_2nd_level_load_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = 2 megabyte page sizes) caused by demand data loads to the total number of c= ompleted instructions. This implies it missed in the Data Translation Looka= side Buffer (DTLB) and further levels of TLB.", + "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRE= D.ANY", + "MetricGroup": "", + "MetricName": "dtlb_2nd_level_2mb_large_page_load_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = all page sizes) caused by demand data stores to the total number of complet= ed instructions. This implies it missed in the DTLB and further levels of T= LB.", + "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY= ", + "MetricGroup": "", + "MetricName": "dtlb_2nd_level_store_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Memory read that miss the last level cache (L= LC) addressed to local DRAM as a percentage of total memory read accesses, = does not include LLC prefetches.", + "MetricExpr": "100 * cha@unc_cha_tor_inserts.ia_miss\\,config1\\= =3D0x4043200000000@ / ( cha@unc_cha_tor_inserts.ia_miss\\,config1\\=3D0x404= 3200000000@ + cha@unc_cha_tor_inserts.ia_miss\\,config1\\=3D0x4043100000000= @ )", + "MetricGroup": "", + "MetricName": "numa_percent_reads_addressed_to_local_dram", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Memory reads that miss the last level cache (= LLC) addressed to remote DRAM as a percentage of total memory read accesses= , does not include LLC prefetches.", + "MetricExpr": "100 * cha@unc_cha_tor_inserts.ia_miss\\,config1\\= =3D0x4043100000000@ / ( cha@unc_cha_tor_inserts.ia_miss\\,config1\\=3D0x404= 3200000000@ + cha@unc_cha_tor_inserts.ia_miss\\,config1\\=3D0x4043100000000= @ )", + "MetricGroup": "", + "MetricName": "numa_percent_reads_addressed_to_remote_dram", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Uncore operating frequency in GHz", + "MetricExpr": "( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_CLOCK= TICKS) * #num_packages ) / 1000000000) / duration_time", + "MetricGroup": "", + "MetricName": "uncore_frequency", + "ScaleUnit": "1GHz" + }, + { + "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data t= ransmit bandwidth (MB/sec)", + "MetricExpr": "( UNC_UPI_TxL_FLITS.ALL_DATA * (64 / 9.0) / 1000000= ) / duration_time", + "MetricGroup": "", + "MetricName": "upi_data_transmit_bw_only_data", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "DDR memory read bandwidth (MB/sec)", + "MetricExpr": "( UNC_M_CAS_COUNT.RD * 64 / 1000000) / duration_tim= e", + "MetricGroup": "", + "MetricName": "memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "DDR memory write bandwidth (MB/sec)", + "MetricExpr": "( UNC_M_CAS_COUNT.WR * 64 / 1000000) / duration_tim= e", + "MetricGroup": "", + "MetricName": "memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "DDR memory bandwidth (MB/sec)", + "MetricExpr": "(( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) * 64 /= 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "memory_bandwidth_total", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO reads that are initiated by e= nd device controllers that are requesting memory from the CPU.", + "MetricExpr": "(( UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO= _DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 ) * 4 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "io_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO writes that are initiated by = end device controllers that are writing memory to the CPU.", + "MetricExpr": "(( UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0 + UNC_I= IO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PA= RT2 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3 ) * 4 / 1000000) / duration_= time", + "MetricGroup": "", + "MetricName": "io_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Uops delivered from decoded instruction cache= (decoded stream buffer or DSB) as a percent of total uops delivered to Ins= truction Decode Queue", + "MetricExpr": "100 * ( IDQ.DSB_UOPS / UOPS_ISSUED.ANY )", + "MetricGroup": "", + "MetricName": "percent_uops_delivered_from_decoded_icache_dsb", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Uops delivered from legacy decode pipeline (M= icro-instruction Translation Engine or MITE) as a percent of total uops del= ivered to Instruction Decode Queue", + "MetricExpr": "100 * ( IDQ.MITE_UOPS / UOPS_ISSUED.ANY )", + "MetricGroup": "", + "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline_= mite", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Uops delivered from microcode sequencer (MS) = as a percent of total uops delivered to Instruction Decode Queue", + "MetricExpr": "100 * ( IDQ.MS_UOPS / UOPS_ISSUED.ANY )", + "MetricGroup": "", + "MetricName": "percent_uops_delivered_from_microcode_sequencer_ms", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Bandwidth (MB/sec) of read requests that miss= the last level cache (LLC) and go to local memory.", + "MetricExpr": "( UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1000000) / du= ration_time", + "MetricGroup": "", + "MetricName": "llc_miss_local_memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth (MB/sec) of write requests that mis= s the last level cache (LLC) and go to local memory.", + "MetricExpr": "( UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1000000) / d= uration_time", + "MetricGroup": "", + "MetricName": "llc_miss_local_memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth (MB/sec) of read requests that miss= the last level cache (LLC) and go to remote memory.", + "MetricExpr": "( UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1000000) / d= uration_time", + "MetricGroup": "", + "MetricName": "llc_miss_remote_memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend. Frontend denotes th= e first part of the processor core responsible to fetch operations that are= executed later on by the Backend part. Within the Frontend; a branch predi= ctor predicts the next address to fetch; cache-lines are fetched from the m= emory subsystem; parsed into instructions; and lastly decoded into micro-op= erations (uops). Ideally the Frontend can issue Machine_Width uops every cy= cle to the Backend. Frontend Bound denotes unutilized issue-slots when ther= e is no Backend stall; i.e. bubbles where Frontend delivered no uops while = Backend could have accepted them. For example; stalls due to instruction-ca= che misses would be categorized under Frontend Bound.", + "MetricExpr": "100 * ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( (= CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREA= D ) ) ) )", + "MetricGroup": "TmaL1;PGO", + "MetricName": "tma_frontend_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = CPU was stalled due to Frontend latency issues. For example; instruction-c= ache misses; iTLB misses or fetch stalls after a branch misprediction are c= ategorized under Frontend Latency. In such cases; the Frontend eventually d= elivers no uops for some period.", + "MetricExpr": "100 * ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOP= S_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on e= lse ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricGroup": "Frontend;TmaL2;m_tma_frontend_bound_percent", + "MetricName": "tma_fetch_latency_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to instruction cache misses.", + "MetricExpr": "100 * ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_= 16B.IFDATA_STALL\\,cmask\\=3D0x1\\,edge\\=3D0x1@ ) / ( CPU_CLK_UNHALTED.THR= EAD ) )", + "MetricGroup": "BigFoot;FetchLat;IcMiss;TmaL3;m_tma_fetch_latency_= percent", + "MetricName": "tma_icache_misses_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Instruction TLB (ITLB) misses.", + "MetricExpr": "100 * ( ICACHE_64B.IFTAG_STALL / ( CPU_CLK_UNHALTED= .THREAD ) )", + "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TmaL3;m_tma_fetch_laten= cy_percent", + "MetricName": "tma_itlb_misses_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Branch Resteers. Branch Resteers estimates the Fron= tend delay in fetching operations from corrected path; following all sorts = of miss-predicted branches. For example; branchy code with lots of miss-pre= dictions might get categorized under Branch Resteers. Note the value of thi= s node may overlap with its siblings.", + "MetricExpr": "100 * ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_U= NHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) )= ", + "MetricGroup": "FetchLat;TmaL3;m_tma_fetch_latency_percent", + "MetricName": "tma_branch_resteers_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decod= ed i-cache) is a Uop Cache where the front-end directly delivers Uops (micr= o operations) avoiding heavy x86 decoding. The DSB pipeline has shorter lat= ency and delivered higher bandwidth than the MITE (legacy instruction decod= e pipeline). Switching between the two pipelines can cause penalties hence = this metric measures the exposed penalty.", + "MetricExpr": "100 * ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CL= K_UNHALTED.THREAD ) )", + "MetricGroup": "DSBmiss;FetchLat;TmaL3;m_tma_fetch_latency_percent= ", + "MetricName": "tma_dsb_switches_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU= was stalled due to Length Changing Prefixes (LCPs). Using proper compiler = flags or Intel Compiler by default will certainly avoid this. #Link: Optimi= zation Guide about LCP BKMs.", + "MetricExpr": "100 * ( ILD_STALL.LCP / ( CPU_CLK_UNHALTED.THREAD )= )", + "MetricGroup": "FetchLat;TmaL3;m_tma_fetch_latency_percent", + "MetricName": "tma_lcp_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates the fraction of cycles = when the CPU was stalled due to switches of uop delivery to the Microcode S= equencer (MS). Commonly used instructions are optimized for delivery by the= DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certa= in operations cannot be handled natively by the execution pipeline; and mus= t be performed by microcode (small programs injected into the execution str= eam). Switching to the MS too often can negatively impact performance. The = MS is designated to deliver long uop flows required by CISC instructions li= ke CPUID; or uncommon conditions like Floating Point Assists when dealing w= ith Denormals.", + "MetricExpr": "100 * ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTE= D.THREAD ) )", + "MetricGroup": "FetchLat;MicroSeq;TmaL3;m_tma_fetch_latency_percen= t", + "MetricName": "tma_ms_switches_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = CPU was stalled due to Frontend bandwidth issues. For example; inefficienc= ies at the instruction decoders; or restrictions for caching in the DSB (de= coded uops cache) are categorized under Fetch Bandwidth. In such cases; the= Frontend typically delivers suboptimal amount of uops to the Backend.", + "MetricExpr": "100 * ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * (= ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THR= EAD ) ) ) ) - ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (= ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UN= HALTED.THREAD ) ) ) ) )", + "MetricGroup": "FetchBW;Frontend;TmaL2;m_tma_frontend_bound_percen= t", + "MetricName": "tma_fetch_bandwidth_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycle= s in which CPU was likely limited due to the MITE pipeline (the legacy deco= de pipeline). This pipeline is used for code that was not pre-cached in the= DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of= long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", + "MetricExpr": "100 * ( ( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MI= TE_CYCLES_4_UOPS ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else = ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", + "MetricGroup": "DSBmiss;FetchBW;TmaL3;m_tma_fetch_bandwidth_percen= t", + "MetricName": "tma_mite_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycle= s in which CPU was likely limited due to DSB (decoded uop cache) fetch pipe= line. For example; inefficient utilization of the DSB cache structure or b= ank conflict when reading from it; are categorized here.", + "MetricExpr": "100 * ( ( IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB= _CYCLES_4_UOPS ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( = CPU_CLK_UNHALTED.THREAD ) ) / 2 )", + "MetricGroup": "DSB;FetchBW;TmaL3;m_tma_fetch_bandwidth_percent", + "MetricName": "tma_dsb_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This category represents fraction of slots wa= sted due to incorrect speculations. This include slots used to issue uops t= hat do not eventually get retired and slots for which the issue-pipeline wa= s blocked due to recovery from earlier incorrect speculation. For example; = wasted work due to miss-predicted branches are categorized under Bad Specul= ation category. Incorrect data speculation followed by Memory Ordering Nuke= s is another example.", + "MetricExpr": "100 * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_S= LOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT= _MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 )= if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricGroup": "TmaL1", + "MetricName": "tma_bad_speculation_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Branch Misprediction. These slots are either wasted = by uops fetched from an incorrectly speculated program path; or stalls when= the out-of-order part of the machine needs to recover its state from a spe= culative path.", + "MetricExpr": "100 * ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_= RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( U= OPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 )= if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHAL= TED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricGroup": "BadSpec;BrMispredicts;TmaL2;m_tma_bad_speculation_= percent", + "MetricName": "tma_branch_mispredicts_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Machine Clears. These slots are either wasted by uop= s fetched prior to the clear; or stalls the out-of-order portion of the mac= hine needs to recover its state after the clear. For example; this can happ= en due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modify= ing-Code (SMC) nukes.", + "MetricExpr": "100 * ( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE= _SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else I= NT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2= ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.= ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * = ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.= RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( = ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNH= ALTED.THREAD ) ) ) ) ) )", + "MetricGroup": "BadSpec;MachineClears;TmaL2;m_tma_bad_speculation_= percent", + "MetricName": "tma_machine_clears_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend. Backend is the portion of the processor cor= e where the out-of-order scheduler dispatches ready uops into their respect= ive execution units; and once completed these uops get retired according to= program order. For example; stalls due to data-cache misses or stalls due = to the divider unit being overloaded are both categorized under Backend Bou= nd. Backend Bound is further divided into two main categories: Memory Bound= and Core Bound.", + "MetricExpr": "100 * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 )= * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED= .THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_= ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_= CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) )= ) )", + "MetricGroup": "TmaL1", + "MetricName": "tma_backend_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = Memory subsystem within the Backend was a bottleneck. Memory Bound estimat= es fraction of slots where pipeline is likely stalled due to demand load or= store instructions. This accounts mainly for (1) non-completed in-flight m= emory demand loads which coincides with execution units starvation; in addi= tion to (2) cases where stores could impose backpressure on the pipeline wh= en many of them get buffered at the same time (less common out of the two).= ", + "MetricExpr": "100 * ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACT= IVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_= PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALT= ED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE= _ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_U= OPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if= #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 )= * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY= _CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on el= se ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricGroup": "Backend;TmaL2;m_tma_backend_bound_percent", + "MetricName": "tma_memory_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was s= talled without loads missing the L1 data cache. The L1 data cache typicall= y has the shortest latency. However; in certain cases like loads blocked o= n older stores; a load might suffer due to high latency even though it is b= eing satisfied by the L1. Another example is loads who miss in the TLB. The= se cases are characterized by execution unit stalls; while some non-complet= ed demand load lives in the machine without having that demand load missing= the L1 cache.", + "MetricExpr": "100 * ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCL= E_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) )", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TmaL3;m_tma_memor= y_bound_percent", + "MetricName": "tma_l1_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was s= talled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 m= isses/L2 hits) can improve the latency and increase performance.", + "MetricExpr": "100 * ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_L= OAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) ) ) / ( ( MEM_LOAD_RETI= RED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS )= ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=3D0x1@ ) ) * ( ( CYCLE_ACTIVIT= Y.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.TH= READ ) ) )", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TmaL3;m_tma_memor= y_bound_percent", + "MetricName": "tma_l2_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was s= talled due to loads accesses to L3 cache or contended with a sibling Core. = Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and= increase performance.", + "MetricExpr": "100 * ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACT= IVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TmaL3;m_tma_memor= y_bound_percent", + "MetricName": "tma_l3_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was s= talled on accesses to external memory (DRAM) by loads. Better caching can i= mprove the latency and increase performance.", + "MetricExpr": "100 * ( min( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( = CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTI= VITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETI= RED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS )= ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( = MEM_LOAD_RETIRED.L1_MISS ) ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=3D0x= 1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS= ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( 1 ) ) )", + "MetricGroup": "MemoryBound;TmaL3mem;TmaL3;m_tma_memory_bound_perc= ent", + "MetricName": "tma_dram_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates how often CPU was stall= ed due to RFO store memory accesses; RFO store issue a read-for-ownership = request before the write. Even though store accesses do not typically stall= out-of-order CPUs; there are few cases where stores can lead to actual sta= lls. This metric will be flagged should RFO stores be a bottleneck.", + "MetricExpr": "100 * ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UN= HALTED.THREAD ) )", + "MetricGroup": "MemoryBound;TmaL3mem;TmaL3;m_tma_memory_bound_perc= ent", + "MetricName": "tma_store_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e Core non-memory issues were of a bottleneck. Shortage in hardware comput= e resources; or dependencies in software's instructions are both categorize= d under Core Bound. Hence it may indicate the machine ran out of an out-of-= order resource; certain execution units are overloaded or dependencies in p= rogram's data- or instruction-flow are limiting the performance (e.g. FP-ch= ained long-latency arithmetic operations).", + "MetricExpr": "100 * ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4= ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALT= ED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLE= S_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CP= U_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD )= ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES= ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS= _RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) i= f #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTI= L ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.COR= E / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_C= LK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOV= ERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 )= * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED= .THREAD ) ) ) ) ) )", + "MetricGroup": "Backend;TmaL2;Compute;m_tma_backend_bound_percent", + "MetricName": "tma_core_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles whe= re the Divider unit was active. Divide and square root instructions are per= formed by the Divider unit and can take considerably longer latency than in= teger or Floating Point addition; subtraction; or multiplication.", + "MetricExpr": "100 * ( ARITH.DIVIDER_ACTIVE / ( CPU_CLK_UNHALTED.T= HREAD ) )", + "MetricGroup": "TmaL3;m_tma_core_bound_percent", + "MetricName": "tma_divider_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles the = CPU performance was potentially limited due to Core computation issues (non= divider-related). Two distinct categories can be attributed into this met= ric: (1) heavy data-dependency among contiguous instructions would manifest= in this metric - such cases are often referred to as low Instruction Level= Parallelism (ILP). (2) Contention on some hardware execution unit other th= an Divider. For example; when there are too many multiply operations.", + "MetricExpr": "100 * ( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( EXE_AC= TIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_C= LK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) = ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARIT= H.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_ME= M_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS = ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_C= LK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALT= ED.THREAD ) )", + "MetricGroup": "PortsUtil;TmaL3;m_tma_core_bound_percent", + "MetricName": "tma_ports_utilization_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired. Ideally= ; all pipeline slots would be attributed to the Retiring category. Retirin= g of 100% would indicate the maximum Pipeline_Width throughput was achieved= . Maximizing Retiring typically increases the Instructions-per-cycle (see = IPC metric). Note that a high Retiring value does not necessary mean there = is no room for more performance. For example; Heavy-operations or Microcod= e Assists are categorized under Retiring. They often indicate suboptimal pe= rformance and can often be optimized or avoided. ", + "MetricExpr": "100 * ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * (= ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THR= EAD ) ) ) )", + "MetricGroup": "TmaL1", + "MetricName": "tma_retiring_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring light-weight operations -- instructions that require= no more than one uop (micro-operation). This correlates with total number = of instructions used by the program. A uops-per-instruction (see UPI metric= ) ratio of 1 or less should be expected for decently optimized software run= ning on Intel Core/Xeon products. While this often indicates efficient X86 = instructions were executed; high value does not necessarily mean better per= formance cannot be achieved.", + "MetricExpr": "100 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) *= ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.T= HREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSE= D - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if= #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricGroup": "Retire;TmaL2;m_tma_retiring_percent", + "MetricName": "tma_light_operations_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents overall arithmetic flo= ating-point (FP) operations fraction the CPU has executed (retired). Note t= his metric's value may exceed its parent due to use of \"Uops\" CountDomain= and FMA double-counting.", + "MetricExpr": "100 * ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 )= * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED= .THREAD ) ) ) ) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD ) + ( ( FP_ARITH= _INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) / ( UOP= S_RETIRED.RETIRE_SLOTS ) ) + ( min( ( ( FP_ARITH_INST_RETIRED.128B_PACKED_D= OUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.25= 6B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST= _RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / = ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1 ) ) ) )", + "MetricGroup": "HPC;TmaL3;m_tma_light_operations_percent", + "MetricName": "tma_fp_arith_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring memory operations -- uops for memory load or store a= ccesses.", + "MetricExpr": "100 * ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 )= * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED= .THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FU= SED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) = if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * MEM_INST_RETIRED.ANY = / INST_RETIRED.ANY )", + "MetricGroup": "Pipeline;TmaL3;m_tma_light_operations_percent", + "MetricName": "tma_memory_operations_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring fused instructions -- where one uop can represent mu= ltiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC= are commonly used examples.", + "MetricExpr": "100 * ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 )= * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED= .THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FU= SED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) = if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * UOPS_RETIRED.MACRO_FU= SED / ( UOPS_RETIRED.RETIRE_SLOTS ) )", + "MetricGroup": "Pipeline;TmaL3;m_tma_light_operations_percent", + "MetricName": "tma_fused_instructions_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring branch instructions that were not fused. Non-conditi= onal branches like direct JMP or CALL would count here. Can be used to exam= ine fusible conditional jumps that were not fused.", + "MetricExpr": "100 * ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 )= * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED= .THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FU= SED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) = if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( BR_INST_RETIRED.ALL= _BRANCHES - UOPS_RETIRED.MACRO_FUSED ) / ( UOPS_RETIRED.RETIRE_SLOTS ) )", + "MetricGroup": "Pipeline;TmaL3;m_tma_light_operations_percent", + "MetricName": "tma_non_fused_branches_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring NOP (no op) instructions. Compilers often use NOPs f= or certain address alignments - e.g. start address of a function or loop bo= dy.", + "MetricExpr": "100 * ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 )= * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED= .THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FU= SED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) = if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * INST_RETIRED.NOP / ( = UOPS_RETIRED.RETIRE_SLOTS ) )", + "MetricGroup": "Pipeline;TmaL3;m_tma_light_operations_percent", + "MetricName": "tma_nop_instructions_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents the remaining light uo= ps fraction the CPU has executed - remaining means not covered by other sib= ling nodes. May undercount due to FMA double counting", + "MetricExpr": "100 * ( max( 0 , ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) = / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK= _UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED= .MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_A= NY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) - ( ( ( ( ( UO= PS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 )= if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * UOPS_EXECUTED.X87 / UO= PS_EXECUTED.THREAD ) + ( ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_I= NST_RETIRED.SCALAR_DOUBLE ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) + ( min( ( ( = FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKE= D_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED= .256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_I= NST_RETIRED.512B_PACKED_SINGLE ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1 ) = ) ) ) + ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTE= D.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( = ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY= ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_= CLK_UNHALTED.THREAD ) ) ) ) ) * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY ) += ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREA= D_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_= RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( = ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNH= ALTED.THREAD ) ) ) ) ) * UOPS_RETIRED.MACRO_FUSED / ( UOPS_RETIRED.RETIRE_S= LOTS ) ) + ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHA= LTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - (= ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.= ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( C= PU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( BR_INST_RETIRED.ALL_BRANCHES - UOPS_RE= TIRED.MACRO_FUSED ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) + ( ( ( ( UOPS_RETIRE= D.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_= on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS= ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_= UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )= ) * INST_RETIRED.NOP / ( UOPS_RETIRED.RETIRE_SLOTS ) ) ) ) )", + "MetricGroup": "Pipeline;TmaL3;m_tma_light_operations_percent", + "MetricName": "tma_other_light_ops_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring heavy-weight operations -- instructions that require= two or more uops or microcoded sequences. This highly-correlates with the = uop length of these instructions/sequences.", + "MetricExpr": "100 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETI= RED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREA= D_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricGroup": "Retire;TmaL2;m_tma_retiring_percent", + "MetricName": "tma_heavy_operations_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring instructions that that are decoder into two or up to= ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of= uops in such instructions.", + "MetricExpr": "100 * ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RE= TIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THR= EAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOP= S_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( = CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD= ) ) ) ) )", + "MetricGroup": "TmaL3;m_tma_heavy_operations_percent", + "MetricName": "tma_few_uops_instructions_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS= is used for CISC instructions not supported by the default decoders (like = repeat move strings; or CPUID); or by microcode assists used to address som= e operation modes (like in Floating Point assists). These cases can often b= e avoided.", + "MetricExpr": "100 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSU= ED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if= #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricGroup": "MicroSeq;TmaL3;m_tma_heavy_operations_percent", + "MetricName": "tma_microcode_sequencer_percent", + "ScaleUnit": "1%" } ] diff --git a/tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json b/t= ools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json index 4dcbac887380..56709633c379 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json @@ -84,6 +84,15 @@ "UMask": "0x4", "Unit": "iMC" }, + { + "BriefDescription": "Pre-charge for writes", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_M_PRE_COUNT.WR", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, { "BriefDescription": "DRAM Page Activate commands sent due to a wri= te request", "Counter": "0,1,2,3", diff --git a/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json b/to= ols/perf/pmu-events/arch/x86/skylakex/uncore-other.json index aa0f67613c4a..abe2d068ea0c 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json @@ -155,6 +155,15 @@ "UMask": "0x04", "Unit": "CHA" }, + { + "BriefDescription": "write requests from remote home agent", + "Counter": "0,1,2,3", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, { "BriefDescription": "UPI interconnect send bandwidth for payload. = Derived from unc_upi_txl_flits.all_data", "Counter": "0,1,2,3", @@ -620,6 +629,576 @@ "UMask": "0x10", "Unit": "CHA" }, + { + "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hi= t the LLC", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", + "Filter": "config1=3D0x40233", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRds issued by iA Cores that H= it the LLC : Counts the number of entries successfully inserted into the TO= R that match qualifications specified by the subevent. Does not include a= ddressless requests such as locks and interrupts.", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hi= t the LLC", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD", + "Filter": "config1=3D0x40433", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores that H= it the LLC : Counts the number of entries successfully inserted into the TO= R that match qualifications specified by the subevent. Does not include a= ddressless requests such as locks and interrupts.", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD", + "Filter": "config1=3D0x4b233", + "PerPkg": "1", + "PublicDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD", + "Filter": "config1=3D0x4b433", + "PerPkg": "1", + "PublicDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores t= hat hit the LLC", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefRFO", + "Filter": "config1=3D0x4b033", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores = that hit the LLC : Counts the number of entries successfully inserted into = the TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hi= t the LLC", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", + "Filter": "config1=3D0x40033", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that H= it the LLC : Counts the number of entries successfully inserted into the TO= R that match qualifications specified by the subevent. Does not include a= ddressless requests such as locks and interrupts.", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Mi= ssed the LLC", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", + "Filter": "config1=3D0x40233", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRds issued by iA Cores that M= issed the LLC : Counts the number of entries successfully inserted into the= TOR that match qualifications specified by the subevent. Does not includ= e addressless requests such as locks and interrupts.", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Mi= ssed the LLC", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "Filter": "config1=3D0x40433", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores that M= issed the LLC : Counts the number of entries successfully inserted into the= TOR that match qualifications specified by the subevent. Does not includ= e addressless requests such as locks and interrupts.", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD", + "Filter": "config1=3D0x4b233", + "PerPkg": "1", + "PublicDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD", + "Filter": "config1=3D0x4b433", + "PerPkg": "1", + "PublicDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores t= hat missed the LLC", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefRFO", + "Filter": "config1=3D0x4b033", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores = that missed the LLC : Counts the number of entries successfully inserted in= to the TOR that match qualifications specified by the subevent. Does not = include addressless requests such as locks and interrupts.", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Mi= ssed the LLC", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", + "Filter": "config1=3D0x40033", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that M= issed the LLC : Counts the number of entries successfully inserted into the= TOR that match qualifications specified by the subevent. Does not includ= e addressless requests such as locks and interrupts.", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.REM_ALL", + "Filter": "CHAfilter1", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. ", + "UMask": "0x30", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", + "Filter": "config1=3D0x40233", + "PerPkg": "1", + "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", + "Filter": "config1=3D0x40433", + "PerPkg": "1", + "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD", + "Filter": "config1=3D0x4b233", + "PerPkg": "1", + "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD", + "Filter": "config1=3D0x4b433", + "PerPkg": "1", + "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO", + "Filter": "config1=3D0x4b033", + "PerPkg": "1", + "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", + "Filter": "config1=3D0x40033", + "PerPkg": "1", + "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", + "Filter": "config1=3D0x40233", + "PerPkg": "1", + "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "Filter": "config1=3D0x40433", + "PerPkg": "1", + "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD", + "Filter": "config1=3D0x4b233", + "PerPkg": "1", + "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD", + "Filter": "config1=3D0x4b433", + "PerPkg": "1", + "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO", + "Filter": "config1=3D0x4b033", + "PerPkg": "1", + "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", + "Filter": "config1=3D0x40033", + "PerPkg": "1", + "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CLOCKTICKS", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventName": "UNC_C_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_CLOCKTICKS", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_FAST_ASSERTED.HORZ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xA5", + "EventName": "UNC_C_FAST_ASSERTED", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_FAST_ASSERTED.HORZ", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_E", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.E_STATE", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_LLC_VICTIMS.TOTAL_E", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_F", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.F_STATE", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_LLC_VICTIMS.TOTAL_F", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_M", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.M_STATE", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_LLC_VICTIMS.TOTAL_M", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_S", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.S_STATE", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_LLC_VICTIMS.TOTAL_S", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.REM_ALL", + "Filter": "CHAfilter1", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. ", + "UMask": "0x30", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.CORE_GTONE", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.CORE_GTONE", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_CORE_SNP.CORE_GTONE", + "UMask": "0x42", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.EVICT_GTONE", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.EVICT_GTONE", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_CORE_SNP.EVICT_GTONE", + "UMask": "0x82", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_DIR_LOOKUP.NO_SNP", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x53", + "EventName": "UNC_H_DIR_LOOKUP.NO_SNP", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_DIR_LOOKUP.NO_SNP", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_DIR_LOOKUP.SNP", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x53", + "EventName": "UNC_H_DIR_LOOKUP.SNP", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_DIR_LOOKUP.SNP", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_DIR_UPDATE.HA", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x54", + "EventName": "UNC_H_DIR_UPDATE.HA", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_DIR_UPDATE.HA", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_DIR_UPDATE.TOR", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x54", + "EventName": "UNC_H_DIR_UPDATE.TOR", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_DIR_UPDATE.TOR", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_HIT.EX_RDS", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5F", + "EventName": "UNC_H_HITME_HIT.EX_RDS", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_HITME_HIT.EX_RDS", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_MISC.RFO_HIT_S", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x39", + "EventName": "UNC_H_MISC.RFO_HIT_S", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_MISC.RFO_HIT_S", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_REQUESTS.INVITOE_LOCAL", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_REQUESTS.INVITOE_LOCAL", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_REQUESTS.INVITOE_REMOTE", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_REQUESTS.INVITOE_REMOTE", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_REQUESTS.READS", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.READS", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_REQUESTS.READS", + "UMask": "0x3", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_REQUESTS.READS_LOCAL", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.READS_LOCAL", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_REQUESTS.READS_LOCAL", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_REQUESTS.WRITES", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.WRITES", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_REQUESTS.WRITES", + "UMask": "0xC", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_REQUESTS.WRITES_LOCAL", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.WRITES_LOCAL", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_REQUESTS.WRITES_LOCAL", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_INSERTS.IRQ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x13", + "EventName": "UNC_H_RxC_INSERTS.IRQ", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_RxC_INSERTS.IRQ", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x19", + "EventName": "UNC_H_RxC_IRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OCCUPANCY.IRQ", + "Deprecated": "1", + "EventCode": "0x11", + "EventName": "UNC_H_RxC_OCCUPANCY.IRQ", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_RxC_OCCUPANCY.IRQ", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSPCNFLCTS", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_SNOOP_RESP.RSPCNFLCTS", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSPIFWD", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSPIFWD", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_SNOOP_RESP.RSPIFWD", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSPSFWD", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSPSFWD", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_SNOOP_RESP.RSPSFWD", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSP_FWD_WB", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_SNOOP_RESP.RSP_FWD_WB", + "UMask": "0x20", + "Unit": "CHA" + }, { "BriefDescription": "Clockticks of the IIO Traffic Controller", "Counter": "0,1,2,3", @@ -1032,6 +1611,110 @@ "UMask": "0x02", "Unit": "IIO" }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "UMask": "0x1", + "Unit": "IIO" + }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by the CPU to IIO Part0", "Counter": "0,1,2,3", @@ -1708,12 +2391,12 @@ "Unit": "M2M" }, { - "BriefDescription": "Prefecth requests that got turn into a demand= request", + "BriefDescription": "Prefetch requests that got turn into a demand= request", "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2M_PREFCAM_DEMAND_PROMOTIONS", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) promote= s a outstanding request in the prefetch queue due to a subsequent demand re= ad request that entered the M2M with the same address. Explanatory Side No= te: The Prefecth queue is made of CAM (Content Addressable Memory)", + "PublicDescription": "Counts when the M2M (Mesh to Memory) promote= s a outstanding request in the prefetch queue due to a subsequent demand re= ad request that entered the M2M with the same address. Explanatory Side No= te: The Prefetch queue is made of CAM (Content Addressable Memory)", "Unit": "M2M" }, { @@ -1722,7 +2405,7 @@ "EventCode": "0x57", "EventName": "UNC_M2M_PREFCAM_INSERTS", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) recieve= s a prefetch request and inserts it into its outstanding prefetch queue. E= xplanatory Side Note: the prefect queue is made from CAM: Content Addressab= le Memory", + "PublicDescription": "Counts when the M2M (Mesh to Memory) receive= s a prefetch request and inserts it into its outstanding prefetch queue. E= xplanatory Side Note: the prefect queue is made from CAM: Content Addressab= le Memory", "Unit": "M2M" }, { @@ -1827,6 +2510,17 @@ "UMask": "0x1", "Unit": "UPI LL" }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_DIRECT_ATTEMPTS.D2U", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x12", + "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_UPI_DIRECT_ATTEMPTS.D2U", + "UMask": "0x2", + "Unit": "UPI LL" + }, { "BriefDescription": "Data Response packets that go direct to Intel= UPI", "Counter": "0,1,2,3", @@ -1861,7 +2555,7 @@ "EventCode": "0x31", "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0", "PerPkg": "1", - "PublicDescription": "Counts incoming FLITs (FLow control unITs) w= hich bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to t= he Egress. This is a latency optimization, and should generally be the com= mon case. If this value is less than the number of FLITs transfered, it im= plies that there was queueing getting onto the ring, and thus the transacti= ons saw higher latency.", + "PublicDescription": "Counts incoming FLITs (FLow control unITs) w= hich bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to t= he Egress. This is a latency optimization, and should generally be the com= mon case. If this value is less than the number of FLITs transferred, it i= mplies that there was queueing getting onto the ring, and thus the transact= ions saw higher latency.", "UMask": "0x1", "Unit": "UPI LL" }, @@ -1871,17 +2565,17 @@ "EventCode": "0x31", "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1", "PerPkg": "1", - "PublicDescription": "Counts incoming FLITs (FLow control unITs) w= hich bypassed the slot1 RxQ buffer (Receive Queue) and passed directly acr= oss the BGF and into the Egress. This is a latency optimization, and shoul= d generally be the common case. If this value is less than the number of F= LITs transfered, it implies that there was queueing getting onto the ring, = and thus the transactions saw higher latency.", + "PublicDescription": "Counts incoming FLITs (FLow control unITs) w= hich bypassed the slot1 RxQ buffer (Receive Queue) and passed directly acr= oss the BGF and into the Egress. This is a latency optimization, and shoul= d generally be the common case. If this value is less than the number of F= LITs transferred, it implies that there was queueing getting onto the ring,= and thus the transactions saw higher latency.", "UMask": "0x2", "Unit": "UPI LL" }, { - "BriefDescription": "FLITs received which bypassed the Slot0 Recie= ve Buffer", + "BriefDescription": "FLITs received which bypassed the Slot0 Recei= ve Buffer", "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2", "PerPkg": "1", - "PublicDescription": "Counts incoming FLITs (FLow control unITs) w= hcih bypassed the slot2 RxQ buffer (Receive Queue) and passed directly to = the Egress. This is a latency optimization, and should generally be the co= mmon case. If this value is less than the number of FLITs transfered, it i= mplies that there was queueing getting onto the ring, and thus the transact= ions saw higher latency.", + "PublicDescription": "Counts incoming FLITs (FLow control unITs) w= hich bypassed the slot2 RxQ buffer (Receive Queue) and passed directly to = the Egress. This is a latency optimization, and should generally be the co= mmon case. If this value is less than the number of FLITs transferred, it = implies that there was queueing getting onto the ring, and thus the transac= tions saw higher latency.", "UMask": "0x4", "Unit": "UPI LL" }, @@ -1915,6 +2609,17 @@ "UMask": "0x97", "Unit": "UPI LL" }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_FLITS.ALL_NULL", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.NULL", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_UPI_RxL_FLITS.ALL_NULL", + "UMask": "0x20", + "Unit": "UPI LL" + }, { "BriefDescription": "Cycles in which the Tx of the Intel Ultra Pat= h Interconnect (UPI) is in L0p power mode", "Counter": "0,1,2,3", @@ -1972,5 +2677,16 @@ "PublicDescription": "Counts protocol header and credit FLITs (80 = bit FLow control unITs) transmitted across any of the 3 UPI (Ultra Path Int= erconnect) slots on this UPI unit.", "UMask": "0x97", "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_FLITS.ALL_NULL", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.NULL", + "PerPkg": "1", + "PublicDescription": "This event is deprecated. Refer to new event= UNC_UPI_TxL_FLITS.ALL_NULL", + "UMask": "0x20", + "Unit": "UPI LL" } ] diff --git a/tools/perf/pmu-events/arch/x86/skylakex/virtual-memory.json b/= tools/perf/pmu-events/arch/x86/skylakex/virtual-memory.json index 792ca39f013a..dd334b416c57 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/virtual-memory.json @@ -281,4 +281,4 @@ "SampleAfterValue": "100007", "UMask": "0x20" } -] \ No newline at end of file +] --=20 2.37.1.359.gd136c6c3e2-goog From nobody Wed Apr 15 05:45:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D9E9C04A68 for ; Wed, 27 Jul 2022 22:13:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232517AbiG0WNr (ORCPT ); Wed, 27 Jul 2022 18:13:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54932 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236038AbiG0WMo (ORCPT ); Wed, 27 Jul 2022 18:12:44 -0400 Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE34D55BF for ; Wed, 27 Jul 2022 15:10:10 -0700 (PDT) Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-2eb7d137101so1031637b3.12 for ; Wed, 27 Jul 2022 15:10:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc:content-transfer-encoding; bh=HXKNEwyNrR8H/7U/Y7ARnXVtZIXdRwMKcmtQOIxYPMc=; b=nR3/3Aq/jmPTWTGQmVQ1sPsrutFwHULfwf9ovqR1TIyQ7FTwiYdnQ94C+l7mWFaQ0m PW9sepK+pIF9J/nDAYkudZYkS7Ledh+32aJqQRVcG3Am3NKK/7qVoiy7+tzDKDtN34OK cUecA4215y1rBuGYHrWxWJzVnHrQQDTBhMEd4OboaCfH4eYidL3rEiOo2dKNjaWFBX22 HZpD3zB+SF6yHafGx9bwGX3Lc6DYYJlD/PQ5aBoFtlEt8Ykmu7A1cY3vRWCTlGYMWTQI VOT4i2eY1LUV0J8pB+Re074okMqQzeg8yFs3NIxLDpPbW3HFL3xPsr79DYyNmKywIVO0 rxfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc:content-transfer-encoding; bh=HXKNEwyNrR8H/7U/Y7ARnXVtZIXdRwMKcmtQOIxYPMc=; b=TIldMJNJeS4/jhom1PjgfVYnGhWVvhfXBYDFlBipkFQKPxQ0ZCeIYIZyUK3APdXFQy VtGQVC944TAziYYApwjcjVjRMm2T+awMaCZnqEf2KHrfNAOG9RhF2RmAn1Bkn8UQshB5 Ih1zd0W6AryrINY/daWxvfvx8cLz/DY/P4QNnUuXe6gLvmO8w4RLMohBKAXwfP9+k5Vz aDNsbB1W3s8UNxr5qLY0Aq5em9QBTvspaKKHxbLOyC/HXx0e15nkqmm03DpDENKfcjir dwr+pYCPLRZtsGOLtJqQeN+qjYhED7Bu3HOAi3OKBEp6U7BKX0fuEDyuhJvQ4HMHT0x5 H/tg== X-Gm-Message-State: AJIora8U7EO8hFgUI91lof0M/LfFI/oblaFPaR3EJ30sCZlJMHqxqTNZ 1MvVbVFqzSNNDU1AAnfUmA7weMzP++c8 X-Google-Smtp-Source: AGRyM1t4cgorxMC9ohtNVK0akNen+jfZZGTm6+8c7EGHX/E8ueOjQdzSzLQb+csDUqHEGCNdTQVXthaqOEBm X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:882a:af57:8cb6:6f9e]) (user=irogers job=sendgmr) by 2002:a25:c545:0:b0:671:6b97:aeb5 with SMTP id v66-20020a25c545000000b006716b97aeb5mr10390183ybe.199.1658959793945; Wed, 27 Jul 2022 15:09:53 -0700 (PDT) Date: Wed, 27 Jul 2022 15:08:28 -0700 In-Reply-To: <20220727220832.2865794-1-irogers@google.com> Message-Id: <20220727220832.2865794-27-irogers@google.com> Mime-Version: 1.0 References: <20220727220832.2865794-1-irogers@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH v3 26/30] perf vendor events: Update Intel tigerlake From: Ian Rogers To: perry.taylor@intel.com, caleb.biggers@intel.com, kshipra.bopardikar@intel.com, Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Sedat Dilek Cc: Stephane Eranian , Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Update to v1.07, the metrics are based on TMA 4.4 full. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/downloa= d_and_gen.py to download and generate the latest events and metrics. Manually copy the tigerlake files into perf and update mapfile.csv. Tested on a non-tigerlake with 'perf test': 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok Signed-off-by: Ian Rogers --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- .../pmu-events/arch/x86/tigerlake/cache.json | 48 ++- .../arch/x86/tigerlake/floating-point.json | 2 +- .../arch/x86/tigerlake/frontend.json | 2 +- .../pmu-events/arch/x86/tigerlake/memory.json | 2 +- .../pmu-events/arch/x86/tigerlake/other.json | 1 - .../arch/x86/tigerlake/pipeline.json | 4 +- .../arch/x86/tigerlake/tgl-metrics.json | 378 +++++++++++++++--- .../arch/x86/tigerlake/uncore-other.json | 65 +++ .../arch/x86/tigerlake/virtual-memory.json | 2 +- 10 files changed, 439 insertions(+), 67 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.j= son diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 14b1707cf8ab..b660d3528b7d 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -24,10 +24,10 @@ GenuineIntel-6-8F,v1.04,sapphirerapids,core GenuineIntel-6-(37|4C|4D),v14,silvermont,core GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v53,skylake,core GenuineIntel-6-55-[01234],v1.28,skylakex,core +GenuineIntel-6-8[CD],v1.07,tigerlake,core GenuineIntel-6-2C,v2,westmereep-dp,core GenuineIntel-6-25,v2,westmereep-sp,core GenuineIntel-6-2F,v2,westmereex,core -GenuineIntel-6-8[CD],v1,tigerlake,core GenuineIntel-6-86,v1,snowridgex,core AuthenticAMD-23-([12][0-9A-F]|[0-9A-F]),v2,amdzen1,core AuthenticAMD-23-[[:xdigit:]]+,v1,amdzen2,core diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/cache.json b/tools/pe= rf/pmu-events/arch/x86/tigerlake/cache.json index 0569b2c704ca..5ccf0edc29ac 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/cache.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/cache.json @@ -112,6 +112,17 @@ "SampleAfterValue": "200003", "UMask": "0xe4" }, + { + "BriefDescription": "Demand Data Read access L2 cache", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts Demand Data Read requests accessing t= he L2 cache. These requests may hit or miss L2 cache. True-miss exclude mis= ses that were merged with ongoing L2 misses. An access is counted once.", + "SampleAfterValue": "200003", + "UMask": "0xe1" + }, { "BriefDescription": "RFO requests to L2 cache", "CollectPEBSRecord": "2", @@ -157,16 +168,38 @@ "UMask": "0xc1" }, { - "BriefDescription": "All requests that miss L2 cache", + "BriefDescription": "Demand Data Read miss L2 cache", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand Data Read requests with true-m= iss in the L2 cache. True-miss excludes misses that were merged with ongoin= g L2 misses. An access is counted once.", + "SampleAfterValue": "200003", + "UMask": "0x21" + }, + { + "BriefDescription": "Read requests with true-miss in L2 cache", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts all requests that miss L2 cache.", + "PublicDescription": "Counts read requests of any type with true-m= iss in the L2 cache. True-miss excludes L2 misses that were merged with ong= oing L2 misses.", "SampleAfterValue": "200003", "UMask": "0x3f" }, + { + "BriefDescription": "All accesses to L2 cache", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.REFERENCES", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts all requests that were hit or true mi= sses in L2 cache. True-miss excludes misses that were merged with ongoing L= 2 misses.", + "SampleAfterValue": "200003", + "UMask": "0xff" + }, { "BriefDescription": "RFO requests that hit L2 cache", "CollectPEBSRecord": "2", @@ -353,7 +386,7 @@ "UMask": "0x12" }, { - "BriefDescription": "TBD", + "BriefDescription": "Snoop hit a modified(HITM) or clean line(HIT_= W_FWD) in another on-pkg core which forwarded the data back due to a retire= d load instruction.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", @@ -361,6 +394,7 @@ "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", "PEBS": "1", "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts retired load instructions where a cro= ss-core snoop hit in another cores caches on this socket, the data was forw= arded back to the requesting core as the data was modified (SNOOP_HITM) or = the L3 did not have the data(SNOOP_HIT_WITH_FWD).", "SampleAfterValue": "20011", "UMask": "0x4" }, @@ -391,7 +425,7 @@ "UMask": "0x8" }, { - "BriefDescription": "TBD", + "BriefDescription": "Snoop hit without forwarding in another on-pk= g core due to a retired load instruction, data was supplied by the L3.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", @@ -399,6 +433,7 @@ "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", "PEBS": "1", "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts retired load instructions in which th= e L3 supplied the data and a cross-core snoop hit in another cores caches o= n this socket but that other core did not forward the data back (SNOOP_HIT_= NO_FWD).", "SampleAfterValue": "20011", "UMask": "0x2" }, @@ -503,7 +538,6 @@ "MSRValue": "0x10003C0001", "Offcore": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -517,7 +551,6 @@ "MSRValue": "0x8003C0001", "Offcore": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -531,7 +564,6 @@ "MSRValue": "0x10003C0002", "Offcore": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -714,4 +746,4 @@ "SampleAfterValue": "100003", "UMask": "0x4" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/floating-point.json b= /tools/perf/pmu-events/arch/x86/tigerlake/floating-point.json index de8eb2b34a3a..978b494c7458 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/floating-point.json @@ -98,4 +98,4 @@ "SampleAfterValue": "100003", "UMask": "0x2" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/frontend.json b/tools= /perf/pmu-events/arch/x86/tigerlake/frontend.json index 2eaa33cc574e..ccdd8fd99556 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/frontend.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/frontend.json @@ -475,4 +475,4 @@ "SampleAfterValue": "1000003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/memory.json b/tools/p= erf/pmu-events/arch/x86/tigerlake/memory.json index 0948de0b160c..6071794cbd32 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/memory.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/memory.json @@ -292,4 +292,4 @@ "SampleAfterValue": "100003", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/other.json b/tools/pe= rf/pmu-events/arch/x86/tigerlake/other.json index 65539490e18f..3ed22dbd0982 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/other.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/other.json @@ -42,7 +42,6 @@ "MSRValue": "0x10800", "Offcore": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" } diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json b/tools= /perf/pmu-events/arch/x86/tigerlake/pipeline.json index a8aa1b455c77..1f273144f8e8 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json @@ -432,13 +432,13 @@ "UMask": "0x40" }, { - "BriefDescription": "Cycles where no uops were executed, the Reser= vation Station was not empty, the Store Buffer was full and there was no ou= tstanding load.", + "BriefDescription": "Cycles no uop executed while RS was not empty= , the SB was not full and there was no outstanding load.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles during which no uops were exec= uted on all ports and Reservation Station (RS) was not empty.", + "PublicDescription": "Number of cycles total of 0 uops executed on= all ports, Reservation Station (RS) was not empty, the Store Buffer (SB) w= as not full and there was no outstanding load.", "SampleAfterValue": "1000003", "UMask": "0x80" }, diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json b/to= ols/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json index 00a16f1a0f44..03c97bd74ad9 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json @@ -1,20 +1,26 @@ [ + { + "BriefDescription": "Total pipeline cost of branch related instruc= tions (used for program control-flow including function calls)", + "MetricExpr": "100 * (( BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED= .NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 *= BR_INST_RETIRED.NEAR_CALL) ) / TOPDOWN.SLOTS)", + "MetricGroup": "Ret", + "MetricName": "Branching_Overhead" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch rela= ted bottlenecks by large code footprint programs (i-side cache; TLB and BTB= misses)", + "MetricExpr": "100 * (( 5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_D= ELIV.CORE - INT_MISC.UOP_DROPPING ) / TOPDOWN.SLOTS) * ( (ICACHE_64B.IFTAG_= STALL / CPU_CLK_UNHALTED.THREAD) + (ICACHE_16B.IFDATA_STALL / CPU_CLK_UNHAL= TED.THREAD) + (10 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(( 5 * IDQ= _UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / TO= PDOWN.SLOTS)", + "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB", + "MetricName": "Big_Code" + }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor= )", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "MetricGroup": "Ret;Summary", "MetricName": "IPC" }, - { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;FetchBW;PGO", - "MetricName": "IpTB" - }, { "BriefDescription": "Cycles Per Instruction (per Logical Processor= )", - "MetricExpr": "1 / IPC", - "MetricGroup": "Pipeline", + "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "Pipeline;Mem", "MetricName": "CPI" }, { @@ -24,28 +30,48 @@ "MetricName": "CLKS" }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.DISTRIBUTED", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core= till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "TOPDOWN.SLOTS", + "MetricGroup": "TmaL1", + "MetricName": "SLOTS" + }, + { + "BriefDescription": "Fraction of Physical Core issue-slots utilize= d by this Logical Processor", + "MetricExpr": "TOPDOWN.SLOTS / ( TOPDOWN.SLOTS / 2 ) if #SMT_on el= se 1", "MetricGroup": "SMT;TmaL1", + "MetricName": "Slots_Utilization" + }, + { + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "Execute_per_Issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio= > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate o= f \"execute\" at rename stage." + }, + { + "BriefDescription": "Instructions Per Cycle across hyper-threads (= per physical core)", + "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.DISTRIBUTED", + "MetricGroup": "Ret;SMT;TmaL1", "MetricName": "CoreIPC" }, { "BriefDescription": "Floating Point Operations Per Cycle", "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_AR= ITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DO= UBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIR= ED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + = FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512= B_PACKED_SINGLE ) / CPU_CLK_UNHALTED.DISTRIBUTED", - "MetricGroup": "Flops", + "MetricGroup": "Ret;Flops", "MetricName": "FLOPc" }, { - "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is at least 1 uop executed)", - "MetricExpr": "UOPS_EXECUTED.THREAD / ( UOPS_EXECUTED.CORE_CYCLES_= GE_1 / 2 )", - "MetricGroup": "Pipeline;PortsUtil", - "MetricName": "ILP" + "BriefDescription": "Actual per-core usage of the Floating Point n= on-X87 execution units (regardless of precision or vector-width)", + "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_I= NST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP= _ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_= DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.5= 12B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) ) / ( 2 * CPU= _CLK_UNHALTED.DISTRIBUTED )", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "FP_Arith_Utilization", + "PublicDescription": "Actual per-core usage of the Floating Point = non-X87 execution units (regardless of precision or vector-width). Values >= 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; = [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less commo= n)." }, { - "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear)", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "BrMispredicts", - "MetricName": "IpMispredict" + "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per-core", + "MetricExpr": "UOPS_EXECUTED.THREAD / (( UOPS_EXECUTED.CORE_CYCLES= _GE_1 / 2 ) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", + "MetricName": "ILP" }, { "BriefDescription": "Core actual clocks when any Logical Processor= is active on the Physical Core", @@ -68,99 +94,279 @@ { "BriefDescription": "Instructions per Branch (lower number means h= igher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;InsType", + "MetricGroup": "Branches;Fed;InsType", "MetricName": "IpBranch" }, { "BriefDescription": "Instructions per (near) call (lower number me= ans higher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches", + "MetricGroup": "Branches;Fed;PGO", "MetricName": "IpCall" }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", + "MetricName": "IpTB" + }, { "BriefDescription": "Branch instructions per taken branch. ", "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR= _TAKEN", - "MetricGroup": "Branches;PGO", + "MetricGroup": "Branches;Fed;PGO", "MetricName": "BpTkBranch" }, { "BriefDescription": "Instructions per Floating Point (FP) Operatio= n (lower number means higher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SC= ALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RET= IRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + = FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.25= 6B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARI= TH_INST_RETIRED.512B_PACKED_SINGLE )", - "MetricGroup": "Flops;FpArith;InsType", + "MetricGroup": "Flops;InsType", "MetricName": "IpFLOP" }, + { + "BriefDescription": "Instructions per FP Arithmetic instruction (l= ower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( (FP_ARITH_INST_RETIRED.SCALAR_= SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B= _PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_R= ETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_A= RITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SI= NGLE) )", + "MetricGroup": "Flops;InsType", + "MetricName": "IpArith", + "PublicDescription": "Instructions per FP Arithmetic instruction (= lower number means higher occurrence rate). May undercount due to FMA doubl= e counting. Approximated prior to BDW." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-= Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SIN= GLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_SP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Single= -Precision instruction (lower number means higher occurrence rate). May und= ercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-= Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOU= BLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_DP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Double= -Precision instruction (lower number means higher occurrence rate). May und= ercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bi= t instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PAC= KED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX128", + "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-b= it instruction (lower number means higher occurrence rate). May undercount = due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit i= nstruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PAC= KED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX256", + "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit = instruction (lower number means higher occurrence rate). May undercount due= to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit in= struction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.512B_PAC= KED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX512", + "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit i= nstruction (lower number means higher occurrence rate). May undercount due = to FMA double counting." + }, + { + "BriefDescription": "Instructions per Software prefetch instructio= n (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrenc= e rate)", + "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umas= k\\=3D0xF@", + "MetricGroup": "Prefetches", + "MetricName": "IpSWPF" + }, { "BriefDescription": "Total number of retired Instructions, Sample = with: INST_RETIRED.PREC_DIST", "MetricExpr": "INST_RETIRED.ANY", "MetricGroup": "Summary;TmaL1", "MetricName": "Instructions" }, + { + "BriefDescription": "", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,c= mask\\=3D1@", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", + "MetricName": "Execute" + }, + { + "BriefDescription": "Average number of Uops issued by front-end wh= en it issued something", + "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=3D1= @", + "MetricGroup": "Fed;FetchBW", + "MetricName": "Fetch_UpC" + }, { "BriefDescription": "Fraction of Uops delivered by the LSD (Loop S= tream Detector; aka Loop Cache)", "MetricExpr": "LSD.UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS= + IDQ.MS_UOPS)", - "MetricGroup": "LSD", + "MetricGroup": "Fed;LSD", "MetricName": "LSD_Coverage" }, { "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_= UOPS + IDQ.MS_UOPS)", - "MetricGroup": "DSB;FetchBW", + "MetricGroup": "DSB;Fed;FetchBW", "MetricName": "DSB_Coverage" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand loads (in core cycles)", + "BriefDescription": "Average number of cycles of a switch from the= DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details= .", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu@DSB2MITE_SWI= TCHES.PENALTY_CYCLES\\,cmask\\=3D1\\,edge@", + "MetricGroup": "DSBmiss", + "MetricName": "DSB_Switch_Cost" + }, + { + "BriefDescription": "Number of Instructions per non-speculative DS= B miss (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", + "MetricGroup": "DSBmiss;Fed", + "MetricName": "IpDSB_Miss_Ret" + }, + { + "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "IpMispredict" + }, + { + "BriefDescription": "Fraction of branches that are non-taken condi= tionals", + "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_B= RANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "Cond_NT" + }, + { + "BriefDescription": "Fraction of branches that are taken condition= als", + "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BR= ANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "Cond_TK" + }, + { + "BriefDescription": "Fraction of branches that are CALL or RET", + "MetricExpr": "( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_= RETURN ) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "CallRet" + }, + { + "BriefDescription": "Fraction of branches that are unconditional (= direct or indirect) jumps", + "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_= TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "Jump" + }, + { + "BriefDescription": "Fraction of branches of other types (not indi= vidually covered by other metrics in Info.Branches group)", + "MetricExpr": "1 - ( (BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRE= D.ALL_BRANCHES) + (BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHE= S) + (( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN ) / BR_INST= _RETIRED.ALL_BRANCHES) + ((BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.CON= D_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES) )", + "MetricGroup": "Bad;Branches", + "MetricName": "Other_Branches" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load operations (in core cycles)", "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS = + MEM_LOAD_RETIRED.FB_HIT )", - "MetricGroup": "MemoryBound;MemoryLat", + "MetricGroup": "Mem;MemoryBound;MemoryLat", "MetricName": "Load_Miss_Real_Latency" }, { "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLE= S", - "MetricGroup": "MemoryBound;MemoryBW", + "MetricGroup": "Mem;MemoryBound;MemoryBW", "MetricName": "MLP" }, + { + "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L1MPKI" + }, + { + "BriefDescription": "L1 cache true misses per kilo instruction for= all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.A= NY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L1MPKI_Load" + }, + { + "BriefDescription": "L2 cache true misses per kilo instruction for= retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;Backend;CacheMisses", + "MetricName": "L2MPKI" + }, + { + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instru= ction for all request types (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses;Offcore", + "MetricName": "L2MPKI_All" + }, + { + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instru= ction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.= ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2MPKI_Load" + }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all re= quest types (including speculative)", + "MetricExpr": "1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / IN= ST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2HPKI_All" + }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all de= mand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.A= NY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2HPKI_Load" + }, + { + "BriefDescription": "L3 cache true misses per kilo instruction for= retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L3MPKI" + }, + { + "BriefDescription": "Fill Buffer (FB) hits per kilo instructions f= or retired demand loads (L1D misses that merge into ongoing miss-handling e= ntries)", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "FB_HPKI" + }, { "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", "MetricConstraint": "NO_NMI_WATCHDOG", - "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_= PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 2 * CORE_CLKS )", - "MetricGroup": "MemoryTLB", + "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_= PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 2 * CPU_CLK_UNHALTED.DISTRIB= UTED )", + "MetricGroup": "Mem;MemoryTLB", "MetricName": "Page_Walks_Utilization" }, { - "BriefDescription": "Average data fill bandwidth to the L1 data ca= che [GB / sec]", + "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", - "MetricGroup": "MemoryBW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L1D_Cache_Fill_BW" }, { - "BriefDescription": "Average data fill bandwidth to the L2 cache [= GB / sec]", + "BriefDescription": "Average per-core data fill bandwidth to the L= 2 cache [GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", - "MetricGroup": "MemoryBW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L2_Cache_Fill_BW" }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L3_Cache_Fill_BW" + }, { "BriefDescription": "Average per-core data access bandwidth to the= L3 cache [GB / sec]", "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / d= uration_time", - "MetricGroup": "MemoryBW;Offcore", + "MetricGroup": "Mem;MemoryBW;Offcore", "MetricName": "L3_Cache_Access_BW" }, { - "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", - "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses", - "MetricName": "L1MPKI" + "BriefDescription": "Average per-thread data fill bandwidth to the= L1 data cache [GB / sec]", + "MetricExpr": "(64 * L1D.REPLACEMENT / 1000000000 / duration_time)= ", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L1D_Cache_Fill_BW_1T" }, { - "BriefDescription": "L2 cache true misses per kilo instruction for= retired demand loads", - "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses", - "MetricName": "L2MPKI" + "BriefDescription": "Average per-thread data fill bandwidth to the= L2 cache [GB / sec]", + "MetricExpr": "(64 * L2_LINES_IN.ALL / 1000000000 / duration_time)= ", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L2_Cache_Fill_BW_1T" }, { - "BriefDescription": "L3 cache true misses per kilo instruction for= retired demand loads", - "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses", - "MetricName": "L3MPKI" + "BriefDescription": "Average per-thread data fill bandwidth to the= L3 cache [GB / sec]", + "MetricExpr": "(64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duratio= n_time)", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L3_Cache_Fill_BW_1T" + }, + { + "BriefDescription": "Average per-thread data access bandwidth to t= he L3 cache [GB / sec]", + "MetricExpr": "(64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / = duration_time)", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "L3_Cache_Access_BW_1T" }, { "BriefDescription": "Average CPU Utilization", @@ -177,8 +383,9 @@ { "BriefDescription": "Giga Floating Point Operations Per Second", "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_= ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_= DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RET= IRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE = + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.5= 12B_PACKED_SINGLE ) / 1000000000 ) / duration_time", - "MetricGroup": "Flops;HPC", - "MetricName": "GFLOPs" + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "GFLOPs", + "PublicDescription": "Giga Floating Point Operations Per Second. A= ggregate across all supported options of: FP precisions, scalar and vector = instructions, vector-width and AMX engine." }, { "BriefDescription": "Average Frequency Utilization relative nomina= l frequency", @@ -186,9 +393,30 @@ "MetricGroup": "Power", "MetricName": "Turbo_Utilization" }, + { + "BriefDescription": "Fraction of Core cycles where the core was ru= nning with power-delivery for baseline license level 0", + "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / CPU_CLK_UNHALTED.DI= STRIBUTED", + "MetricGroup": "Power", + "MetricName": "Power_License0_Utilization", + "PublicDescription": "Fraction of Core cycles where the core was r= unning with power-delivery for baseline license level 0. This includes non= -AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes." + }, + { + "BriefDescription": "Fraction of Core cycles where the core was ru= nning with power-delivery for license level 1", + "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / CPU_CLK_UNHALTED.DI= STRIBUTED", + "MetricGroup": "Power", + "MetricName": "Power_License1_Utilization", + "PublicDescription": "Fraction of Core cycles where the core was r= unning with power-delivery for license level 1. This includes high current= AVX 256-bit instructions as well as low current AVX 512-bit instructions." + }, + { + "BriefDescription": "Fraction of Core cycles where the core was ru= nning with power-delivery for license level 2 (introduced in SKX)", + "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / CPU_CLK_UNHALTED.DI= STRIBUTED", + "MetricGroup": "Power", + "MetricName": "Power_License2_Utilization", + "PublicDescription": "Fraction of Core cycles where the core was r= unning with power-delivery for license level 2 (introduced in SKX). This i= ncludes high current AVX 512-bit instructions." + }, { "BriefDescription": "Fraction of cycles where both hardware Logica= l Processors were active", - "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UN= HALTED.REF_DISTRIBUTED", + "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UN= HALTED.REF_DISTRIBUTED if #SMT_on else 0", "MetricGroup": "SMT", "MetricName": "SMT_2T_Utilization" }, @@ -198,6 +426,24 @@ "MetricGroup": "OS", "MetricName": "Kernel_Utilization" }, + { + "BriefDescription": "Cycles Per Instruction for the Operating Syst= em (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "Kernel_CPI" + }, + { + "BriefDescription": "Average external Memory Bandwidth Use for rea= ds and writes [GB / sec]", + "MetricExpr": "64 * ( arb@event\\=3D0x81\\,umask\\=3D0x1@ + arb@ev= ent\\=3D0x84\\,umask\\=3D0x1@ ) / 1000000 / duration_time / 1000", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", + "MetricName": "DRAM_BW_Use" + }, + { + "BriefDescription": "Average number of parallel requests to extern= al memory. Accounts for all requests", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=3D0x81\\,um= ask\\=3D0x1@", + "MetricGroup": "Mem;SoC", + "MetricName": "MEM_Parallel_Requests" + }, { "BriefDescription": "Instructions per Far Branch ( Far Branches ap= ply upon transition from application to operating system, handling interrup= ts, exceptions) [lower number means higher occurrence rate]", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", @@ -216,6 +462,18 @@ "MetricGroup": "Power", "MetricName": "C7_Core_Residency" }, + { + "BriefDescription": "C2 residency percent per package", + "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100", + "MetricGroup": "Power", + "MetricName": "C2_Pkg_Residency" + }, + { + "BriefDescription": "C3 residency percent per package", + "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100", + "MetricGroup": "Power", + "MetricName": "C3_Pkg_Residency" + }, { "BriefDescription": "C6 residency percent per package", "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100", @@ -227,5 +485,23 @@ "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C7_Pkg_Residency" + }, + { + "BriefDescription": "C8 residency percent per package", + "MetricExpr": "(cstate_pkg@c8\\-residency@ / msr@tsc@) * 100", + "MetricGroup": "Power", + "MetricName": "C8_Pkg_Residency" + }, + { + "BriefDescription": "C9 residency percent per package", + "MetricExpr": "(cstate_pkg@c9\\-residency@ / msr@tsc@) * 100", + "MetricGroup": "Power", + "MetricName": "C9_Pkg_Residency" + }, + { + "BriefDescription": "C10 residency percent per package", + "MetricExpr": "(cstate_pkg@c10\\-residency@ / msr@tsc@) * 100", + "MetricGroup": "Power", + "MetricName": "C10_Pkg_Residency" } ] diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json b/t= ools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json new file mode 100644 index 000000000000..734b1845c8e2 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json @@ -0,0 +1,65 @@ +[ + { + "BriefDescription": "Each cycle count number of all outgoing valid= entries in ReqTrk. Such entry is defined as valid from it's allocation in = ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", + "PerPkg": "1", + "PublicDescription": "UNC_ARB_TRK_OCCUPANCY.ALL", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Counts every read (RdCAS) issued by the Memor= y Controller to DRAM (sum of all channels). All requests result in 64 byte = data transfers from DRAM.", + "Counter": "1", + "CounterType": "FREERUN", + "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN", + "PerPkg": "1", + "PublicDescription": "UNC_MC0_RDCAS_COUNT_FREERUN", + "Unit": "h_imc" + }, + { + "BriefDescription": "Counts every 64B read and write request enter= ing the Memory Controller to DRAM (sum of all channels). Each write request= counts as a new request incrementing this counter. However, same cache lin= e write requests (both full and partial) are combined to a single 64 byte d= ata transfer to DRAM.", + "CounterType": "FREERUN", + "EventName": "UNC_MC0_TOTAL_REQCOUNT_FREERUN", + "PerPkg": "1", + "PublicDescription": "UNC_MC0_TOTAL_REQCOUNT_FREERUN", + "Unit": "h_imc" + }, + { + "BriefDescription": "Counts every write (WrCAS) issued by the Memo= ry Controller to DRAM (sum of all channels). All requests result in 64 byte= data transfers from DRAM.", + "Counter": "2", + "CounterType": "FREERUN", + "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN", + "PerPkg": "1", + "PublicDescription": "UNC_MC0_WRCAS_COUNT_FREERUN", + "Unit": "h_imc" + }, + { + "BriefDescription": "Counts every read (RdCAS) issued by the Memor= y Controller to DRAM (sum of all channels). All requests result in 64 byte = data transfers from DRAM.", + "Counter": "4", + "CounterType": "FREERUN", + "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN", + "PerPkg": "1", + "PublicDescription": "UNC_MC1_RDCAS_COUNT_FREERUN", + "Unit": "h_imc" + }, + { + "BriefDescription": "Counts every 64B read and write request enter= ing the Memory Controller to DRAM (sum of all channels). Each write request= counts as a new request incrementing this counter. However, same cache lin= e write requests (both full and partial) are combined to a single 64 byte d= ata transfer to DRAM.", + "Counter": "3", + "CounterType": "FREERUN", + "EventName": "UNC_MC1_TOTAL_REQCOUNT_FREERUN", + "PerPkg": "1", + "PublicDescription": "UNC_MC1_TOTAL_REQCOUNT_FREERUN", + "Unit": "h_imc" + }, + { + "BriefDescription": "Counts every write (WrCAS) issued by the Memo= ry Controller to DRAM (sum of all channels). All requests result in 64 byte= data transfers from DRAM.", + "Counter": "5", + "CounterType": "FREERUN", + "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN", + "PerPkg": "1", + "PublicDescription": "UNC_MC1_WRCAS_COUNT_FREERUN", + "Unit": "h_imc" + } +] diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/virtual-memory.json b= /tools/perf/pmu-events/arch/x86/tigerlake/virtual-memory.json index 3ebec78969b0..fd364abf8002 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/virtual-memory.json @@ -222,4 +222,4 @@ "SampleAfterValue": "100007", "UMask": "0x20" } -] \ No newline at end of file +] --=20 2.37.1.359.gd136c6c3e2-goog From nobody Wed Apr 15 05:45:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5E94C19F29 for ; Wed, 27 Jul 2022 22:13:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236676AbiG0WNo (ORCPT ); Wed, 27 Jul 2022 18:13:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54832 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237388AbiG0WMm (ORCPT ); Wed, 27 Jul 2022 18:12:42 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2D860E08B for ; Wed, 27 Jul 2022 15:10:11 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id a11-20020a5b090b000000b00672acbe13c1so258206ybq.2 for ; Wed, 27 Jul 2022 15:10:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=8pN3twcMAxYA80ZD4DEEJfFP2dE7IQ0k6stG34SCEVY=; b=Rk00fQYzWE/+T3/aWAD2+vsfkXrS/m7JyO8AIWUDXS9kdfoeaUJMoQ+Dv5V0udI+im 0YscWbWDGlXripQQ8k9LWXTCYL3vY4Hym7B1Em6TOwkbAwtdBNCqzbQgSpiIoieqBEfO q0YxgAaGNKAGOcJEEBaRCkxrVHNdUxRxTgJM0qmoo4z76PO9RcPNTnxVxSqgQDgfD/PP +8YGaD+OLbvHBPO6Q5mJQSWUrak2NNHJqAAGmXe/fhvfbo6//PLldR+Va+tur00Y/zh4 aObyn3UL+Z7d9O2ciqMyuoFbmbeFp/I2SdMsqA8uxDz9OT8C1RUKUuV0qRPk9H+rDIFl jPfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=8pN3twcMAxYA80ZD4DEEJfFP2dE7IQ0k6stG34SCEVY=; b=qCRf/W2AJQUs86MHcQmXnmCWR8zH31UECLounMuMgMrf/c7ISXzYlT6YVLLAlD5fNo rZxI2miO676Urma2GGMnmCTKlOih/S72chAg0NE3/JmuuCx93dcKUJxj3kNuM0pyzPyY 5AQRBdC75gkzhJy6YIqBdy+n+0LUzkFQ5QPjEasn/peQJ7smvaTB8O5ZSXRY9fC456XS 6a42uxLs5jI/1PUJIpbtIHxHbZS8HWEIqP+iZl13V9ybwZSkEy5YoxKVxsjv0Em9o7zj 9pwXpVnpRNo95DcyZMmRKftcYakRhFFrYgR3YDQYwbIE0JN/CqpTEKOafO8x/jtt/d+r CI3A== X-Gm-Message-State: AJIora9Mg1GNx9pq65AfeGx5tYd+mDhXyZW9Ke2rFWoWZUfhxFXOm8Y6 gr7mK8LIltDitgb/Huepg3mtishOX2Ip X-Google-Smtp-Source: AGRyM1tqS2qztnHvbydy/RZbaTgto/0/M5eZXLb2wNIrVPz+adygKu8ccITcSM2BPXBuwh8yARoca7eY6Bg5 X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:882a:af57:8cb6:6f9e]) (user=irogers job=sendgmr) by 2002:a05:6902:124a:b0:670:d03a:14fb with SMTP id t10-20020a056902124a00b00670d03a14fbmr19521998ybu.406.1658959796238; Wed, 27 Jul 2022 15:09:56 -0700 (PDT) Date: Wed, 27 Jul 2022 15:08:29 -0700 In-Reply-To: <20220727220832.2865794-1-irogers@google.com> Message-Id: <20220727220832.2865794-28-irogers@google.com> Mime-Version: 1.0 References: <20220727220832.2865794-1-irogers@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH v3 27/30] perf vendor events: Update Intel westmereep-dp From: Ian Rogers To: perry.taylor@intel.com, caleb.biggers@intel.com, kshipra.bopardikar@intel.com, Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Sedat Dilek Cc: Stephane Eranian , Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update to v2, the metrics are based on TMA 4.4 full. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/downloa= d_and_gen.py to download and generate the latest events and metrics. Manually copy the westmereep-dp files into perf and update mapfile.csv. This change just aligns whitespace. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json | 2 +- .../perf/pmu-events/arch/x86/westmereep-dp/floating-point.json | 2 +- tools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json | 2 +- tools/perf/pmu-events/arch/x86/westmereep-dp/memory.json | 2 +- .../perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json b/tool= s/perf/pmu-events/arch/x86/westmereep-dp/cache.json index 0f01cf223777..37ed2742fec6 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json @@ -2814,4 +2814,4 @@ "SampleAfterValue": "200000", "UMask": "0x8" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.js= on b/tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json index 39af1329224a..666e466d351c 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json @@ -226,4 +226,4 @@ "SampleAfterValue": "200000", "UMask": "0x8" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json b/t= ools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json index 8ac5c24888c5..c561ac24d91d 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json @@ -23,4 +23,4 @@ "SampleAfterValue": "2000000", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/memory.json b/too= ls/perf/pmu-events/arch/x86/westmereep-dp/memory.json index 36fbea313c6f..7e529b367c21 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-dp/memory.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/memory.json @@ -755,4 +755,4 @@ "SampleAfterValue": "100000", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.js= on b/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json index d63e469a43e1..8099e6700e31 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json @@ -170,4 +170,4 @@ "SampleAfterValue": "200000", "UMask": "0x1" } -] \ No newline at end of file +] --=20 2.37.1.359.gd136c6c3e2-goog From nobody Wed Apr 15 05:45:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A4B8C04A68 for ; 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Wed, 27 Jul 2022 15:09:58 -0700 (PDT) Date: Wed, 27 Jul 2022 15:08:30 -0700 In-Reply-To: <20220727220832.2865794-1-irogers@google.com> Message-Id: <20220727220832.2865794-29-irogers@google.com> Mime-Version: 1.0 References: <20220727220832.2865794-1-irogers@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH v3 28/30] perf vendor events: Update Intel westmereep-sp From: Ian Rogers To: perry.taylor@intel.com, caleb.biggers@intel.com, kshipra.bopardikar@intel.com, Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Sedat Dilek Cc: Stephane Eranian , Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update to v3, the metrics are based on TMA 4.4 full. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/downloa= d_and_gen.py to download and generate the latest events and metrics. Manually copy the westmereep-sp files into perf and update mapfile.csv. This change just aligns whitespace and updates the version number. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- .../perf/pmu-events/arch/x86/westmereep-sp/floating-point.json | 2 +- tools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json | 2 +- .../perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index b660d3528b7d..d1cabfc62c39 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -26,7 +26,7 @@ GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v53,skylake,core GenuineIntel-6-55-[01234],v1.28,skylakex,core GenuineIntel-6-8[CD],v1.07,tigerlake,core GenuineIntel-6-2C,v2,westmereep-dp,core -GenuineIntel-6-25,v2,westmereep-sp,core +GenuineIntel-6-25,v3,westmereep-sp,core GenuineIntel-6-2F,v2,westmereex,core GenuineIntel-6-86,v1,snowridgex,core AuthenticAMD-23-([12][0-9A-F]|[0-9A-F]),v2,amdzen1,core diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.js= on b/tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.json index 39af1329224a..666e466d351c 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.json @@ -226,4 +226,4 @@ "SampleAfterValue": "200000", "UMask": "0x8" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json b/t= ools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json index 8ac5c24888c5..c561ac24d91d 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json @@ -23,4 +23,4 @@ "SampleAfterValue": "2000000", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.js= on b/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json index 0252f77a844b..e7affdf7f41b 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json @@ -146,4 +146,4 @@ "SampleAfterValue": "200000", "UMask": "0x1" } -] \ No newline at end of file +] --=20 2.37.1.359.gd136c6c3e2-goog From nobody Wed Apr 15 05:45:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07D87C04A68 for ; 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Wed, 27 Jul 2022 15:10:00 -0700 (PDT) Date: Wed, 27 Jul 2022 15:08:31 -0700 In-Reply-To: <20220727220832.2865794-1-irogers@google.com> Message-Id: <20220727220832.2865794-30-irogers@google.com> Mime-Version: 1.0 References: <20220727220832.2865794-1-irogers@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH v3 29/30] perf vendor events: Update Intel westmereex From: Ian Rogers To: perry.taylor@intel.com, caleb.biggers@intel.com, kshipra.bopardikar@intel.com, Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Sedat Dilek Cc: Stephane Eranian , Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update to v3, the metrics are based on TMA 4.4 full. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/downloa= d_and_gen.py to download and generate the latest events and metrics. Manually copy the westmereex files into perf and update mapfile.csv. This change just aligns whitespace and updates the version number. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- tools/perf/pmu-events/arch/x86/westmereex/floating-point.json | 2 +- tools/perf/pmu-events/arch/x86/westmereex/frontend.json | 2 +- tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index d1cabfc62c39..c607f4155556 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -27,7 +27,7 @@ GenuineIntel-6-55-[01234],v1.28,skylakex,core GenuineIntel-6-8[CD],v1.07,tigerlake,core GenuineIntel-6-2C,v2,westmereep-dp,core GenuineIntel-6-25,v3,westmereep-sp,core -GenuineIntel-6-2F,v2,westmereex,core +GenuineIntel-6-2F,v3,westmereex,core GenuineIntel-6-86,v1,snowridgex,core AuthenticAMD-23-([12][0-9A-F]|[0-9A-F]),v2,amdzen1,core AuthenticAMD-23-[[:xdigit:]]+,v1,amdzen2,core diff --git a/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json = b/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json index 39af1329224a..666e466d351c 100644 --- a/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json @@ -226,4 +226,4 @@ "SampleAfterValue": "200000", "UMask": "0x8" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/westmereex/frontend.json b/tool= s/perf/pmu-events/arch/x86/westmereex/frontend.json index 8ac5c24888c5..c561ac24d91d 100644 --- a/tools/perf/pmu-events/arch/x86/westmereex/frontend.json +++ b/tools/perf/pmu-events/arch/x86/westmereex/frontend.json @@ -23,4 +23,4 @@ "SampleAfterValue": "2000000", "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json = b/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json index 5d1e017d1261..0c3501e6e5a3 100644 --- a/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json @@ -170,4 +170,4 @@ "SampleAfterValue": "200000", "UMask": "0x1" } -] \ No newline at end of file +] --=20 2.37.1.359.gd136c6c3e2-goog From nobody Wed Apr 15 05:45:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB696C04A68 for ; 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Wed, 27 Jul 2022 15:10:03 -0700 (PDT) Date: Wed, 27 Jul 2022 15:08:32 -0700 In-Reply-To: <20220727220832.2865794-1-irogers@google.com> Message-Id: <20220727220832.2865794-31-irogers@google.com> Mime-Version: 1.0 References: <20220727220832.2865794-1-irogers@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH v3 30/30] perf vendor events: Update Intel snowridgex From: Ian Rogers To: perry.taylor@intel.com, caleb.biggers@intel.com, kshipra.bopardikar@intel.com, Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Sedat Dilek Cc: Stephane Eranian , Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update to v1.20, the metrics are based on TMA 4.4 full. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/downloa= d_and_gen.py to download and generate the latest events and metrics. Manually copy the snowridgex files into perf and update mapfile.csv. Tested on a non-snowridgex with 'perf test': 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok This change just updates the version number. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index c607f4155556..7f2d777fd97f 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -24,11 +24,11 @@ GenuineIntel-6-8F,v1.04,sapphirerapids,core GenuineIntel-6-(37|4C|4D),v14,silvermont,core GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v53,skylake,core GenuineIntel-6-55-[01234],v1.28,skylakex,core +GenuineIntel-6-86,v1.20,snowridgex,core GenuineIntel-6-8[CD],v1.07,tigerlake,core GenuineIntel-6-2C,v2,westmereep-dp,core GenuineIntel-6-25,v3,westmereep-sp,core GenuineIntel-6-2F,v3,westmereex,core -GenuineIntel-6-86,v1,snowridgex,core AuthenticAMD-23-([12][0-9A-F]|[0-9A-F]),v2,amdzen1,core AuthenticAMD-23-[[:xdigit:]]+,v1,amdzen2,core AuthenticAMD-25-[[:xdigit:]]+,v1,amdzen3,core --=20 2.37.1.359.gd136c6c3e2-goog