From nobody Wed Apr 15 02:54:31 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD093C04A68 for ; Wed, 27 Jul 2022 11:44:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232347AbiG0LoE (ORCPT ); Wed, 27 Jul 2022 07:44:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33148 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232319AbiG0LoB (ORCPT ); Wed, 27 Jul 2022 07:44:01 -0400 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 12FAD49B78 for ; Wed, 27 Jul 2022 04:43:59 -0700 (PDT) Received: by mail-pl1-x636.google.com with SMTP id x7so1996367pll.7 for ; Wed, 27 Jul 2022 04:43:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/CPQHjznoZ6b2glx4mv5BleZiD6F9CrQGa2QjZHjYAk=; b=FRPQ5DEeON6hr+ON1ZUCBRqVaD6UKtMN7FWnG+TiJ551KlCqDdy0r3uLcwH2HL6QJH l7WDhuWl9MkfjaS0XSPgW9n1unZhtd6+ZfZIrtE0tIBXUKu/nxEI8OzSdaFZhd36YBw+ wbWNIjvHFN6IOiBHmHuSoXwZjtEnI3g6Aquz2voLi7ZqtjwNt9yj4UpVrKUpMt9LYOLV YFedqPoHh7qK8JDHl3M9tTn+9SS3ruir8rwhVtM13Btz83igBcjWQzRMQYfrDzbONY4O MQyTStOXmK5oUhHGLHrZVgYo3MU7fQNWgfu66fsCss8DYRVxISd/TFoUlrgTkqMwzjIR fSlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/CPQHjznoZ6b2glx4mv5BleZiD6F9CrQGa2QjZHjYAk=; b=5p9OHcxuFFeCQBAi5S/df8WvCkYti4MSnaVWHQhSPWKzm4urCDu3+kBl6jbbNQgQ0h yMnBapXGDzOItDEZ7uSZcFRWuwkwFfktuM/LuSiaSgFN/QQH6R9W3ZlQJiouFjDPfAef wAei+Z8ui7scFlw3roV9tZzigZG3WcPR1L+YomHotKKBZATdYY3l7XT0cOUOMNxagxrk ra+LHeuVFEDDpODYN7mCyb6EXUYVeM5PSRRlz+Fn0sDqJ3H6ABIY3e1eXz/11ORH+Cjt BSXDv5oYRz9a8+dYDie2OIT55RfpxoMEx9vQyMLneVmNZsynKUFhm4toD8232eIEBg43 c9sw== X-Gm-Message-State: AJIora9bbZ2/LsToVPfmtCOzcpK/Nf6djRj/hMWQSxJSnKIStgS9lNf6 Vi/76eZTW0zaoR4WJaTruNc4jg== X-Google-Smtp-Source: AGRyM1vnaKRmTMYomS9eDouKLzyJu05leK/dJlguPo3uyJqQ85jD8Cdr1zYUFAC0wnfYAIhPgdEy4w== X-Received: by 2002:a17:90a:9bc4:b0:1f2:389a:7faa with SMTP id b4-20020a17090a9bc400b001f2389a7faamr4282213pjw.72.1658922238405; Wed, 27 Jul 2022 04:43:58 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.87.63]) by smtp.gmail.com with ESMTPSA id o8-20020a170902d4c800b0016be9fa6807sm13486685plg.284.2022.07.27.04.43.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Jul 2022 04:43:57 -0700 (PDT) From: Anup Patel To: Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Daniel Lezcano , Thomas Gleixner Cc: Andrew Jones , Atish Patra , Samuel Holland , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v2 1/2] dt-bindings: riscv: Add optional DT property riscv,timer-can-wake-cpu Date: Wed, 27 Jul 2022 17:13:01 +0530 Message-Id: <20220727114302.302201-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220727114302.302201-1-apatel@ventanamicro.com> References: <20220727114302.302201-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We add an optional DT property riscv,timer-can-wake-cpu which if present in CPU DT node then CPU timer is always powered-on and never loses context. Signed-off-by: Anup Patel --- Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentat= ion/devicetree/bindings/riscv/cpus.yaml index d632ac76532e..b60b64b4113a 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -78,6 +78,12 @@ properties: - rv64imac - rv64imafdc =20 + riscv,timer-can-wake-cpu: + type: boolean + description: + If present, the timer interrupt can wake up the CPU from + suspend/idle state. + # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false =20 --=20 2.34.1 From nobody Wed Apr 15 02:54:31 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3979AC04A68 for ; Wed, 27 Jul 2022 11:44:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232404AbiG0Lo3 (ORCPT ); Wed, 27 Jul 2022 07:44:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33150 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232433AbiG0LoF (ORCPT ); Wed, 27 Jul 2022 07:44:05 -0400 Received: from mail-pg1-x534.google.com (mail-pg1-x534.google.com [IPv6:2607:f8b0:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D3EA14A812 for ; Wed, 27 Jul 2022 04:44:04 -0700 (PDT) Received: by mail-pg1-x534.google.com with SMTP id q22so10545649pgt.9 for ; Wed, 27 Jul 2022 04:44:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZDeYW4AY28vTxurFqUXv3ebNyVNdEODpLRCvig5J+Z8=; b=aqjEe3mvrZ/sXf2TJhUGnviXYa1l1LYvbO7SQNCsbRoBm0VTSB5S/Vn+NZ3BombPyd c/hYAThtpLetobdizee3fkOS/RlfZitV1e4eh2Sk4CmKvhXeGs41oltsGCrZGXrdUf48 KqR1b30FD6/M8sVRF0rEJQ51pt9SPXLoBxvDhX4eVN/KXOe2sdLQPZNBb9CRlQ/bPmuo Wp4KqHYcaAC+mWT20tlu1Bk2gicSXZDrADeE+ruejivezkjr9GXD9SOCjeCwsDvBrAAh sQUbAXEjW9hO/WPRC9DvATAtc4z6/vfE48At2mxmtoyzPv5qgLh6b7VpH8SrqxlEuomp YRPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZDeYW4AY28vTxurFqUXv3ebNyVNdEODpLRCvig5J+Z8=; b=r2K+PqylP2Kt7KJTBZFlUltfdYVpoDpf77UtvSew9LP2zL2Km48XR++ylSW6KMdPOZ S46b5OA1FGv9IaJ6WDmWbtP5D8TYs7Tp324UmYfzmtDhxokDP3PCnLbuEFZE/w4gKre8 uW2Z/ynFXjzk1iSGxIl1v6TymUue2OasbOrz9OsIpcVr+sdQ0pPPAmYbNoyNoOP0DIBc WHScp5TyVvkkMRnUZBzFt8N2SNBTqnCe8D5CTxvsBJxstC62CtjYyl88Ph22E3IIdTh9 Y8PQPQZeMU3jHuwlet3zDxPs0WWCy/oTOd5xf5m/By61Z4xAb8S/Zd73znKSfJ2rU305 YEmg== X-Gm-Message-State: AJIora+VtbjgKirgarpMT3w8bGk71VPE71Gf19si692gvVc+GTXz7bCC VtW2YBZd9dp4H2USxATkHXzcAg== X-Google-Smtp-Source: AGRyM1vgoJVgOpNZ5zoSEMsNCq+Vu0AoGtr3UpQlEBz0aThV4QkKeFQREyfDS6te99XytVvnKPacaA== X-Received: by 2002:a63:fd4f:0:b0:41b:539b:ba8e with SMTP id m15-20020a63fd4f000000b0041b539bba8emr812287pgj.17.1658922244094; Wed, 27 Jul 2022 04:44:04 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.87.63]) by smtp.gmail.com with ESMTPSA id o8-20020a170902d4c800b0016be9fa6807sm13486685plg.284.2022.07.27.04.43.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Jul 2022 04:44:03 -0700 (PDT) From: Anup Patel To: Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Daniel Lezcano , Thomas Gleixner Cc: Andrew Jones , Atish Patra , Samuel Holland , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v2 2/2] clocksource: timer-riscv: Set CLOCK_EVT_FEAT_C3STOP based on DT property Date: Wed, 27 Jul 2022 17:13:02 +0530 Message-Id: <20220727114302.302201-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220727114302.302201-1-apatel@ventanamicro.com> References: <20220727114302.302201-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We should set CLOCK_EVT_FEAT_C3STOP for a clock_event_device only when riscv,timer-can-wake-cpu DT property is not present for the corresponding CPU. This way CLOCK_EVT_FEAT_C3STOP feature is set for clock_event_device based on RISC-V platform capabilities rather than having it set for all RISC-V platforms. Signed-off-by: Anup Patel --- drivers/clocksource/timer-riscv.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-= riscv.c index 593d5a957b69..92a0b9832d8c 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -34,7 +34,7 @@ static int riscv_clock_next_event(unsigned long delta, static unsigned int riscv_clock_event_irq; static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) =3D { .name =3D "riscv_timer_clockevent", - .features =3D CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP, + .features =3D CLOCK_EVT_FEAT_ONESHOT, .rating =3D 100, .set_next_event =3D riscv_clock_next_event, }; @@ -65,9 +65,13 @@ static struct clocksource riscv_clocksource =3D { static int riscv_timer_starting_cpu(unsigned int cpu) { struct clock_event_device *ce =3D per_cpu_ptr(&riscv_clock_event, cpu); + struct device_node *np =3D of_get_cpu_node(cpu, NULL); =20 ce->cpumask =3D cpumask_of(cpu); ce->irq =3D riscv_clock_event_irq; + if (!of_property_read_bool(np, "riscv,timer-can-wake-cpu")) + ce->features |=3D CLOCK_EVT_FEAT_C3STOP; + of_node_put(np); clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff); =20 enable_percpu_irq(riscv_clock_event_irq, --=20 2.34.1