From nobody Wed Apr 15 03:04:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98D78C04A68 for ; Wed, 27 Jul 2022 11:35:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232106AbiG0Lft (ORCPT ); Wed, 27 Jul 2022 07:35:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230110AbiG0Lfn (ORCPT ); Wed, 27 Jul 2022 07:35:43 -0400 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 55F9143E54; Wed, 27 Jul 2022 04:35:42 -0700 (PDT) Received: by mail-ej1-x62e.google.com with SMTP id l23so31000139ejr.5; Wed, 27 Jul 2022 04:35:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=lhvDDsJvBpWETgobXmvcinrpM6pJWb5xW40JaSHYLtA=; b=kmbStV5h1V5rK3xavw4QDCyr9Ovdu9p1aFAGN3WvZMHmmRPaMagRJKdP28uZsBy8tl y70fHyjeOwhGCakMJ0pF3EkSxaSQLuXguGohytVL43VS2UmLlcIEOzgbzzXf1VW5jauU uxGawNp8Tphr58jbr9iVr9Lzk8H4zS1/83Xj6jCkqCQquo+FlcLXbpXzr75pMFdJHYU9 Q5s0rcCQD7cS31RE3iuIKooSRgY3CvsT+/dL4QAYLqvY56J3a3oKqs6hGX/pCGQykexo DS8HSQe5Mh2VYgns7hWQohBUY9HJJ9O3RoXgBol0b6W4rJIfhaIG6OxVPTAog9MuW0oF d95w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lhvDDsJvBpWETgobXmvcinrpM6pJWb5xW40JaSHYLtA=; b=SmiF262N58E/psylW5YFv7SWkvUF7Qj8TTMlZ3s/eXbLnpYVgXVwpAji/2sK12Kyvo TDl6HpvO14Dh9vbwpY3L77PuL1nNKO1Caqf12plSasmjd/pp1dU/RTVeTX6Bun4XBqVF 3NJ4XAhoKtL7L3OrfwNxXQsGAQb79jAK90nFTcJZI60x+2goK//KQ0zlLpJyBOAveBST 4RVc3ry5ZM1CYRB5gl8jpC/ZQfgE1GYbIde37wtnU1K+TUNbQGcQTxjt6RWYW96Mg95L j2SHa5JuPXl30L5zPkRM2kxdz6SaXQYrb1EdXgjVpqlOhbmnuqXjSlZaVSfFgxZUp/U8 DwXw== X-Gm-Message-State: AJIora9NKsbQgSUsfFSUijwhwCSFWmm58A52Xu8to47hUrNoKrLeNUHd RZlkYjuJLmTHGWheOlpQWvY= X-Google-Smtp-Source: AGRyM1vQLY0WEfwif8hEzFvoN1kO8+10tahucJPJv5Z+BZD91cnBrWfkkFaqa0YAU8bhgV7MNfNuwg== X-Received: by 2002:a17:906:dc95:b0:72f:ab47:1692 with SMTP id cs21-20020a170906dc9500b0072fab471692mr17093133ejc.319.1658921740559; Wed, 27 Jul 2022 04:35:40 -0700 (PDT) Received: from localhost.localdomain (c105-182.i13-27.melita.com. [94.17.105.182]) by smtp.googlemail.com with ESMTPSA id p25-20020aa7cc99000000b0043ca6fb7e7dsm1334056edt.68.2022.07.27.04.35.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Jul 2022 04:35:40 -0700 (PDT) From: Christian Marangi To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Greg Kroah-Hartman , Jens Axboe , Christian Marangi , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: [net-next PATCH v5 01/14] net: dsa: qca8k: cache match data to speed up access Date: Wed, 27 Jul 2022 13:35:10 +0200 Message-Id: <20220727113523.19742-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220727113523.19742-1-ansuelsmth@gmail.com> References: <20220727113523.19742-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Using of_device_get_match_data is expensive. Cache match data to speed up access and rework user of match data to use the new cached value. Signed-off-by: Christian Marangi Reviewed-by: Florian Fainelli Reviewed-by: Vladimir Oltean --- drivers/net/dsa/qca/qca8k.c | 35 +++++++++++------------------------ drivers/net/dsa/qca/qca8k.h | 1 + 2 files changed, 12 insertions(+), 24 deletions(-) diff --git a/drivers/net/dsa/qca/qca8k.c b/drivers/net/dsa/qca/qca8k.c index 1cbb05b0323f..64524a721221 100644 --- a/drivers/net/dsa/qca/qca8k.c +++ b/drivers/net/dsa/qca/qca8k.c @@ -1462,8 +1462,8 @@ static int qca8k_find_cpu_port(struct dsa_switch *ds) static int qca8k_setup_of_pws_reg(struct qca8k_priv *priv) { + const struct qca8k_match_data *data =3D priv->info; struct device_node *node =3D priv->dev->of_node; - const struct qca8k_match_data *data; u32 val =3D 0; int ret; =20 @@ -1472,8 +1472,6 @@ qca8k_setup_of_pws_reg(struct qca8k_priv *priv) * Should be applied by default but we set this just to make sure. */ if (priv->switch_id =3D=3D QCA8K_ID_QCA8327) { - data =3D of_device_get_match_data(priv->dev); - /* Set the correct package of 148 pin for QCA8327 */ if (data->reduced_package) val |=3D QCA8327_PWS_PACKAGE148_EN; @@ -1996,23 +1994,19 @@ static void qca8k_setup_pcs(struct qca8k_priv *priv= , struct qca8k_pcs *qpcs, static void qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t = *data) { - const struct qca8k_match_data *match_data; struct qca8k_priv *priv =3D ds->priv; int i; =20 if (stringset !=3D ETH_SS_STATS) return; =20 - match_data =3D of_device_get_match_data(priv->dev); - - for (i =3D 0; i < match_data->mib_count; i++) + for (i =3D 0; i < priv->info->mib_count; i++) strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name, ETH_GSTRING_LEN); } =20 static void qca8k_mib_autocast_handler(struct dsa_switch *ds, struct sk_bu= ff *skb) { - const struct qca8k_match_data *match_data; struct qca8k_mib_eth_data *mib_eth_data; struct qca8k_priv *priv =3D ds->priv; const struct qca8k_mib_desc *mib; @@ -2031,10 +2025,9 @@ static void qca8k_mib_autocast_handler(struct dsa_sw= itch *ds, struct sk_buff *sk if (port !=3D mib_eth_data->req_port) goto exit; =20 - match_data =3D device_get_match_data(priv->dev); data =3D mib_eth_data->data; =20 - for (i =3D 0; i < match_data->mib_count; i++) { + for (i =3D 0; i < priv->info->mib_count; i++) { mib =3D &ar8327_mib[i]; =20 /* First 3 mib are present in the skb head */ @@ -2106,7 +2099,6 @@ qca8k_get_ethtool_stats(struct dsa_switch *ds, int po= rt, uint64_t *data) { struct qca8k_priv *priv =3D (struct qca8k_priv *)ds->priv; - const struct qca8k_match_data *match_data; const struct qca8k_mib_desc *mib; u32 reg, i, val; u32 hi =3D 0; @@ -2116,9 +2108,7 @@ qca8k_get_ethtool_stats(struct dsa_switch *ds, int po= rt, qca8k_get_ethtool_stats_eth(ds, port, data) > 0) return; =20 - match_data =3D of_device_get_match_data(priv->dev); - - for (i =3D 0; i < match_data->mib_count; i++) { + for (i =3D 0; i < priv->info->mib_count; i++) { mib =3D &ar8327_mib[i]; reg =3D QCA8K_PORT_MIB_COUNTER(port) + mib->offset; =20 @@ -2141,15 +2131,12 @@ qca8k_get_ethtool_stats(struct dsa_switch *ds, int = port, static int qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset) { - const struct qca8k_match_data *match_data; struct qca8k_priv *priv =3D ds->priv; =20 if (sset !=3D ETH_SS_STATS) return 0; =20 - match_data =3D of_device_get_match_data(priv->dev); - - return match_data->mib_count; + return priv->info->mib_count; } =20 static int @@ -3093,14 +3080,11 @@ static const struct dsa_switch_ops qca8k_switch_ops= =3D { =20 static int qca8k_read_switch_id(struct qca8k_priv *priv) { - const struct qca8k_match_data *data; u32 val; u8 id; int ret; =20 - /* get the switches ID from the compatible */ - data =3D of_device_get_match_data(priv->dev); - if (!data) + if (!priv->info) return -ENODEV; =20 ret =3D qca8k_read(priv, QCA8K_REG_MASK_CTRL, &val); @@ -3108,8 +3092,10 @@ static int qca8k_read_switch_id(struct qca8k_priv *p= riv) return -ENODEV; =20 id =3D QCA8K_MASK_CTRL_DEVICE_ID(val); - if (id !=3D data->id) { - dev_err(priv->dev, "Switch id detected %x but expected %x", id, data->id= ); + if (id !=3D priv->info->id) { + dev_err(priv->dev, + "Switch id detected %x but expected %x", + id, priv->info->id); return -ENODEV; } =20 @@ -3134,6 +3120,7 @@ qca8k_sw_probe(struct mdio_device *mdiodev) if (!priv) return -ENOMEM; =20 + priv->info =3D of_device_get_match_data(priv->dev); priv->bus =3D mdiodev->bus; priv->dev =3D &mdiodev->dev; =20 diff --git a/drivers/net/dsa/qca/qca8k.h b/drivers/net/dsa/qca/qca8k.h index ec58d0e80a70..0b990b46890a 100644 --- a/drivers/net/dsa/qca/qca8k.h +++ b/drivers/net/dsa/qca/qca8k.h @@ -401,6 +401,7 @@ struct qca8k_priv { struct qca8k_mdio_cache mdio_cache; struct qca8k_pcs pcs_port_0; struct qca8k_pcs pcs_port_6; + const struct qca8k_match_data *info; }; =20 struct qca8k_mib_desc { --=20 2.36.1 From nobody Wed Apr 15 03:04:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66539C04A68 for ; Wed, 27 Jul 2022 11:35:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232129AbiG0Lfx (ORCPT ); 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[94.17.105.182]) by smtp.googlemail.com with ESMTPSA id p25-20020aa7cc99000000b0043ca6fb7e7dsm1334056edt.68.2022.07.27.04.35.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Jul 2022 04:35:41 -0700 (PDT) From: Christian Marangi To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Greg Kroah-Hartman , Jens Axboe , Christian Marangi , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: [net-next PATCH v5 02/14] net: dsa: qca8k: make mib autocast feature optional Date: Wed, 27 Jul 2022 13:35:11 +0200 Message-Id: <20220727113523.19742-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220727113523.19742-1-ansuelsmth@gmail.com> References: <20220727113523.19742-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Some switch may not support mib autocast feature and require the legacy way of reading the regs directly. Make the mib autocast feature optional and permit to declare support for it using match_data struct in a dedicated qca8k_info_ops struct. Signed-off-by: Christian Marangi Reviewed-by: Florian Fainelli Reviewed-by: Vladimir Oltean --- drivers/net/dsa/qca/qca8k.c | 11 +++++++++-- drivers/net/dsa/qca/qca8k.h | 5 +++++ 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/qca/qca8k.c b/drivers/net/dsa/qca/qca8k.c index 64524a721221..02a4765f267e 100644 --- a/drivers/net/dsa/qca/qca8k.c +++ b/drivers/net/dsa/qca/qca8k.c @@ -2104,8 +2104,8 @@ qca8k_get_ethtool_stats(struct dsa_switch *ds, int po= rt, u32 hi =3D 0; int ret; =20 - if (priv->mgmt_master && - qca8k_get_ethtool_stats_eth(ds, port, data) > 0) + if (priv->mgmt_master && priv->info->ops->autocast_mib && + priv->info->ops->autocast_mib(ds, port, data) > 0) return; =20 for (i =3D 0; i < priv->info->mib_count; i++) { @@ -3243,20 +3243,27 @@ static int qca8k_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(qca8k_pm_ops, qca8k_suspend, qca8k_resume); =20 +static const struct qca8k_info_ops qca8xxx_ops =3D { + .autocast_mib =3D qca8k_get_ethtool_stats_eth, +}; + static const struct qca8k_match_data qca8327 =3D { .id =3D QCA8K_ID_QCA8327, .reduced_package =3D true, .mib_count =3D QCA8K_QCA832X_MIB_COUNT, + .ops =3D &qca8xxx_ops, }; =20 static const struct qca8k_match_data qca8328 =3D { .id =3D QCA8K_ID_QCA8327, .mib_count =3D QCA8K_QCA832X_MIB_COUNT, + .ops =3D &qca8xxx_ops, }; =20 static const struct qca8k_match_data qca833x =3D { .id =3D QCA8K_ID_QCA8337, .mib_count =3D QCA8K_QCA833X_MIB_COUNT, + .ops =3D &qca8xxx_ops, }; =20 static const struct of_device_id qca8k_of_match[] =3D { diff --git a/drivers/net/dsa/qca/qca8k.h b/drivers/net/dsa/qca/qca8k.h index 0b990b46890a..377ce8c72914 100644 --- a/drivers/net/dsa/qca/qca8k.h +++ b/drivers/net/dsa/qca/qca8k.h @@ -324,10 +324,15 @@ enum qca8k_mid_cmd { QCA8K_MIB_CAST =3D 3, }; =20 +struct qca8k_info_ops { + int (*autocast_mib)(struct dsa_switch *ds, int port, u64 *data); +}; + struct qca8k_match_data { u8 id; bool reduced_package; u8 mib_count; + const struct qca8k_info_ops *ops; }; =20 enum { --=20 2.36.1 From nobody Wed Apr 15 03:04:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02972C04A68 for ; Wed, 27 Jul 2022 11:35:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232146AbiG0Lf4 (ORCPT ); Wed, 27 Jul 2022 07:35:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52434 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232068AbiG0Lfr (ORCPT ); Wed, 27 Jul 2022 07:35:47 -0400 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5BF94491E4; Wed, 27 Jul 2022 04:35:45 -0700 (PDT) Received: by mail-ej1-x629.google.com with SMTP id b11so30908422eju.10; Wed, 27 Jul 2022 04:35:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=zdWeXDg380Y+sDMxFJqg27oxgrMdmEgfg0KLhnU3oqA=; b=qsIylPTAGN+uf396M1Gq96+9xM/3U8A91+3AMTDplUFxHz0FoMhqlHhTLsLZ/j6hPL AruFVVcSpLfATochHwiQmQf0lqH6BZz4J2MP8T0ZUk7i7HPmcDbqyB3fY13e2FmGca+B E/aI7utaGBySNsUzU0OZTLXijyEAEWr7rG++wtVRX4h4/eUzZZKneIrSAZyyb609FjvF tCCnjrF3GGqByevYkB6ycMbT5I9bavojgzSWUAfDp92dWSHX8sLyOc8XmoDzF03BR5XZ TV5vNZ8ii9xaauWZ8h9ZB08i/nrIdldAGVyJOdNvRFJ6gdnwpq0lsV66FTPt39LQKmZ/ +3nA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zdWeXDg380Y+sDMxFJqg27oxgrMdmEgfg0KLhnU3oqA=; b=gWctOODk+8WqKJqBT1ZLM9PbuAfWPrcM6BWNBdGH3W80q9jBod7pdWpafiiM/sI5zX sd/H09VjgmI2Q9aP75hlTOjgovy+Rfzy4/YiUljjsK7JFRL0kCWGTTA9dNkGdz9oKQwH z19ZWfDB9NW2WduDdGduxl52oTMIESs+Y2kCSPT/Lp6E5mFZbh/sC86YJGzgQ9PlqVXI dSsr6NPYuMLOh2f0sIRzk0HHD5sxBTHdq/zbBvtCrXhQO8Fxn7awdz8NOGVX1rOa5emk 3iAWqnh1rtswwe6QzJlHs8t8NaF6yd8AOZ+gRJaVC6+9tks63iQKiznM0Y5TFLDY7elD N1lQ== X-Gm-Message-State: AJIora/2QYnDGhQ57Kp/ivJSxg6gf7Yr6EHEXpScNejs9rWZ8BaI1pHo xy50TyY6VrAPDbdyD64r9lQ= X-Google-Smtp-Source: AGRyM1tz2zNutRZEL7XHFZQs951rgo9HG1cl6tKCVQzho50Th7EADLY/HKEOZ04Y3affo9CEuig/WA== X-Received: by 2002:a17:907:2bc6:b0:72e:ceea:862b with SMTP id gv6-20020a1709072bc600b0072eceea862bmr17883965ejc.134.1658921743590; Wed, 27 Jul 2022 04:35:43 -0700 (PDT) Received: from localhost.localdomain (c105-182.i13-27.melita.com. [94.17.105.182]) by smtp.googlemail.com with ESMTPSA id p25-20020aa7cc99000000b0043ca6fb7e7dsm1334056edt.68.2022.07.27.04.35.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Jul 2022 04:35:43 -0700 (PDT) From: Christian Marangi To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Greg Kroah-Hartman , Jens Axboe , Christian Marangi , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: [net-next PATCH v5 03/14] net: dsa: qca8k: move mib struct to common code Date: Wed, 27 Jul 2022 13:35:12 +0200 Message-Id: <20220727113523.19742-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220727113523.19742-1-ansuelsmth@gmail.com> References: <20220727113523.19742-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The same MIB struct is used by drivers based on qca8k family switch. Move it to common code to make it accessible also by other drivers. Signed-off-by: Christian Marangi Reviewed-by: Vladimir Oltean Reviewed-by: Florian Fainelli --- drivers/net/dsa/qca/Makefile | 1 + drivers/net/dsa/qca/{qca8k.c =3D> qca8k-8xxx.c} | 51 --------------- drivers/net/dsa/qca/qca8k-common.c | 63 +++++++++++++++++++ drivers/net/dsa/qca/qca8k.h | 3 + 4 files changed, 67 insertions(+), 51 deletions(-) rename drivers/net/dsa/qca/{qca8k.c =3D> qca8k-8xxx.c} (98%) create mode 100644 drivers/net/dsa/qca/qca8k-common.c diff --git a/drivers/net/dsa/qca/Makefile b/drivers/net/dsa/qca/Makefile index 40bb7c27285b..701f1d199e93 100644 --- a/drivers/net/dsa/qca/Makefile +++ b/drivers/net/dsa/qca/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_NET_DSA_AR9331) +=3D ar9331.o obj-$(CONFIG_NET_DSA_QCA8K) +=3D qca8k.o +qca8k-y +=3D qca8k-common.o qca8k-8xxx.o diff --git a/drivers/net/dsa/qca/qca8k.c b/drivers/net/dsa/qca/qca8k-8xxx.c similarity index 98% rename from drivers/net/dsa/qca/qca8k.c rename to drivers/net/dsa/qca/qca8k-8xxx.c index 02a4765f267e..e9c4a54bc97a 100644 --- a/drivers/net/dsa/qca/qca8k.c +++ b/drivers/net/dsa/qca/qca8k-8xxx.c @@ -24,57 +24,6 @@ =20 #include "qca8k.h" =20 -#define MIB_DESC(_s, _o, _n) \ - { \ - .size =3D (_s), \ - .offset =3D (_o), \ - .name =3D (_n), \ - } - -static const struct qca8k_mib_desc ar8327_mib[] =3D { - MIB_DESC(1, 0x00, "RxBroad"), - MIB_DESC(1, 0x04, "RxPause"), - MIB_DESC(1, 0x08, "RxMulti"), - MIB_DESC(1, 0x0c, "RxFcsErr"), - MIB_DESC(1, 0x10, "RxAlignErr"), - MIB_DESC(1, 0x14, "RxRunt"), - MIB_DESC(1, 0x18, "RxFragment"), - MIB_DESC(1, 0x1c, "Rx64Byte"), - MIB_DESC(1, 0x20, "Rx128Byte"), - MIB_DESC(1, 0x24, "Rx256Byte"), - MIB_DESC(1, 0x28, "Rx512Byte"), - MIB_DESC(1, 0x2c, "Rx1024Byte"), - MIB_DESC(1, 0x30, "Rx1518Byte"), - MIB_DESC(1, 0x34, "RxMaxByte"), - MIB_DESC(1, 0x38, "RxTooLong"), - MIB_DESC(2, 0x3c, "RxGoodByte"), - MIB_DESC(2, 0x44, "RxBadByte"), - MIB_DESC(1, 0x4c, "RxOverFlow"), - MIB_DESC(1, 0x50, "Filtered"), - MIB_DESC(1, 0x54, "TxBroad"), - MIB_DESC(1, 0x58, "TxPause"), - MIB_DESC(1, 0x5c, "TxMulti"), - MIB_DESC(1, 0x60, "TxUnderRun"), - MIB_DESC(1, 0x64, "Tx64Byte"), - MIB_DESC(1, 0x68, "Tx128Byte"), - MIB_DESC(1, 0x6c, "Tx256Byte"), - MIB_DESC(1, 0x70, "Tx512Byte"), - MIB_DESC(1, 0x74, "Tx1024Byte"), - MIB_DESC(1, 0x78, "Tx1518Byte"), - MIB_DESC(1, 0x7c, "TxMaxByte"), - MIB_DESC(1, 0x80, "TxOverSize"), - MIB_DESC(2, 0x84, "TxByte"), - MIB_DESC(1, 0x8c, "TxCollision"), - MIB_DESC(1, 0x90, "TxAbortCol"), - MIB_DESC(1, 0x94, "TxMultiCol"), - MIB_DESC(1, 0x98, "TxSingleCol"), - MIB_DESC(1, 0x9c, "TxExcDefer"), - MIB_DESC(1, 0xa0, "TxDefer"), - MIB_DESC(1, 0xa4, "TxLateCol"), - MIB_DESC(1, 0xa8, "RXUnicast"), - MIB_DESC(1, 0xac, "TXUnicast"), -}; - static void qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page) { diff --git a/drivers/net/dsa/qca/qca8k-common.c b/drivers/net/dsa/qca/qca8k= -common.c new file mode 100644 index 000000000000..7a63e96c8c08 --- /dev/null +++ b/drivers/net/dsa/qca/qca8k-common.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2009 Felix Fietkau + * Copyright (C) 2011-2012 Gabor Juhos + * Copyright (c) 2015, 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2016 John Crispin + */ + +#include +#include + +#include "qca8k.h" + +#define MIB_DESC(_s, _o, _n) \ + { \ + .size =3D (_s), \ + .offset =3D (_o), \ + .name =3D (_n), \ + } + +const struct qca8k_mib_desc ar8327_mib[] =3D { + MIB_DESC(1, 0x00, "RxBroad"), + MIB_DESC(1, 0x04, "RxPause"), + MIB_DESC(1, 0x08, "RxMulti"), + MIB_DESC(1, 0x0c, "RxFcsErr"), + MIB_DESC(1, 0x10, "RxAlignErr"), + MIB_DESC(1, 0x14, "RxRunt"), + MIB_DESC(1, 0x18, "RxFragment"), + MIB_DESC(1, 0x1c, "Rx64Byte"), + MIB_DESC(1, 0x20, "Rx128Byte"), + MIB_DESC(1, 0x24, "Rx256Byte"), + MIB_DESC(1, 0x28, "Rx512Byte"), + MIB_DESC(1, 0x2c, "Rx1024Byte"), + MIB_DESC(1, 0x30, "Rx1518Byte"), + MIB_DESC(1, 0x34, "RxMaxByte"), + MIB_DESC(1, 0x38, "RxTooLong"), + MIB_DESC(2, 0x3c, "RxGoodByte"), + MIB_DESC(2, 0x44, "RxBadByte"), + MIB_DESC(1, 0x4c, "RxOverFlow"), + MIB_DESC(1, 0x50, "Filtered"), + MIB_DESC(1, 0x54, "TxBroad"), + MIB_DESC(1, 0x58, "TxPause"), + MIB_DESC(1, 0x5c, "TxMulti"), + MIB_DESC(1, 0x60, "TxUnderRun"), + MIB_DESC(1, 0x64, "Tx64Byte"), + MIB_DESC(1, 0x68, "Tx128Byte"), + MIB_DESC(1, 0x6c, "Tx256Byte"), + MIB_DESC(1, 0x70, "Tx512Byte"), + MIB_DESC(1, 0x74, "Tx1024Byte"), + MIB_DESC(1, 0x78, "Tx1518Byte"), + MIB_DESC(1, 0x7c, "TxMaxByte"), + MIB_DESC(1, 0x80, "TxOverSize"), + MIB_DESC(2, 0x84, "TxByte"), + MIB_DESC(1, 0x8c, "TxCollision"), + MIB_DESC(1, 0x90, "TxAbortCol"), + MIB_DESC(1, 0x94, "TxMultiCol"), + MIB_DESC(1, 0x98, "TxSingleCol"), + MIB_DESC(1, 0x9c, "TxExcDefer"), + MIB_DESC(1, 0xa0, "TxDefer"), + MIB_DESC(1, 0xa4, "TxLateCol"), + MIB_DESC(1, 0xa8, "RXUnicast"), + MIB_DESC(1, 0xac, "TXUnicast"), +}; diff --git a/drivers/net/dsa/qca/qca8k.h b/drivers/net/dsa/qca/qca8k.h index 377ce8c72914..0f274bb350f8 100644 --- a/drivers/net/dsa/qca/qca8k.h +++ b/drivers/net/dsa/qca/qca8k.h @@ -422,4 +422,7 @@ struct qca8k_fdb { u8 mac[6]; }; =20 +/* Common setup function */ +extern const struct qca8k_mib_desc ar8327_mib[]; + #endif /* __QCA8K_H */ --=20 2.36.1 From nobody Wed Apr 15 03:04:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B927EC19F29 for ; Wed, 27 Jul 2022 11:36:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232231AbiG0LgB (ORCPT ); Wed, 27 Jul 2022 07:36:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52506 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232103AbiG0Lfs (ORCPT ); Wed, 27 Jul 2022 07:35:48 -0400 Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B19C49B5F; Wed, 27 Jul 2022 04:35:47 -0700 (PDT) Received: by mail-ed1-x534.google.com with SMTP id i13so11895665edj.11; Wed, 27 Jul 2022 04:35:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=u/CWUdj4wodMemeG+T6sKoKJ2OETDAnhTSH8WgMVAKg=; b=F96vQaH8SPWleJGyLGMRks4P2Jiv9ib7SmGdUkYQn+F4dAIKR8nCWK1VavDdorq4dv +DVmlZWP8o4UGBMLK8ihUVltGNYllmVMBLk9z7j/emsAEz9rbbOiU2VQwZr7sXzb7gz9 IthJAWzmz/yiRwXcRuTEPrc6dUb4DRqWrPbYHVBzcfu+hMtNoH/1N9ft69OyPfurSH3f KVANbAA0ohGTMG66OtcCGmCljUDK5qv2EDdVEoMC35gUFRArBEDyTBc0v3m/2Q6wi1oA 3MMgX9zkpaYGMdCW40Z92sI5PesTWuOi+5SV1uhdfwq2eO3Ye95cv/YGOOk1OAgvFS7m X41g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=u/CWUdj4wodMemeG+T6sKoKJ2OETDAnhTSH8WgMVAKg=; b=7qyV+z9v7SazxQrt4DhaMxwb7w6ZL+8zuybswosRZknW2zRG+yr1xnphmmHT79KKHJ W7Dad8+c2WM8XeVgcDPvAWf4dcOwB6+3AflGybzuNK2cKTP5ovPl0V2MHmwUiStnCCpB ilrTDBssEdTCNjCqIl2JWzBOu8IoO7pm8b1mXi2cddK2KCGOwrjvs26HghycUbjDfEIK FUrOdI3KAaIDu2V2o7EutyVDLiREXFRLJ6DrQvf8A2cu5lQaDWdwWYuRG5ZmW2zEcLbQ r6M+rpgoABMlNAxdstO/a2YCMU1wWcJO5XcDlfCf+Z97Jn1yhX5kzKVBPRymqaCWSFs2 qc+A== X-Gm-Message-State: AJIora83TDuEdlF7fAuH0psTWY69PsxjxDEZ1FHhYuuJct4igQLxJ2jH djWsr38UmrdvArctEw4BBHY= X-Google-Smtp-Source: AGRyM1vV1mvzp29XzQCyJ4hk0kfpsNNOxWDMIK2RlKrFXH29GTGbFOSpnwmzDP1XrNeQpMTAMZ6urA== X-Received: by 2002:aa7:c3d1:0:b0:43c:c713:fac8 with SMTP id l17-20020aa7c3d1000000b0043cc713fac8mr1058277edr.371.1658921745633; Wed, 27 Jul 2022 04:35:45 -0700 (PDT) Received: from localhost.localdomain (c105-182.i13-27.melita.com. [94.17.105.182]) by smtp.googlemail.com with ESMTPSA id p25-20020aa7cc99000000b0043ca6fb7e7dsm1334056edt.68.2022.07.27.04.35.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Jul 2022 04:35:45 -0700 (PDT) From: Christian Marangi To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Greg Kroah-Hartman , Jens Axboe , Christian Marangi , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: [net-next PATCH v5 04/14] net: dsa: qca8k: move qca8k read/write/rmw and reg table to common code Date: Wed, 27 Jul 2022 13:35:13 +0200 Message-Id: <20220727113523.19742-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220727113523.19742-1-ansuelsmth@gmail.com> References: <20220727113523.19742-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The same reg table and read/write/rmw function are used by drivers based on qca8k family switch. Move them to common code to make it accessible also by other drivers. Signed-off-by: Christian Marangi Reviewed-by: Vladimir Oltean Reviewed-by: Florian Fainelli --- drivers/net/dsa/qca/qca8k-8xxx.c | 42 ------------------------------ drivers/net/dsa/qca/qca8k-common.c | 38 +++++++++++++++++++++++++++ drivers/net/dsa/qca/qca8k.h | 6 +++++ 3 files changed, 44 insertions(+), 42 deletions(-) diff --git a/drivers/net/dsa/qca/qca8k-8xxx.c b/drivers/net/dsa/qca/qca8k-8= xxx.c index e9c4a54bc97a..2c31b7925aae 100644 --- a/drivers/net/dsa/qca/qca8k-8xxx.c +++ b/drivers/net/dsa/qca/qca8k-8xxx.c @@ -133,24 +133,6 @@ qca8k_set_page(struct qca8k_priv *priv, u16 page) return 0; } =20 -static int -qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val) -{ - return regmap_read(priv->regmap, reg, val); -} - -static int -qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val) -{ - return regmap_write(priv->regmap, reg, val); -} - -static int -qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val) -{ - return regmap_update_bits(priv->regmap, reg, mask, write_val); -} - static void qca8k_rw_reg_ack_handler(struct dsa_switch *ds, struct sk_buff= *skb) { struct qca8k_mgmt_eth_data *mgmt_eth_data; @@ -483,30 +465,6 @@ qca8k_regmap_update_bits(void *ctx, uint32_t reg, uint= 32_t mask, uint32_t write_ return ret; } =20 -static const struct regmap_range qca8k_readable_ranges[] =3D { - regmap_reg_range(0x0000, 0x00e4), /* Global control */ - regmap_reg_range(0x0100, 0x0168), /* EEE control */ - regmap_reg_range(0x0200, 0x0270), /* Parser control */ - regmap_reg_range(0x0400, 0x0454), /* ACL */ - regmap_reg_range(0x0600, 0x0718), /* Lookup */ - regmap_reg_range(0x0800, 0x0b70), /* QM */ - regmap_reg_range(0x0c00, 0x0c80), /* PKT */ - regmap_reg_range(0x0e00, 0x0e98), /* L3 */ - regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */ - regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */ - regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */ - regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */ - regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */ - regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */ - regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */ - -}; - -static const struct regmap_access_table qca8k_readable_table =3D { - .yes_ranges =3D qca8k_readable_ranges, - .n_yes_ranges =3D ARRAY_SIZE(qca8k_readable_ranges), -}; - static struct regmap_config qca8k_regmap_config =3D { .reg_bits =3D 16, .val_bits =3D 32, diff --git a/drivers/net/dsa/qca/qca8k-common.c b/drivers/net/dsa/qca/qca8k= -common.c index 7a63e96c8c08..880a49de22b1 100644 --- a/drivers/net/dsa/qca/qca8k-common.c +++ b/drivers/net/dsa/qca/qca8k-common.c @@ -61,3 +61,41 @@ const struct qca8k_mib_desc ar8327_mib[] =3D { MIB_DESC(1, 0xa8, "RXUnicast"), MIB_DESC(1, 0xac, "TXUnicast"), }; + +int qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val) +{ + return regmap_read(priv->regmap, reg, val); +} + +int qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val) +{ + return regmap_write(priv->regmap, reg, val); +} + +int qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val) +{ + return regmap_update_bits(priv->regmap, reg, mask, write_val); +} + +static const struct regmap_range qca8k_readable_ranges[] =3D { + regmap_reg_range(0x0000, 0x00e4), /* Global control */ + regmap_reg_range(0x0100, 0x0168), /* EEE control */ + regmap_reg_range(0x0200, 0x0270), /* Parser control */ + regmap_reg_range(0x0400, 0x0454), /* ACL */ + regmap_reg_range(0x0600, 0x0718), /* Lookup */ + regmap_reg_range(0x0800, 0x0b70), /* QM */ + regmap_reg_range(0x0c00, 0x0c80), /* PKT */ + regmap_reg_range(0x0e00, 0x0e98), /* L3 */ + regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */ + regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */ + regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */ + regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */ + regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */ + regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */ + regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */ +}; + +const struct regmap_access_table qca8k_readable_table =3D { + .yes_ranges =3D qca8k_readable_ranges, + .n_yes_ranges =3D ARRAY_SIZE(qca8k_readable_ranges), +}; diff --git a/drivers/net/dsa/qca/qca8k.h b/drivers/net/dsa/qca/qca8k.h index 0f274bb350f8..c9b753743dfd 100644 --- a/drivers/net/dsa/qca/qca8k.h +++ b/drivers/net/dsa/qca/qca8k.h @@ -424,5 +424,11 @@ struct qca8k_fdb { =20 /* Common setup function */ extern const struct qca8k_mib_desc ar8327_mib[]; +extern const struct regmap_access_table qca8k_readable_table; + +/* Common read/write/rmw function */ +int qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val); +int qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val); +int qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val); =20 #endif /* __QCA8K_H */ --=20 2.36.1 From nobody Wed Apr 15 03:04:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93B67C19F29 for ; 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[94.17.105.182]) by smtp.googlemail.com with ESMTPSA id p25-20020aa7cc99000000b0043ca6fb7e7dsm1334056edt.68.2022.07.27.04.35.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Jul 2022 04:35:46 -0700 (PDT) From: Christian Marangi To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Greg Kroah-Hartman , Jens Axboe , Christian Marangi , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: [net-next PATCH v5 05/14] net: dsa: qca8k: move qca8k bulk read/write helper to common code Date: Wed, 27 Jul 2022 13:35:14 +0200 Message-Id: <20220727113523.19742-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220727113523.19742-1-ansuelsmth@gmail.com> References: <20220727113523.19742-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The same ATU function are used by drivers based on qca8k family switch. Move the bulk read/write helper to common code to declare these shared ATU functions in common code. These helper will be dropped when regmap correctly support bulk read/write. Signed-off-by: Christian Marangi Reviewed-by: Vladimir Oltean Reviewed-by: Florian Fainelli --- drivers/net/dsa/qca/qca8k-8xxx.c | 39 ++---------------------------- drivers/net/dsa/qca/qca8k-common.c | 39 ++++++++++++++++++++++++++++++ drivers/net/dsa/qca/qca8k.h | 8 ++++++ 3 files changed, 49 insertions(+), 37 deletions(-) diff --git a/drivers/net/dsa/qca/qca8k-8xxx.c b/drivers/net/dsa/qca/qca8k-8= xxx.c index 2c31b7925aae..8a5529844c7a 100644 --- a/drivers/net/dsa/qca/qca8k-8xxx.c +++ b/drivers/net/dsa/qca/qca8k-8xxx.c @@ -342,43 +342,6 @@ qca8k_regmap_update_bits_eth(struct qca8k_priv *priv, = u32 reg, u32 mask, u32 wri return qca8k_write_eth(priv, reg, &val, sizeof(val)); } =20 -static int -qca8k_bulk_read(struct qca8k_priv *priv, u32 reg, u32 *val, int len) -{ - int i, count =3D len / sizeof(u32), ret; - - if (priv->mgmt_master && !qca8k_read_eth(priv, reg, val, len)) - return 0; - - for (i =3D 0; i < count; i++) { - ret =3D regmap_read(priv->regmap, reg + (i * 4), val + i); - if (ret < 0) - return ret; - } - - return 0; -} - -static int -qca8k_bulk_write(struct qca8k_priv *priv, u32 reg, u32 *val, int len) -{ - int i, count =3D len / sizeof(u32), ret; - u32 tmp; - - if (priv->mgmt_master && !qca8k_write_eth(priv, reg, val, len)) - return 0; - - for (i =3D 0; i < count; i++) { - tmp =3D val[i]; - - ret =3D regmap_write(priv->regmap, reg + (i * 4), tmp); - if (ret < 0) - return ret; - } - - return 0; -} - static int qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val) { @@ -3152,6 +3115,8 @@ static SIMPLE_DEV_PM_OPS(qca8k_pm_ops, =20 static const struct qca8k_info_ops qca8xxx_ops =3D { .autocast_mib =3D qca8k_get_ethtool_stats_eth, + .read_eth =3D qca8k_read_eth, + .write_eth =3D qca8k_write_eth, }; =20 static const struct qca8k_match_data qca8327 =3D { diff --git a/drivers/net/dsa/qca/qca8k-common.c b/drivers/net/dsa/qca/qca8k= -common.c index 880a49de22b1..a47f876033ba 100644 --- a/drivers/net/dsa/qca/qca8k-common.c +++ b/drivers/net/dsa/qca/qca8k-common.c @@ -99,3 +99,42 @@ const struct regmap_access_table qca8k_readable_table = =3D { .yes_ranges =3D qca8k_readable_ranges, .n_yes_ranges =3D ARRAY_SIZE(qca8k_readable_ranges), }; + +/* TODO: remove these extra ops when we can support regmap bulk read/write= */ +int qca8k_bulk_read(struct qca8k_priv *priv, u32 reg, u32 *val, int len) +{ + int i, count =3D len / sizeof(u32), ret; + + if (priv->mgmt_master && priv->info->ops->read_eth && + !priv->info->ops->read_eth(priv, reg, val, len)) + return 0; + + for (i =3D 0; i < count; i++) { + ret =3D regmap_read(priv->regmap, reg + (i * 4), val + i); + if (ret < 0) + return ret; + } + + return 0; +} + +/* TODO: remove these extra ops when we can support regmap bulk read/write= */ +int qca8k_bulk_write(struct qca8k_priv *priv, u32 reg, u32 *val, int len) +{ + int i, count =3D len / sizeof(u32), ret; + u32 tmp; + + if (priv->mgmt_master && priv->info->ops->write_eth && + !priv->info->ops->write_eth(priv, reg, val, len)) + return 0; + + for (i =3D 0; i < count; i++) { + tmp =3D val[i]; + + ret =3D regmap_write(priv->regmap, reg + (i * 4), tmp); + if (ret < 0) + return ret; + } + + return 0; +} diff --git a/drivers/net/dsa/qca/qca8k.h b/drivers/net/dsa/qca/qca8k.h index c9b753743dfd..df32c1e3a797 100644 --- a/drivers/net/dsa/qca/qca8k.h +++ b/drivers/net/dsa/qca/qca8k.h @@ -324,8 +324,13 @@ enum qca8k_mid_cmd { QCA8K_MIB_CAST =3D 3, }; =20 +struct qca8k_priv; + struct qca8k_info_ops { int (*autocast_mib)(struct dsa_switch *ds, int port, u64 *data); + /* TODO: remove these extra ops when we can support regmap bulk read/writ= e */ + int (*read_eth)(struct qca8k_priv *priv, u32 reg, u32 *val, int len); + int (*write_eth)(struct qca8k_priv *priv, u32 reg, u32 *val, int len); }; =20 struct qca8k_match_data { @@ -431,4 +436,7 @@ int qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *v= al); int qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val); int qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val); =20 +int qca8k_bulk_read(struct qca8k_priv *priv, u32 reg, u32 *val, int len); +int qca8k_bulk_write(struct qca8k_priv *priv, u32 reg, u32 *val, int len); + #endif /* __QCA8K_H */ --=20 2.36.1 From nobody Wed Apr 15 03:04:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50FD8C19F29 for ; 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[94.17.105.182]) by smtp.googlemail.com with ESMTPSA id p25-20020aa7cc99000000b0043ca6fb7e7dsm1334056edt.68.2022.07.27.04.35.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Jul 2022 04:35:48 -0700 (PDT) From: Christian Marangi To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Greg Kroah-Hartman , Jens Axboe , Christian Marangi , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: [net-next PATCH v5 06/14] net: dsa: qca8k: move mib init function to common code Date: Wed, 27 Jul 2022 13:35:15 +0200 Message-Id: <20220727113523.19742-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220727113523.19742-1-ansuelsmth@gmail.com> References: <20220727113523.19742-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The same mib function is used by drivers based on qca8k family switch. Move it to common code to make it accessible also by other drivers. Signed-off-by: Christian Marangi Reviewed-by: Florian Fainelli Reviewed-by: Vladimir Oltean --- drivers/net/dsa/qca/qca8k-8xxx.c | 37 ------------------------------ drivers/net/dsa/qca/qca8k-common.c | 35 ++++++++++++++++++++++++++++ drivers/net/dsa/qca/qca8k.h | 4 ++++ 3 files changed, 39 insertions(+), 37 deletions(-) diff --git a/drivers/net/dsa/qca/qca8k-8xxx.c b/drivers/net/dsa/qca/qca8k-8= xxx.c index 8a5529844c7a..b4daa097a7fc 100644 --- a/drivers/net/dsa/qca/qca8k-8xxx.c +++ b/drivers/net/dsa/qca/qca8k-8xxx.c @@ -441,15 +441,6 @@ static struct regmap_config qca8k_regmap_config =3D { .cache_type =3D REGCACHE_NONE, /* Explicitly disable CACHE */ }; =20 -static int -qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask) -{ - u32 val; - - return regmap_read_poll_timeout(priv->regmap, reg, val, !(val & mask), 0, - QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC); -} - static int qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb) { @@ -777,34 +768,6 @@ qca8k_vlan_del(struct qca8k_priv *priv, u8 port, u16 v= id) return ret; } =20 -static int -qca8k_mib_init(struct qca8k_priv *priv) -{ - int ret; - - mutex_lock(&priv->reg_mutex); - ret =3D regmap_update_bits(priv->regmap, QCA8K_REG_MIB, - QCA8K_MIB_FUNC | QCA8K_MIB_BUSY, - FIELD_PREP(QCA8K_MIB_FUNC, QCA8K_MIB_FLUSH) | - QCA8K_MIB_BUSY); - if (ret) - goto exit; - - ret =3D qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY); - if (ret) - goto exit; - - ret =3D regmap_set_bits(priv->regmap, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP); - if (ret) - goto exit; - - ret =3D qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB); - -exit: - mutex_unlock(&priv->reg_mutex); - return ret; -} - static void qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable) { diff --git a/drivers/net/dsa/qca/qca8k-common.c b/drivers/net/dsa/qca/qca8k= -common.c index a47f876033ba..7da3547f9d97 100644 --- a/drivers/net/dsa/qca/qca8k-common.c +++ b/drivers/net/dsa/qca/qca8k-common.c @@ -138,3 +138,38 @@ int qca8k_bulk_write(struct qca8k_priv *priv, u32 reg,= u32 *val, int len) =20 return 0; } + +int qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask) +{ + u32 val; + + return regmap_read_poll_timeout(priv->regmap, reg, val, !(val & mask), 0, + QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC); +} + +int qca8k_mib_init(struct qca8k_priv *priv) +{ + int ret; + + mutex_lock(&priv->reg_mutex); + ret =3D regmap_update_bits(priv->regmap, QCA8K_REG_MIB, + QCA8K_MIB_FUNC | QCA8K_MIB_BUSY, + FIELD_PREP(QCA8K_MIB_FUNC, QCA8K_MIB_FLUSH) | + QCA8K_MIB_BUSY); + if (ret) + goto exit; + + ret =3D qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY); + if (ret) + goto exit; + + ret =3D regmap_set_bits(priv->regmap, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP); + if (ret) + goto exit; + + ret =3D qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB); + +exit: + mutex_unlock(&priv->reg_mutex); + return ret; +} diff --git a/drivers/net/dsa/qca/qca8k.h b/drivers/net/dsa/qca/qca8k.h index df32c1e3a797..f55ef97f826f 100644 --- a/drivers/net/dsa/qca/qca8k.h +++ b/drivers/net/dsa/qca/qca8k.h @@ -430,6 +430,7 @@ struct qca8k_fdb { /* Common setup function */ extern const struct qca8k_mib_desc ar8327_mib[]; extern const struct regmap_access_table qca8k_readable_table; +int qca8k_mib_init(struct qca8k_priv *priv); =20 /* Common read/write/rmw function */ int qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val); @@ -439,4 +440,7 @@ int qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mas= k, u32 write_val); int qca8k_bulk_read(struct qca8k_priv *priv, u32 reg, u32 *val, int len); int qca8k_bulk_write(struct qca8k_priv *priv, u32 reg, u32 *val, int len); =20 +/* Common ops function */ +int qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask); + #endif /* __QCA8K_H */ --=20 2.36.1 From nobody Wed Apr 15 03:04:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B43EEC04A68 for ; Wed, 27 Jul 2022 11:36:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232304AbiG0LgO (ORCPT ); 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[94.17.105.182]) by smtp.googlemail.com with ESMTPSA id p25-20020aa7cc99000000b0043ca6fb7e7dsm1334056edt.68.2022.07.27.04.35.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Jul 2022 04:35:49 -0700 (PDT) From: Christian Marangi To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Greg Kroah-Hartman , Jens Axboe , Christian Marangi , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: [net-next PATCH v5 07/14] net: dsa: qca8k: move port set status/eee/ethtool stats function to common code Date: Wed, 27 Jul 2022 13:35:16 +0200 Message-Id: <20220727113523.19742-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220727113523.19742-1-ansuelsmth@gmail.com> References: <20220727113523.19742-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The same logic to disable/enable port, set eee and get ethtool stats is used by drivers based on qca8k family switch. Move it to common code to make it accessible also by other drivers. While at it also drop unnecessary qca8k_priv cast for void pointers. Signed-off-by: Christian Marangi Reviewed-by: Vladimir Oltean Reviewed-by: Florian Fainelli --- drivers/net/dsa/qca/qca8k-8xxx.c | 105 ----------------------------- drivers/net/dsa/qca/qca8k-common.c | 102 ++++++++++++++++++++++++++++ drivers/net/dsa/qca/qca8k.h | 11 +++ 3 files changed, 113 insertions(+), 105 deletions(-) diff --git a/drivers/net/dsa/qca/qca8k-8xxx.c b/drivers/net/dsa/qca/qca8k-8= xxx.c index b4daa097a7fc..9729aabbd83d 100644 --- a/drivers/net/dsa/qca/qca8k-8xxx.c +++ b/drivers/net/dsa/qca/qca8k-8xxx.c @@ -768,21 +768,6 @@ qca8k_vlan_del(struct qca8k_priv *priv, u8 port, u16 v= id) return ret; } =20 -static void -qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable) -{ - u32 mask =3D QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC; - - /* Port 0 and 6 have no internal PHY */ - if (port > 0 && port < 6) - mask |=3D QCA8K_PORT_STATUS_LINK_AUTO; - - if (enable) - regmap_set_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask); - else - regmap_clear_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask); -} - static int qca8k_phy_eth_busy_wait(struct qca8k_mgmt_eth_data *mgmt_eth_data, struct sk_buff *read_skb, u32 *val) @@ -1824,20 +1809,6 @@ static void qca8k_setup_pcs(struct qca8k_priv *priv,= struct qca8k_pcs *qpcs, qpcs->port =3D port; } =20 -static void -qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t = *data) -{ - struct qca8k_priv *priv =3D ds->priv; - int i; - - if (stringset !=3D ETH_SS_STATS) - return; - - for (i =3D 0; i < priv->info->mib_count; i++) - strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name, - ETH_GSTRING_LEN); -} - static void qca8k_mib_autocast_handler(struct dsa_switch *ds, struct sk_bu= ff *skb) { struct qca8k_mib_eth_data *mib_eth_data; @@ -1927,82 +1898,6 @@ qca8k_get_ethtool_stats_eth(struct dsa_switch *ds, i= nt port, u64 *data) return ret; } =20 -static void -qca8k_get_ethtool_stats(struct dsa_switch *ds, int port, - uint64_t *data) -{ - struct qca8k_priv *priv =3D (struct qca8k_priv *)ds->priv; - const struct qca8k_mib_desc *mib; - u32 reg, i, val; - u32 hi =3D 0; - int ret; - - if (priv->mgmt_master && priv->info->ops->autocast_mib && - priv->info->ops->autocast_mib(ds, port, data) > 0) - return; - - for (i =3D 0; i < priv->info->mib_count; i++) { - mib =3D &ar8327_mib[i]; - reg =3D QCA8K_PORT_MIB_COUNTER(port) + mib->offset; - - ret =3D qca8k_read(priv, reg, &val); - if (ret < 0) - continue; - - if (mib->size =3D=3D 2) { - ret =3D qca8k_read(priv, reg + 4, &hi); - if (ret < 0) - continue; - } - - data[i] =3D val; - if (mib->size =3D=3D 2) - data[i] |=3D (u64)hi << 32; - } -} - -static int -qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset) -{ - struct qca8k_priv *priv =3D ds->priv; - - if (sset !=3D ETH_SS_STATS) - return 0; - - return priv->info->mib_count; -} - -static int -qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *eee) -{ - struct qca8k_priv *priv =3D (struct qca8k_priv *)ds->priv; - u32 lpi_en =3D QCA8K_REG_EEE_CTRL_LPI_EN(port); - u32 reg; - int ret; - - mutex_lock(&priv->reg_mutex); - ret =3D qca8k_read(priv, QCA8K_REG_EEE_CTRL, ®); - if (ret < 0) - goto exit; - - if (eee->eee_enabled) - reg |=3D lpi_en; - else - reg &=3D ~lpi_en; - ret =3D qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg); - -exit: - mutex_unlock(&priv->reg_mutex); - return ret; -} - -static int -qca8k_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) -{ - /* Nothing to do on the port's MAC */ - return 0; -} - static void qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) { diff --git a/drivers/net/dsa/qca/qca8k-common.c b/drivers/net/dsa/qca/qca8k= -common.c index 7da3547f9d97..c662fdbae51f 100644 --- a/drivers/net/dsa/qca/qca8k-common.c +++ b/drivers/net/dsa/qca/qca8k-common.c @@ -173,3 +173,105 @@ int qca8k_mib_init(struct qca8k_priv *priv) mutex_unlock(&priv->reg_mutex); return ret; } + +void qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable) +{ + u32 mask =3D QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC; + + /* Port 0 and 6 have no internal PHY */ + if (port > 0 && port < 6) + mask |=3D QCA8K_PORT_STATUS_LINK_AUTO; + + if (enable) + regmap_set_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask); + else + regmap_clear_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask); +} + +void qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, + uint8_t *data) +{ + struct qca8k_priv *priv =3D ds->priv; + int i; + + if (stringset !=3D ETH_SS_STATS) + return; + + for (i =3D 0; i < priv->info->mib_count; i++) + strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name, + ETH_GSTRING_LEN); +} + +void qca8k_get_ethtool_stats(struct dsa_switch *ds, int port, + uint64_t *data) +{ + struct qca8k_priv *priv =3D ds->priv; + const struct qca8k_mib_desc *mib; + u32 reg, i, val; + u32 hi =3D 0; + int ret; + + if (priv->mgmt_master && priv->info->ops->autocast_mib && + priv->info->ops->autocast_mib(ds, port, data) > 0) + return; + + for (i =3D 0; i < priv->info->mib_count; i++) { + mib =3D &ar8327_mib[i]; + reg =3D QCA8K_PORT_MIB_COUNTER(port) + mib->offset; + + ret =3D qca8k_read(priv, reg, &val); + if (ret < 0) + continue; + + if (mib->size =3D=3D 2) { + ret =3D qca8k_read(priv, reg + 4, &hi); + if (ret < 0) + continue; + } + + data[i] =3D val; + if (mib->size =3D=3D 2) + data[i] |=3D (u64)hi << 32; + } +} + +int qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset) +{ + struct qca8k_priv *priv =3D ds->priv; + + if (sset !=3D ETH_SS_STATS) + return 0; + + return priv->info->mib_count; +} + +int qca8k_set_mac_eee(struct dsa_switch *ds, int port, + struct ethtool_eee *eee) +{ + u32 lpi_en =3D QCA8K_REG_EEE_CTRL_LPI_EN(port); + struct qca8k_priv *priv =3D ds->priv; + u32 reg; + int ret; + + mutex_lock(&priv->reg_mutex); + ret =3D qca8k_read(priv, QCA8K_REG_EEE_CTRL, ®); + if (ret < 0) + goto exit; + + if (eee->eee_enabled) + reg |=3D lpi_en; + else + reg &=3D ~lpi_en; + ret =3D qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg); + +exit: + mutex_unlock(&priv->reg_mutex); + return ret; +} + +int qca8k_get_mac_eee(struct dsa_switch *ds, int port, + struct ethtool_eee *e) +{ + /* Nothing to do on the port's MAC */ + return 0; +} diff --git a/drivers/net/dsa/qca/qca8k.h b/drivers/net/dsa/qca/qca8k.h index f55ef97f826f..c73cbdfc6ac6 100644 --- a/drivers/net/dsa/qca/qca8k.h +++ b/drivers/net/dsa/qca/qca8k.h @@ -431,6 +431,7 @@ struct qca8k_fdb { extern const struct qca8k_mib_desc ar8327_mib[]; extern const struct regmap_access_table qca8k_readable_table; int qca8k_mib_init(struct qca8k_priv *priv); +void qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable); =20 /* Common read/write/rmw function */ int qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val); @@ -443,4 +444,14 @@ int qca8k_bulk_write(struct qca8k_priv *priv, u32 reg,= u32 *val, int len); /* Common ops function */ int qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask); =20 +/* Common ethtool stats function */ +void qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uin= t8_t *data); +void qca8k_get_ethtool_stats(struct dsa_switch *ds, int port, + uint64_t *data); +int qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset); + +/* Common eee function */ +int qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee = *eee); +int qca8k_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee = *e); + #endif /* __QCA8K_H */ --=20 2.36.1 From nobody Wed Apr 15 03:04:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17A44C04A68 for ; Wed, 27 Jul 2022 11:36:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232408AbiG0Lgk (ORCPT ); Wed, 27 Jul 2022 07:36:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53138 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232249AbiG0LgF (ORCPT ); Wed, 27 Jul 2022 07:36:05 -0400 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B26CB4A80B; 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[94.17.105.182]) by smtp.googlemail.com with ESMTPSA id p25-20020aa7cc99000000b0043ca6fb7e7dsm1334056edt.68.2022.07.27.04.35.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Jul 2022 04:35:51 -0700 (PDT) From: Christian Marangi To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Greg Kroah-Hartman , Jens Axboe , Christian Marangi , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: [net-next PATCH v5 08/14] net: dsa: qca8k: move bridge functions to common code Date: Wed, 27 Jul 2022 13:35:17 +0200 Message-Id: <20220727113523.19742-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220727113523.19742-1-ansuelsmth@gmail.com> References: <20220727113523.19742-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The same bridge functions are used by drivers based on qca8k family switch. Move them to common code to make them accessible also by other drivers. While at it also drop unnecessary qca8k_priv cast for void pointers. Signed-off-by: Christian Marangi Reviewed-by: Vladimir Oltean Reviewed-by: Florian Fainelli --- drivers/net/dsa/qca/qca8k-8xxx.c | 93 ------------------------------ drivers/net/dsa/qca/qca8k-common.c | 93 ++++++++++++++++++++++++++++++ drivers/net/dsa/qca/qca8k.h | 9 +++ 3 files changed, 102 insertions(+), 93 deletions(-) diff --git a/drivers/net/dsa/qca/qca8k-8xxx.c b/drivers/net/dsa/qca/qca8k-8= xxx.c index 9729aabbd83d..11d3116733af 100644 --- a/drivers/net/dsa/qca/qca8k-8xxx.c +++ b/drivers/net/dsa/qca/qca8k-8xxx.c @@ -1898,99 +1898,6 @@ qca8k_get_ethtool_stats_eth(struct dsa_switch *ds, i= nt port, u64 *data) return ret; } =20 -static void -qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) -{ - struct qca8k_priv *priv =3D (struct qca8k_priv *)ds->priv; - u32 stp_state; - - switch (state) { - case BR_STATE_DISABLED: - stp_state =3D QCA8K_PORT_LOOKUP_STATE_DISABLED; - break; - case BR_STATE_BLOCKING: - stp_state =3D QCA8K_PORT_LOOKUP_STATE_BLOCKING; - break; - case BR_STATE_LISTENING: - stp_state =3D QCA8K_PORT_LOOKUP_STATE_LISTENING; - break; - case BR_STATE_LEARNING: - stp_state =3D QCA8K_PORT_LOOKUP_STATE_LEARNING; - break; - case BR_STATE_FORWARDING: - default: - stp_state =3D QCA8K_PORT_LOOKUP_STATE_FORWARD; - break; - } - - qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), - QCA8K_PORT_LOOKUP_STATE_MASK, stp_state); -} - -static int qca8k_port_bridge_join(struct dsa_switch *ds, int port, - struct dsa_bridge bridge, - bool *tx_fwd_offload, - struct netlink_ext_ack *extack) -{ - struct qca8k_priv *priv =3D (struct qca8k_priv *)ds->priv; - int port_mask, cpu_port; - int i, ret; - - cpu_port =3D dsa_to_port(ds, port)->cpu_dp->index; - port_mask =3D BIT(cpu_port); - - for (i =3D 0; i < QCA8K_NUM_PORTS; i++) { - if (dsa_is_cpu_port(ds, i)) - continue; - if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) - continue; - /* Add this port to the portvlan mask of the other ports - * in the bridge - */ - ret =3D regmap_set_bits(priv->regmap, - QCA8K_PORT_LOOKUP_CTRL(i), - BIT(port)); - if (ret) - return ret; - if (i !=3D port) - port_mask |=3D BIT(i); - } - - /* Add all other ports to this ports portvlan mask */ - ret =3D qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), - QCA8K_PORT_LOOKUP_MEMBER, port_mask); - - return ret; -} - -static void qca8k_port_bridge_leave(struct dsa_switch *ds, int port, - struct dsa_bridge bridge) -{ - struct qca8k_priv *priv =3D (struct qca8k_priv *)ds->priv; - int cpu_port, i; - - cpu_port =3D dsa_to_port(ds, port)->cpu_dp->index; - - for (i =3D 0; i < QCA8K_NUM_PORTS; i++) { - if (dsa_is_cpu_port(ds, i)) - continue; - if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) - continue; - /* Remove this port to the portvlan mask of the other ports - * in the bridge - */ - regmap_clear_bits(priv->regmap, - QCA8K_PORT_LOOKUP_CTRL(i), - BIT(port)); - } - - /* Set the cpu port to be the only one in the portvlan mask of - * this port - */ - qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), - QCA8K_PORT_LOOKUP_MEMBER, BIT(cpu_port)); -} - static void qca8k_port_fast_age(struct dsa_switch *ds, int port) { diff --git a/drivers/net/dsa/qca/qca8k-common.c b/drivers/net/dsa/qca/qca8k= -common.c index c662fdbae51f..13069c9ba3e6 100644 --- a/drivers/net/dsa/qca/qca8k-common.c +++ b/drivers/net/dsa/qca/qca8k-common.c @@ -8,6 +8,7 @@ =20 #include #include +#include =20 #include "qca8k.h" =20 @@ -275,3 +276,95 @@ int qca8k_get_mac_eee(struct dsa_switch *ds, int port, /* Nothing to do on the port's MAC */ return 0; } + +void qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) +{ + struct qca8k_priv *priv =3D ds->priv; + u32 stp_state; + + switch (state) { + case BR_STATE_DISABLED: + stp_state =3D QCA8K_PORT_LOOKUP_STATE_DISABLED; + break; + case BR_STATE_BLOCKING: + stp_state =3D QCA8K_PORT_LOOKUP_STATE_BLOCKING; + break; + case BR_STATE_LISTENING: + stp_state =3D QCA8K_PORT_LOOKUP_STATE_LISTENING; + break; + case BR_STATE_LEARNING: + stp_state =3D QCA8K_PORT_LOOKUP_STATE_LEARNING; + break; + case BR_STATE_FORWARDING: + default: + stp_state =3D QCA8K_PORT_LOOKUP_STATE_FORWARD; + break; + } + + qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), + QCA8K_PORT_LOOKUP_STATE_MASK, stp_state); +} + +int qca8k_port_bridge_join(struct dsa_switch *ds, int port, + struct dsa_bridge bridge, + bool *tx_fwd_offload, + struct netlink_ext_ack *extack) +{ + struct qca8k_priv *priv =3D ds->priv; + int port_mask, cpu_port; + int i, ret; + + cpu_port =3D dsa_to_port(ds, port)->cpu_dp->index; + port_mask =3D BIT(cpu_port); + + for (i =3D 0; i < QCA8K_NUM_PORTS; i++) { + if (dsa_is_cpu_port(ds, i)) + continue; + if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) + continue; + /* Add this port to the portvlan mask of the other ports + * in the bridge + */ + ret =3D regmap_set_bits(priv->regmap, + QCA8K_PORT_LOOKUP_CTRL(i), + BIT(port)); + if (ret) + return ret; + if (i !=3D port) + port_mask |=3D BIT(i); + } + + /* Add all other ports to this ports portvlan mask */ + ret =3D qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), + QCA8K_PORT_LOOKUP_MEMBER, port_mask); + + return ret; +} + +void qca8k_port_bridge_leave(struct dsa_switch *ds, int port, + struct dsa_bridge bridge) +{ + struct qca8k_priv *priv =3D ds->priv; + int cpu_port, i; + + cpu_port =3D dsa_to_port(ds, port)->cpu_dp->index; + + for (i =3D 0; i < QCA8K_NUM_PORTS; i++) { + if (dsa_is_cpu_port(ds, i)) + continue; + if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) + continue; + /* Remove this port to the portvlan mask of the other ports + * in the bridge + */ + regmap_clear_bits(priv->regmap, + QCA8K_PORT_LOOKUP_CTRL(i), + BIT(port)); + } + + /* Set the cpu port to be the only one in the portvlan mask of + * this port + */ + qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), + QCA8K_PORT_LOOKUP_MEMBER, BIT(cpu_port)); +} diff --git a/drivers/net/dsa/qca/qca8k.h b/drivers/net/dsa/qca/qca8k.h index c73cbdfc6ac6..edb2b23a02b9 100644 --- a/drivers/net/dsa/qca/qca8k.h +++ b/drivers/net/dsa/qca/qca8k.h @@ -454,4 +454,13 @@ int qca8k_get_sset_count(struct dsa_switch *ds, int po= rt, int sset); int qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee = *eee); int qca8k_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee = *e); =20 +/* Common bridge function */ +void qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); +int qca8k_port_bridge_join(struct dsa_switch *ds, int port, + struct dsa_bridge bridge, + bool *tx_fwd_offload, + struct netlink_ext_ack *extack); +void qca8k_port_bridge_leave(struct dsa_switch *ds, int port, + struct dsa_bridge bridge); + #endif /* __QCA8K_H */ --=20 2.36.1 From nobody Wed Apr 15 03:04:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3C5EC04A68 for ; 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[94.17.105.182]) by smtp.googlemail.com with ESMTPSA id p25-20020aa7cc99000000b0043ca6fb7e7dsm1334056edt.68.2022.07.27.04.35.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Jul 2022 04:35:53 -0700 (PDT) From: Christian Marangi To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Greg Kroah-Hartman , Jens Axboe , Christian Marangi , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: [net-next PATCH v5 09/14] net: dsa: qca8k: move set age/MTU/port enable/disable functions to common code Date: Wed, 27 Jul 2022 13:35:18 +0200 Message-Id: <20220727113523.19742-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220727113523.19742-1-ansuelsmth@gmail.com> References: <20220727113523.19742-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The same set age, MTU and port enable/disable function are used by driver based on qca8k family switch. Move them to common code to make them accessible also by other drivers. While at it also drop unnecessary qca8k_priv cast for void pointers. Signed-off-by: Christian Marangi Reviewed-by: Florian Fainelli Reviewed-by: Vladimir Oltean --- drivers/net/dsa/qca/qca8k-8xxx.c | 88 ------------------------------ drivers/net/dsa/qca/qca8k-common.c | 85 +++++++++++++++++++++++++++++ drivers/net/dsa/qca/qca8k.h | 12 ++++ 3 files changed, 97 insertions(+), 88 deletions(-) diff --git a/drivers/net/dsa/qca/qca8k-8xxx.c b/drivers/net/dsa/qca/qca8k-8= xxx.c index 11d3116733af..1815863502c9 100644 --- a/drivers/net/dsa/qca/qca8k-8xxx.c +++ b/drivers/net/dsa/qca/qca8k-8xxx.c @@ -1908,94 +1908,6 @@ qca8k_port_fast_age(struct dsa_switch *ds, int port) mutex_unlock(&priv->reg_mutex); } =20 -static int -qca8k_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) -{ - struct qca8k_priv *priv =3D ds->priv; - unsigned int secs =3D msecs / 1000; - u32 val; - - /* AGE_TIME reg is set in 7s step */ - val =3D secs / 7; - - /* Handle case with 0 as val to NOT disable - * learning - */ - if (!val) - val =3D 1; - - return regmap_update_bits(priv->regmap, QCA8K_REG_ATU_CTRL, QCA8K_ATU_AGE= _TIME_MASK, - QCA8K_ATU_AGE_TIME(val)); -} - -static int -qca8k_port_enable(struct dsa_switch *ds, int port, - struct phy_device *phy) -{ - struct qca8k_priv *priv =3D (struct qca8k_priv *)ds->priv; - - qca8k_port_set_status(priv, port, 1); - priv->port_enabled_map |=3D BIT(port); - - if (dsa_is_user_port(ds, port)) - phy_support_asym_pause(phy); - - return 0; -} - -static void -qca8k_port_disable(struct dsa_switch *ds, int port) -{ - struct qca8k_priv *priv =3D (struct qca8k_priv *)ds->priv; - - qca8k_port_set_status(priv, port, 0); - priv->port_enabled_map &=3D ~BIT(port); -} - -static int -qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) -{ - struct qca8k_priv *priv =3D ds->priv; - int ret; - - /* We have only have a general MTU setting. - * DSA always set the CPU port's MTU to the largest MTU of the slave - * ports. - * Setting MTU just for the CPU port is sufficient to correctly set a - * value for every port. - */ - if (!dsa_is_cpu_port(ds, port)) - return 0; - - /* To change the MAX_FRAME_SIZE the cpu ports must be off or - * the switch panics. - * Turn off both cpu ports before applying the new value to prevent - * this. - */ - if (priv->port_enabled_map & BIT(0)) - qca8k_port_set_status(priv, 0, 0); - - if (priv->port_enabled_map & BIT(6)) - qca8k_port_set_status(priv, 6, 0); - - /* Include L2 header / FCS length */ - ret =3D qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, new_mtu + ETH_HLEN + ETH_= FCS_LEN); - - if (priv->port_enabled_map & BIT(0)) - qca8k_port_set_status(priv, 0, 1); - - if (priv->port_enabled_map & BIT(6)) - qca8k_port_set_status(priv, 6, 1); - - return ret; -} - -static int -qca8k_port_max_mtu(struct dsa_switch *ds, int port) -{ - return QCA8K_MAX_MTU; -} - static int qca8k_port_fdb_insert(struct qca8k_priv *priv, const u8 *addr, u16 port_mask, u16 vid) diff --git a/drivers/net/dsa/qca/qca8k-common.c b/drivers/net/dsa/qca/qca8k= -common.c index 13069c9ba3e6..e25df4b23b9a 100644 --- a/drivers/net/dsa/qca/qca8k-common.c +++ b/drivers/net/dsa/qca/qca8k-common.c @@ -368,3 +368,88 @@ void qca8k_port_bridge_leave(struct dsa_switch *ds, in= t port, qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), QCA8K_PORT_LOOKUP_MEMBER, BIT(cpu_port)); } + +int qca8k_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) +{ + struct qca8k_priv *priv =3D ds->priv; + unsigned int secs =3D msecs / 1000; + u32 val; + + /* AGE_TIME reg is set in 7s step */ + val =3D secs / 7; + + /* Handle case with 0 as val to NOT disable + * learning + */ + if (!val) + val =3D 1; + + return regmap_update_bits(priv->regmap, QCA8K_REG_ATU_CTRL, + QCA8K_ATU_AGE_TIME_MASK, + QCA8K_ATU_AGE_TIME(val)); +} + +int qca8k_port_enable(struct dsa_switch *ds, int port, + struct phy_device *phy) +{ + struct qca8k_priv *priv =3D ds->priv; + + qca8k_port_set_status(priv, port, 1); + priv->port_enabled_map |=3D BIT(port); + + if (dsa_is_user_port(ds, port)) + phy_support_asym_pause(phy); + + return 0; +} + +void qca8k_port_disable(struct dsa_switch *ds, int port) +{ + struct qca8k_priv *priv =3D ds->priv; + + qca8k_port_set_status(priv, port, 0); + priv->port_enabled_map &=3D ~BIT(port); +} + +int qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) +{ + struct qca8k_priv *priv =3D ds->priv; + int ret; + + /* We have only have a general MTU setting. + * DSA always set the CPU port's MTU to the largest MTU of the slave + * ports. + * Setting MTU just for the CPU port is sufficient to correctly set a + * value for every port. + */ + if (!dsa_is_cpu_port(ds, port)) + return 0; + + /* To change the MAX_FRAME_SIZE the cpu ports must be off or + * the switch panics. + * Turn off both cpu ports before applying the new value to prevent + * this. + */ + if (priv->port_enabled_map & BIT(0)) + qca8k_port_set_status(priv, 0, 0); + + if (priv->port_enabled_map & BIT(6)) + qca8k_port_set_status(priv, 6, 0); + + /* Include L2 header / FCS length */ + ret =3D qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, new_mtu + + ETH_HLEN + ETH_FCS_LEN); + + if (priv->port_enabled_map & BIT(0)) + qca8k_port_set_status(priv, 0, 1); + + if (priv->port_enabled_map & BIT(6)) + qca8k_port_set_status(priv, 6, 1); + + return ret; +} + +int qca8k_port_max_mtu(struct dsa_switch *ds, int port) +{ + return QCA8K_MAX_MTU; +} diff --git a/drivers/net/dsa/qca/qca8k.h b/drivers/net/dsa/qca/qca8k.h index edb2b23a02b9..e7d4df253b8c 100644 --- a/drivers/net/dsa/qca/qca8k.h +++ b/drivers/net/dsa/qca/qca8k.h @@ -463,4 +463,16 @@ int qca8k_port_bridge_join(struct dsa_switch *ds, int = port, void qca8k_port_bridge_leave(struct dsa_switch *ds, int port, struct dsa_bridge bridge); =20 +/* Common port enable/disable function */ +int qca8k_port_enable(struct dsa_switch *ds, int port, + struct phy_device *phy); +void qca8k_port_disable(struct dsa_switch *ds, int port); + +/* Common MTU function */ +int qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu); +int qca8k_port_max_mtu(struct dsa_switch *ds, int port); + +/* Common fast age function */ +int qca8k_set_ageing_time(struct dsa_switch *ds, unsigned int msecs); + #endif /* __QCA8K_H */ --=20 2.36.1 From nobody Wed Apr 15 03:04:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7F64C19F29 for ; Wed, 27 Jul 2022 11:36:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232523AbiG0Lgx (ORCPT ); Wed, 27 Jul 2022 07:36:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52822 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232147AbiG0Lg3 (ORCPT ); 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[94.17.105.182]) by smtp.googlemail.com with ESMTPSA id p25-20020aa7cc99000000b0043ca6fb7e7dsm1334056edt.68.2022.07.27.04.35.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Jul 2022 04:35:54 -0700 (PDT) From: Christian Marangi To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Greg Kroah-Hartman , Jens Axboe , Christian Marangi , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: [net-next PATCH v5 10/14] net: dsa: qca8k: move port FDB/MDB function to common code Date: Wed, 27 Jul 2022 13:35:19 +0200 Message-Id: <20220727113523.19742-11-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220727113523.19742-1-ansuelsmth@gmail.com> References: <20220727113523.19742-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The same port FDB/MDB function are used by drivers based on qca8k family switch. Move them to common code to make them accessible also by other drivers. Also drop bulk read/write functions and make them static Signed-off-by: Christian Marangi Reviewed-by: Florian Fainelli Reviewed-by: Vladimir Oltean --- drivers/net/dsa/qca/qca8k-8xxx.c | 306 ----------------------------- drivers/net/dsa/qca/qca8k-common.c | 297 +++++++++++++++++++++++++++- drivers/net/dsa/qca/qca8k.h | 25 ++- 3 files changed, 317 insertions(+), 311 deletions(-) diff --git a/drivers/net/dsa/qca/qca8k-8xxx.c b/drivers/net/dsa/qca/qca8k-8= xxx.c index 1815863502c9..bf4dd1cd0f9d 100644 --- a/drivers/net/dsa/qca/qca8k-8xxx.c +++ b/drivers/net/dsa/qca/qca8k-8xxx.c @@ -441,217 +441,6 @@ static struct regmap_config qca8k_regmap_config =3D { .cache_type =3D REGCACHE_NONE, /* Explicitly disable CACHE */ }; =20 -static int -qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb) -{ - u32 reg[3]; - int ret; - - /* load the ARL table into an array */ - ret =3D qca8k_bulk_read(priv, QCA8K_REG_ATU_DATA0, reg, sizeof(reg)); - if (ret) - return ret; - - /* vid - 83:72 */ - fdb->vid =3D FIELD_GET(QCA8K_ATU_VID_MASK, reg[2]); - /* aging - 67:64 */ - fdb->aging =3D FIELD_GET(QCA8K_ATU_STATUS_MASK, reg[2]); - /* portmask - 54:48 */ - fdb->port_mask =3D FIELD_GET(QCA8K_ATU_PORT_MASK, reg[1]); - /* mac - 47:0 */ - fdb->mac[0] =3D FIELD_GET(QCA8K_ATU_ADDR0_MASK, reg[1]); - fdb->mac[1] =3D FIELD_GET(QCA8K_ATU_ADDR1_MASK, reg[1]); - fdb->mac[2] =3D FIELD_GET(QCA8K_ATU_ADDR2_MASK, reg[0]); - fdb->mac[3] =3D FIELD_GET(QCA8K_ATU_ADDR3_MASK, reg[0]); - fdb->mac[4] =3D FIELD_GET(QCA8K_ATU_ADDR4_MASK, reg[0]); - fdb->mac[5] =3D FIELD_GET(QCA8K_ATU_ADDR5_MASK, reg[0]); - - return 0; -} - -static void -qca8k_fdb_write(struct qca8k_priv *priv, u16 vid, u8 port_mask, const u8 *= mac, - u8 aging) -{ - u32 reg[3] =3D { 0 }; - - /* vid - 83:72 */ - reg[2] =3D FIELD_PREP(QCA8K_ATU_VID_MASK, vid); - /* aging - 67:64 */ - reg[2] |=3D FIELD_PREP(QCA8K_ATU_STATUS_MASK, aging); - /* portmask - 54:48 */ - reg[1] =3D FIELD_PREP(QCA8K_ATU_PORT_MASK, port_mask); - /* mac - 47:0 */ - reg[1] |=3D FIELD_PREP(QCA8K_ATU_ADDR0_MASK, mac[0]); - reg[1] |=3D FIELD_PREP(QCA8K_ATU_ADDR1_MASK, mac[1]); - reg[0] |=3D FIELD_PREP(QCA8K_ATU_ADDR2_MASK, mac[2]); - reg[0] |=3D FIELD_PREP(QCA8K_ATU_ADDR3_MASK, mac[3]); - reg[0] |=3D FIELD_PREP(QCA8K_ATU_ADDR4_MASK, mac[4]); - reg[0] |=3D FIELD_PREP(QCA8K_ATU_ADDR5_MASK, mac[5]); - - /* load the array into the ARL table */ - qca8k_bulk_write(priv, QCA8K_REG_ATU_DATA0, reg, sizeof(reg)); -} - -static int -qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port) -{ - u32 reg; - int ret; - - /* Set the command and FDB index */ - reg =3D QCA8K_ATU_FUNC_BUSY; - reg |=3D cmd; - if (port >=3D 0) { - reg |=3D QCA8K_ATU_FUNC_PORT_EN; - reg |=3D FIELD_PREP(QCA8K_ATU_FUNC_PORT_MASK, port); - } - - /* Write the function register triggering the table access */ - ret =3D qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg); - if (ret) - return ret; - - /* wait for completion */ - ret =3D qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY); - if (ret) - return ret; - - /* Check for table full violation when adding an entry */ - if (cmd =3D=3D QCA8K_FDB_LOAD) { - ret =3D qca8k_read(priv, QCA8K_REG_ATU_FUNC, ®); - if (ret < 0) - return ret; - if (reg & QCA8K_ATU_FUNC_FULL) - return -1; - } - - return 0; -} - -static int -qca8k_fdb_next(struct qca8k_priv *priv, struct qca8k_fdb *fdb, int port) -{ - int ret; - - qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging); - ret =3D qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port); - if (ret < 0) - return ret; - - return qca8k_fdb_read(priv, fdb); -} - -static int -qca8k_fdb_add(struct qca8k_priv *priv, const u8 *mac, u16 port_mask, - u16 vid, u8 aging) -{ - int ret; - - mutex_lock(&priv->reg_mutex); - qca8k_fdb_write(priv, vid, port_mask, mac, aging); - ret =3D qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1); - mutex_unlock(&priv->reg_mutex); - - return ret; -} - -static int -qca8k_fdb_del(struct qca8k_priv *priv, const u8 *mac, u16 port_mask, u16 v= id) -{ - int ret; - - mutex_lock(&priv->reg_mutex); - qca8k_fdb_write(priv, vid, port_mask, mac, 0); - ret =3D qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1); - mutex_unlock(&priv->reg_mutex); - - return ret; -} - -static void -qca8k_fdb_flush(struct qca8k_priv *priv) -{ - mutex_lock(&priv->reg_mutex); - qca8k_fdb_access(priv, QCA8K_FDB_FLUSH, -1); - mutex_unlock(&priv->reg_mutex); -} - -static int -qca8k_fdb_search_and_insert(struct qca8k_priv *priv, u8 port_mask, - const u8 *mac, u16 vid) -{ - struct qca8k_fdb fdb =3D { 0 }; - int ret; - - mutex_lock(&priv->reg_mutex); - - qca8k_fdb_write(priv, vid, 0, mac, 0); - ret =3D qca8k_fdb_access(priv, QCA8K_FDB_SEARCH, -1); - if (ret < 0) - goto exit; - - ret =3D qca8k_fdb_read(priv, &fdb); - if (ret < 0) - goto exit; - - /* Rule exist. Delete first */ - if (!fdb.aging) { - ret =3D qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1); - if (ret) - goto exit; - } - - /* Add port to fdb portmask */ - fdb.port_mask |=3D port_mask; - - qca8k_fdb_write(priv, vid, fdb.port_mask, mac, fdb.aging); - ret =3D qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1); - -exit: - mutex_unlock(&priv->reg_mutex); - return ret; -} - -static int -qca8k_fdb_search_and_del(struct qca8k_priv *priv, u8 port_mask, - const u8 *mac, u16 vid) -{ - struct qca8k_fdb fdb =3D { 0 }; - int ret; - - mutex_lock(&priv->reg_mutex); - - qca8k_fdb_write(priv, vid, 0, mac, 0); - ret =3D qca8k_fdb_access(priv, QCA8K_FDB_SEARCH, -1); - if (ret < 0) - goto exit; - - /* Rule doesn't exist. Why delete? */ - if (!fdb.aging) { - ret =3D -EINVAL; - goto exit; - } - - ret =3D qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1); - if (ret) - goto exit; - - /* Only port in the rule is this port. Don't re insert */ - if (fdb.port_mask =3D=3D port_mask) - goto exit; - - /* Remove port from port mask */ - fdb.port_mask &=3D ~port_mask; - - qca8k_fdb_write(priv, vid, fdb.port_mask, mac, fdb.aging); - ret =3D qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1); - -exit: - mutex_unlock(&priv->reg_mutex); - return ret; -} - static int qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vi= d) { @@ -1898,101 +1687,6 @@ qca8k_get_ethtool_stats_eth(struct dsa_switch *ds, = int port, u64 *data) return ret; } =20 -static void -qca8k_port_fast_age(struct dsa_switch *ds, int port) -{ - struct qca8k_priv *priv =3D ds->priv; - - mutex_lock(&priv->reg_mutex); - qca8k_fdb_access(priv, QCA8K_FDB_FLUSH_PORT, port); - mutex_unlock(&priv->reg_mutex); -} - -static int -qca8k_port_fdb_insert(struct qca8k_priv *priv, const u8 *addr, - u16 port_mask, u16 vid) -{ - /* Set the vid to the port vlan id if no vid is set */ - if (!vid) - vid =3D QCA8K_PORT_VID_DEF; - - return qca8k_fdb_add(priv, addr, port_mask, vid, - QCA8K_ATU_STATUS_STATIC); -} - -static int -qca8k_port_fdb_add(struct dsa_switch *ds, int port, - const unsigned char *addr, u16 vid, - struct dsa_db db) -{ - struct qca8k_priv *priv =3D (struct qca8k_priv *)ds->priv; - u16 port_mask =3D BIT(port); - - return qca8k_port_fdb_insert(priv, addr, port_mask, vid); -} - -static int -qca8k_port_fdb_del(struct dsa_switch *ds, int port, - const unsigned char *addr, u16 vid, - struct dsa_db db) -{ - struct qca8k_priv *priv =3D (struct qca8k_priv *)ds->priv; - u16 port_mask =3D BIT(port); - - if (!vid) - vid =3D QCA8K_PORT_VID_DEF; - - return qca8k_fdb_del(priv, addr, port_mask, vid); -} - -static int -qca8k_port_fdb_dump(struct dsa_switch *ds, int port, - dsa_fdb_dump_cb_t *cb, void *data) -{ - struct qca8k_priv *priv =3D (struct qca8k_priv *)ds->priv; - struct qca8k_fdb _fdb =3D { 0 }; - int cnt =3D QCA8K_NUM_FDB_RECORDS; - bool is_static; - int ret =3D 0; - - mutex_lock(&priv->reg_mutex); - while (cnt-- && !qca8k_fdb_next(priv, &_fdb, port)) { - if (!_fdb.aging) - break; - is_static =3D (_fdb.aging =3D=3D QCA8K_ATU_STATUS_STATIC); - ret =3D cb(_fdb.mac, _fdb.vid, is_static, data); - if (ret) - break; - } - mutex_unlock(&priv->reg_mutex); - - return 0; -} - -static int -qca8k_port_mdb_add(struct dsa_switch *ds, int port, - const struct switchdev_obj_port_mdb *mdb, - struct dsa_db db) -{ - struct qca8k_priv *priv =3D ds->priv; - const u8 *addr =3D mdb->addr; - u16 vid =3D mdb->vid; - - return qca8k_fdb_search_and_insert(priv, BIT(port), addr, vid); -} - -static int -qca8k_port_mdb_del(struct dsa_switch *ds, int port, - const struct switchdev_obj_port_mdb *mdb, - struct dsa_db db) -{ - struct qca8k_priv *priv =3D ds->priv; - const u8 *addr =3D mdb->addr; - u16 vid =3D mdb->vid; - - return qca8k_fdb_search_and_del(priv, BIT(port), addr, vid); -} - static int qca8k_port_mirror_add(struct dsa_switch *ds, int port, struct dsa_mall_mirror_tc_entry *mirror, diff --git a/drivers/net/dsa/qca/qca8k-common.c b/drivers/net/dsa/qca/qca8k= -common.c index e25df4b23b9a..8e92837781ee 100644 --- a/drivers/net/dsa/qca/qca8k-common.c +++ b/drivers/net/dsa/qca/qca8k-common.c @@ -102,7 +102,7 @@ const struct regmap_access_table qca8k_readable_table = =3D { }; =20 /* TODO: remove these extra ops when we can support regmap bulk read/write= */ -int qca8k_bulk_read(struct qca8k_priv *priv, u32 reg, u32 *val, int len) +static int qca8k_bulk_read(struct qca8k_priv *priv, u32 reg, u32 *val, int= len) { int i, count =3D len / sizeof(u32), ret; =20 @@ -120,7 +120,7 @@ int qca8k_bulk_read(struct qca8k_priv *priv, u32 reg, u= 32 *val, int len) } =20 /* TODO: remove these extra ops when we can support regmap bulk read/write= */ -int qca8k_bulk_write(struct qca8k_priv *priv, u32 reg, u32 *val, int len) +static int qca8k_bulk_write(struct qca8k_priv *priv, u32 reg, u32 *val, in= t len) { int i, count =3D len / sizeof(u32), ret; u32 tmp; @@ -148,6 +148,211 @@ int qca8k_busy_wait(struct qca8k_priv *priv, u32 reg,= u32 mask) QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC); } =20 +static int qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb) +{ + u32 reg[3]; + int ret; + + /* load the ARL table into an array */ + ret =3D qca8k_bulk_read(priv, QCA8K_REG_ATU_DATA0, reg, sizeof(reg)); + if (ret) + return ret; + + /* vid - 83:72 */ + fdb->vid =3D FIELD_GET(QCA8K_ATU_VID_MASK, reg[2]); + /* aging - 67:64 */ + fdb->aging =3D FIELD_GET(QCA8K_ATU_STATUS_MASK, reg[2]); + /* portmask - 54:48 */ + fdb->port_mask =3D FIELD_GET(QCA8K_ATU_PORT_MASK, reg[1]); + /* mac - 47:0 */ + fdb->mac[0] =3D FIELD_GET(QCA8K_ATU_ADDR0_MASK, reg[1]); + fdb->mac[1] =3D FIELD_GET(QCA8K_ATU_ADDR1_MASK, reg[1]); + fdb->mac[2] =3D FIELD_GET(QCA8K_ATU_ADDR2_MASK, reg[0]); + fdb->mac[3] =3D FIELD_GET(QCA8K_ATU_ADDR3_MASK, reg[0]); + fdb->mac[4] =3D FIELD_GET(QCA8K_ATU_ADDR4_MASK, reg[0]); + fdb->mac[5] =3D FIELD_GET(QCA8K_ATU_ADDR5_MASK, reg[0]); + + return 0; +} + +static void qca8k_fdb_write(struct qca8k_priv *priv, u16 vid, u8 port_mask, + const u8 *mac, u8 aging) +{ + u32 reg[3] =3D { 0 }; + + /* vid - 83:72 */ + reg[2] =3D FIELD_PREP(QCA8K_ATU_VID_MASK, vid); + /* aging - 67:64 */ + reg[2] |=3D FIELD_PREP(QCA8K_ATU_STATUS_MASK, aging); + /* portmask - 54:48 */ + reg[1] =3D FIELD_PREP(QCA8K_ATU_PORT_MASK, port_mask); + /* mac - 47:0 */ + reg[1] |=3D FIELD_PREP(QCA8K_ATU_ADDR0_MASK, mac[0]); + reg[1] |=3D FIELD_PREP(QCA8K_ATU_ADDR1_MASK, mac[1]); + reg[0] |=3D FIELD_PREP(QCA8K_ATU_ADDR2_MASK, mac[2]); + reg[0] |=3D FIELD_PREP(QCA8K_ATU_ADDR3_MASK, mac[3]); + reg[0] |=3D FIELD_PREP(QCA8K_ATU_ADDR4_MASK, mac[4]); + reg[0] |=3D FIELD_PREP(QCA8K_ATU_ADDR5_MASK, mac[5]); + + /* load the array into the ARL table */ + qca8k_bulk_write(priv, QCA8K_REG_ATU_DATA0, reg, sizeof(reg)); +} + +static int qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cm= d, + int port) +{ + u32 reg; + int ret; + + /* Set the command and FDB index */ + reg =3D QCA8K_ATU_FUNC_BUSY; + reg |=3D cmd; + if (port >=3D 0) { + reg |=3D QCA8K_ATU_FUNC_PORT_EN; + reg |=3D FIELD_PREP(QCA8K_ATU_FUNC_PORT_MASK, port); + } + + /* Write the function register triggering the table access */ + ret =3D qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg); + if (ret) + return ret; + + /* wait for completion */ + ret =3D qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY); + if (ret) + return ret; + + /* Check for table full violation when adding an entry */ + if (cmd =3D=3D QCA8K_FDB_LOAD) { + ret =3D qca8k_read(priv, QCA8K_REG_ATU_FUNC, ®); + if (ret < 0) + return ret; + if (reg & QCA8K_ATU_FUNC_FULL) + return -1; + } + + return 0; +} + +static int qca8k_fdb_next(struct qca8k_priv *priv, struct qca8k_fdb *fdb, + int port) +{ + int ret; + + qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging); + ret =3D qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port); + if (ret < 0) + return ret; + + return qca8k_fdb_read(priv, fdb); +} + +static int qca8k_fdb_add(struct qca8k_priv *priv, const u8 *mac, + u16 port_mask, u16 vid, u8 aging) +{ + int ret; + + mutex_lock(&priv->reg_mutex); + qca8k_fdb_write(priv, vid, port_mask, mac, aging); + ret =3D qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1); + mutex_unlock(&priv->reg_mutex); + + return ret; +} + +static int qca8k_fdb_del(struct qca8k_priv *priv, const u8 *mac, + u16 port_mask, u16 vid) +{ + int ret; + + mutex_lock(&priv->reg_mutex); + qca8k_fdb_write(priv, vid, port_mask, mac, 0); + ret =3D qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1); + mutex_unlock(&priv->reg_mutex); + + return ret; +} + +void qca8k_fdb_flush(struct qca8k_priv *priv) +{ + mutex_lock(&priv->reg_mutex); + qca8k_fdb_access(priv, QCA8K_FDB_FLUSH, -1); + mutex_unlock(&priv->reg_mutex); +} + +static int qca8k_fdb_search_and_insert(struct qca8k_priv *priv, u8 port_ma= sk, + const u8 *mac, u16 vid) +{ + struct qca8k_fdb fdb =3D { 0 }; + int ret; + + mutex_lock(&priv->reg_mutex); + + qca8k_fdb_write(priv, vid, 0, mac, 0); + ret =3D qca8k_fdb_access(priv, QCA8K_FDB_SEARCH, -1); + if (ret < 0) + goto exit; + + ret =3D qca8k_fdb_read(priv, &fdb); + if (ret < 0) + goto exit; + + /* Rule exist. Delete first */ + if (!fdb.aging) { + ret =3D qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1); + if (ret) + goto exit; + } + + /* Add port to fdb portmask */ + fdb.port_mask |=3D port_mask; + + qca8k_fdb_write(priv, vid, fdb.port_mask, mac, fdb.aging); + ret =3D qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1); + +exit: + mutex_unlock(&priv->reg_mutex); + return ret; +} + +static int qca8k_fdb_search_and_del(struct qca8k_priv *priv, u8 port_mask, + const u8 *mac, u16 vid) +{ + struct qca8k_fdb fdb =3D { 0 }; + int ret; + + mutex_lock(&priv->reg_mutex); + + qca8k_fdb_write(priv, vid, 0, mac, 0); + ret =3D qca8k_fdb_access(priv, QCA8K_FDB_SEARCH, -1); + if (ret < 0) + goto exit; + + /* Rule doesn't exist. Why delete? */ + if (!fdb.aging) { + ret =3D -EINVAL; + goto exit; + } + + ret =3D qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1); + if (ret) + goto exit; + + /* Only port in the rule is this port. Don't re insert */ + if (fdb.port_mask =3D=3D port_mask) + goto exit; + + /* Remove port from port mask */ + fdb.port_mask &=3D ~port_mask; + + qca8k_fdb_write(priv, vid, fdb.port_mask, mac, fdb.aging); + ret =3D qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1); + +exit: + mutex_unlock(&priv->reg_mutex); + return ret; +} + int qca8k_mib_init(struct qca8k_priv *priv) { int ret; @@ -369,6 +574,15 @@ void qca8k_port_bridge_leave(struct dsa_switch *ds, in= t port, QCA8K_PORT_LOOKUP_MEMBER, BIT(cpu_port)); } =20 +void qca8k_port_fast_age(struct dsa_switch *ds, int port) +{ + struct qca8k_priv *priv =3D ds->priv; + + mutex_lock(&priv->reg_mutex); + qca8k_fdb_access(priv, QCA8K_FDB_FLUSH_PORT, port); + mutex_unlock(&priv->reg_mutex); +} + int qca8k_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) { struct qca8k_priv *priv =3D ds->priv; @@ -453,3 +667,82 @@ int qca8k_port_max_mtu(struct dsa_switch *ds, int port) { return QCA8K_MAX_MTU; } + +int qca8k_port_fdb_insert(struct qca8k_priv *priv, const u8 *addr, + u16 port_mask, u16 vid) +{ + /* Set the vid to the port vlan id if no vid is set */ + if (!vid) + vid =3D QCA8K_PORT_VID_DEF; + + return qca8k_fdb_add(priv, addr, port_mask, vid, + QCA8K_ATU_STATUS_STATIC); +} + +int qca8k_port_fdb_add(struct dsa_switch *ds, int port, + const unsigned char *addr, u16 vid, + struct dsa_db db) +{ + struct qca8k_priv *priv =3D (struct qca8k_priv *)ds->priv; + u16 port_mask =3D BIT(port); + + return qca8k_port_fdb_insert(priv, addr, port_mask, vid); +} + +int qca8k_port_fdb_del(struct dsa_switch *ds, int port, + const unsigned char *addr, u16 vid, + struct dsa_db db) +{ + struct qca8k_priv *priv =3D (struct qca8k_priv *)ds->priv; + u16 port_mask =3D BIT(port); + + if (!vid) + vid =3D QCA8K_PORT_VID_DEF; + + return qca8k_fdb_del(priv, addr, port_mask, vid); +} + +int qca8k_port_fdb_dump(struct dsa_switch *ds, int port, + dsa_fdb_dump_cb_t *cb, void *data) +{ + struct qca8k_priv *priv =3D (struct qca8k_priv *)ds->priv; + struct qca8k_fdb _fdb =3D { 0 }; + int cnt =3D QCA8K_NUM_FDB_RECORDS; + bool is_static; + int ret =3D 0; + + mutex_lock(&priv->reg_mutex); + while (cnt-- && !qca8k_fdb_next(priv, &_fdb, port)) { + if (!_fdb.aging) + break; + is_static =3D (_fdb.aging =3D=3D QCA8K_ATU_STATUS_STATIC); + ret =3D cb(_fdb.mac, _fdb.vid, is_static, data); + if (ret) + break; + } + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +int qca8k_port_mdb_add(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_mdb *mdb, + struct dsa_db db) +{ + struct qca8k_priv *priv =3D ds->priv; + const u8 *addr =3D mdb->addr; + u16 vid =3D mdb->vid; + + return qca8k_fdb_search_and_insert(priv, BIT(port), addr, vid); +} + +int qca8k_port_mdb_del(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_mdb *mdb, + struct dsa_db db) +{ + struct qca8k_priv *priv =3D ds->priv; + const u8 *addr =3D mdb->addr; + u16 vid =3D mdb->vid; + + return qca8k_fdb_search_and_del(priv, BIT(port), addr, vid); +} diff --git a/drivers/net/dsa/qca/qca8k.h b/drivers/net/dsa/qca/qca8k.h index e7d4df253b8c..9da7928de83c 100644 --- a/drivers/net/dsa/qca/qca8k.h +++ b/drivers/net/dsa/qca/qca8k.h @@ -438,11 +438,9 @@ int qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *= val); int qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val); int qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val); =20 -int qca8k_bulk_read(struct qca8k_priv *priv, u32 reg, u32 *val, int len); -int qca8k_bulk_write(struct qca8k_priv *priv, u32 reg, u32 *val, int len); - /* Common ops function */ int qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask); +void qca8k_fdb_flush(struct qca8k_priv *priv); =20 /* Common ethtool stats function */ void qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uin= t8_t *data); @@ -473,6 +471,27 @@ int qca8k_port_change_mtu(struct dsa_switch *ds, int p= ort, int new_mtu); int qca8k_port_max_mtu(struct dsa_switch *ds, int port); =20 /* Common fast age function */ +void qca8k_port_fast_age(struct dsa_switch *ds, int port); int qca8k_set_ageing_time(struct dsa_switch *ds, unsigned int msecs); =20 +/* Common FDB function */ +int qca8k_port_fdb_insert(struct qca8k_priv *priv, const u8 *addr, + u16 port_mask, u16 vid); +int qca8k_port_fdb_add(struct dsa_switch *ds, int port, + const unsigned char *addr, u16 vid, + struct dsa_db db); +int qca8k_port_fdb_del(struct dsa_switch *ds, int port, + const unsigned char *addr, u16 vid, + struct dsa_db db); +int qca8k_port_fdb_dump(struct dsa_switch *ds, int port, + dsa_fdb_dump_cb_t *cb, void *data); + +/* Common MDB function */ +int qca8k_port_mdb_add(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_mdb *mdb, + struct dsa_db db); +int qca8k_port_mdb_del(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_mdb *mdb, + struct dsa_db db); + #endif /* __QCA8K_H */ --=20 2.36.1 From nobody Wed Apr 15 03:04:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E288C19F29 for ; Wed, 27 Jul 2022 11:36:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232493AbiG0Lgs (ORCPT ); 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[94.17.105.182]) by smtp.googlemail.com with ESMTPSA id p25-20020aa7cc99000000b0043ca6fb7e7dsm1334056edt.68.2022.07.27.04.35.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Jul 2022 04:35:55 -0700 (PDT) From: Christian Marangi To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Greg Kroah-Hartman , Jens Axboe , Christian Marangi , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: [net-next PATCH v5 11/14] net: dsa: qca8k: move port mirror functions to common code Date: Wed, 27 Jul 2022 13:35:20 +0200 Message-Id: <20220727113523.19742-12-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220727113523.19742-1-ansuelsmth@gmail.com> References: <20220727113523.19742-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The same port mirror functions are used by drivers based on qca8k family switch. Move them to common code to make them accessible also by other drivers. Signed-off-by: Christian Marangi Reviewed-by: Vladimir Oltean Reviewed-by: Florian Fainelli --- drivers/net/dsa/qca/qca8k-8xxx.c | 93 ------------------------------ drivers/net/dsa/qca/qca8k-common.c | 91 +++++++++++++++++++++++++++++ drivers/net/dsa/qca/qca8k.h | 7 +++ 3 files changed, 98 insertions(+), 93 deletions(-) diff --git a/drivers/net/dsa/qca/qca8k-8xxx.c b/drivers/net/dsa/qca/qca8k-8= xxx.c index bf4dd1cd0f9d..f6ea5a82da9e 100644 --- a/drivers/net/dsa/qca/qca8k-8xxx.c +++ b/drivers/net/dsa/qca/qca8k-8xxx.c @@ -1687,99 +1687,6 @@ qca8k_get_ethtool_stats_eth(struct dsa_switch *ds, i= nt port, u64 *data) return ret; } =20 -static int -qca8k_port_mirror_add(struct dsa_switch *ds, int port, - struct dsa_mall_mirror_tc_entry *mirror, - bool ingress, struct netlink_ext_ack *extack) -{ - struct qca8k_priv *priv =3D ds->priv; - int monitor_port, ret; - u32 reg, val; - - /* Check for existent entry */ - if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) - return -EEXIST; - - ret =3D regmap_read(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0, &val); - if (ret) - return ret; - - /* QCA83xx can have only one port set to mirror mode. - * Check that the correct port is requested and return error otherwise. - * When no mirror port is set, the values is set to 0xF - */ - monitor_port =3D FIELD_GET(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val); - if (monitor_port !=3D 0xF && monitor_port !=3D mirror->to_local_port) - return -EEXIST; - - /* Set the monitor port */ - val =3D FIELD_PREP(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, - mirror->to_local_port); - ret =3D regmap_update_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0, - QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val); - if (ret) - return ret; - - if (ingress) { - reg =3D QCA8K_PORT_LOOKUP_CTRL(port); - val =3D QCA8K_PORT_LOOKUP_ING_MIRROR_EN; - } else { - reg =3D QCA8K_REG_PORT_HOL_CTRL1(port); - val =3D QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN; - } - - ret =3D regmap_update_bits(priv->regmap, reg, val, val); - if (ret) - return ret; - - /* Track mirror port for tx and rx to decide when the - * mirror port has to be disabled. - */ - if (ingress) - priv->mirror_rx |=3D BIT(port); - else - priv->mirror_tx |=3D BIT(port); - - return 0; -} - -static void -qca8k_port_mirror_del(struct dsa_switch *ds, int port, - struct dsa_mall_mirror_tc_entry *mirror) -{ - struct qca8k_priv *priv =3D ds->priv; - u32 reg, val; - int ret; - - if (mirror->ingress) { - reg =3D QCA8K_PORT_LOOKUP_CTRL(port); - val =3D QCA8K_PORT_LOOKUP_ING_MIRROR_EN; - } else { - reg =3D QCA8K_REG_PORT_HOL_CTRL1(port); - val =3D QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN; - } - - ret =3D regmap_clear_bits(priv->regmap, reg, val); - if (ret) - goto err; - - if (mirror->ingress) - priv->mirror_rx &=3D ~BIT(port); - else - priv->mirror_tx &=3D ~BIT(port); - - /* No port set to send packet to mirror port. Disable mirror port */ - if (!priv->mirror_rx && !priv->mirror_tx) { - val =3D FIELD_PREP(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, 0xF); - ret =3D regmap_update_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0, - QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val); - if (ret) - goto err; - } -err: - dev_err(priv->dev, "Failed to del mirror port from %d", port); -} - static int qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filte= ring, struct netlink_ext_ack *extack) diff --git a/drivers/net/dsa/qca/qca8k-common.c b/drivers/net/dsa/qca/qca8k= -common.c index 8e92837781ee..c0a088418c20 100644 --- a/drivers/net/dsa/qca/qca8k-common.c +++ b/drivers/net/dsa/qca/qca8k-common.c @@ -746,3 +746,94 @@ int qca8k_port_mdb_del(struct dsa_switch *ds, int port, =20 return qca8k_fdb_search_and_del(priv, BIT(port), addr, vid); } + +int qca8k_port_mirror_add(struct dsa_switch *ds, int port, + struct dsa_mall_mirror_tc_entry *mirror, + bool ingress, struct netlink_ext_ack *extack) +{ + struct qca8k_priv *priv =3D ds->priv; + int monitor_port, ret; + u32 reg, val; + + /* Check for existent entry */ + if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) + return -EEXIST; + + ret =3D regmap_read(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0, &val); + if (ret) + return ret; + + /* QCA83xx can have only one port set to mirror mode. + * Check that the correct port is requested and return error otherwise. + * When no mirror port is set, the values is set to 0xF + */ + monitor_port =3D FIELD_GET(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val); + if (monitor_port !=3D 0xF && monitor_port !=3D mirror->to_local_port) + return -EEXIST; + + /* Set the monitor port */ + val =3D FIELD_PREP(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, + mirror->to_local_port); + ret =3D regmap_update_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0, + QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val); + if (ret) + return ret; + + if (ingress) { + reg =3D QCA8K_PORT_LOOKUP_CTRL(port); + val =3D QCA8K_PORT_LOOKUP_ING_MIRROR_EN; + } else { + reg =3D QCA8K_REG_PORT_HOL_CTRL1(port); + val =3D QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN; + } + + ret =3D regmap_update_bits(priv->regmap, reg, val, val); + if (ret) + return ret; + + /* Track mirror port for tx and rx to decide when the + * mirror port has to be disabled. + */ + if (ingress) + priv->mirror_rx |=3D BIT(port); + else + priv->mirror_tx |=3D BIT(port); + + return 0; +} + +void qca8k_port_mirror_del(struct dsa_switch *ds, int port, + struct dsa_mall_mirror_tc_entry *mirror) +{ + struct qca8k_priv *priv =3D ds->priv; + u32 reg, val; + int ret; + + if (mirror->ingress) { + reg =3D QCA8K_PORT_LOOKUP_CTRL(port); + val =3D QCA8K_PORT_LOOKUP_ING_MIRROR_EN; + } else { + reg =3D QCA8K_REG_PORT_HOL_CTRL1(port); + val =3D QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN; + } + + ret =3D regmap_clear_bits(priv->regmap, reg, val); + if (ret) + goto err; + + if (mirror->ingress) + priv->mirror_rx &=3D ~BIT(port); + else + priv->mirror_tx &=3D ~BIT(port); + + /* No port set to send packet to mirror port. Disable mirror port */ + if (!priv->mirror_rx && !priv->mirror_tx) { + val =3D FIELD_PREP(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, 0xF); + ret =3D regmap_update_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0, + QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val); + if (ret) + goto err; + } +err: + dev_err(priv->dev, "Failed to del mirror port from %d", port); +} diff --git a/drivers/net/dsa/qca/qca8k.h b/drivers/net/dsa/qca/qca8k.h index 9da7928de83c..3a2131b7abfa 100644 --- a/drivers/net/dsa/qca/qca8k.h +++ b/drivers/net/dsa/qca/qca8k.h @@ -494,4 +494,11 @@ int qca8k_port_mdb_del(struct dsa_switch *ds, int port, const struct switchdev_obj_port_mdb *mdb, struct dsa_db db); =20 +/* Common port mirror function */ +int qca8k_port_mirror_add(struct dsa_switch *ds, int port, + struct dsa_mall_mirror_tc_entry *mirror, + bool ingress, struct netlink_ext_ack *extack); +void qca8k_port_mirror_del(struct dsa_switch *ds, int port, + struct dsa_mall_mirror_tc_entry *mirror); + #endif /* __QCA8K_H */ --=20 2.36.1 From nobody Wed Apr 15 03:04:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC64FC19F29 for ; Wed, 27 Jul 2022 11:37:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232357AbiG0Lg6 (ORCPT ); Wed, 27 Jul 2022 07:36:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52884 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232155AbiG0Lgg (ORCPT ); Wed, 27 Jul 2022 07:36:36 -0400 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E934B49B6D; Wed, 27 Jul 2022 04:35:59 -0700 (PDT) Received: by mail-ed1-x52c.google.com with SMTP id z15so9210235edc.7; Wed, 27 Jul 2022 04:35:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=avF5wLxx2Zfmm599FR13rOs75WXYhwlJqUIz5CV3ZW0=; b=E15UcQxzWzHb7ZYxdMycHuVFE/h1HNcydww0DnpoizVP51TCA4+CHYQbSk/PzQEHTs kPPZwbrcVLUB1I2HkCADyOPkPtnRhpNpQA8T3cRnDma4rn+EV4ZqCbwXkpLoIeSx/G2u CpiEVsmur4wwuRB2qnRLWLSmsRt2xrFYBqxkezkBdMILB9EnLWEg9LOEzCvm9xb5B2nG w6fbnhkm96kvULM2wbcPd6o/GC9rpiRTx+H1P3fNosOesF0NhsAjUA1qqoKeMic01I1O 7MoqKKX3eWWVUGrlkjyKhrdy80DnXbrXa6WyMWp4Ec2EYGHQ8nH2+Qz42xYH63qnFkO9 KQGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=avF5wLxx2Zfmm599FR13rOs75WXYhwlJqUIz5CV3ZW0=; b=oexSOiP8bMlL8VqtWNGZAhqkuW+w8asOXn4WGv1sGbaGEkMQdNv3ZID9R8BTvXfGUx ZCiETnDEoUOqbeHNwqWgWtYzPepoE0jgvzqNDg6Pv29tG1nvMQCOktQ3cYwCkTU57TdZ 4wClan6HjG+NK7xGN7/RbFqYPbjB6+ND3sZXj5AVRJIPdfvTCn7vXxPY4R6yzNBMUXDB uRZ+jeHJeoR1x8RU92VfUEW+kfri6epOq/krwvmFnVotqe11e7+KJSHLrE7zFy1w1JKH MOo1Da9Kxi7gtdCZyuwtefivfo7Uhic+mzSC8sTWjZzPAL4aJKfP42uC+PqLr839132S 4bPA== X-Gm-Message-State: AJIora8kLcmbde2JM+KhTYrAu85cgN6Tjg9pTkpEV8iD3re0V+Q0xxBM g6IDC7DAVpguPCEB2wDvPik= X-Google-Smtp-Source: AGRyM1vU0L9BkCNjyY1XoqFNYLySQKkimOvFgUFzSJNvKP2pJpA/C0CyW9BKFhgAslyaOMbHsR+YdQ== X-Received: by 2002:aa7:d753:0:b0:43b:a7df:60b0 with SMTP id a19-20020aa7d753000000b0043ba7df60b0mr22631913eds.191.1658921757949; Wed, 27 Jul 2022 04:35:57 -0700 (PDT) Received: from localhost.localdomain (c105-182.i13-27.melita.com. [94.17.105.182]) by smtp.googlemail.com with ESMTPSA id p25-20020aa7cc99000000b0043ca6fb7e7dsm1334056edt.68.2022.07.27.04.35.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Jul 2022 04:35:57 -0700 (PDT) From: Christian Marangi To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Greg Kroah-Hartman , Jens Axboe , Christian Marangi , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: [net-next PATCH v5 12/14] net: dsa: qca8k: move port VLAN functions to common code Date: Wed, 27 Jul 2022 13:35:21 +0200 Message-Id: <20220727113523.19742-13-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220727113523.19742-1-ansuelsmth@gmail.com> References: <20220727113523.19742-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The same port VLAN functions are used by drivers based on qca8k family switch. Move them to common code to make them accessible also by other drivers. Also drop exposing busy_wait and make it static. Signed-off-by: Christian Marangi Reviewed-by: Vladimir Oltean Reviewed-by: Florian Fainelli --- drivers/net/dsa/qca/qca8k-8xxx.c | 182 ----------------------------- drivers/net/dsa/qca/qca8k-common.c | 179 +++++++++++++++++++++++++++- drivers/net/dsa/qca/qca8k.h | 10 +- 3 files changed, 187 insertions(+), 184 deletions(-) diff --git a/drivers/net/dsa/qca/qca8k-8xxx.c b/drivers/net/dsa/qca/qca8k-8= xxx.c index f6ea5a82da9e..545f86e3c6ed 100644 --- a/drivers/net/dsa/qca/qca8k-8xxx.c +++ b/drivers/net/dsa/qca/qca8k-8xxx.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include @@ -441,122 +440,6 @@ static struct regmap_config qca8k_regmap_config =3D { .cache_type =3D REGCACHE_NONE, /* Explicitly disable CACHE */ }; =20 -static int -qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vi= d) -{ - u32 reg; - int ret; - - /* Set the command and VLAN index */ - reg =3D QCA8K_VTU_FUNC1_BUSY; - reg |=3D cmd; - reg |=3D FIELD_PREP(QCA8K_VTU_FUNC1_VID_MASK, vid); - - /* Write the function register triggering the table access */ - ret =3D qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg); - if (ret) - return ret; - - /* wait for completion */ - ret =3D qca8k_busy_wait(priv, QCA8K_REG_VTU_FUNC1, QCA8K_VTU_FUNC1_BUSY); - if (ret) - return ret; - - /* Check for table full violation when adding an entry */ - if (cmd =3D=3D QCA8K_VLAN_LOAD) { - ret =3D qca8k_read(priv, QCA8K_REG_VTU_FUNC1, ®); - if (ret < 0) - return ret; - if (reg & QCA8K_VTU_FUNC1_FULL) - return -ENOMEM; - } - - return 0; -} - -static int -qca8k_vlan_add(struct qca8k_priv *priv, u8 port, u16 vid, bool untagged) -{ - u32 reg; - int ret; - - /* - We do the right thing with VLAN 0 and treat it as untagged while - preserving the tag on egress. - */ - if (vid =3D=3D 0) - return 0; - - mutex_lock(&priv->reg_mutex); - ret =3D qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid); - if (ret < 0) - goto out; - - ret =3D qca8k_read(priv, QCA8K_REG_VTU_FUNC0, ®); - if (ret < 0) - goto out; - reg |=3D QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN; - reg &=3D ~QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(port); - if (untagged) - reg |=3D QCA8K_VTU_FUNC0_EG_MODE_PORT_UNTAG(port); - else - reg |=3D QCA8K_VTU_FUNC0_EG_MODE_PORT_TAG(port); - - ret =3D qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg); - if (ret) - goto out; - ret =3D qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid); - -out: - mutex_unlock(&priv->reg_mutex); - - return ret; -} - -static int -qca8k_vlan_del(struct qca8k_priv *priv, u8 port, u16 vid) -{ - u32 reg, mask; - int ret, i; - bool del; - - mutex_lock(&priv->reg_mutex); - ret =3D qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid); - if (ret < 0) - goto out; - - ret =3D qca8k_read(priv, QCA8K_REG_VTU_FUNC0, ®); - if (ret < 0) - goto out; - reg &=3D ~QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(port); - reg |=3D QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(port); - - /* Check if we're the last member to be removed */ - del =3D true; - for (i =3D 0; i < QCA8K_NUM_PORTS; i++) { - mask =3D QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(i); - - if ((reg & mask) !=3D mask) { - del =3D false; - break; - } - } - - if (del) { - ret =3D qca8k_vlan_access(priv, QCA8K_VLAN_PURGE, vid); - } else { - ret =3D qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg); - if (ret) - goto out; - ret =3D qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid); - } - -out: - mutex_unlock(&priv->reg_mutex); - - return ret; -} - static int qca8k_phy_eth_busy_wait(struct qca8k_mgmt_eth_data *mgmt_eth_data, struct sk_buff *read_skb, u32 *val) @@ -1687,71 +1570,6 @@ qca8k_get_ethtool_stats_eth(struct dsa_switch *ds, i= nt port, u64 *data) return ret; } =20 -static int -qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filte= ring, - struct netlink_ext_ack *extack) -{ - struct qca8k_priv *priv =3D ds->priv; - int ret; - - if (vlan_filtering) { - ret =3D qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), - QCA8K_PORT_LOOKUP_VLAN_MODE_MASK, - QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE); - } else { - ret =3D qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), - QCA8K_PORT_LOOKUP_VLAN_MODE_MASK, - QCA8K_PORT_LOOKUP_VLAN_MODE_NONE); - } - - return ret; -} - -static int -qca8k_port_vlan_add(struct dsa_switch *ds, int port, - const struct switchdev_obj_port_vlan *vlan, - struct netlink_ext_ack *extack) -{ - bool untagged =3D vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; - bool pvid =3D vlan->flags & BRIDGE_VLAN_INFO_PVID; - struct qca8k_priv *priv =3D ds->priv; - int ret; - - ret =3D qca8k_vlan_add(priv, port, vlan->vid, untagged); - if (ret) { - dev_err(priv->dev, "Failed to add VLAN to port %d (%d)", port, ret); - return ret; - } - - if (pvid) { - ret =3D qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port), - QCA8K_EGREES_VLAN_PORT_MASK(port), - QCA8K_EGREES_VLAN_PORT(port, vlan->vid)); - if (ret) - return ret; - - ret =3D qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port), - QCA8K_PORT_VLAN_CVID(vlan->vid) | - QCA8K_PORT_VLAN_SVID(vlan->vid)); - } - - return ret; -} - -static int -qca8k_port_vlan_del(struct dsa_switch *ds, int port, - const struct switchdev_obj_port_vlan *vlan) -{ - struct qca8k_priv *priv =3D ds->priv; - int ret; - - ret =3D qca8k_vlan_del(priv, port, vlan->vid); - if (ret) - dev_err(priv->dev, "Failed to delete VLAN from port %d (%d)", port, ret); - - return ret; -} - static u32 qca8k_get_phy_flags(struct dsa_switch *ds, int port) { struct qca8k_priv *priv =3D ds->priv; diff --git a/drivers/net/dsa/qca/qca8k-common.c b/drivers/net/dsa/qca/qca8k= -common.c index c0a088418c20..0e5ce532accd 100644 --- a/drivers/net/dsa/qca/qca8k-common.c +++ b/drivers/net/dsa/qca/qca8k-common.c @@ -140,7 +140,7 @@ static int qca8k_bulk_write(struct qca8k_priv *priv, u3= 2 reg, u32 *val, int len) return 0; } =20 -int qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask) +static int qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask) { u32 val; =20 @@ -353,6 +353,120 @@ static int qca8k_fdb_search_and_del(struct qca8k_priv= *priv, u8 port_mask, return ret; } =20 +static int qca8k_vlan_access(struct qca8k_priv *priv, + enum qca8k_vlan_cmd cmd, u16 vid) +{ + u32 reg; + int ret; + + /* Set the command and VLAN index */ + reg =3D QCA8K_VTU_FUNC1_BUSY; + reg |=3D cmd; + reg |=3D FIELD_PREP(QCA8K_VTU_FUNC1_VID_MASK, vid); + + /* Write the function register triggering the table access */ + ret =3D qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg); + if (ret) + return ret; + + /* wait for completion */ + ret =3D qca8k_busy_wait(priv, QCA8K_REG_VTU_FUNC1, QCA8K_VTU_FUNC1_BUSY); + if (ret) + return ret; + + /* Check for table full violation when adding an entry */ + if (cmd =3D=3D QCA8K_VLAN_LOAD) { + ret =3D qca8k_read(priv, QCA8K_REG_VTU_FUNC1, ®); + if (ret < 0) + return ret; + if (reg & QCA8K_VTU_FUNC1_FULL) + return -ENOMEM; + } + + return 0; +} + +static int qca8k_vlan_add(struct qca8k_priv *priv, u8 port, u16 vid, + bool untagged) +{ + u32 reg; + int ret; + + /* We do the right thing with VLAN 0 and treat it as untagged while + * preserving the tag on egress. + */ + if (vid =3D=3D 0) + return 0; + + mutex_lock(&priv->reg_mutex); + ret =3D qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid); + if (ret < 0) + goto out; + + ret =3D qca8k_read(priv, QCA8K_REG_VTU_FUNC0, ®); + if (ret < 0) + goto out; + reg |=3D QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN; + reg &=3D ~QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(port); + if (untagged) + reg |=3D QCA8K_VTU_FUNC0_EG_MODE_PORT_UNTAG(port); + else + reg |=3D QCA8K_VTU_FUNC0_EG_MODE_PORT_TAG(port); + + ret =3D qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg); + if (ret) + goto out; + ret =3D qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid); + +out: + mutex_unlock(&priv->reg_mutex); + + return ret; +} + +static int qca8k_vlan_del(struct qca8k_priv *priv, u8 port, u16 vid) +{ + u32 reg, mask; + int ret, i; + bool del; + + mutex_lock(&priv->reg_mutex); + ret =3D qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid); + if (ret < 0) + goto out; + + ret =3D qca8k_read(priv, QCA8K_REG_VTU_FUNC0, ®); + if (ret < 0) + goto out; + reg &=3D ~QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(port); + reg |=3D QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(port); + + /* Check if we're the last member to be removed */ + del =3D true; + for (i =3D 0; i < QCA8K_NUM_PORTS; i++) { + mask =3D QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(i); + + if ((reg & mask) !=3D mask) { + del =3D false; + break; + } + } + + if (del) { + ret =3D qca8k_vlan_access(priv, QCA8K_VLAN_PURGE, vid); + } else { + ret =3D qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg); + if (ret) + goto out; + ret =3D qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid); + } + +out: + mutex_unlock(&priv->reg_mutex); + + return ret; +} + int qca8k_mib_init(struct qca8k_priv *priv) { int ret; @@ -837,3 +951,66 @@ void qca8k_port_mirror_del(struct dsa_switch *ds, int = port, err: dev_err(priv->dev, "Failed to del mirror port from %d", port); } + +int qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, + bool vlan_filtering, + struct netlink_ext_ack *extack) +{ + struct qca8k_priv *priv =3D ds->priv; + int ret; + + if (vlan_filtering) { + ret =3D qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), + QCA8K_PORT_LOOKUP_VLAN_MODE_MASK, + QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE); + } else { + ret =3D qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), + QCA8K_PORT_LOOKUP_VLAN_MODE_MASK, + QCA8K_PORT_LOOKUP_VLAN_MODE_NONE); + } + + return ret; +} + +int qca8k_port_vlan_add(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_vlan *vlan, + struct netlink_ext_ack *extack) +{ + bool untagged =3D vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; + bool pvid =3D vlan->flags & BRIDGE_VLAN_INFO_PVID; + struct qca8k_priv *priv =3D ds->priv; + int ret; + + ret =3D qca8k_vlan_add(priv, port, vlan->vid, untagged); + if (ret) { + dev_err(priv->dev, "Failed to add VLAN to port %d (%d)", port, ret); + return ret; + } + + if (pvid) { + ret =3D qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port), + QCA8K_EGREES_VLAN_PORT_MASK(port), + QCA8K_EGREES_VLAN_PORT(port, vlan->vid)); + if (ret) + return ret; + + ret =3D qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port), + QCA8K_PORT_VLAN_CVID(vlan->vid) | + QCA8K_PORT_VLAN_SVID(vlan->vid)); + } + + return ret; +} + +int qca8k_port_vlan_del(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_vlan *vlan) +{ + struct qca8k_priv *priv =3D ds->priv; + int ret; + + ret =3D qca8k_vlan_del(priv, port, vlan->vid); + if (ret) + dev_err(priv->dev, "Failed to delete VLAN from port %d (%d)", port, ret); + + return ret; +} diff --git a/drivers/net/dsa/qca/qca8k.h b/drivers/net/dsa/qca/qca8k.h index 3a2131b7abfa..91f7abc5beb1 100644 --- a/drivers/net/dsa/qca/qca8k.h +++ b/drivers/net/dsa/qca/qca8k.h @@ -439,7 +439,6 @@ int qca8k_write(struct qca8k_priv *priv, u32 reg, u32 v= al); int qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val); =20 /* Common ops function */ -int qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask); void qca8k_fdb_flush(struct qca8k_priv *priv); =20 /* Common ethtool stats function */ @@ -501,4 +500,13 @@ int qca8k_port_mirror_add(struct dsa_switch *ds, int p= ort, void qca8k_port_mirror_del(struct dsa_switch *ds, int port, struct dsa_mall_mirror_tc_entry *mirror); =20 +/* Common port VLAN function */ +int qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_f= iltering, + struct netlink_ext_ack *extack); +int qca8k_port_vlan_add(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_vlan *vlan, + struct netlink_ext_ack *extack); +int qca8k_port_vlan_del(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_vlan *vlan); + #endif /* __QCA8K_H */ --=20 2.36.1 From nobody Wed Apr 15 03:04:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1ED5EC04A68 for ; Wed, 27 Jul 2022 11:37:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232543AbiG0LhB (ORCPT ); Wed, 27 Jul 2022 07:37:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232347AbiG0Lgh (ORCPT ); Wed, 27 Jul 2022 07:36:37 -0400 Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BA6B84AD4F; Wed, 27 Jul 2022 04:36:01 -0700 (PDT) Received: by mail-ej1-x62a.google.com with SMTP id j22so30998929ejs.2; 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[94.17.105.182]) by smtp.googlemail.com with ESMTPSA id p25-20020aa7cc99000000b0043ca6fb7e7dsm1334056edt.68.2022.07.27.04.35.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Jul 2022 04:35:58 -0700 (PDT) From: Christian Marangi To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Greg Kroah-Hartman , Jens Axboe , Christian Marangi , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: [net-next PATCH v5 13/14] net: dsa: qca8k: move port LAG functions to common code Date: Wed, 27 Jul 2022 13:35:22 +0200 Message-Id: <20220727113523.19742-14-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220727113523.19742-1-ansuelsmth@gmail.com> References: <20220727113523.19742-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The same port LAG functions are used by drivers based on qca8k family switch. Move them to common code to make them accessible also by other drivers. Signed-off-by: Christian Marangi Reviewed-by: Vladimir Oltean --- drivers/net/dsa/qca/qca8k-8xxx.c | 168 ----------------------------- drivers/net/dsa/qca/qca8k-common.c | 165 ++++++++++++++++++++++++++++ drivers/net/dsa/qca/qca8k.h | 6 ++ 3 files changed, 171 insertions(+), 168 deletions(-) diff --git a/drivers/net/dsa/qca/qca8k-8xxx.c b/drivers/net/dsa/qca/qca8k-8= xxx.c index 545f86e3c6ed..4d6ea47a4469 100644 --- a/drivers/net/dsa/qca/qca8k-8xxx.c +++ b/drivers/net/dsa/qca/qca8k-8xxx.c @@ -1593,174 +1593,6 @@ qca8k_get_tag_protocol(struct dsa_switch *ds, int p= ort, return DSA_TAG_PROTO_QCA; } =20 -static bool -qca8k_lag_can_offload(struct dsa_switch *ds, struct dsa_lag lag, - struct netdev_lag_upper_info *info) -{ - struct dsa_port *dp; - int members =3D 0; - - if (!lag.id) - return false; - - dsa_lag_foreach_port(dp, ds->dst, &lag) - /* Includes the port joining the LAG */ - members++; - - if (members > QCA8K_NUM_PORTS_FOR_LAG) - return false; - - if (info->tx_type !=3D NETDEV_LAG_TX_TYPE_HASH) - return false; - - if (info->hash_type !=3D NETDEV_LAG_HASH_L2 && - info->hash_type !=3D NETDEV_LAG_HASH_L23) - return false; - - return true; -} - -static int -qca8k_lag_setup_hash(struct dsa_switch *ds, struct dsa_lag lag, - struct netdev_lag_upper_info *info) -{ - struct net_device *lag_dev =3D lag.dev; - struct qca8k_priv *priv =3D ds->priv; - bool unique_lag =3D true; - unsigned int i; - u32 hash =3D 0; - - switch (info->hash_type) { - case NETDEV_LAG_HASH_L23: - hash |=3D QCA8K_TRUNK_HASH_SIP_EN; - hash |=3D QCA8K_TRUNK_HASH_DIP_EN; - fallthrough; - case NETDEV_LAG_HASH_L2: - hash |=3D QCA8K_TRUNK_HASH_SA_EN; - hash |=3D QCA8K_TRUNK_HASH_DA_EN; - break; - default: /* We should NEVER reach this */ - return -EOPNOTSUPP; - } - - /* Check if we are the unique configured LAG */ - dsa_lags_foreach_id(i, ds->dst) - if (i !=3D lag.id && dsa_lag_by_id(ds->dst, i)) { - unique_lag =3D false; - break; - } - - /* Hash Mode is global. Make sure the same Hash Mode - * is set to all the 4 possible lag. - * If we are the unique LAG we can set whatever hash - * mode we want. - * To change hash mode it's needed to remove all LAG - * and change the mode with the latest. - */ - if (unique_lag) { - priv->lag_hash_mode =3D hash; - } else if (priv->lag_hash_mode !=3D hash) { - netdev_err(lag_dev, "Error: Mismatched Hash Mode across different lag is= not supported\n"); - return -EOPNOTSUPP; - } - - return regmap_update_bits(priv->regmap, QCA8K_TRUNK_HASH_EN_CTRL, - QCA8K_TRUNK_HASH_MASK, hash); -} - -static int -qca8k_lag_refresh_portmap(struct dsa_switch *ds, int port, - struct dsa_lag lag, bool delete) -{ - struct qca8k_priv *priv =3D ds->priv; - int ret, id, i; - u32 val; - - /* DSA LAG IDs are one-based, hardware is zero-based */ - id =3D lag.id - 1; - - /* Read current port member */ - ret =3D regmap_read(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL0, &val); - if (ret) - return ret; - - /* Shift val to the correct trunk */ - val >>=3D QCA8K_REG_GOL_TRUNK_SHIFT(id); - val &=3D QCA8K_REG_GOL_TRUNK_MEMBER_MASK; - if (delete) - val &=3D ~BIT(port); - else - val |=3D BIT(port); - - /* Update port member. With empty portmap disable trunk */ - ret =3D regmap_update_bits(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL0, - QCA8K_REG_GOL_TRUNK_MEMBER(id) | - QCA8K_REG_GOL_TRUNK_EN(id), - !val << QCA8K_REG_GOL_TRUNK_SHIFT(id) | - val << QCA8K_REG_GOL_TRUNK_SHIFT(id)); - - /* Search empty member if adding or port on deleting */ - for (i =3D 0; i < QCA8K_NUM_PORTS_FOR_LAG; i++) { - ret =3D regmap_read(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL(id), &val); - if (ret) - return ret; - - val >>=3D QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i); - val &=3D QCA8K_REG_GOL_TRUNK_ID_MEM_ID_MASK; - - if (delete) { - /* If port flagged to be disabled assume this member is - * empty - */ - if (val !=3D QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK) - continue; - - val &=3D QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT_MASK; - if (val !=3D port) - continue; - } else { - /* If port flagged to be enabled assume this member is - * already set - */ - if (val =3D=3D QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK) - continue; - } - - /* We have found the member to add/remove */ - break; - } - - /* Set port in the correct port mask or disable port if in delete mode */ - return regmap_update_bits(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL(id), - QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN(id, i) | - QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT(id, i), - !delete << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i) | - port << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i)); -} - -static int -qca8k_port_lag_join(struct dsa_switch *ds, int port, struct dsa_lag lag, - struct netdev_lag_upper_info *info) -{ - int ret; - - if (!qca8k_lag_can_offload(ds, lag, info)) - return -EOPNOTSUPP; - - ret =3D qca8k_lag_setup_hash(ds, lag, info); - if (ret) - return ret; - - return qca8k_lag_refresh_portmap(ds, port, lag, false); -} - -static int -qca8k_port_lag_leave(struct dsa_switch *ds, int port, - struct dsa_lag lag) -{ - return qca8k_lag_refresh_portmap(ds, port, lag, true); -} - static void qca8k_master_change(struct dsa_switch *ds, const struct net_device *master, bool operational) diff --git a/drivers/net/dsa/qca/qca8k-common.c b/drivers/net/dsa/qca/qca8k= -common.c index 0e5ce532accd..c881a95441dd 100644 --- a/drivers/net/dsa/qca/qca8k-common.c +++ b/drivers/net/dsa/qca/qca8k-common.c @@ -1014,3 +1014,168 @@ int qca8k_port_vlan_del(struct dsa_switch *ds, int = port, =20 return ret; } + +static bool qca8k_lag_can_offload(struct dsa_switch *ds, + struct dsa_lag lag, + struct netdev_lag_upper_info *info) +{ + struct dsa_port *dp; + int members =3D 0; + + if (!lag.id) + return false; + + dsa_lag_foreach_port(dp, ds->dst, &lag) + /* Includes the port joining the LAG */ + members++; + + if (members > QCA8K_NUM_PORTS_FOR_LAG) + return false; + + if (info->tx_type !=3D NETDEV_LAG_TX_TYPE_HASH) + return false; + + if (info->hash_type !=3D NETDEV_LAG_HASH_L2 && + info->hash_type !=3D NETDEV_LAG_HASH_L23) + return false; + + return true; +} + +static int qca8k_lag_setup_hash(struct dsa_switch *ds, + struct dsa_lag lag, + struct netdev_lag_upper_info *info) +{ + struct net_device *lag_dev =3D lag.dev; + struct qca8k_priv *priv =3D ds->priv; + bool unique_lag =3D true; + unsigned int i; + u32 hash =3D 0; + + switch (info->hash_type) { + case NETDEV_LAG_HASH_L23: + hash |=3D QCA8K_TRUNK_HASH_SIP_EN; + hash |=3D QCA8K_TRUNK_HASH_DIP_EN; + fallthrough; + case NETDEV_LAG_HASH_L2: + hash |=3D QCA8K_TRUNK_HASH_SA_EN; + hash |=3D QCA8K_TRUNK_HASH_DA_EN; + break; + default: /* We should NEVER reach this */ + return -EOPNOTSUPP; + } + + /* Check if we are the unique configured LAG */ + dsa_lags_foreach_id(i, ds->dst) + if (i !=3D lag.id && dsa_lag_by_id(ds->dst, i)) { + unique_lag =3D false; + break; + } + + /* Hash Mode is global. Make sure the same Hash Mode + * is set to all the 4 possible lag. + * If we are the unique LAG we can set whatever hash + * mode we want. + * To change hash mode it's needed to remove all LAG + * and change the mode with the latest. + */ + if (unique_lag) { + priv->lag_hash_mode =3D hash; + } else if (priv->lag_hash_mode !=3D hash) { + netdev_err(lag_dev, "Error: Mismatched Hash Mode across different lag is= not supported\n"); + return -EOPNOTSUPP; + } + + return regmap_update_bits(priv->regmap, QCA8K_TRUNK_HASH_EN_CTRL, + QCA8K_TRUNK_HASH_MASK, hash); +} + +static int qca8k_lag_refresh_portmap(struct dsa_switch *ds, int port, + struct dsa_lag lag, bool delete) +{ + struct qca8k_priv *priv =3D ds->priv; + int ret, id, i; + u32 val; + + /* DSA LAG IDs are one-based, hardware is zero-based */ + id =3D lag.id - 1; + + /* Read current port member */ + ret =3D regmap_read(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL0, &val); + if (ret) + return ret; + + /* Shift val to the correct trunk */ + val >>=3D QCA8K_REG_GOL_TRUNK_SHIFT(id); + val &=3D QCA8K_REG_GOL_TRUNK_MEMBER_MASK; + if (delete) + val &=3D ~BIT(port); + else + val |=3D BIT(port); + + /* Update port member. With empty portmap disable trunk */ + ret =3D regmap_update_bits(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL0, + QCA8K_REG_GOL_TRUNK_MEMBER(id) | + QCA8K_REG_GOL_TRUNK_EN(id), + !val << QCA8K_REG_GOL_TRUNK_SHIFT(id) | + val << QCA8K_REG_GOL_TRUNK_SHIFT(id)); + + /* Search empty member if adding or port on deleting */ + for (i =3D 0; i < QCA8K_NUM_PORTS_FOR_LAG; i++) { + ret =3D regmap_read(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL(id), &val); + if (ret) + return ret; + + val >>=3D QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i); + val &=3D QCA8K_REG_GOL_TRUNK_ID_MEM_ID_MASK; + + if (delete) { + /* If port flagged to be disabled assume this member is + * empty + */ + if (val !=3D QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK) + continue; + + val &=3D QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT_MASK; + if (val !=3D port) + continue; + } else { + /* If port flagged to be enabled assume this member is + * already set + */ + if (val =3D=3D QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK) + continue; + } + + /* We have found the member to add/remove */ + break; + } + + /* Set port in the correct port mask or disable port if in delete mode */ + return regmap_update_bits(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL(id), + QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN(id, i) | + QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT(id, i), + !delete << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i) | + port << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i)); +} + +int qca8k_port_lag_join(struct dsa_switch *ds, int port, struct dsa_lag la= g, + struct netdev_lag_upper_info *info) +{ + int ret; + + if (!qca8k_lag_can_offload(ds, lag, info)) + return -EOPNOTSUPP; + + ret =3D qca8k_lag_setup_hash(ds, lag, info); + if (ret) + return ret; + + return qca8k_lag_refresh_portmap(ds, port, lag, false); +} + +int qca8k_port_lag_leave(struct dsa_switch *ds, int port, + struct dsa_lag lag) +{ + return qca8k_lag_refresh_portmap(ds, port, lag, true); +} diff --git a/drivers/net/dsa/qca/qca8k.h b/drivers/net/dsa/qca/qca8k.h index 91f7abc5beb1..e87bfee837c1 100644 --- a/drivers/net/dsa/qca/qca8k.h +++ b/drivers/net/dsa/qca/qca8k.h @@ -509,4 +509,10 @@ int qca8k_port_vlan_add(struct dsa_switch *ds, int por= t, int qca8k_port_vlan_del(struct dsa_switch *ds, int port, const struct switchdev_obj_port_vlan *vlan); =20 +/* Common port LAG function */ +int qca8k_port_lag_join(struct dsa_switch *ds, int port, struct dsa_lag la= g, + struct netdev_lag_upper_info *info); +int qca8k_port_lag_leave(struct dsa_switch *ds, int port, + struct dsa_lag lag); + #endif /* __QCA8K_H */ --=20 2.36.1 From nobody Wed Apr 15 03:04:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE07FC04A68 for ; Wed, 27 Jul 2022 11:37:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232421AbiG0LhJ (ORCPT ); Wed, 27 Jul 2022 07:37:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232390AbiG0Lgj (ORCPT ); Wed, 27 Jul 2022 07:36:39 -0400 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 103244AD56; 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[94.17.105.182]) by smtp.googlemail.com with ESMTPSA id p25-20020aa7cc99000000b0043ca6fb7e7dsm1334056edt.68.2022.07.27.04.35.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Jul 2022 04:36:00 -0700 (PDT) From: Christian Marangi To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Greg Kroah-Hartman , Jens Axboe , Christian Marangi , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: [net-next PATCH v5 14/14] net: dsa: qca8k: move read_switch_id function to common code Date: Wed, 27 Jul 2022 13:35:23 +0200 Message-Id: <20220727113523.19742-15-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220727113523.19742-1-ansuelsmth@gmail.com> References: <20220727113523.19742-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The same function to read the switch id is used by drivers based on qca8k family switch. Move them to common code to make them accessible also by other drivers. Signed-off-by: Christian Marangi --- drivers/net/dsa/qca/qca8k-8xxx.c | 29 ----------------------------- drivers/net/dsa/qca/qca8k-common.c | 29 +++++++++++++++++++++++++++++ drivers/net/dsa/qca/qca8k.h | 1 + 3 files changed, 30 insertions(+), 29 deletions(-) diff --git a/drivers/net/dsa/qca/qca8k-8xxx.c b/drivers/net/dsa/qca/qca8k-8= xxx.c index 4d6ea47a4469..1d3e7782a71f 100644 --- a/drivers/net/dsa/qca/qca8k-8xxx.c +++ b/drivers/net/dsa/qca/qca8k-8xxx.c @@ -1876,35 +1876,6 @@ static const struct dsa_switch_ops qca8k_switch_ops = =3D { .connect_tag_protocol =3D qca8k_connect_tag_protocol, }; =20 -static int qca8k_read_switch_id(struct qca8k_priv *priv) -{ - u32 val; - u8 id; - int ret; - - if (!priv->info) - return -ENODEV; - - ret =3D qca8k_read(priv, QCA8K_REG_MASK_CTRL, &val); - if (ret < 0) - return -ENODEV; - - id =3D QCA8K_MASK_CTRL_DEVICE_ID(val); - if (id !=3D priv->info->id) { - dev_err(priv->dev, - "Switch id detected %x but expected %x", - id, priv->info->id); - return -ENODEV; - } - - priv->switch_id =3D id; - - /* Save revision to communicate to the internal PHY driver */ - priv->switch_revision =3D QCA8K_MASK_CTRL_REV_ID(val); - - return 0; -} - static int qca8k_sw_probe(struct mdio_device *mdiodev) { diff --git a/drivers/net/dsa/qca/qca8k-common.c b/drivers/net/dsa/qca/qca8k= -common.c index c881a95441dd..bba95613e218 100644 --- a/drivers/net/dsa/qca/qca8k-common.c +++ b/drivers/net/dsa/qca/qca8k-common.c @@ -1179,3 +1179,32 @@ int qca8k_port_lag_leave(struct dsa_switch *ds, int = port, { return qca8k_lag_refresh_portmap(ds, port, lag, true); } + +int qca8k_read_switch_id(struct qca8k_priv *priv) +{ + u32 val; + u8 id; + int ret; + + if (!priv->info) + return -ENODEV; + + ret =3D qca8k_read(priv, QCA8K_REG_MASK_CTRL, &val); + if (ret < 0) + return -ENODEV; + + id =3D QCA8K_MASK_CTRL_DEVICE_ID(val); + if (id !=3D priv->info->id) { + dev_err(priv->dev, + "Switch id detected %x but expected %x", + id, priv->info->id); + return -ENODEV; + } + + priv->switch_id =3D id; + + /* Save revision to communicate to the internal PHY driver */ + priv->switch_revision =3D QCA8K_MASK_CTRL_REV_ID(val); + + return 0; +} diff --git a/drivers/net/dsa/qca/qca8k.h b/drivers/net/dsa/qca/qca8k.h index e87bfee837c1..e36ecc9777f4 100644 --- a/drivers/net/dsa/qca/qca8k.h +++ b/drivers/net/dsa/qca/qca8k.h @@ -432,6 +432,7 @@ extern const struct qca8k_mib_desc ar8327_mib[]; extern const struct regmap_access_table qca8k_readable_table; int qca8k_mib_init(struct qca8k_priv *priv); void qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable); +int qca8k_read_switch_id(struct qca8k_priv *priv); =20 /* Common read/write/rmw function */ int qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val); --=20 2.36.1