From nobody Wed Apr 15 04:16:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41950C00140 for ; Tue, 26 Jul 2022 14:23:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234137AbiGZOXy (ORCPT ); Tue, 26 Jul 2022 10:23:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60886 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238631AbiGZOXs (ORCPT ); Tue, 26 Jul 2022 10:23:48 -0400 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2E67427CC6 for ; Tue, 26 Jul 2022 07:23:45 -0700 (PDT) Received: by mail-wr1-x433.google.com with SMTP id d8so20293570wrp.6 for ; Tue, 26 Jul 2022 07:23:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iN4g8Q0MhfeR/u597UBROPVWFRobvvZk7geE/5YXWMo=; b=AmybggQ/afwLbYKutEwikc3w0YLeHJQvVO81EIa5bCBowVO0mViSM+LX8xqbgeCwLc 4G2OkRdKPPUQtonPOAkYMx0+0V6oyBKvP/9+1UgTyl2GA3fWu1ZJ0ETAcqwf+ybIIrjK OiSj+VD5HtJjH3W2qYldwcTZGjVtVHAKeH9bd2//J7r9FKhG1CIBsXoJUqkEuWLOhQax 8miUjFDD/jMfUW6ZmRxS3wyCA+5LQvWq1ZuGVNzl1+nn+6qNHZgkPFnBGbuIwo6w3jCb jD3VmWu15x6xA2Az+bv1TvTKjwnGgVbVBslli8NBtF7xqm2e34wD79JaLQDIMele9cxY Y4og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iN4g8Q0MhfeR/u597UBROPVWFRobvvZk7geE/5YXWMo=; b=FT29Pe98SCxyVn+Rh+/4WkprHrJVLSaayPGR619nXUKREsmsSh8nAW3MpMEuZpKcuH PEyK7k5EsvgE53OCA/EXlGxI/HUk40A3KW6w7v7P8L1BCk5XT/qsj3g/Xj3NJ0LeLqQ9 qL2wM7feSaoUsLvtZqFCuVUU1No7cdpkjnf2+pOmy5mQ6Y2Yl0bhOUqitGUluvLCTk6j TDUSTBPsjl62NkFAMGfenq9BVw671nHjCzmrC66hMXD0zQN/vIz/vlYxq9LEY6jYPQr+ p/lqUW+v0995zQS8pZZ1xeBCckcIZ5iFTrAx0SV5Raykpupin8E784ThNra2sZSbVaYy ErkQ== X-Gm-Message-State: AJIora8DHU/gOM+FMeyh/yvU+lnK9rgcvVhFPw+bnqTvxYEdeLVsgQ/J tHDM59pwcqbRih/2E4TQL75M3Q== X-Google-Smtp-Source: AGRyM1tov4IGbHdLhoHIVZ1JTGggwsyOjMaENX4QMjzTNb/yYyfyp9LzGNuW+Pxx31lkOrgMF6dd+g== X-Received: by 2002:adf:ea8c:0:b0:21e:463e:7480 with SMTP id s12-20020adfea8c000000b0021e463e7480mr11131837wrm.171.1658845423762; Tue, 26 Jul 2022 07:23:43 -0700 (PDT) Received: from localhost.localdomain ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id t21-20020a1c7715000000b003a331c6bffdsm17017119wmi.47.2022.07.26.07.23.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Jul 2022 07:23:43 -0700 (PDT) From: Abel Vesa To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Mike Turquette , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Linux Kernel Mailing List , Abel Vesa Subject: [RFC 1/9] clk: qcom: qcc-sdm845: Collapse gdsc structs into macros Date: Tue, 26 Jul 2022 17:22:55 +0300 Message-Id: <20220726142303.4126434-2-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.3 In-Reply-To: <20220726142303.4126434-1-abel.vesa@linaro.org> References: <20220726142303.4126434-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Collapse gdsc structs definitions into macros to make them more compact visually. Signed-off-by: Abel Vesa --- drivers/clk/qcom/gcc-sdm845.c | 129 ++++------------------------------ drivers/clk/qcom/gdsc.h | 10 +++ 2 files changed, 23 insertions(+), 116 deletions(-) diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c index 58aa3ec9a7fc..8529e9c8c90c 100644 --- a/drivers/clk/qcom/gcc-sdm845.c +++ b/drivers/clk/qcom/gcc-sdm845.c @@ -3191,122 +3191,19 @@ static struct clk_branch gcc_lpass_sway_clk =3D { }; #endif =20 -static struct gdsc pcie_0_gdsc =3D { - .gdscr =3D 0x6b004, - .pd =3D { - .name =3D "pcie_0_gdsc", - }, - .pwrsts =3D PWRSTS_OFF_ON, - .flags =3D POLL_CFG_GDSCR, -}; - -static struct gdsc pcie_1_gdsc =3D { - .gdscr =3D 0x8d004, - .pd =3D { - .name =3D "pcie_1_gdsc", - }, - .pwrsts =3D PWRSTS_OFF_ON, - .flags =3D POLL_CFG_GDSCR, -}; - -static struct gdsc ufs_card_gdsc =3D { - .gdscr =3D 0x75004, - .pd =3D { - .name =3D "ufs_card_gdsc", - }, - .pwrsts =3D PWRSTS_OFF_ON, - .flags =3D POLL_CFG_GDSCR, -}; - -static struct gdsc ufs_phy_gdsc =3D { - .gdscr =3D 0x77004, - .pd =3D { - .name =3D "ufs_phy_gdsc", - }, - .pwrsts =3D PWRSTS_OFF_ON, - .flags =3D POLL_CFG_GDSCR, -}; - -static struct gdsc usb30_prim_gdsc =3D { - .gdscr =3D 0xf004, - .pd =3D { - .name =3D "usb30_prim_gdsc", - }, - .pwrsts =3D PWRSTS_OFF_ON, - .flags =3D POLL_CFG_GDSCR, -}; - -static struct gdsc usb30_sec_gdsc =3D { - .gdscr =3D 0x10004, - .pd =3D { - .name =3D "usb30_sec_gdsc", - }, - .pwrsts =3D PWRSTS_OFF_ON, - .flags =3D POLL_CFG_GDSCR, -}; - -static struct gdsc hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc =3D { - .gdscr =3D 0x7d030, - .pd =3D { - .name =3D "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc", - }, - .pwrsts =3D PWRSTS_OFF_ON, - .flags =3D VOTABLE, -}; - -static struct gdsc hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc =3D { - .gdscr =3D 0x7d03c, - .pd =3D { - .name =3D "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc", - }, - .pwrsts =3D PWRSTS_OFF_ON, - .flags =3D VOTABLE, -}; - -static struct gdsc hlos1_vote_aggre_noc_mmu_tbu1_gdsc =3D { - .gdscr =3D 0x7d034, - .pd =3D { - .name =3D "hlos1_vote_aggre_noc_mmu_tbu1_gdsc", - }, - .pwrsts =3D PWRSTS_OFF_ON, - .flags =3D VOTABLE, -}; - -static struct gdsc hlos1_vote_aggre_noc_mmu_tbu2_gdsc =3D { - .gdscr =3D 0x7d038, - .pd =3D { - .name =3D "hlos1_vote_aggre_noc_mmu_tbu2_gdsc", - }, - .pwrsts =3D PWRSTS_OFF_ON, - .flags =3D VOTABLE, -}; - -static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc =3D { - .gdscr =3D 0x7d040, - .pd =3D { - .name =3D "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc", - }, - .pwrsts =3D PWRSTS_OFF_ON, - .flags =3D VOTABLE, -}; - -static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc =3D { - .gdscr =3D 0x7d048, - .pd =3D { - .name =3D "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc", - }, - .pwrsts =3D PWRSTS_OFF_ON, - .flags =3D VOTABLE, -}; - -static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc =3D { - .gdscr =3D 0x7d044, - .pd =3D { - .name =3D "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc", - }, - .pwrsts =3D PWRSTS_OFF_ON, - .flags =3D VOTABLE, -}; +DEFINE_QCOM_CC_GDSC(pcie_0_gdsc, 0x6b004, "pcie_0_gdsc", PWRSTS_OFF_ON, PO= LL_CFG_GDSCR); +DEFINE_QCOM_CC_GDSC(pcie_1_gdsc, 0x8d004, "pcie_1_gdsc", PWRSTS_OFF_ON, PO= LL_CFG_GDSCR); +DEFINE_QCOM_CC_GDSC(ufs_card_gdsc, 0x75004, "ufs_card_gdsc", PWRSTS_OFF_ON= , POLL_CFG_GDSCR); +DEFINE_QCOM_CC_GDSC(ufs_phy_gdsc, 0x77004, "ufs_phy_gdsc", PWRSTS_OFF_ON, = POLL_CFG_GDSCR); +DEFINE_QCOM_CC_GDSC(usb30_prim_gdsc, 0xf004, "usb30_prim_gdsc", PWRSTS_OFF= _ON, POLL_CFG_GDSCR); +DEFINE_QCOM_CC_GDSC(usb30_sec_gdsc, 0x10004, "usb30_sec_gdsc", PWRSTS_OFF_= ON, POLL_CFG_GDSCR); +DEFINE_QCOM_CC_GDSC(hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc, 0x7d030, "hlo= s1_vote_aggre_noc_mmu_audio_tbu_gdsc", PWRSTS_OFF_ON, VOTABLE); +DEFINE_QCOM_CC_GDSC(hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc, 0x7d03c, "hlos= 1_vote_aggre_noc_mmu_pcie_tbu_gdsc", PWRSTS_OFF_ON, VOTABLE); +DEFINE_QCOM_CC_GDSC(hlos1_vote_aggre_noc_mmu_tbu1_gdsc, 0x7d034, "hlos1_vo= te_aggre_noc_mmu_tbu1_gdsc", PWRSTS_OFF_ON, VOTABLE); +DEFINE_QCOM_CC_GDSC(hlos1_vote_aggre_noc_mmu_tbu2_gdsc, 0x7d038, "hlos1_vo= te_aggre_noc_mmu_tbu2_gdsc", PWRSTS_OFF_ON, VOTABLE); +DEFINE_QCOM_CC_GDSC(hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc, 0x7d040, "hlos1_vot= e_mmnoc_mmu_tbu_hf0_gdsc", PWRSTS_OFF_ON, VOTABLE); +DEFINE_QCOM_CC_GDSC(hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc, 0x7d048, "hlos1_vot= e_mmnoc_mmu_tbu_hf1_gdsc", PWRSTS_OFF_ON, VOTABLE); +DEFINE_QCOM_CC_GDSC(hlos1_vote_mmnoc_mmu_tbu_sf_gdsc, 0x7d044, "hlos1_vote= _mmnoc_mmu_tbu_sf_gdsc", PWRSTS_OFF_ON, VOTABLE); =20 static struct clk_regmap *gcc_sdm845_clocks[] =3D { [GCC_AGGRE_NOC_PCIE_TBU_CLK] =3D &gcc_aggre_noc_pcie_tbu_clk.clkr, diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h index 5de48c9439b2..c0e616b49dee 100644 --- a/drivers/clk/qcom/gdsc.h +++ b/drivers/clk/qcom/gdsc.h @@ -78,6 +78,16 @@ struct gdsc_desc { size_t num; }; =20 +#define DEFINE_QCOM_CC_GDSC(_name, _gdscr, _pd_name, _pwrsts, _flags) \ + static struct gdsc _name =3D { \ + .gdscr =3D _gdscr, \ + .pd =3D { \ + .name =3D _pd_name, \ + }, \ + .pwrsts =3D _pwrsts, \ + .flags =3D _flags, \ + } + #ifdef CONFIG_QCOM_GDSC int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *, struct regmap *); --=20 2.34.3 From nobody Wed Apr 15 04:16:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56E03C00140 for ; Tue, 26 Jul 2022 14:24:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239279AbiGZOYC (ORCPT ); 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Tue, 26 Jul 2022 07:23:44 -0700 (PDT) From: Abel Vesa To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Mike Turquette , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Linux Kernel Mailing List , Abel Vesa Subject: [RFC 2/9] clk: qcom: gcc-sdm845: Switch from parent_hws to parent_data Date: Tue, 26 Jul 2022 17:22:56 +0300 Message-Id: <20220726142303.4126434-3-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.3 In-Reply-To: <20220726142303.4126434-1-abel.vesa@linaro.org> References: <20220726142303.4126434-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" By using parent_data instead of parent_hws, we align more with those clocks that pass fw_name. This will allow us to have cleaner macros for defining them later on. Signed-off-by: Abel Vesa --- drivers/clk/qcom/gcc-sdm845.c | 256 +++++++++++++++++----------------- 1 file changed, 128 insertions(+), 128 deletions(-) diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c index 8529e9c8c90c..599e7d23aeca 100644 --- a/drivers/clk/qcom/gcc-sdm845.c +++ b/drivers/clk/qcom/gcc-sdm845.c @@ -1028,8 +1028,8 @@ static struct clk_branch gcc_aggre_ufs_card_axi_clk = =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_aggre_ufs_card_axi_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_ufs_card_axi_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_ufs_card_axi_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -1048,8 +1048,8 @@ static struct clk_branch gcc_aggre_ufs_phy_axi_clk = =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_aggre_ufs_phy_axi_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_ufs_phy_axi_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_ufs_phy_axi_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -1066,8 +1066,8 @@ static struct clk_branch gcc_aggre_usb3_prim_axi_clk = =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_aggre_usb3_prim_axi_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_usb30_prim_master_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_usb30_prim_master_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -1084,8 +1084,8 @@ static struct clk_branch gcc_aggre_usb3_sec_axi_clk = =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_aggre_usb3_sec_axi_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_usb30_sec_master_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_usb30_sec_master_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -1102,8 +1102,8 @@ static struct clk_branch gcc_apc_vs_clk =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_apc_vs_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_vsensor_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_vsensor_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -1219,8 +1219,8 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_cl= k =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_cfg_noc_usb3_prim_axi_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_usb30_prim_master_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_usb30_prim_master_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -1237,8 +1237,8 @@ static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk= =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_cfg_noc_usb3_sec_axi_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_usb30_sec_master_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_usb30_sec_master_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -1255,8 +1255,8 @@ static struct clk_branch gcc_cpuss_ahb_clk =3D { .enable_mask =3D BIT(21), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_cpuss_ahb_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_cpuss_ahb_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_cpuss_ahb_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, @@ -1273,8 +1273,8 @@ static struct clk_branch gcc_cpuss_rbcpr_clk =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_cpuss_rbcpr_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_cpuss_rbcpr_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_cpuss_rbcpr_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -1332,8 +1332,8 @@ static struct clk_branch gcc_disp_gpll0_clk_src =3D { .enable_mask =3D BIT(18), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_disp_gpll0_clk_src", - .parent_hws =3D (const struct clk_hw*[]){ - &gpll0.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gpll0.clkr.hw, }, .num_parents =3D 1, .ops =3D &clk_branch2_aon_ops, @@ -1348,8 +1348,8 @@ static struct clk_branch gcc_disp_gpll0_div_clk_src = =3D { .enable_mask =3D BIT(19), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_disp_gpll0_div_clk_src", - .parent_hws =3D (const struct clk_hw*[]){ - &gpll0_out_even.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gpll0_out_even.clkr.hw, }, .num_parents =3D 1, .ops =3D &clk_branch2_ops, @@ -1379,8 +1379,8 @@ static struct clk_branch gcc_gp1_clk =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_gp1_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_gp1_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_gp1_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -1397,8 +1397,8 @@ static struct clk_branch gcc_gp2_clk =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_gp2_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_gp2_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_gp2_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -1415,8 +1415,8 @@ static struct clk_branch gcc_gp3_clk =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_gp3_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_gp3_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_gp3_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -1448,8 +1448,8 @@ static struct clk_branch gcc_gpu_gpll0_clk_src =3D { .enable_mask =3D BIT(15), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_gpu_gpll0_clk_src", - .parent_hws =3D (const struct clk_hw*[]){ - &gpll0.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gpll0.clkr.hw, }, .num_parents =3D 1, .ops =3D &clk_branch2_ops, @@ -1464,8 +1464,8 @@ static struct clk_branch gcc_gpu_gpll0_div_clk_src = =3D { .enable_mask =3D BIT(16), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_gpu_gpll0_div_clk_src", - .parent_hws =3D (const struct clk_hw*[]){ - &gpll0_out_even.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gpll0_out_even.clkr.hw, }, .num_parents =3D 1, .ops =3D &clk_branch2_ops, @@ -1520,8 +1520,8 @@ static struct clk_branch gcc_gpu_vs_clk =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_gpu_vs_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_vsensor_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_vsensor_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -1619,8 +1619,8 @@ static struct clk_branch gcc_mss_vs_clk =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_mss_vs_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_vsensor_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_vsensor_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -1637,8 +1637,8 @@ static struct clk_branch gcc_pcie_0_aux_clk =3D { .enable_mask =3D BIT(3), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_pcie_0_aux_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_pcie_0_aux_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_pcie_0_aux_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -1741,8 +1741,8 @@ static struct clk_branch gcc_pcie_1_aux_clk =3D { .enable_mask =3D BIT(29), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_pcie_1_aux_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_pcie_1_aux_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_pcie_1_aux_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -1844,8 +1844,8 @@ static struct clk_branch gcc_pcie_phy_aux_clk =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_pcie_phy_aux_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_pcie_0_aux_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_pcie_0_aux_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -1862,8 +1862,8 @@ static struct clk_branch gcc_pcie_phy_refgen_clk =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_pcie_phy_refgen_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_pcie_phy_refgen_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_pcie_phy_refgen_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -1880,8 +1880,8 @@ static struct clk_branch gcc_pdm2_clk =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_pdm2_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_pdm2_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_pdm2_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -1999,8 +1999,8 @@ static struct clk_branch gcc_qspi_core_clk =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_qspi_core_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_qspi_core_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_qspi_core_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2017,8 +2017,8 @@ static struct clk_branch gcc_qupv3_wrap0_s0_clk =3D { .enable_mask =3D BIT(10), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_qupv3_wrap0_s0_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2035,8 +2035,8 @@ static struct clk_branch gcc_qupv3_wrap0_s1_clk =3D { .enable_mask =3D BIT(11), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_qupv3_wrap0_s1_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2053,8 +2053,8 @@ static struct clk_branch gcc_qupv3_wrap0_s2_clk =3D { .enable_mask =3D BIT(12), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_qupv3_wrap0_s2_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2071,8 +2071,8 @@ static struct clk_branch gcc_qupv3_wrap0_s3_clk =3D { .enable_mask =3D BIT(13), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_qupv3_wrap0_s3_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2089,8 +2089,8 @@ static struct clk_branch gcc_qupv3_wrap0_s4_clk =3D { .enable_mask =3D BIT(14), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_qupv3_wrap0_s4_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2107,8 +2107,8 @@ static struct clk_branch gcc_qupv3_wrap0_s5_clk =3D { .enable_mask =3D BIT(15), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_qupv3_wrap0_s5_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2125,8 +2125,8 @@ static struct clk_branch gcc_qupv3_wrap0_s6_clk =3D { .enable_mask =3D BIT(16), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_qupv3_wrap0_s6_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2143,8 +2143,8 @@ static struct clk_branch gcc_qupv3_wrap0_s7_clk =3D { .enable_mask =3D BIT(17), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_qupv3_wrap0_s7_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2161,8 +2161,8 @@ static struct clk_branch gcc_qupv3_wrap1_s0_clk =3D { .enable_mask =3D BIT(22), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_qupv3_wrap1_s0_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2179,8 +2179,8 @@ static struct clk_branch gcc_qupv3_wrap1_s1_clk =3D { .enable_mask =3D BIT(23), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_qupv3_wrap1_s1_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2197,8 +2197,8 @@ static struct clk_branch gcc_qupv3_wrap1_s2_clk =3D { .enable_mask =3D BIT(24), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_qupv3_wrap1_s2_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2215,8 +2215,8 @@ static struct clk_branch gcc_qupv3_wrap1_s3_clk =3D { .enable_mask =3D BIT(25), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_qupv3_wrap1_s3_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2233,8 +2233,8 @@ static struct clk_branch gcc_qupv3_wrap1_s4_clk =3D { .enable_mask =3D BIT(26), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_qupv3_wrap1_s4_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2251,8 +2251,8 @@ static struct clk_branch gcc_qupv3_wrap1_s5_clk =3D { .enable_mask =3D BIT(27), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_qupv3_wrap1_s5_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2269,8 +2269,8 @@ static struct clk_branch gcc_qupv3_wrap1_s6_clk =3D { .enable_mask =3D BIT(28), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_qupv3_wrap1_s6_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2287,8 +2287,8 @@ static struct clk_branch gcc_qupv3_wrap1_s7_clk =3D { .enable_mask =3D BIT(29), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_qupv3_wrap1_s7_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2374,8 +2374,8 @@ static struct clk_branch gcc_sdcc2_apps_clk =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_sdcc2_apps_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_sdcc2_apps_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_sdcc2_apps_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2405,8 +2405,8 @@ static struct clk_branch gcc_sdcc4_apps_clk =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_sdcc4_apps_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_sdcc4_apps_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_sdcc4_apps_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2423,8 +2423,8 @@ static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_sys_noc_cpuss_ahb_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_cpuss_ahb_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_cpuss_ahb_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, @@ -2467,8 +2467,8 @@ static struct clk_branch gcc_tsif_ref_clk =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_tsif_ref_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_tsif_ref_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_tsif_ref_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2502,8 +2502,8 @@ static struct clk_branch gcc_ufs_card_axi_clk =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_ufs_card_axi_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_ufs_card_axi_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_ufs_card_axi_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2535,8 +2535,8 @@ static struct clk_branch gcc_ufs_card_ice_core_clk = =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_ufs_card_ice_core_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_ufs_card_ice_core_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_ufs_card_ice_core_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2555,8 +2555,8 @@ static struct clk_branch gcc_ufs_card_phy_aux_clk =3D= { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_ufs_card_phy_aux_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_ufs_card_phy_aux_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_ufs_card_phy_aux_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2611,8 +2611,8 @@ static struct clk_branch gcc_ufs_card_unipro_core_clk= =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_ufs_card_unipro_core_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_ufs_card_unipro_core_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_ufs_card_unipro_core_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2659,8 +2659,8 @@ static struct clk_branch gcc_ufs_phy_axi_clk =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_ufs_phy_axi_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_ufs_phy_axi_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_ufs_phy_axi_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2679,8 +2679,8 @@ static struct clk_branch gcc_ufs_phy_ice_core_clk =3D= { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_ufs_phy_ice_core_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_ufs_phy_ice_core_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_ufs_phy_ice_core_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2699,8 +2699,8 @@ static struct clk_branch gcc_ufs_phy_phy_aux_clk =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_ufs_phy_phy_aux_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2755,8 +2755,8 @@ static struct clk_branch gcc_ufs_phy_unipro_core_clk = =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_ufs_phy_unipro_core_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2773,8 +2773,8 @@ static struct clk_branch gcc_usb30_prim_master_clk = =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_usb30_prim_master_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_usb30_prim_master_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_usb30_prim_master_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2791,8 +2791,8 @@ static struct clk_branch gcc_usb30_prim_mock_utmi_clk= =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_usb30_prim_mock_utmi_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2822,8 +2822,8 @@ static struct clk_branch gcc_usb30_sec_master_clk =3D= { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_usb30_sec_master_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_usb30_sec_master_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_usb30_sec_master_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2840,8 +2840,8 @@ static struct clk_branch gcc_usb30_sec_mock_utmi_clk = =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_usb30_sec_mock_utmi_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2884,8 +2884,8 @@ static struct clk_branch gcc_usb3_prim_phy_aux_clk = =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_usb3_prim_phy_aux_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2902,8 +2902,8 @@ static struct clk_branch gcc_usb3_prim_phy_com_aux_cl= k =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_usb3_prim_phy_com_aux_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2945,8 +2945,8 @@ static struct clk_branch gcc_usb3_sec_phy_aux_clk =3D= { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_usb3_sec_phy_aux_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -2963,8 +2963,8 @@ static struct clk_branch gcc_usb3_sec_phy_com_aux_clk= =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_usb3_sec_phy_com_aux_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -3008,8 +3008,8 @@ static struct clk_branch gcc_vdda_vs_clk =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_vdda_vs_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_vsensor_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_vsensor_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -3026,8 +3026,8 @@ static struct clk_branch gcc_vddcx_vs_clk =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_vddcx_vs_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_vsensor_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_vsensor_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -3044,8 +3044,8 @@ static struct clk_branch gcc_vddmx_vs_clk =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_vddmx_vs_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_vsensor_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_vsensor_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -3120,8 +3120,8 @@ static struct clk_branch gcc_vs_ctrl_clk =3D { .enable_mask =3D BIT(0), .hw.init =3D &(struct clk_init_data){ .name =3D "gcc_vs_ctrl_clk", - .parent_hws =3D (const struct clk_hw*[]){ - &gcc_vs_ctrl_clk_src.clkr.hw, + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gcc_vs_ctrl_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, --=20 2.34.3 From nobody Wed Apr 15 04:16:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D14D4C3F6B0 for ; Tue, 26 Jul 2022 14:23:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239272AbiGZOX5 (ORCPT ); Tue, 26 Jul 2022 10:23:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60910 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239205AbiGZOXt (ORCPT ); Tue, 26 Jul 2022 10:23:49 -0400 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0332D28E2E for ; Tue, 26 Jul 2022 07:23:48 -0700 (PDT) Received: by mail-wr1-x436.google.com with SMTP id k12so2659381wrm.13 for ; Tue, 26 Jul 2022 07:23:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=67Kung7YNnKtWIpbVwyocJw5kSHWraC1xtSnaCDvJXU=; b=veuzAA2UYQLNvpy8h8QV2ZWzdOP4fC4yqJOXWuyxIPxsKrGdjp4t1/Q1FNBiMe4a7H 0Io/7OBVJFx/jXt6mwc+qoVifk4dbjJ5LmqzMkahgaX1v+/Gqa6aWmiXLECE9WE9qAgB G3zSFOYSKubQJKoD8oGuJ+O1mmw6yWCbCphyWGXTQFl52IXxiiTLjSr5f6UBWJbbL+o0 c7V72n6fS4fKqOf00ei9Ue34FW4fNstxbOagNiIbzNUZBgZ6CYU+FdHJem7iJhPDEUW2 Cz+F1JeQAMtUKUIy+mZFww//eNE7xPnCZ1FMuMsPewbAB2bCplKAJMSgR76UHXA8aouD 7WNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=67Kung7YNnKtWIpbVwyocJw5kSHWraC1xtSnaCDvJXU=; b=WTKnOhfv4IiUWxiytW1t2eGSWrQKM1PT1moGPc/TmULNTYM7Yiy0oGhMTDsD2FaQse jyrjDWPa6ForOSMAmxmllEeci5G3KsJQDwJWNLT0EOx+0X0rpgl98bA6paCA151oQjIs qSHVm/x4y8GegC5R1P3SAqrYrlCH7W6PuvpLCFjXjBoLT8M6aiL7oHtcXqLqNm5FQ8rb 8z3pTizUah7yaYE+S94hLa0ghHPwg14f/17XqnSnZlDefgG7rs9F7vT7Ws83VXlnBRq9 dmKkOajNQgv1b1RXW0hx74aPsOylyrTfmvTwJaH/HtIDngAYYULdhTIBs7ViBa2UHF5b G9pQ== X-Gm-Message-State: AJIora+wltLjQKE593igbhJj2PKH0EGWvcP8deet0HxJSaY2Oh1A1BiM 2UaspmHtLob46oAzu1qpITsr+w== X-Google-Smtp-Source: AGRyM1tHDx6KLAsjX8mxUIEt8ym0CLyglaM4t6kgRaiIFyZIvTzO3F4zOki/jIerxgufztRtlzAilA== X-Received: by 2002:adf:fcca:0:b0:21d:68ff:2e5a with SMTP id f10-20020adffcca000000b0021d68ff2e5amr11557233wrs.453.1658845426592; Tue, 26 Jul 2022 07:23:46 -0700 (PDT) Received: from localhost.localdomain ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id t21-20020a1c7715000000b003a331c6bffdsm17017119wmi.47.2022.07.26.07.23.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Jul 2022 07:23:46 -0700 (PDT) From: Abel Vesa To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Mike Turquette , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Linux Kernel Mailing List , Abel Vesa Subject: [RFC 3/9] clk: qcom: rcg: Add macros to collapse definition Date: Tue, 26 Jul 2022 17:22:57 +0300 Message-Id: <20220726142303.4126434-4-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.3 In-Reply-To: <20220726142303.4126434-1-abel.vesa@linaro.org> References: <20220726142303.4126434-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add macros for a visually more compact rcg clocks definition, one for each type of rcg2 ops struct. These are only the ones used by gcc-sdm845 driver. More will be added later on. Signed-off-by: Abel Vesa --- drivers/clk/qcom/clk-rcg.h | 40 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h index 012e745794fd..e856d472a14e 100644 --- a/drivers/clk/qcom/clk-rcg.h +++ b/drivers/clk/qcom/clk-rcg.h @@ -180,6 +180,46 @@ struct clk_rcg_dfs_data { struct clk_init_data *init; }; =20 +#define __DEFINE_QCOM_CC_CLK_RCG2(_name, _cmd_rcgr, _mnd_width, \ + _hid_width, _parent_map, _freq_tbl, \ + _parent_data, _ops, _flags) \ + static struct clk_init_data _name##_init =3D { \ + .name =3D #_name, \ + .parent_data =3D _parent_data, \ + .num_parents =3D ARRAY_SIZE(_parent_data), \ + .ops =3D _ops, \ + }; \ + \ + static struct clk_rcg2 _name =3D { \ + .cmd_rcgr =3D _cmd_rcgr, \ + .mnd_width =3D _mnd_width, \ + .hid_width =3D _hid_width, \ + .parent_map =3D _parent_map, \ + .freq_tbl =3D _freq_tbl, \ + .clkr.hw.init =3D &_name##_init, \ + } + +#define DEFINE_QCOM_CC_CLK_RCG2(_name, _cmd_rcgr, _mnd_width, \ + _hid_width, _parent_map, _freq_tbl, \ + _parent_data) \ + __DEFINE_QCOM_CC_CLK_RCG2(_name, _cmd_rcgr, _mnd_width, \ + _hid_width, _parent_map, _freq_tbl, \ + _parent_data, &clk_rcg2_ops, 0) + +#define DEFINE_QCOM_CC_CLK_RCG2_SHARED(_name, _cmd_rcgr, _mnd_width, \ + _hid_width, _parent_map, _freq_tbl, \ + _parent_data) \ + __DEFINE_QCOM_CC_CLK_RCG2(_name, _cmd_rcgr, _mnd_width, \ + _hid_width, _parent_map, _freq_tbl, \ + _parent_data, &clk_rcg2_shared_ops, 0) + +#define DEFINE_QCOM_CC_CLK_RCG2_FLOOR(_name, _cmd_rcgr, _mnd_width, \ + _hid_width, _parent_map, _freq_tbl, \ + _parent_data) \ + __DEFINE_QCOM_CC_CLK_RCG2(_name, _cmd_rcgr, _mnd_width, \ + _hid_width, _parent_map, _freq_tbl, \ + _parent_data, &clk_rcg2_floor_ops, 0) + #define DEFINE_RCG_DFS(r) \ { .rcg =3D &r, .init =3D &r##_init } =20 --=20 2.34.3 From nobody Wed Apr 15 04:16:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 485BBC00140 for ; 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Tue, 26 Jul 2022 07:23:47 -0700 (PDT) From: Abel Vesa To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Mike Turquette , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Linux Kernel Mailing List , Abel Vesa Subject: [RFC 4/9] clk: qcom: alpha-pll: Add macros to collapse definition Date: Tue, 26 Jul 2022 17:22:58 +0300 Message-Id: <20220726142303.4126434-5-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.3 In-Reply-To: <20220726142303.4126434-1-abel.vesa@linaro.org> References: <20220726142303.4126434-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add macros for a visually more compact alpha-pll clocks definition, one for alpha-pll and one for alpha-pll postdiv. These are only the ones used by gcc-sdm845 driver. More will be added later on. Signed-off-by: Abel Vesa --- drivers/clk/qcom/clk-alpha-pll.h | 61 ++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-= pll.h index 447efb82fe59..1bf7a3ecb7f1 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -127,6 +127,67 @@ struct alpha_pll_config { u32 vco_mask; }; =20 +#define __DEFINE_QCOM_CC_CLK_ALPHA_PLL(_name, _offset, _regs, \ + _enable_reg, _enable_mask, \ + _parent_fw_name, _flags, _ops) \ + static struct clk_alpha_pll _name =3D { \ + .offset =3D _offset, \ + .regs =3D _regs, \ + .clkr =3D { \ + .enable_reg =3D _enable_reg, \ + .enable_mask =3D _enable_mask, \ + .hw.init =3D &(struct clk_init_data){ \ + .name =3D #_name, \ + .parent_data =3D &(const struct clk_parent_data){ \ + .fw_name =3D _parent_fw_name, \ + .name =3D _parent_fw_name, \ + }, \ + .num_parents =3D 1, \ + .ops =3D _ops, \ + .flags =3D _flags, \ + }, \ + }, \ + } + +#define __DEFINE_QCOM_CC_CLK_ALPHA_PLL_POSTDIV(_name, _offset, \ + _post_div_shift, _post_div_table, \ + _width, _regs, \ + _parent_hws, _flags, _ops) \ + static struct clk_alpha_pll_postdiv _name =3D { \ + .offset =3D _offset, \ + .post_div_shift =3D _post_div_shift, \ + .post_div_table =3D _post_div_table, \ + .num_post_div =3D ARRAY_SIZE(_post_div_table), \ + .width =3D _width, \ + .regs =3D _regs, \ + .clkr.hw.init =3D &(struct clk_init_data){ \ + .name =3D #_name, \ + .parent_hws =3D (const struct clk_hw*[]){ \ + _parent_hws, \ + }, \ + .num_parents =3D 1, \ + .ops =3D _ops, \ + .flags =3D _flags, \ + }, \ + } + +#define DEFINE_QCOM_CC_CLK_ALPHA_PLL(_name, _offset, \ + _enable_reg, _enable_mask, \ + _parent_fw_name) \ + __DEFINE_QCOM_CC_CLK_ALPHA_PLL(_name, _offset, \ + clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], \ + _enable_reg, _enable_mask, \ + _parent_fw_name, 0, \ + &clk_alpha_pll_fixed_fabia_ops) + +#define DEFINE_QCOM_CC_CLK_ALPHA_PLL_POSTDIV(_name, _offset, \ + _post_div_shift, _post_div_table, \ + _width, _parent_hws) \ + __DEFINE_QCOM_CC_CLK_ALPHA_PLL_POSTDIV(_name, _offset, \ + _post_div_shift, _post_div_table, _width, \ + clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], \ + _parent_hws, 0, &clk_alpha_pll_postdiv_fabia_ops) + extern const struct clk_ops clk_alpha_pll_ops; extern const struct clk_ops clk_alpha_pll_fixed_ops; extern const struct clk_ops clk_alpha_pll_hwfsm_ops; --=20 2.34.3 From nobody Wed Apr 15 04:16:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47809C04A68 for ; Tue, 26 Jul 2022 14:24:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239337AbiGZOYI (ORCPT ); Tue, 26 Jul 2022 10:24:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32824 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239073AbiGZOXy (ORCPT ); Tue, 26 Jul 2022 10:23:54 -0400 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B390D28E0D for ; Tue, 26 Jul 2022 07:23:50 -0700 (PDT) Received: by mail-wm1-x32f.google.com with SMTP id i205-20020a1c3bd6000000b003a2fa488efdso5673063wma.4 for ; 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Tue, 26 Jul 2022 07:23:49 -0700 (PDT) Received: from localhost.localdomain ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id t21-20020a1c7715000000b003a331c6bffdsm17017119wmi.47.2022.07.26.07.23.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Jul 2022 07:23:48 -0700 (PDT) From: Abel Vesa To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Mike Turquette , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Linux Kernel Mailing List , Abel Vesa Subject: [RFC 5/9] clk: qcom: branch: Add macros to collapse definition Date: Tue, 26 Jul 2022 17:22:59 +0300 Message-Id: <20220726142303.4126434-6-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.3 In-Reply-To: <20220726142303.4126434-1-abel.vesa@linaro.org> References: <20220726142303.4126434-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add macros for a visually more compact branch clocks definition, one for the common branch and one for branch_aon. They differ from ops point of view, like their name suggest. There are also three different macros to define the clk.hw.init depending on the number and type of parent passed on as argument. Also, the macros added here are only the ones used by gcc-sdm845 driver. More will be added later on. Signed-off-by: Abel Vesa --- drivers/clk/qcom/clk-branch.h | 82 +++++++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h index 17a58119165e..a12ffebf0e5f 100644 --- a/drivers/clk/qcom/clk-branch.h +++ b/drivers/clk/qcom/clk-branch.h @@ -37,6 +37,88 @@ struct clk_branch { struct clk_regmap clkr; }; =20 +#define INIT_QCOM_CC_CLKR_HW_2(_name, _flags, _ops, _fw_name) \ + { \ + .name =3D #_name, \ + .parent_data =3D &(const struct clk_parent_data) { \ + .fw_name =3D _fw_name, \ + .name =3D _fw_name, \ + }, \ + .num_parents =3D 1, \ + .flags =3D _flags, \ + .ops =3D _ops, \ + } + +#define INIT_QCOM_CC_CLKR_HW_1(_name, _flags, _ops, _parent_hw) \ + { \ + .name =3D #_name, \ + .parent_data =3D &(const struct clk_parent_data) { \ + .hw =3D _parent_hw, \ + }, \ + .num_parents =3D 1, \ + .flags =3D _flags, \ + .ops =3D _ops, \ + } + +#define INIT_QCOM_CC_CLKR_HW_0(_name, _flags, _ops, ...) \ + { \ + .name =3D #_name, \ + .flags =3D _flags, \ + .ops =3D _ops, \ + } + +#define INIT_QCOM_CC_CLKR(_num_parents, _enable_reg, _enable_mask, \ + _name, _flags, _ops, ...) \ + { \ + .enable_reg =3D _enable_reg, \ + .enable_mask =3D _enable_mask, \ + .hw.init =3D &(struct clk_init_data) \ + INIT_QCOM_CC_CLKR_HW_##_num_parents(_name, \ + _flags, \ + _ops, __VA_ARGS__), \ + } + +#define __DEFINE_QCOM_CC_CLK_BRANCH(_halt_check, _name, _num_parents, \ + _halt_reg, \ + _hwcg_reg, _hwcg_bit, \ + _enable_reg, _enable_mask, \ + _flags, _ops, ...) \ + static struct clk_branch _name =3D { \ + .halt_reg =3D _halt_reg, \ + .halt_check =3D BRANCH_##_halt_check, \ + .hwcg_reg =3D _hwcg_reg, \ + .hwcg_bit =3D _hwcg_bit, \ + .clkr =3D INIT_QCOM_CC_CLKR(_num_parents, _enable_reg, \ + _enable_mask, \ + _name, _flags, \ + _ops, __VA_ARGS__), \ + } + +#define DEFINE_QCOM_CC_CLK_BRANCH(_halt_check, _name, _num_parents, \ + _halt_reg, \ + _hwcg_reg, _hwcg_bit, \ + _enable_reg, _enable_mask, \ + _flags, ...) \ + __DEFINE_QCOM_CC_CLK_BRANCH(_halt_check, _name, _num_parents, \ + _halt_reg, \ + _hwcg_reg, _hwcg_bit, \ + _enable_reg, _enable_mask, \ + _flags, \ + &clk_branch2_ops, __VA_ARGS__) + +#define DEFINE_QCOM_CC_CLK_BRANCH_AON(_halt_check, _name, _num_parents, \ + _halt_reg, \ + _hwcg_reg, _hwcg_bit, \ + _enable_reg, _enable_mask, \ + _flags, ...) \ + __DEFINE_QCOM_CC_CLK_BRANCH(_halt_check, _name, _num_parents, \ + _halt_reg, \ + _hwcg_reg, _hwcg_bit, \ + _enable_reg, _enable_mask, \ + _flags, \ + &clk_branch2_aon_ops, \ + __VA_ARGS__) + extern const struct clk_ops clk_branch_ops; extern const struct clk_ops clk_branch2_ops; extern const struct clk_ops clk_branch_simple_ops; --=20 2.34.3 From nobody Wed Apr 15 04:16:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5776C00140 for ; Tue, 26 Jul 2022 14:24:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239321AbiGZOYE (ORCPT ); Tue, 26 Jul 2022 10:24:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32788 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239256AbiGZOXx (ORCPT ); Tue, 26 Jul 2022 10:23:53 -0400 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EA8A528E2E for ; Tue, 26 Jul 2022 07:23:51 -0700 (PDT) Received: by mail-wm1-x335.google.com with SMTP id v67-20020a1cac46000000b003a1888b9d36so11463725wme.0 for ; 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Tue, 26 Jul 2022 07:23:50 -0700 (PDT) Received: from localhost.localdomain ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id t21-20020a1c7715000000b003a331c6bffdsm17017119wmi.47.2022.07.26.07.23.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Jul 2022 07:23:49 -0700 (PDT) From: Abel Vesa To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Mike Turquette , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Linux Kernel Mailing List , Abel Vesa Subject: [RFC 6/9] clk: qcom: common: Add macro wrapper for all clock types Date: Tue, 26 Jul 2022 17:23:00 +0300 Message-Id: <20220726142303.4126434-7-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.3 In-Reply-To: <20220726142303.4126434-1-abel.vesa@linaro.org> References: <20220726142303.4126434-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a generic macro that uses the clk_type to figure out which clock type specific macro to call. Signed-off-by: Abel Vesa --- drivers/clk/qcom/common.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h index 9c8f7b798d9f..475febd19dba 100644 --- a/drivers/clk/qcom/common.h +++ b/drivers/clk/qcom/common.h @@ -19,6 +19,9 @@ struct clk_hw; #define PLL_VOTE_FSM_ENA BIT(20) #define PLL_VOTE_FSM_RESET BIT(21) =20 +#define DEFINE_QCOM_CC_CLK(clk_type, ...) \ + DEFINE_QCOM_CC_CLK_##clk_type(__VA_ARGS__) + struct qcom_cc_desc { const struct regmap_config *config; struct clk_regmap **clks; --=20 2.34.3 From nobody Wed Apr 15 04:16:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E25DC00140 for ; Tue, 26 Jul 2022 14:24:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239354AbiGZOYV (ORCPT ); Tue, 26 Jul 2022 10:24:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32784 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239205AbiGZOX5 (ORCPT ); Tue, 26 Jul 2022 10:23:57 -0400 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B366529C93 for ; Tue, 26 Jul 2022 07:23:52 -0700 (PDT) Received: by mail-wr1-x42e.google.com with SMTP id q18so9964433wrx.8 for ; Tue, 26 Jul 2022 07:23:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TrNPWubvkYWFFe9pWDXo+s+KPbQXOw/xubvlLGQjNNs=; b=suNtiP8y9LMJ/BqiHhCTEYHgsWOnctpd0b9wDtCSbBC4YmFvpuxipo25r7Bc4rtkYn 42Gru7IeCfAsL5P44jXW9t5g4Ut8oDlB2z7nXua5mKufPI9x76sI4ypu0kRLUuQ/cu8H H18CcfEotNixzdZc3P88Gv0Cw0v8NrHs4zXzTBoKhkAziJdHvp6vjU625r71JjZtHkca rU/ONWblhjHopRI/1di8haqcApCbD92gtHRoXmp1aZHZTx0WXd9p1fVz/ag4HGfxJHb/ GI+zuhGHRL6UibaboPi+rZd5NPAbwFWTiwo+jSB0tVuvSioR3LgA+BJbDCPjan+o94lX b6Jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TrNPWubvkYWFFe9pWDXo+s+KPbQXOw/xubvlLGQjNNs=; b=57dfo5ovxlqD9M9EerPrPtgK2/TlLIjps1cAvxqxcCs/obf0BFR/Re6/248EWCx4nt FESNekQRnp7T3F1XAqKBjYQuaOcpUVNpQ9J465OQVUjDRVKK5U4svzKF5W3yiMU7hktR 6wRmRqbP5xVvOWW6E3nJLUo1FJKKb5/kdXgBpkfrhV7qKipP2rGuAEdLhvtHXpbDLuYQ 12Ze+oVjzdNIffABNo/Wxo0Y6fnN96uLZAu9tAHKVHXMuaWSwrmbmeljDY/t2HrrzYvY pPXM6mfBbQ+Bua691yHbt+BgkhottjjfIc2n9wxqxbXolIjIy3q8Fh3bpXok0078este fFBQ== X-Gm-Message-State: AJIora+WAD4vwd7+eJOYmHxF7UJcx0467OFOsd6nDv9M9t+KZcv/3ZnH InXC7R8tkXC5D3tdwPrqb2Wbig== X-Google-Smtp-Source: AGRyM1vQRvwRo83wwSwlEXSX48zRlrRIAvc5AtGldJX/XwumqGcU6AVqaP25qQ0oPMOjLGuHeOQWlg== X-Received: by 2002:adf:efc6:0:b0:21e:6120:edfe with SMTP id i6-20020adfefc6000000b0021e6120edfemr10703752wrp.542.1658845431850; Tue, 26 Jul 2022 07:23:51 -0700 (PDT) Received: from localhost.localdomain ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id t21-20020a1c7715000000b003a331c6bffdsm17017119wmi.47.2022.07.26.07.23.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Jul 2022 07:23:51 -0700 (PDT) From: Abel Vesa To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Mike Turquette , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Linux Kernel Mailing List , Abel Vesa Subject: [RFC 7/9] clk: qcom: gcc-sdm845: Switch to macros to collapse branch clocks definitions Date: Tue, 26 Jul 2022 17:23:01 +0300 Message-Id: <20220726142303.4126434-8-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.3 In-Reply-To: <20220726142303.4126434-1-abel.vesa@linaro.org> References: <20220726142303.4126434-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Switch from the expanded branch clocks definitions to the more compact macro. Signed-off-by: Abel Vesa --- drivers/clk/qcom/gcc-sdm845.c | 2319 ++------------------------------- 1 file changed, 138 insertions(+), 2181 deletions(-) diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c index 599e7d23aeca..2e66256599d3 100644 --- a/drivers/clk/qcom/gcc-sdm845.c +++ b/drivers/clk/qcom/gcc-sdm845.c @@ -1005,2190 +1005,147 @@ static struct clk_rcg2 gcc_vsensor_clk_src =3D { }, }; =20 -static struct clk_branch gcc_aggre_noc_pcie_tbu_clk =3D { - .halt_reg =3D 0x90014, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x90014, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_aggre_noc_pcie_tbu_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_ufs_card_axi_clk =3D { - .halt_reg =3D 0x82028, - .halt_check =3D BRANCH_HALT, - .hwcg_reg =3D 0x82028, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x82028, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_aggre_ufs_card_axi_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_ufs_card_axi_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_ufs_phy_axi_clk =3D { - .halt_reg =3D 0x82024, - .halt_check =3D BRANCH_HALT, - .hwcg_reg =3D 0x82024, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x82024, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_aggre_ufs_phy_axi_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_ufs_phy_axi_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_usb3_prim_axi_clk =3D { - .halt_reg =3D 0x8201c, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8201c, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_aggre_usb3_prim_axi_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_usb30_prim_master_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_usb3_sec_axi_clk =3D { - .halt_reg =3D 0x82020, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x82020, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_aggre_usb3_sec_axi_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_usb30_sec_master_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_apc_vs_clk =3D { - .halt_reg =3D 0x7a050, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x7a050, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_apc_vs_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_vsensor_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_boot_rom_ahb_clk =3D { - .halt_reg =3D 0x38004, - .halt_check =3D BRANCH_HALT_VOTED, - .hwcg_reg =3D 0x38004, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x52004, - .enable_mask =3D BIT(10), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_boot_rom_ahb_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_camera_ahb_clk =3D { - .halt_reg =3D 0xb008, - .halt_check =3D BRANCH_HALT, - .hwcg_reg =3D 0xb008, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0xb008, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_camera_ahb_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_camera_axi_clk =3D { - .halt_reg =3D 0xb020, - .halt_check =3D BRANCH_VOTED, - .clkr =3D { - .enable_reg =3D 0xb020, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_camera_axi_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_camera_xo_clk =3D { - .halt_reg =3D 0xb02c, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0xb02c, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_camera_xo_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ce1_ahb_clk =3D { - .halt_reg =3D 0x4100c, - .halt_check =3D BRANCH_HALT_VOTED, - .hwcg_reg =3D 0x4100c, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x52004, - .enable_mask =3D BIT(3), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_ce1_ahb_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ce1_axi_clk =3D { - .halt_reg =3D 0x41008, - .halt_check =3D BRANCH_HALT_VOTED, - .clkr =3D { - .enable_reg =3D 0x52004, - .enable_mask =3D BIT(4), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_ce1_axi_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ce1_clk =3D { - .halt_reg =3D 0x41004, - .halt_check =3D BRANCH_HALT_VOTED, - .clkr =3D { - .enable_reg =3D 0x52004, - .enable_mask =3D BIT(5), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_ce1_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk =3D { - .halt_reg =3D 0x502c, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x502c, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_cfg_noc_usb3_prim_axi_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_usb30_prim_master_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk =3D { - .halt_reg =3D 0x5030, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x5030, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_cfg_noc_usb3_sec_axi_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_usb30_sec_master_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cpuss_ahb_clk =3D { - .halt_reg =3D 0x48000, - .halt_check =3D BRANCH_HALT_VOTED, - .clkr =3D { - .enable_reg =3D 0x52004, - .enable_mask =3D BIT(21), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_cpuss_ahb_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_cpuss_ahb_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cpuss_rbcpr_clk =3D { - .halt_reg =3D 0x48008, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x48008, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_cpuss_rbcpr_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_cpuss_rbcpr_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ddrss_gpu_axi_clk =3D { - .halt_reg =3D 0x44038, - .halt_check =3D BRANCH_VOTED, - .clkr =3D { - .enable_reg =3D 0x44038, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_ddrss_gpu_axi_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_disp_ahb_clk =3D { - .halt_reg =3D 0xb00c, - .halt_check =3D BRANCH_HALT, - .hwcg_reg =3D 0xb00c, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0xb00c, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_disp_ahb_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_disp_axi_clk =3D { - .halt_reg =3D 0xb024, - .halt_check =3D BRANCH_VOTED, - .clkr =3D { - .enable_reg =3D 0xb024, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_disp_axi_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_disp_gpll0_clk_src =3D { - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x52004, - .enable_mask =3D BIT(18), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_disp_gpll0_clk_src", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gpll0.clkr.hw, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_aon_ops, - }, - }, -}; - -static struct clk_branch gcc_disp_gpll0_div_clk_src =3D { - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x52004, - .enable_mask =3D BIT(19), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_disp_gpll0_div_clk_src", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gpll0_out_even.clkr.hw, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_disp_xo_clk =3D { - .halt_reg =3D 0xb030, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0xb030, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_disp_xo_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gp1_clk =3D { - .halt_reg =3D 0x64000, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x64000, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_gp1_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_gp1_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gp2_clk =3D { - .halt_reg =3D 0x65000, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x65000, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_gp2_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_gp2_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gp3_clk =3D { - .halt_reg =3D 0x66000, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x66000, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_gp3_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_gp3_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_cfg_ahb_clk =3D { - .halt_reg =3D 0x71004, - .halt_check =3D BRANCH_HALT, - .hwcg_reg =3D 0x71004, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x71004, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_gpu_cfg_ahb_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_gpll0_clk_src =3D { - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x52004, - .enable_mask =3D BIT(15), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_gpu_gpll0_clk_src", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gpll0.clkr.hw, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_gpll0_div_clk_src =3D { - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x52004, - .enable_mask =3D BIT(16), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_gpu_gpll0_div_clk_src", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gpll0_out_even.clkr.hw, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_iref_clk =3D { - .halt_reg =3D 0x8c010, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8c010, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_gpu_iref_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_memnoc_gfx_clk =3D { - .halt_reg =3D 0x7100c, - .halt_check =3D BRANCH_VOTED, - .clkr =3D { - .enable_reg =3D 0x7100c, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_gpu_memnoc_gfx_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk =3D { - .halt_reg =3D 0x71018, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x71018, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_gpu_snoc_dvm_gfx_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_vs_clk =3D { - .halt_reg =3D 0x7a04c, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x7a04c, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_gpu_vs_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_vsensor_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_mss_axis2_clk =3D { - .halt_reg =3D 0x8a008, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8a008, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_mss_axis2_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_mss_cfg_ahb_clk =3D { - .halt_reg =3D 0x8a000, - .halt_check =3D BRANCH_HALT, - .hwcg_reg =3D 0x8a000, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x8a000, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_mss_cfg_ahb_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_mss_gpll0_div_clk_src =3D { - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x52004, - .enable_mask =3D BIT(17), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_mss_gpll0_div_clk_src", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_mss_mfab_axis_clk =3D { - .halt_reg =3D 0x8a004, - .halt_check =3D BRANCH_VOTED, - .hwcg_reg =3D 0x8a004, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x8a004, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_mss_mfab_axis_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_mss_q6_memnoc_axi_clk =3D { - .halt_reg =3D 0x8a154, - .halt_check =3D BRANCH_VOTED, - .clkr =3D { - .enable_reg =3D 0x8a154, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_mss_q6_memnoc_axi_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_mss_snoc_axi_clk =3D { - .halt_reg =3D 0x8a150, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8a150, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_mss_snoc_axi_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_mss_vs_clk =3D { - .halt_reg =3D 0x7a048, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x7a048, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_mss_vs_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_vsensor_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_aux_clk =3D { - .halt_reg =3D 0x6b01c, - .halt_check =3D BRANCH_HALT_VOTED, - .clkr =3D { - .enable_reg =3D 0x5200c, - .enable_mask =3D BIT(3), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_pcie_0_aux_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_pcie_0_aux_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_cfg_ahb_clk =3D { - .halt_reg =3D 0x6b018, - .halt_check =3D BRANCH_HALT_VOTED, - .hwcg_reg =3D 0x6b018, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x5200c, - .enable_mask =3D BIT(2), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_pcie_0_cfg_ahb_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_clkref_clk =3D { - .halt_reg =3D 0x8c00c, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8c00c, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_pcie_0_clkref_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_mstr_axi_clk =3D { - .halt_reg =3D 0x6b014, - .halt_check =3D BRANCH_HALT_VOTED, - .clkr =3D { - .enable_reg =3D 0x5200c, - .enable_mask =3D BIT(1), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_pcie_0_mstr_axi_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_pipe_clk =3D { - .halt_check =3D BRANCH_HALT_SKIP, - .clkr =3D { - .enable_reg =3D 0x5200c, - .enable_mask =3D BIT(4), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_pcie_0_pipe_clk", - .parent_data =3D &(const struct clk_parent_data){ - .fw_name =3D "pcie_0_pipe_clk", .name =3D "pcie_0_pipe_clk", - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_slv_axi_clk =3D { - .halt_reg =3D 0x6b010, - .halt_check =3D BRANCH_HALT_VOTED, - .hwcg_reg =3D 0x6b010, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x5200c, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_pcie_0_slv_axi_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk =3D { - .halt_reg =3D 0x6b00c, - .halt_check =3D BRANCH_HALT_VOTED, - .clkr =3D { - .enable_reg =3D 0x5200c, - .enable_mask =3D BIT(5), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_pcie_0_slv_q2a_axi_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_aux_clk =3D { - .halt_reg =3D 0x8d01c, - .halt_check =3D BRANCH_HALT_VOTED, - .clkr =3D { - .enable_reg =3D 0x52004, - .enable_mask =3D BIT(29), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_pcie_1_aux_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_pcie_1_aux_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_cfg_ahb_clk =3D { - .halt_reg =3D 0x8d018, - .halt_check =3D BRANCH_HALT_VOTED, - .hwcg_reg =3D 0x8d018, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x52004, - .enable_mask =3D BIT(28), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_pcie_1_cfg_ahb_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_clkref_clk =3D { - .halt_reg =3D 0x8c02c, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8c02c, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_pcie_1_clkref_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_mstr_axi_clk =3D { - .halt_reg =3D 0x8d014, - .halt_check =3D BRANCH_HALT_VOTED, - .clkr =3D { - .enable_reg =3D 0x52004, - .enable_mask =3D BIT(27), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_pcie_1_mstr_axi_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_pipe_clk =3D { - .halt_check =3D BRANCH_HALT_SKIP, - .clkr =3D { - .enable_reg =3D 0x52004, - .enable_mask =3D BIT(30), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_pcie_1_pipe_clk", - .parent_data =3D &(const struct clk_parent_data){ - .fw_name =3D "pcie_1_pipe_clk", .name =3D "pcie_1_pipe_clk", - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_slv_axi_clk =3D { - .halt_reg =3D 0x8d010, - .halt_check =3D BRANCH_HALT_VOTED, - .hwcg_reg =3D 0x8d010, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x52004, - .enable_mask =3D BIT(26), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_pcie_1_slv_axi_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk =3D { - .halt_reg =3D 0x8d00c, - .halt_check =3D BRANCH_HALT_VOTED, - .clkr =3D { - .enable_reg =3D 0x52004, - .enable_mask =3D BIT(25), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_pcie_1_slv_q2a_axi_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_phy_aux_clk =3D { - .halt_reg =3D 0x6f004, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x6f004, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_pcie_phy_aux_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_pcie_0_aux_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_phy_refgen_clk =3D { - .halt_reg =3D 0x6f02c, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x6f02c, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_pcie_phy_refgen_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_pcie_phy_refgen_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pdm2_clk =3D { - .halt_reg =3D 0x3300c, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x3300c, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_pdm2_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_pdm2_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pdm_ahb_clk =3D { - .halt_reg =3D 0x33004, - .halt_check =3D BRANCH_HALT, - .hwcg_reg =3D 0x33004, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x33004, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_pdm_ahb_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pdm_xo4_clk =3D { - .halt_reg =3D 0x33008, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x33008, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_pdm_xo4_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_prng_ahb_clk =3D { - .halt_reg =3D 0x34004, - .halt_check =3D BRANCH_HALT_VOTED, - .hwcg_reg =3D 0x34004, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x52004, - .enable_mask =3D BIT(13), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_prng_ahb_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qmip_camera_ahb_clk =3D { - .halt_reg =3D 0xb014, - .halt_check =3D BRANCH_HALT, - .hwcg_reg =3D 0xb014, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0xb014, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_qmip_camera_ahb_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qmip_disp_ahb_clk =3D { - .halt_reg =3D 0xb018, - .halt_check =3D BRANCH_HALT, - .hwcg_reg =3D 0xb018, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0xb018, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_qmip_disp_ahb_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qmip_video_ahb_clk =3D { - .halt_reg =3D 0xb010, - .halt_check =3D BRANCH_HALT, - .hwcg_reg =3D 0xb010, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0xb010, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_qmip_video_ahb_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk =3D { - .halt_reg =3D 0x4b000, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x4b000, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_qspi_cnoc_periph_ahb_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qspi_core_clk =3D { - .halt_reg =3D 0x4b004, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x4b004, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_qspi_core_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_qspi_core_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s0_clk =3D { - .halt_reg =3D 0x17030, - .halt_check =3D BRANCH_HALT_VOTED, - .clkr =3D { - .enable_reg =3D 0x5200c, - .enable_mask =3D BIT(10), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_qupv3_wrap0_s0_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s1_clk =3D { - .halt_reg =3D 0x17160, - .halt_check =3D BRANCH_HALT_VOTED, - .clkr =3D { - .enable_reg =3D 0x5200c, - .enable_mask =3D BIT(11), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_qupv3_wrap0_s1_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s2_clk =3D { - .halt_reg =3D 0x17290, - .halt_check =3D BRANCH_HALT_VOTED, - .clkr =3D { - .enable_reg =3D 0x5200c, - .enable_mask =3D BIT(12), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_qupv3_wrap0_s2_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s3_clk =3D { - .halt_reg =3D 0x173c0, - .halt_check =3D BRANCH_HALT_VOTED, - .clkr =3D { - .enable_reg =3D 0x5200c, - .enable_mask =3D BIT(13), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_qupv3_wrap0_s3_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s4_clk =3D { - .halt_reg =3D 0x174f0, - .halt_check =3D BRANCH_HALT_VOTED, - .clkr =3D { - .enable_reg =3D 0x5200c, - .enable_mask =3D BIT(14), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_qupv3_wrap0_s4_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s5_clk =3D { - .halt_reg =3D 0x17620, - .halt_check =3D BRANCH_HALT_VOTED, - .clkr =3D { - .enable_reg =3D 0x5200c, - .enable_mask =3D BIT(15), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_qupv3_wrap0_s5_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s6_clk =3D { - .halt_reg =3D 0x17750, - .halt_check =3D BRANCH_HALT_VOTED, - .clkr =3D { - .enable_reg =3D 0x5200c, - .enable_mask =3D BIT(16), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_qupv3_wrap0_s6_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s7_clk =3D { - .halt_reg =3D 0x17880, - .halt_check =3D BRANCH_HALT_VOTED, - .clkr =3D { - .enable_reg =3D 0x5200c, - .enable_mask =3D BIT(17), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_qupv3_wrap0_s7_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s0_clk =3D { - .halt_reg =3D 0x18014, - .halt_check =3D BRANCH_HALT_VOTED, - .clkr =3D { - .enable_reg =3D 0x5200c, - .enable_mask =3D BIT(22), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_qupv3_wrap1_s0_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s1_clk =3D { - .halt_reg =3D 0x18144, - .halt_check =3D BRANCH_HALT_VOTED, - .clkr =3D { - .enable_reg =3D 0x5200c, - .enable_mask =3D BIT(23), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_qupv3_wrap1_s1_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s2_clk =3D { - .halt_reg =3D 0x18274, - .halt_check =3D BRANCH_HALT_VOTED, - .clkr =3D { - .enable_reg =3D 0x5200c, - .enable_mask =3D BIT(24), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_qupv3_wrap1_s2_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s3_clk =3D { - .halt_reg =3D 0x183a4, - .halt_check =3D BRANCH_HALT_VOTED, - .clkr =3D { - .enable_reg =3D 0x5200c, - .enable_mask =3D BIT(25), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_qupv3_wrap1_s3_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s4_clk =3D { - .halt_reg =3D 0x184d4, - .halt_check =3D BRANCH_HALT_VOTED, - .clkr =3D { - .enable_reg =3D 0x5200c, - .enable_mask =3D BIT(26), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_qupv3_wrap1_s4_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s5_clk =3D { - .halt_reg =3D 0x18604, - .halt_check =3D BRANCH_HALT_VOTED, - .clkr =3D { - .enable_reg =3D 0x5200c, - .enable_mask =3D BIT(27), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_qupv3_wrap1_s5_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s6_clk =3D { - .halt_reg =3D 0x18734, - .halt_check =3D BRANCH_HALT_VOTED, - .clkr =3D { - .enable_reg =3D 0x5200c, - .enable_mask =3D BIT(28), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_qupv3_wrap1_s6_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s7_clk =3D { - .halt_reg =3D 0x18864, - .halt_check =3D BRANCH_HALT_VOTED, - .clkr =3D { - .enable_reg =3D 0x5200c, - .enable_mask =3D BIT(29), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_qupv3_wrap1_s7_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk =3D { - .halt_reg =3D 0x17004, - .halt_check =3D BRANCH_HALT_VOTED, - .clkr =3D { - .enable_reg =3D 0x5200c, - .enable_mask =3D BIT(6), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_qupv3_wrap_0_m_ahb_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk =3D { - .halt_reg =3D 0x17008, - .halt_check =3D BRANCH_HALT_VOTED, - .hwcg_reg =3D 0x17008, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x5200c, - .enable_mask =3D BIT(7), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_qupv3_wrap_0_s_ahb_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk =3D { - .halt_reg =3D 0x1800c, - .halt_check =3D BRANCH_HALT_VOTED, - .clkr =3D { - .enable_reg =3D 0x5200c, - .enable_mask =3D BIT(20), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_qupv3_wrap_1_m_ahb_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk =3D { - .halt_reg =3D 0x18010, - .halt_check =3D BRANCH_HALT_VOTED, - .hwcg_reg =3D 0x18010, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x5200c, - .enable_mask =3D BIT(21), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_qupv3_wrap_1_s_ahb_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc2_ahb_clk =3D { - .halt_reg =3D 0x14008, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x14008, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_sdcc2_ahb_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc2_apps_clk =3D { - .halt_reg =3D 0x14004, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x14004, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_sdcc2_apps_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_sdcc2_apps_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc4_ahb_clk =3D { - .halt_reg =3D 0x16008, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x16008, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_sdcc4_ahb_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc4_apps_clk =3D { - .halt_reg =3D 0x16004, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x16004, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_sdcc4_apps_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_sdcc4_apps_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sys_noc_cpuss_ahb_clk =3D { - .halt_reg =3D 0x414c, - .halt_check =3D BRANCH_HALT_VOTED, - .clkr =3D { - .enable_reg =3D 0x52004, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_sys_noc_cpuss_ahb_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_cpuss_ahb_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_tsif_ahb_clk =3D { - .halt_reg =3D 0x36004, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x36004, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_tsif_ahb_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_tsif_inactivity_timers_clk =3D { - .halt_reg =3D 0x3600c, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x3600c, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_tsif_inactivity_timers_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_tsif_ref_clk =3D { - .halt_reg =3D 0x36008, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x36008, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_tsif_ref_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_tsif_ref_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_ahb_clk =3D { - .halt_reg =3D 0x75010, - .halt_check =3D BRANCH_HALT, - .hwcg_reg =3D 0x75010, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x75010, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_ufs_card_ahb_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_axi_clk =3D { - .halt_reg =3D 0x7500c, - .halt_check =3D BRANCH_HALT, - .hwcg_reg =3D 0x7500c, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x7500c, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_ufs_card_axi_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_ufs_card_axi_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_clkref_clk =3D { - .halt_reg =3D 0x8c004, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8c004, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_ufs_card_clkref_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_ice_core_clk =3D { - .halt_reg =3D 0x75058, - .halt_check =3D BRANCH_HALT, - .hwcg_reg =3D 0x75058, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x75058, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_ufs_card_ice_core_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_ufs_card_ice_core_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_phy_aux_clk =3D { - .halt_reg =3D 0x7508c, - .halt_check =3D BRANCH_HALT, - .hwcg_reg =3D 0x7508c, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x7508c, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_ufs_card_phy_aux_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_ufs_card_phy_aux_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_rx_symbol_0_clk =3D { - .halt_check =3D BRANCH_HALT_SKIP, - .clkr =3D { - .enable_reg =3D 0x75018, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_ufs_card_rx_symbol_0_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_rx_symbol_1_clk =3D { - .halt_check =3D BRANCH_HALT_SKIP, - .clkr =3D { - .enable_reg =3D 0x750a8, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_ufs_card_rx_symbol_1_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_tx_symbol_0_clk =3D { - .halt_check =3D BRANCH_HALT_SKIP, - .clkr =3D { - .enable_reg =3D 0x75014, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_ufs_card_tx_symbol_0_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_card_unipro_core_clk =3D { - .halt_reg =3D 0x75054, - .halt_check =3D BRANCH_HALT, - .hwcg_reg =3D 0x75054, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x75054, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_ufs_card_unipro_core_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_ufs_card_unipro_core_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_mem_clkref_clk =3D { - .halt_reg =3D 0x8c000, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8c000, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_ufs_mem_clkref_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_ahb_clk =3D { - .halt_reg =3D 0x77010, - .halt_check =3D BRANCH_HALT, - .hwcg_reg =3D 0x77010, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x77010, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_ufs_phy_ahb_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_axi_clk =3D { - .halt_reg =3D 0x7700c, - .halt_check =3D BRANCH_HALT, - .hwcg_reg =3D 0x7700c, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x7700c, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_ufs_phy_axi_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_ufs_phy_axi_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_ice_core_clk =3D { - .halt_reg =3D 0x77058, - .halt_check =3D BRANCH_HALT, - .hwcg_reg =3D 0x77058, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x77058, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_ufs_phy_ice_core_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_ufs_phy_ice_core_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_phy_aux_clk =3D { - .halt_reg =3D 0x7708c, - .halt_check =3D BRANCH_HALT, - .hwcg_reg =3D 0x7708c, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x7708c, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_ufs_phy_phy_aux_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk =3D { - .halt_check =3D BRANCH_HALT_SKIP, - .clkr =3D { - .enable_reg =3D 0x77018, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_ufs_phy_rx_symbol_0_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk =3D { - .halt_check =3D BRANCH_HALT_SKIP, - .clkr =3D { - .enable_reg =3D 0x770a8, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_ufs_phy_rx_symbol_1_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk =3D { - .halt_check =3D BRANCH_HALT_SKIP, - .clkr =3D { - .enable_reg =3D 0x77014, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_ufs_phy_tx_symbol_0_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_unipro_core_clk =3D { - .halt_reg =3D 0x77054, - .halt_check =3D BRANCH_HALT, - .hwcg_reg =3D 0x77054, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x77054, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_ufs_phy_unipro_core_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_prim_master_clk =3D { - .halt_reg =3D 0xf00c, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0xf00c, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_usb30_prim_master_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_usb30_prim_master_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_prim_mock_utmi_clk =3D { - .halt_reg =3D 0xf014, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0xf014, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_usb30_prim_mock_utmi_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_prim_sleep_clk =3D { - .halt_reg =3D 0xf010, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0xf010, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_usb30_prim_sleep_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_sec_master_clk =3D { - .halt_reg =3D 0x1000c, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x1000c, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_usb30_sec_master_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_usb30_sec_master_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_sec_mock_utmi_clk =3D { - .halt_reg =3D 0x10014, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x10014, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_usb30_sec_mock_utmi_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_sec_sleep_clk =3D { - .halt_reg =3D 0x10010, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x10010, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_usb30_sec_sleep_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_prim_clkref_clk =3D { - .halt_reg =3D 0x8c008, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8c008, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_usb3_prim_clkref_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_prim_phy_aux_clk =3D { - .halt_reg =3D 0xf04c, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0xf04c, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_usb3_prim_phy_aux_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_prim_phy_com_aux_clk =3D { - .halt_reg =3D 0xf050, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0xf050, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_usb3_prim_phy_com_aux_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_prim_phy_pipe_clk =3D { - .halt_check =3D BRANCH_HALT_SKIP, - .clkr =3D { - .enable_reg =3D 0xf054, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_usb3_prim_phy_pipe_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_sec_clkref_clk =3D { - .halt_reg =3D 0x8c028, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8c028, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_usb3_sec_clkref_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_sec_phy_aux_clk =3D { - .halt_reg =3D 0x1004c, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x1004c, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_usb3_sec_phy_aux_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_sec_phy_com_aux_clk =3D { - .halt_reg =3D 0x10050, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x10050, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_usb3_sec_phy_com_aux_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_sec_phy_pipe_clk =3D { - .halt_check =3D BRANCH_HALT_SKIP, - .clkr =3D { - .enable_reg =3D 0x10054, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_usb3_sec_phy_pipe_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk =3D { - .halt_reg =3D 0x6a004, - .halt_check =3D BRANCH_HALT, - .hwcg_reg =3D 0x6a004, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x6a004, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_usb_phy_cfg_ahb2phy_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_vdda_vs_clk =3D { - .halt_reg =3D 0x7a00c, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x7a00c, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_vdda_vs_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_vsensor_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_vddcx_vs_clk =3D { - .halt_reg =3D 0x7a004, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x7a004, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_vddcx_vs_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_vsensor_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_vddmx_vs_clk =3D { - .halt_reg =3D 0x7a008, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x7a008, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_vddmx_vs_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_vsensor_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_video_ahb_clk =3D { - .halt_reg =3D 0xb004, - .halt_check =3D BRANCH_HALT, - .hwcg_reg =3D 0xb004, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0xb004, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_video_ahb_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_video_axi_clk =3D { - .halt_reg =3D 0xb01c, - .halt_check =3D BRANCH_VOTED, - .clkr =3D { - .enable_reg =3D 0xb01c, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_video_axi_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_video_xo_clk =3D { - .halt_reg =3D 0xb028, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0xb028, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_video_xo_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_vs_ctrl_ahb_clk =3D { - .halt_reg =3D 0x7a014, - .halt_check =3D BRANCH_HALT, - .hwcg_reg =3D 0x7a014, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x7a014, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_vs_ctrl_ahb_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_vs_ctrl_clk =3D { - .halt_reg =3D 0x7a010, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x7a010, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_vs_ctrl_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gcc_vs_ctrl_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cpuss_dvm_bus_clk =3D { - .halt_reg =3D 0x48190, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x48190, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_cpuss_dvm_bus_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cpuss_gnoc_clk =3D { - .halt_reg =3D 0x48004, - .halt_check =3D BRANCH_HALT_VOTED, - .hwcg_reg =3D 0x48004, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x52004, - .enable_mask =3D BIT(22), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_cpuss_gnoc_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_aggre_noc_pcie_tbu_clk, 0, 0x90014, 0= , 0, 0x90014, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_aggre_ufs_card_axi_clk, 1, 0x82028, 0= x82028, 1, 0x82028, BIT(0), CLK_SET_RATE_PARENT, &gcc_ufs_card_axi_clk_src.= clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_aggre_ufs_phy_axi_clk, 1, 0x82024, 0x= 82024, 1, 0x82024, BIT(0), CLK_SET_RATE_PARENT, &gcc_ufs_phy_axi_clk_src.cl= kr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_aggre_usb3_prim_axi_clk, 1, 0x8201c, = 0, 0, 0x8201c, BIT(0), CLK_SET_RATE_PARENT, &gcc_usb30_prim_master_clk_src.= clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_aggre_usb3_sec_axi_clk, 1, 0x82020, 0= , 0, 0x82020, BIT(0), CLK_SET_RATE_PARENT, &gcc_usb30_sec_master_clk_src.cl= kr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_apc_vs_clk, 1, 0x7a050, 0, 0, 0x7a050= , BIT(0), CLK_SET_RATE_PARENT, &gcc_vsensor_clk_src.clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_boot_rom_ahb_clk, 0, 0x38004, 0= x38004, 1, 0x52004, BIT(10), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_camera_ahb_clk, 0, 0xb008, 0xb008, 1,= 0xb008, BIT(0), CLK_IS_CRITICAL); +DEFINE_QCOM_CC_CLK(BRANCH, VOTED, gcc_camera_axi_clk, 0, 0xb020, 0, 0, 0xb= 020, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_camera_xo_clk, 0, 0xb02c, 0, 0, 0xb02= c, BIT(0), CLK_IS_CRITICAL); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_ce1_ahb_clk, 0, 0x4100c, 0x4100= c, 1, 0x52004, BIT(3), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_ce1_axi_clk, 0, 0x41008, 0, 0, = 0x52004, BIT(4), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_ce1_clk, 0, 0x41004, 0, 0, 0x52= 004, BIT(5), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_cfg_noc_usb3_prim_axi_clk, 1, 0x502c,= 0, 0, 0x502c, BIT(0), CLK_SET_RATE_PARENT, &gcc_usb30_prim_master_clk_src.= clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_cfg_noc_usb3_sec_axi_clk, 1, 0x5030, = 0, 0, 0x5030, BIT(0), CLK_SET_RATE_PARENT, &gcc_usb30_sec_master_clk_src.cl= kr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_cpuss_ahb_clk, 1, 0x48000, 0, 0= , 0x52004, BIT(21), CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, &gcc_cpuss_ahb_c= lk_src.clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_cpuss_rbcpr_clk, 1, 0x48008, 0, 0, 0x= 48008, BIT(0), CLK_SET_RATE_PARENT, &gcc_cpuss_rbcpr_clk_src.clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, VOTED, gcc_ddrss_gpu_axi_clk, 0, 0x44038, 0, 0,= 0x44038, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_disp_ahb_clk, 0, 0xb00c, 0xb00c, 1, 0= xb00c, BIT(0), CLK_IS_CRITICAL); +DEFINE_QCOM_CC_CLK(BRANCH, VOTED, gcc_disp_axi_clk, 0, 0xb024, 0, 0, 0xb02= 4, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH_AON, HALT_DELAY, gcc_disp_gpll0_clk_src, 1, 0, 0= , 0, 0x52004, BIT(18), 0, &gpll0.clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_DELAY, gcc_disp_gpll0_div_clk_src, 1, 0, 0= , 0, 0x52004, BIT(19), 0, &gpll0_out_even.clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_disp_xo_clk, 0, 0xb030, 0, 0, 0xb030,= BIT(0), CLK_IS_CRITICAL); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_gp1_clk, 1, 0x64000, 0, 0, 0x64000, B= IT(0), CLK_SET_RATE_PARENT, &gcc_gp1_clk_src.clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_gp2_clk, 1, 0x65000, 0, 0, 0x65000, B= IT(0), CLK_SET_RATE_PARENT, &gcc_gp2_clk_src.clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_gp3_clk, 1, 0x66000, 0, 0, 0x66000, B= IT(0), CLK_SET_RATE_PARENT, &gcc_gp3_clk_src.clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_gpu_cfg_ahb_clk, 0, 0x71004, 0x71004,= 1, 0x71004, BIT(0), CLK_IS_CRITICAL); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_DELAY, gcc_gpu_gpll0_clk_src, 1, 0, 0, 0, = 0x52004, BIT(15), 0, &gpll0.clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_DELAY, gcc_gpu_gpll0_div_clk_src, 1, 0, 0,= 0, 0x52004, BIT(16), 0, &gpll0_out_even.clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_gpu_iref_clk, 0, 0x8c010, 0, 0, 0x8c0= 10, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, VOTED, gcc_gpu_memnoc_gfx_clk, 0, 0x7100c, 0, 0= , 0x7100c, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_gpu_snoc_dvm_gfx_clk, 0, 0x71018, 0, = 0, 0x71018, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_gpu_vs_clk, 1, 0x7a04c, 0, 0, 0x7a04c= , BIT(0), CLK_SET_RATE_PARENT, &gcc_vsensor_clk_src.clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_mss_axis2_clk, 0, 0x8a008, 0, 0, 0x8a= 008, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_mss_cfg_ahb_clk, 0, 0x8a000, 0x8a000,= 1, 0x8a000, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_DELAY, gcc_mss_gpll0_div_clk_src, 0, 0, 0,= 0, 0x52004, BIT(17), 0); +DEFINE_QCOM_CC_CLK(BRANCH, VOTED, gcc_mss_mfab_axis_clk, 0, 0x8a004, 0x8a0= 04, 1, 0x8a004, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, VOTED, gcc_mss_q6_memnoc_axi_clk, 0, 0x8a154, 0= , 0, 0x8a154, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_mss_snoc_axi_clk, 0, 0x8a150, 0, 0, 0= x8a150, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_mss_vs_clk, 1, 0x7a048, 0, 0, 0x7a048= , BIT(0), CLK_SET_RATE_PARENT, &gcc_vsensor_clk_src.clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_pcie_0_aux_clk, 1, 0x6b01c, 0, = 0, 0x5200c, BIT(3), CLK_SET_RATE_PARENT, &gcc_pcie_0_aux_clk_src.clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_pcie_0_cfg_ahb_clk, 0, 0x6b018,= 0x6b018, 1, 0x5200c, BIT(2), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_pcie_0_clkref_clk, 0, 0x8c00c, 0, 0, = 0x8c00c, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_pcie_0_mstr_axi_clk, 0, 0x6b014= , 0, 0, 0x5200c, BIT(1), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_SKIP, gcc_pcie_0_pipe_clk, 2, 0, 0, 0, 0x5= 200c, BIT(4), CLK_SET_RATE_PARENT, "pcie_0_pipe_clk"); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_pcie_0_slv_axi_clk, 0, 0x6b010,= 0x6b010, 1, 0x5200c, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_pcie_0_slv_q2a_axi_clk, 0, 0x6b= 00c, 0, 0, 0x5200c, BIT(5), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_pcie_1_aux_clk, 1, 0x8d01c, 0, = 0, 0x52004, BIT(29), CLK_SET_RATE_PARENT, &gcc_pcie_1_aux_clk_src.clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_pcie_1_cfg_ahb_clk, 0, 0x8d018,= 0x8d018, 1, 0x52004, BIT(28), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_pcie_1_clkref_clk, 0, 0x8c02c, 0, 0, = 0x8c02c, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_pcie_1_mstr_axi_clk, 0, 0x8d014= , 0, 0, 0x52004, BIT(27), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_SKIP, gcc_pcie_1_pipe_clk, 2, 0, 0, 0, 0x5= 2004, BIT(30), 0, "pcie_1_pipe_clk"); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_pcie_1_slv_axi_clk, 0, 0x8d010,= 0x8d010, 1, 0x52004, BIT(26), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_pcie_1_slv_q2a_axi_clk, 0, 0x8d= 00c, 0, 0, 0x52004, BIT(25), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_pcie_phy_aux_clk, 1, 0x6f004, 0, 0, 0= x6f004, BIT(0), CLK_SET_RATE_PARENT, &gcc_pcie_0_aux_clk_src.clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_pcie_phy_refgen_clk, 1, 0x6f02c, 0, 0= , 0x6f02c, BIT(0), CLK_SET_RATE_PARENT, &gcc_pcie_phy_refgen_clk_src.clkr.h= w); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_pdm2_clk, 1, 0x3300c, 0, 0, 0x3300c, = BIT(0), CLK_SET_RATE_PARENT, &gcc_pdm2_clk_src.clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_pdm_ahb_clk, 0, 0x33004, 0x33004, 1, = 0x33004, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_pdm_xo4_clk, 0, 0x33008, 0, 0, 0x3300= 8, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_prng_ahb_clk, 0, 0x34004, 0x340= 04, 1, 0x52004, BIT(13), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_qmip_camera_ahb_clk, 0, 0xb014, 0xb01= 4, 1, 0xb014, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_qmip_disp_ahb_clk, 0, 0xb018, 0xb018,= 1, 0xb018, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_qmip_video_ahb_clk, 0, 0xb010, 0xb010= , 1, 0xb010, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_qspi_cnoc_periph_ahb_clk, 0, 0x4b000,= 0, 0, 0x4b000, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_qspi_core_clk, 1, 0x4b004, 0, 0, 0x4b= 004, BIT(0), CLK_SET_RATE_PARENT, &gcc_qspi_core_clk_src.clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_qupv3_wrap0_s0_clk, 1, 0x17030,= 0, 0, 0x5200c, BIT(10), CLK_SET_RATE_PARENT, &gcc_qupv3_wrap0_s0_clk_src.c= lkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_qupv3_wrap0_s1_clk, 1, 0x17160,= 0, 0, 0x5200c, BIT(11), CLK_SET_RATE_PARENT, &gcc_qupv3_wrap0_s1_clk_src.c= lkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_qupv3_wrap0_s2_clk, 1, 0x17290,= 0, 0, 0x5200c, BIT(12), CLK_SET_RATE_PARENT, &gcc_qupv3_wrap0_s2_clk_src.c= lkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_qupv3_wrap0_s3_clk, 1, 0x173c0,= 0, 0, 0x5200c, BIT(13), CLK_SET_RATE_PARENT, &gcc_qupv3_wrap0_s3_clk_src.c= lkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_qupv3_wrap0_s4_clk, 1, 0x174f0,= 0, 0, 0x5200c, BIT(14), CLK_SET_RATE_PARENT, &gcc_qupv3_wrap0_s4_clk_src.c= lkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_qupv3_wrap0_s5_clk, 1, 0x17620,= 0, 0, 0x5200c, BIT(15), CLK_SET_RATE_PARENT, &gcc_qupv3_wrap0_s5_clk_src.c= lkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_qupv3_wrap0_s6_clk, 1, 0x17750,= 0, 0, 0x5200c, BIT(16), CLK_SET_RATE_PARENT, &gcc_qupv3_wrap0_s6_clk_src.c= lkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_qupv3_wrap0_s7_clk, 1, 0x17880,= 0, 0, 0x5200c, BIT(17), CLK_SET_RATE_PARENT, &gcc_qupv3_wrap0_s7_clk_src.c= lkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_qupv3_wrap1_s0_clk, 1, 0x18014,= 0, 0, 0x5200c, BIT(22), CLK_SET_RATE_PARENT, &gcc_qupv3_wrap1_s0_clk_src.c= lkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_qupv3_wrap1_s1_clk, 1, 0x18144,= 0, 0, 0x5200c, BIT(23), CLK_SET_RATE_PARENT, &gcc_qupv3_wrap1_s1_clk_src.c= lkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_qupv3_wrap1_s2_clk, 1, 0x18274,= 0, 0, 0x5200c, BIT(24), CLK_SET_RATE_PARENT, &gcc_qupv3_wrap1_s2_clk_src.c= lkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_qupv3_wrap1_s3_clk, 1, 0x183a4,= 0, 0, 0x5200c, BIT(25), CLK_SET_RATE_PARENT, &gcc_qupv3_wrap1_s3_clk_src.c= lkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_qupv3_wrap1_s4_clk, 1, 0x184d4,= 0, 0, 0x5200c, BIT(26), CLK_SET_RATE_PARENT, &gcc_qupv3_wrap1_s4_clk_src.c= lkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_qupv3_wrap1_s5_clk, 1, 0x18604,= 0, 0, 0x5200c, BIT(27), CLK_SET_RATE_PARENT, &gcc_qupv3_wrap1_s5_clk_src.c= lkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_qupv3_wrap1_s6_clk, 1, 0x18734,= 0, 0, 0x5200c, BIT(28), CLK_SET_RATE_PARENT, &gcc_qupv3_wrap1_s6_clk_src.c= lkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_qupv3_wrap1_s7_clk, 1, 0x18864,= 0, 0, 0x5200c, BIT(29), CLK_SET_RATE_PARENT, &gcc_qupv3_wrap1_s7_clk_src.c= lkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_qupv3_wrap_0_m_ahb_clk, 0, 0x17= 004, 0, 0, 0x5200c, BIT(6), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_qupv3_wrap_0_s_ahb_clk, 0, 0x17= 008, 0x17008, 1, 0x5200c, BIT(7), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_qupv3_wrap_1_m_ahb_clk, 0, 0x18= 00c, 0, 0, 0x5200c, BIT(20), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_qupv3_wrap_1_s_ahb_clk, 0, 0x18= 010, 0x18010, 1, 0x5200c, BIT(21), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_sdcc2_ahb_clk, 0, 0x14008, 0, 0, 0x14= 008, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_sdcc2_apps_clk, 1, 0x14004, 0, 0, 0x1= 4004, BIT(0), CLK_SET_RATE_PARENT, &gcc_sdcc2_apps_clk_src.clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_sdcc4_ahb_clk, 0, 0x16008, 0, 0, 0x16= 008, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_sdcc4_apps_clk, 1, 0x16004, 0, 0, 0x1= 6004, BIT(0), CLK_SET_RATE_PARENT, &gcc_sdcc4_apps_clk_src.clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_sys_noc_cpuss_ahb_clk, 1, 0x414= c, 0, 0, 0x52004, BIT(0), CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, &gcc_cpuss= _ahb_clk_src.clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_tsif_ahb_clk, 0, 0x36004, 0, 0, 0x360= 04, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_tsif_inactivity_timers_clk, 0, 0x3600= c, 0, 0, 0x3600c, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_tsif_ref_clk, 1, 0x36008, 0, 0, 0x360= 08, BIT(0), CLK_SET_RATE_PARENT, &gcc_tsif_ref_clk_src.clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_ufs_card_ahb_clk, 0, 0x75010, 0x75010= , 1, 0x75010, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_ufs_card_axi_clk, 1, 0x7500c, 0x7500c= , 1, 0x7500c, BIT(0), CLK_SET_RATE_PARENT, &gcc_ufs_card_axi_clk_src.clkr.h= w); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_ufs_card_clkref_clk, 0, 0x8c004, 0, 0= , 0x8c004, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_ufs_card_ice_core_clk, 1, 0x75058, 0x= 75058, 1, 0x75058, BIT(0), CLK_SET_RATE_PARENT, &gcc_ufs_card_ice_core_clk_= src.clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_ufs_card_phy_aux_clk, 1, 0x7508c, 0x7= 508c, 1, 0x7508c, BIT(0), CLK_SET_RATE_PARENT, &gcc_ufs_card_phy_aux_clk_sr= c.clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_SKIP, gcc_ufs_card_rx_symbol_0_clk, 0, 0, = 0, 0, 0x75018, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_SKIP, gcc_ufs_card_rx_symbol_1_clk, 0, 0, = 0, 0, 0x750a8, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_SKIP, gcc_ufs_card_tx_symbol_0_clk, 0, 0, = 0, 0, 0x75014, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_ufs_card_unipro_core_clk, 1, 0x75054,= 0x75054, 1, 0x75054, BIT(0), CLK_SET_RATE_PARENT, &gcc_ufs_card_unipro_cor= e_clk_src.clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_ufs_mem_clkref_clk, 0, 0x8c000, 0, 0,= 0x8c000, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_ufs_phy_ahb_clk, 0, 0x77010, 0x77010,= 1, 0x77010, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_ufs_phy_axi_clk, 1, 0x7700c, 0x7700c,= 1, 0x7700c, BIT(0), CLK_SET_RATE_PARENT, &gcc_ufs_phy_axi_clk_src.clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_ufs_phy_ice_core_clk, 1, 0x77058, 0x7= 7058, 1, 0x77058, BIT(0), CLK_SET_RATE_PARENT, &gcc_ufs_phy_ice_core_clk_sr= c.clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_ufs_phy_phy_aux_clk, 1, 0x7708c, 0x77= 08c, 1, 0x7708c, BIT(0), CLK_SET_RATE_PARENT, &gcc_ufs_phy_phy_aux_clk_src.= clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_SKIP, gcc_ufs_phy_rx_symbol_0_clk, 0, 0, 0= , 0, 0x77018, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_SKIP, gcc_ufs_phy_rx_symbol_1_clk, 0, 0, 0= , 0, 0x770a8, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_SKIP, gcc_ufs_phy_tx_symbol_0_clk, 0, 0, 0= , 0, 0x77014, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_ufs_phy_unipro_core_clk, 1, 0x77054, = 0x77054, 1, 0x77054, BIT(0), CLK_SET_RATE_PARENT, &gcc_ufs_phy_unipro_core_= clk_src.clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_usb30_prim_master_clk, 1, 0xf00c, 0, = 0, 0xf00c, BIT(0), CLK_SET_RATE_PARENT, &gcc_usb30_prim_master_clk_src.clkr= .hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_usb30_prim_mock_utmi_clk, 1, 0xf014, = 0, 0, 0xf014, BIT(0), CLK_SET_RATE_PARENT, &gcc_usb30_prim_mock_utmi_clk_sr= c.clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_usb30_prim_sleep_clk, 0, 0xf010, 0, 0= , 0xf010, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_usb30_sec_master_clk, 1, 0x1000c, 0, = 0, 0x1000c, BIT(0), CLK_SET_RATE_PARENT, &gcc_usb30_sec_master_clk_src.clkr= .hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_usb30_sec_mock_utmi_clk, 1, 0x10014, = 0, 0, 0x10014, BIT(0), CLK_SET_RATE_PARENT, &gcc_usb30_sec_mock_utmi_clk_sr= c.clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_usb30_sec_sleep_clk, 0, 0x10010, 0, 0= , 0x10010, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_usb3_prim_clkref_clk, 0, 0x8c008, 0, = 0, 0x8c008, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_usb3_prim_phy_aux_clk, 1, 0xf04c, 0, = 0, 0xf04c, BIT(0), CLK_SET_RATE_PARENT, &gcc_usb3_prim_phy_aux_clk_src.clkr= .hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_usb3_prim_phy_com_aux_clk, 1, 0xf050,= 0, 0, 0xf050, BIT(0), CLK_SET_RATE_PARENT, &gcc_usb3_prim_phy_aux_clk_src.= clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_SKIP, gcc_usb3_prim_phy_pipe_clk, 0, 0, 0,= 0, 0xf054, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_usb3_sec_clkref_clk, 0, 0x8c028, 0, 0= , 0x8c028, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_usb3_sec_phy_aux_clk, 1, 0x1004c, 0, = 0, 0x1004c, BIT(0), CLK_SET_RATE_PARENT, &gcc_usb3_sec_phy_aux_clk_src.clkr= .hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_usb3_sec_phy_com_aux_clk, 1, 0x10050,= 0, 0, 0x10050, BIT(0), CLK_SET_RATE_PARENT, &gcc_usb3_sec_phy_aux_clk_src.= clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_SKIP, gcc_usb3_sec_phy_pipe_clk, 0, 0, 0, = 0, 0x10054, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_usb_phy_cfg_ahb2phy_clk, 0, 0x6a004, = 0x6a004, 1, 0x6a004, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_vdda_vs_clk, 1, 0x7a00c, 0, 0, 0x7a00= c, BIT(0), CLK_SET_RATE_PARENT, &gcc_vsensor_clk_src.clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_vddcx_vs_clk, 1, 0x7a004, 0, 0, 0x7a0= 04, BIT(0), CLK_SET_RATE_PARENT, &gcc_vsensor_clk_src.clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_vddmx_vs_clk, 1, 0x7a008, 0, 0, 0x7a0= 08, BIT(0), CLK_SET_RATE_PARENT, &gcc_vsensor_clk_src.clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_video_ahb_clk, 0, 0xb004, 0xb004, 1, = 0xb004, BIT(0), CLK_IS_CRITICAL); +DEFINE_QCOM_CC_CLK(BRANCH, VOTED, gcc_video_axi_clk, 0, 0xb01c, 0, 0, 0xb0= 1c, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_video_xo_clk, 0, 0xb028, 0, 0, 0xb028= , BIT(0), CLK_IS_CRITICAL); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_vs_ctrl_ahb_clk, 0, 0x7a014, 0x7a014,= 1, 0x7a014, BIT(0), 0); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_vs_ctrl_clk, 1, 0x7a010, 0, 0, 0x7a01= 0, BIT(0), CLK_SET_RATE_PARENT, &gcc_vs_ctrl_clk_src.clkr.hw); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_cpuss_dvm_bus_clk, 0, 0x48190, 0, 0, = 0x48190, BIT(0), CLK_IS_CRITICAL); +DEFINE_QCOM_CC_CLK(BRANCH, HALT_VOTED, gcc_cpuss_gnoc_clk, 0, 0x48004, 0x4= 8004, 1, 0x52004, BIT(22), CLK_IS_CRITICAL); =20 /* TODO: Remove after DTS updated to protect these */ #ifdef CONFIG_SDM_LPASSCC_845 -static struct clk_branch gcc_lpass_q6_axi_clk =3D { - .halt_reg =3D 0x47000, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x47000, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_lpass_q6_axi_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_lpass_sway_clk =3D { - .halt_reg =3D 0x47008, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x47008, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_lpass_sway_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_lpass_q6_axi_clk, 0, 0x47000, 0, 0, 0= x47000, BIT(0), CLK_IS_CRITICAL); +DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_lpass_sway_clk, 0, 0x47008, 0, 0, 0x4= 7008, BIT(0), CLK_IS_CRITICAL); #endif =20 DEFINE_QCOM_CC_GDSC(pcie_0_gdsc, 0x6b004, "pcie_0_gdsc", PWRSTS_OFF_ON, PO= LL_CFG_GDSCR); --=20 2.34.3 From nobody Wed Apr 15 04:16:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29DACC3F6B0 for ; Tue, 26 Jul 2022 14:24:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239308AbiGZOYS (ORCPT ); Tue, 26 Jul 2022 10:24:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32792 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239267AbiGZOX4 (ORCPT ); Tue, 26 Jul 2022 10:23:56 -0400 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B2D6827CE8 for ; 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Tue, 26 Jul 2022 07:23:53 -0700 (PDT) Received: from localhost.localdomain ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id t21-20020a1c7715000000b003a331c6bffdsm17017119wmi.47.2022.07.26.07.23.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Jul 2022 07:23:52 -0700 (PDT) From: Abel Vesa To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Mike Turquette , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Linux Kernel Mailing List , Abel Vesa Subject: [RFC 8/9] clk: qcom: gcc-sdm845: Switch to macros to collapse rcg2 clocks definitions Date: Tue, 26 Jul 2022 17:23:02 +0300 Message-Id: <20220726142303.4126434-9-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.3 In-Reply-To: <20220726142303.4126434-1-abel.vesa@linaro.org> References: <20220726142303.4126434-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Switch from the expanded rcg2 clocks definitions to the more compact macros. Signed-off-by: Abel Vesa --- drivers/clk/qcom/gcc-sdm845.c | 712 +++------------------------------- 1 file changed, 51 insertions(+), 661 deletions(-) diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c index 2e66256599d3..d9751d7e617c 100644 --- a/drivers/clk/qcom/gcc-sdm845.c +++ b/drivers/clk/qcom/gcc-sdm845.c @@ -200,39 +200,11 @@ static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_s= rc[] =3D { { } }; =20 -static struct clk_rcg2 gcc_cpuss_ahb_clk_src =3D { - .cmd_rcgr =3D 0x48014, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_0, - .freq_tbl =3D ftbl_gcc_cpuss_ahb_clk_src, - .clkr.hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_cpuss_ahb_clk_src", - .parent_data =3D gcc_parent_data_7_ao, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_7_ao), - .ops =3D &clk_rcg2_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_cpuss_rbcpr_clk_src[] =3D { F(19200000, P_BI_TCXO, 1, 0, 0), { } }; =20 -static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src =3D { - .cmd_rcgr =3D 0x4815c, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_3, - .freq_tbl =3D ftbl_gcc_cpuss_rbcpr_clk_src, - .clkr.hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_cpuss_rbcpr_clk_src", - .parent_data =3D gcc_parent_data_8_ao, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_8_ao), - .ops =3D &clk_rcg2_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_gp1_clk_src[] =3D { F(19200000, P_BI_TCXO, 1, 0, 0), F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), @@ -242,102 +214,18 @@ static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = =3D { { } }; =20 -static struct clk_rcg2 gcc_gp1_clk_src =3D { - .cmd_rcgr =3D 0x64004, - .mnd_width =3D 8, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_1, - .freq_tbl =3D ftbl_gcc_gp1_clk_src, - .clkr.hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_gp1_clk_src", - .parent_data =3D gcc_parent_data_1, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), - .ops =3D &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_gp2_clk_src =3D { - .cmd_rcgr =3D 0x65004, - .mnd_width =3D 8, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_1, - .freq_tbl =3D ftbl_gcc_gp1_clk_src, - .clkr.hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_gp2_clk_src", - .parent_data =3D gcc_parent_data_1, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), - .ops =3D &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_gp3_clk_src =3D { - .cmd_rcgr =3D 0x66004, - .mnd_width =3D 8, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_1, - .freq_tbl =3D ftbl_gcc_gp1_clk_src, - .clkr.hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_gp3_clk_src", - .parent_data =3D gcc_parent_data_1, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), - .ops =3D &clk_rcg2_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] =3D { F(9600000, P_BI_TCXO, 2, 0, 0), F(19200000, P_BI_TCXO, 1, 0, 0), { } }; =20 -static struct clk_rcg2 gcc_pcie_0_aux_clk_src =3D { - .cmd_rcgr =3D 0x6b028, - .mnd_width =3D 16, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_2, - .freq_tbl =3D ftbl_gcc_pcie_0_aux_clk_src, - .clkr.hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_pcie_0_aux_clk_src", - .parent_data =3D gcc_parent_data_2, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), - .ops =3D &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_pcie_1_aux_clk_src =3D { - .cmd_rcgr =3D 0x8d028, - .mnd_width =3D 16, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_2, - .freq_tbl =3D ftbl_gcc_pcie_0_aux_clk_src, - .clkr.hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_pcie_1_aux_clk_src", - .parent_data =3D gcc_parent_data_2, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), - .ops =3D &clk_rcg2_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] =3D { F(19200000, P_BI_TCXO, 1, 0, 0), F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), { } }; =20 -static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src =3D { - .cmd_rcgr =3D 0x6f014, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_0, - .freq_tbl =3D ftbl_gcc_pcie_phy_refgen_clk_src, - .clkr.hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_pcie_phy_refgen_clk_src", - .parent_data =3D gcc_parent_data_0, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] =3D { F(19200000, P_BI_TCXO, 1, 0, 0), F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), @@ -346,20 +234,6 @@ static const struct freq_tbl ftbl_gcc_qspi_core_clk_sr= c[] =3D { { } }; =20 -static struct clk_rcg2 gcc_qspi_core_clk_src =3D { - .cmd_rcgr =3D 0x4b008, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_0, - .freq_tbl =3D ftbl_gcc_qspi_core_clk_src, - .clkr.hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_qspi_core_clk_src", - .parent_data =3D gcc_parent_data_0, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_floor_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] =3D { F(9600000, P_BI_TCXO, 2, 0, 0), F(19200000, P_BI_TCXO, 1, 0, 0), @@ -367,20 +241,6 @@ static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = =3D { { } }; =20 -static struct clk_rcg2 gcc_pdm2_clk_src =3D { - .cmd_rcgr =3D 0x33010, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_0, - .freq_tbl =3D ftbl_gcc_pdm2_clk_src, - .clkr.hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_pdm2_clk_src", - .parent_data =3D gcc_parent_data_0, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] =3D { F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), @@ -400,262 +260,6 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_= clk_src[] =3D { { } }; =20 -static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init =3D { - .name =3D "gcc_qupv3_wrap0_s0_clk_src", - .parent_data =3D gcc_parent_data_0, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src =3D { - .cmd_rcgr =3D 0x17034, - .mnd_width =3D 16, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_0, - .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init =3D &gcc_qupv3_wrap0_s0_clk_src_init, -}; - -static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init =3D { - .name =3D "gcc_qupv3_wrap0_s1_clk_src", - .parent_data =3D gcc_parent_data_0, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src =3D { - .cmd_rcgr =3D 0x17164, - .mnd_width =3D 16, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_0, - .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init =3D &gcc_qupv3_wrap0_s1_clk_src_init, -}; - -static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init =3D { - .name =3D "gcc_qupv3_wrap0_s2_clk_src", - .parent_data =3D gcc_parent_data_0, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src =3D { - .cmd_rcgr =3D 0x17294, - .mnd_width =3D 16, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_0, - .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init =3D &gcc_qupv3_wrap0_s2_clk_src_init, -}; - -static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init =3D { - .name =3D "gcc_qupv3_wrap0_s3_clk_src", - .parent_data =3D gcc_parent_data_0, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src =3D { - .cmd_rcgr =3D 0x173c4, - .mnd_width =3D 16, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_0, - .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init =3D &gcc_qupv3_wrap0_s3_clk_src_init, -}; - -static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init =3D { - .name =3D "gcc_qupv3_wrap0_s4_clk_src", - .parent_data =3D gcc_parent_data_0, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src =3D { - .cmd_rcgr =3D 0x174f4, - .mnd_width =3D 16, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_0, - .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init =3D &gcc_qupv3_wrap0_s4_clk_src_init, -}; - -static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init =3D { - .name =3D "gcc_qupv3_wrap0_s5_clk_src", - .parent_data =3D gcc_parent_data_0, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src =3D { - .cmd_rcgr =3D 0x17624, - .mnd_width =3D 16, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_0, - .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init =3D &gcc_qupv3_wrap0_s5_clk_src_init, -}; - -static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init =3D { - .name =3D "gcc_qupv3_wrap0_s6_clk_src", - .parent_data =3D gcc_parent_data_0, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src =3D { - .cmd_rcgr =3D 0x17754, - .mnd_width =3D 16, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_0, - .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init =3D &gcc_qupv3_wrap0_s6_clk_src_init, -}; - -static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init =3D { - .name =3D "gcc_qupv3_wrap0_s7_clk_src", - .parent_data =3D gcc_parent_data_0, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src =3D { - .cmd_rcgr =3D 0x17884, - .mnd_width =3D 16, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_0, - .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init =3D &gcc_qupv3_wrap0_s7_clk_src_init, -}; - -static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init =3D { - .name =3D "gcc_qupv3_wrap1_s0_clk_src", - .parent_data =3D gcc_parent_data_0, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src =3D { - .cmd_rcgr =3D 0x18018, - .mnd_width =3D 16, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_0, - .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init =3D &gcc_qupv3_wrap1_s0_clk_src_init, -}; - -static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init =3D { - .name =3D "gcc_qupv3_wrap1_s1_clk_src", - .parent_data =3D gcc_parent_data_0, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src =3D { - .cmd_rcgr =3D 0x18148, - .mnd_width =3D 16, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_0, - .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init =3D &gcc_qupv3_wrap1_s1_clk_src_init, -}; - -static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init =3D { - .name =3D "gcc_qupv3_wrap1_s2_clk_src", - .parent_data =3D gcc_parent_data_0, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src =3D { - .cmd_rcgr =3D 0x18278, - .mnd_width =3D 16, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_0, - .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init =3D &gcc_qupv3_wrap1_s2_clk_src_init, -}; - -static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init =3D { - .name =3D "gcc_qupv3_wrap1_s3_clk_src", - .parent_data =3D gcc_parent_data_0, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src =3D { - .cmd_rcgr =3D 0x183a8, - .mnd_width =3D 16, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_0, - .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init =3D &gcc_qupv3_wrap1_s3_clk_src_init, -}; - -static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init =3D { - .name =3D "gcc_qupv3_wrap1_s4_clk_src", - .parent_data =3D gcc_parent_data_0, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src =3D { - .cmd_rcgr =3D 0x184d8, - .mnd_width =3D 16, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_0, - .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init =3D &gcc_qupv3_wrap1_s4_clk_src_init, -}; - -static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init =3D { - .name =3D "gcc_qupv3_wrap1_s5_clk_src", - .parent_data =3D gcc_parent_data_0, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src =3D { - .cmd_rcgr =3D 0x18608, - .mnd_width =3D 16, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_0, - .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init =3D &gcc_qupv3_wrap1_s5_clk_src_init, -}; - -static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init =3D { - .name =3D "gcc_qupv3_wrap1_s6_clk_src", - .parent_data =3D gcc_parent_data_0, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src =3D { - .cmd_rcgr =3D 0x18738, - .mnd_width =3D 16, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_0, - .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init =3D &gcc_qupv3_wrap1_s6_clk_src_init, -}; - -static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init =3D { - .name =3D "gcc_qupv3_wrap1_s7_clk_src", - .parent_data =3D gcc_parent_data_0, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src =3D { - .cmd_rcgr =3D 0x18868, - .mnd_width =3D 16, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_0, - .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init =3D &gcc_qupv3_wrap1_s7_clk_src_init, -}; - static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] =3D { F(400000, P_BI_TCXO, 12, 1, 4), F(9600000, P_BI_TCXO, 2, 0, 0), @@ -667,20 +271,6 @@ static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_s= rc[] =3D { { } }; =20 -static struct clk_rcg2 gcc_sdcc2_apps_clk_src =3D { - .cmd_rcgr =3D 0x1400c, - .mnd_width =3D 8, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_10, - .freq_tbl =3D ftbl_gcc_sdcc2_apps_clk_src, - .clkr.hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_sdcc2_apps_clk_src", - .parent_data =3D gcc_parent_data_10, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_10), - .ops =3D &clk_rcg2_floor_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] =3D { F(400000, P_BI_TCXO, 12, 1, 4), F(9600000, P_BI_TCXO, 2, 0, 0), @@ -691,39 +281,11 @@ static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_= src[] =3D { { } }; =20 -static struct clk_rcg2 gcc_sdcc4_apps_clk_src =3D { - .cmd_rcgr =3D 0x1600c, - .mnd_width =3D 8, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_0, - .freq_tbl =3D ftbl_gcc_sdcc4_apps_clk_src, - .clkr.hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_sdcc4_apps_clk_src", - .parent_data =3D gcc_parent_data_0, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_floor_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] =3D { F(105495, P_BI_TCXO, 2, 1, 91), { } }; =20 -static struct clk_rcg2 gcc_tsif_ref_clk_src =3D { - .cmd_rcgr =3D 0x36010, - .mnd_width =3D 8, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_6, - .freq_tbl =3D ftbl_gcc_tsif_ref_clk_src, - .clkr.hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_tsif_ref_clk_src", - .parent_data =3D gcc_parent_data_6, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_6), - .ops =3D &clk_rcg2_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] =3D { F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), @@ -733,20 +295,6 @@ static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk= _src[] =3D { { } }; =20 -static struct clk_rcg2 gcc_ufs_card_axi_clk_src =3D { - .cmd_rcgr =3D 0x7501c, - .mnd_width =3D 8, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_0, - .freq_tbl =3D ftbl_gcc_ufs_card_axi_clk_src, - .clkr.hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_ufs_card_axi_clk_src", - .parent_data =3D gcc_parent_data_0, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] =3D { F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), @@ -755,34 +303,6 @@ static const struct freq_tbl ftbl_gcc_ufs_card_ice_cor= e_clk_src[] =3D { { } }; =20 -static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src =3D { - .cmd_rcgr =3D 0x7505c, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_0, - .freq_tbl =3D ftbl_gcc_ufs_card_ice_core_clk_src, - .clkr.hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_ufs_card_ice_core_clk_src", - .parent_data =3D gcc_parent_data_0, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, - }, -}; - -static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src =3D { - .cmd_rcgr =3D 0x75090, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_4, - .freq_tbl =3D ftbl_gcc_cpuss_rbcpr_clk_src, - .clkr.hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_ufs_card_phy_aux_clk_src", - .parent_data =3D gcc_parent_data_4, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_4), - .ops =3D &clk_rcg2_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] =3D { F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), @@ -790,20 +310,6 @@ static const struct freq_tbl ftbl_gcc_ufs_card_unipro_= core_clk_src[] =3D { { } }; =20 -static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src =3D { - .cmd_rcgr =3D 0x75074, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_0, - .freq_tbl =3D ftbl_gcc_ufs_card_unipro_core_clk_src, - .clkr.hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_ufs_card_unipro_core_clk_src", - .parent_data =3D gcc_parent_data_0, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] =3D { F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), @@ -813,62 +319,6 @@ static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_= src[] =3D { { } }; =20 -static struct clk_rcg2 gcc_ufs_phy_axi_clk_src =3D { - .cmd_rcgr =3D 0x7701c, - .mnd_width =3D 8, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_0, - .freq_tbl =3D ftbl_gcc_ufs_phy_axi_clk_src, - .clkr.hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_ufs_phy_axi_clk_src", - .parent_data =3D gcc_parent_data_0, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, - }, -}; - -static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src =3D { - .cmd_rcgr =3D 0x7705c, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_0, - .freq_tbl =3D ftbl_gcc_ufs_card_ice_core_clk_src, - .clkr.hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_ufs_phy_ice_core_clk_src", - .parent_data =3D gcc_parent_data_0, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, - }, -}; - -static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src =3D { - .cmd_rcgr =3D 0x77090, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_4, - .freq_tbl =3D ftbl_gcc_pcie_0_aux_clk_src, - .clkr.hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_ufs_phy_phy_aux_clk_src", - .parent_data =3D gcc_parent_data_4, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_4), - .ops =3D &clk_rcg2_shared_ops, - }, -}; - -static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src =3D { - .cmd_rcgr =3D 0x77074, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_0, - .freq_tbl =3D ftbl_gcc_ufs_card_unipro_core_clk_src, - .clkr.hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_ufs_phy_unipro_core_clk_src", - .parent_data =3D gcc_parent_data_0, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] =3D { F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0), F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), @@ -878,20 +328,6 @@ static const struct freq_tbl ftbl_gcc_usb30_prim_maste= r_clk_src[] =3D { { } }; =20 -static struct clk_rcg2 gcc_usb30_prim_master_clk_src =3D { - .cmd_rcgr =3D 0xf018, - .mnd_width =3D 8, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_0, - .freq_tbl =3D ftbl_gcc_usb30_prim_master_clk_src, - .clkr.hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_usb30_prim_master_clk_src", - .parent_data =3D gcc_parent_data_0, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] =3D { F(19200000, P_BI_TCXO, 1, 0, 0), F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0), @@ -900,90 +336,6 @@ static const struct freq_tbl ftbl_gcc_usb30_prim_mock_= utmi_clk_src[] =3D { { } }; =20 -static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src =3D { - .cmd_rcgr =3D 0xf030, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_0, - .freq_tbl =3D ftbl_gcc_usb30_prim_mock_utmi_clk_src, - .clkr.hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_usb30_prim_mock_utmi_clk_src", - .parent_data =3D gcc_parent_data_0, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, - }, -}; - -static struct clk_rcg2 gcc_usb30_sec_master_clk_src =3D { - .cmd_rcgr =3D 0x10018, - .mnd_width =3D 8, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_0, - .freq_tbl =3D ftbl_gcc_usb30_prim_master_clk_src, - .clkr.hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_usb30_sec_master_clk_src", - .parent_data =3D gcc_parent_data_0, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src =3D { - .cmd_rcgr =3D 0x10030, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_0, - .freq_tbl =3D ftbl_gcc_usb30_prim_mock_utmi_clk_src, - .clkr.hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_usb30_sec_mock_utmi_clk_src", - .parent_data =3D gcc_parent_data_0, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src =3D { - .cmd_rcgr =3D 0xf05c, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_2, - .freq_tbl =3D ftbl_gcc_cpuss_rbcpr_clk_src, - .clkr.hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_usb3_prim_phy_aux_clk_src", - .parent_data =3D gcc_parent_data_2, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), - .ops =3D &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src =3D { - .cmd_rcgr =3D 0x1005c, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_2, - .freq_tbl =3D ftbl_gcc_cpuss_rbcpr_clk_src, - .clkr.hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_usb3_sec_phy_aux_clk_src", - .parent_data =3D gcc_parent_data_2, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), - .ops =3D &clk_rcg2_shared_ops, - }, -}; - -static struct clk_rcg2 gcc_vs_ctrl_clk_src =3D { - .cmd_rcgr =3D 0x7a030, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_3, - .freq_tbl =3D ftbl_gcc_cpuss_rbcpr_clk_src, - .clkr.hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_vs_ctrl_clk_src", - .parent_data =3D gcc_parent_data_3, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), - .ops =3D &clk_rcg2_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_vsensor_clk_src[] =3D { F(19200000, P_BI_TCXO, 1, 0, 0), F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), @@ -991,19 +343,57 @@ static const struct freq_tbl ftbl_gcc_vsensor_clk_src= [] =3D { { } }; =20 -static struct clk_rcg2 gcc_vsensor_clk_src =3D { - .cmd_rcgr =3D 0x7a018, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D gcc_parent_map_3, - .freq_tbl =3D ftbl_gcc_vsensor_clk_src, - .clkr.hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_vsensor_clk_src", - .parent_data =3D gcc_parent_data_8, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_8), - .ops =3D &clk_rcg2_ops, - }, -}; +DEFINE_QCOM_CC_CLK(RCG2, gcc_cpuss_ahb_clk_src, 0x48014, 0, 5, gcc_parent_= map_0, ftbl_gcc_cpuss_ahb_clk_src, gcc_parent_data_7_ao); +DEFINE_QCOM_CC_CLK(RCG2, gcc_cpuss_rbcpr_clk_src, 0x4815c, 0, 5, gcc_paren= t_map_3, ftbl_gcc_cpuss_rbcpr_clk_src, gcc_parent_data_8_ao); +DEFINE_QCOM_CC_CLK(RCG2, gcc_gp1_clk_src, 0x64004, 8, 5, gcc_parent_map_1,= ftbl_gcc_gp1_clk_src, gcc_parent_data_1); +DEFINE_QCOM_CC_CLK(RCG2, gcc_gp2_clk_src, 0x65004, 8, 5, gcc_parent_map_1,= ftbl_gcc_gp1_clk_src, gcc_parent_data_1); +DEFINE_QCOM_CC_CLK(RCG2, gcc_gp3_clk_src, 0x6b028, 8, 5, gcc_parent_map_1,= ftbl_gcc_gp1_clk_src, gcc_parent_data_1); +DEFINE_QCOM_CC_CLK(RCG2, gcc_pcie_0_aux_clk_src, 0x6b028, 16, 5, gcc_paren= t_map_2, ftbl_gcc_pcie_0_aux_clk_src, gcc_parent_data_2); +DEFINE_QCOM_CC_CLK(RCG2, gcc_pcie_1_aux_clk_src, 0x8d028, 16, 5, gcc_paren= t_map_2, ftbl_gcc_pcie_0_aux_clk_src, gcc_parent_data_2); +DEFINE_QCOM_CC_CLK(RCG2, gcc_pcie_phy_refgen_clk_src, 0x6f014, 0, 5, gcc_p= arent_map_0, ftbl_gcc_pcie_phy_refgen_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_FLOOR, gcc_qspi_core_clk_src, 0x4b008, 0, 5, gcc_p= arent_map_0, ftbl_gcc_qspi_core_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2, gcc_pdm2_clk_src, 0x33010, 0, 5, gcc_parent_map_0= , ftbl_gcc_pdm2_clk_src, gcc_parent_data_0); + +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_qupv3_wrap0_s0_clk_src, 0x17034, 16, 5= , gcc_parent_map_0, ftbl_gcc_qupv3_wrap0_s0_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_qupv3_wrap0_s1_clk_src, 0x17164, 16, 5= , gcc_parent_map_0, ftbl_gcc_qupv3_wrap0_s0_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_qupv3_wrap0_s2_clk_src, 0x17294, 16, 5= , gcc_parent_map_0, ftbl_gcc_qupv3_wrap0_s0_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_qupv3_wrap0_s3_clk_src, 0x173c4, 16, 5= , gcc_parent_map_0, ftbl_gcc_qupv3_wrap0_s0_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_qupv3_wrap0_s4_clk_src, 0x174f4, 16, 5= , gcc_parent_map_0, ftbl_gcc_qupv3_wrap0_s0_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_qupv3_wrap0_s5_clk_src, 0x17624, 16, 5= , gcc_parent_map_0, ftbl_gcc_qupv3_wrap0_s0_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_qupv3_wrap0_s6_clk_src, 0x17754, 16, 5= , gcc_parent_map_0, ftbl_gcc_qupv3_wrap0_s0_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_qupv3_wrap0_s7_clk_src, 0x17884, 16, 5= , gcc_parent_map_0, ftbl_gcc_qupv3_wrap0_s0_clk_src, gcc_parent_data_0); + +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_qupv3_wrap1_s0_clk_src, 0x18018, 16, 5= , gcc_parent_map_0, ftbl_gcc_qupv3_wrap0_s0_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_qupv3_wrap1_s1_clk_src, 0x18148, 16, 5= , gcc_parent_map_0, ftbl_gcc_qupv3_wrap0_s0_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_qupv3_wrap1_s2_clk_src, 0x18278, 16, 5= , gcc_parent_map_0, ftbl_gcc_qupv3_wrap0_s0_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_qupv3_wrap1_s3_clk_src, 0x183a8, 16, 5= , gcc_parent_map_0, ftbl_gcc_qupv3_wrap0_s0_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_qupv3_wrap1_s4_clk_src, 0x184d8, 16, 5= , gcc_parent_map_0, ftbl_gcc_qupv3_wrap0_s0_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_qupv3_wrap1_s5_clk_src, 0x18608, 16, 5= , gcc_parent_map_0, ftbl_gcc_qupv3_wrap0_s0_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_qupv3_wrap1_s6_clk_src, 0x18738, 16, 5= , gcc_parent_map_0, ftbl_gcc_qupv3_wrap0_s0_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_qupv3_wrap1_s7_clk_src, 0x18868, 16, 5= , gcc_parent_map_0, ftbl_gcc_qupv3_wrap0_s0_clk_src, gcc_parent_data_0); + +DEFINE_QCOM_CC_CLK(RCG2_FLOOR, gcc_sdcc2_apps_clk_src, 0x1400c, 8, 5, gcc_= parent_map_10, ftbl_gcc_sdcc2_apps_clk_src, gcc_parent_data_10); +DEFINE_QCOM_CC_CLK(RCG2_FLOOR, gcc_sdcc4_apps_clk_src, 0x1600c, 8, 5, gcc_= parent_map_0, ftbl_gcc_sdcc4_apps_clk_src, gcc_parent_data_0); + +DEFINE_QCOM_CC_CLK(RCG2, gcc_tsif_ref_clk_src, 0x36010, 8, 5, gcc_parent_m= ap_6, ftbl_gcc_tsif_ref_clk_src, gcc_parent_data_6); + +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_ufs_card_axi_clk_src, 0x7501c, 8, 5, g= cc_parent_map_0, ftbl_gcc_ufs_card_axi_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_ufs_card_ice_core_clk_src, 0x7505c, 0,= 5, gcc_parent_map_0, ftbl_gcc_ufs_card_ice_core_clk_src, gcc_parent_data_0= ); +DEFINE_QCOM_CC_CLK(RCG2, gcc_ufs_card_phy_aux_clk_src, 0x75090, 0, 5, gcc_= parent_map_4, ftbl_gcc_cpuss_rbcpr_clk_src, gcc_parent_data_4); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_ufs_card_unipro_core_clk_src, 0x75074,= 0, 5, gcc_parent_map_0, ftbl_gcc_ufs_card_unipro_core_clk_src, gcc_parent_= data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_ufs_phy_axi_clk_src, 0x7701c, 8, 5, gc= c_parent_map_0, ftbl_gcc_ufs_phy_axi_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_ufs_phy_ice_core_clk_src, 0x7705c, 0, = 5, gcc_parent_map_0, ftbl_gcc_ufs_card_ice_core_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_ufs_phy_phy_aux_clk_src, 0x77090, 0, 5= , gcc_parent_map_4, ftbl_gcc_pcie_0_aux_clk_src, gcc_parent_data_4); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_ufs_phy_unipro_core_clk_src, 0x77074, = 0, 5, gcc_parent_map_0, ftbl_gcc_ufs_card_ice_core_clk_src, gcc_parent_data= _0); + +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_usb30_prim_master_clk_src, 0xf018, 8, = 5, gcc_parent_map_0, ftbl_gcc_usb30_prim_master_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_usb30_prim_mock_utmi_clk_src, 0xf030, = 8, 5, gcc_parent_map_0, ftbl_gcc_usb30_prim_mock_utmi_clk_src, gcc_parent_d= ata_0); +DEFINE_QCOM_CC_CLK(RCG2, gcc_usb30_sec_master_clk_src, 0x10018, 8, 5, gcc_= parent_map_0, ftbl_gcc_usb30_prim_master_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2, gcc_usb30_sec_mock_utmi_clk_src, 0x10030, 0, 5, g= cc_parent_map_0, ftbl_gcc_usb30_prim_master_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2, gcc_usb3_prim_phy_aux_clk_src, 0xf05c, 0, 5, gcc_= parent_map_2, ftbl_gcc_cpuss_rbcpr_clk_src, gcc_parent_data_2); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_usb3_sec_phy_aux_clk_src, 0x1005c, 8, = 5, gcc_parent_map_2, ftbl_gcc_cpuss_rbcpr_clk_src, gcc_parent_data_2); +DEFINE_QCOM_CC_CLK(RCG2, gcc_vs_ctrl_clk_src, 0x7a030, 0, 5, gcc_parent_ma= p_3, ftbl_gcc_cpuss_rbcpr_clk_src, gcc_parent_data_3); +DEFINE_QCOM_CC_CLK(RCG2, gcc_vsensor_clk_src, 0x7a018, 0, 5, gcc_parent_ma= p_3, ftbl_gcc_vsensor_clk_src, gcc_parent_data_3); =20 DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_aggre_noc_pcie_tbu_clk, 0, 0x90014, 0= , 0, 0x90014, BIT(0), 0); DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_aggre_ufs_card_axi_clk, 1, 0x82028, 0= x82028, 1, 0x82028, BIT(0), CLK_SET_RATE_PARENT, &gcc_ufs_card_axi_clk_src.= clkr.hw); --=20 2.34.3 From nobody Wed Apr 15 04:16:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A799C00140 for ; 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Tue, 26 Jul 2022 07:23:53 -0700 (PDT) From: Abel Vesa To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Mike Turquette , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Linux Kernel Mailing List , Abel Vesa Subject: [RFC 9/9] clk: qcom: gcc-sdm845: Switch to macros to collapse alpha-pll clocks definitions Date: Tue, 26 Jul 2022 17:23:03 +0300 Message-Id: <20220726142303.4126434-10-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.3 In-Reply-To: <20220726142303.4126434-1-abel.vesa@linaro.org> References: <20220726142303.4126434-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Switch from the expanded alpha-pll clocks definitions to the more compact macros. Signed-off-by: Abel Vesa --- drivers/clk/qcom/gcc-sdm845.c | 54 +++-------------------------------- 1 file changed, 4 insertions(+), 50 deletions(-) diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c index d9751d7e617c..ed85d3ba771a 100644 --- a/drivers/clk/qcom/gcc-sdm845.c +++ b/drivers/clk/qcom/gcc-sdm845.c @@ -34,40 +34,6 @@ enum { P_SLEEP_CLK, }; =20 -static struct clk_alpha_pll gpll0 =3D { - .offset =3D 0x0, - .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], - .clkr =3D { - .enable_reg =3D 0x52000, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gpll0", - .parent_data =3D &(const struct clk_parent_data){ - .fw_name =3D "bi_tcxo", .name =3D "bi_tcxo", - }, - .num_parents =3D 1, - .ops =3D &clk_alpha_pll_fixed_fabia_ops, - }, - }, -}; - -static struct clk_alpha_pll gpll4 =3D { - .offset =3D 0x76000, - .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], - .clkr =3D { - .enable_reg =3D 0x52000, - .enable_mask =3D BIT(4), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gpll4", - .parent_data =3D &(const struct clk_parent_data){ - .fw_name =3D "bi_tcxo", .name =3D "bi_tcxo", - }, - .num_parents =3D 1, - .ops =3D &clk_alpha_pll_fixed_fabia_ops, - }, - }, -}; - static const struct clk_div_table post_div_table_fabia_even[] =3D { { 0x0, 1 }, { 0x1, 2 }, @@ -76,22 +42,10 @@ static const struct clk_div_table post_div_table_fabia_= even[] =3D { { } }; =20 -static struct clk_alpha_pll_postdiv gpll0_out_even =3D { - .offset =3D 0x0, - .post_div_shift =3D 8, - .post_div_table =3D post_div_table_fabia_even, - .num_post_div =3D ARRAY_SIZE(post_div_table_fabia_even), - .width =3D 4, - .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], - .clkr.hw.init =3D &(struct clk_init_data){ - .name =3D "gpll0_out_even", - .parent_hws =3D (const struct clk_hw*[]){ - &gpll0.clkr.hw, - }, - .num_parents =3D 1, - .ops =3D &clk_alpha_pll_postdiv_fabia_ops, - }, -}; +DEFINE_QCOM_CC_CLK(ALPHA_PLL, gpll0, 0x0, 0x52000, BIT(0), "bi_tcxo"); +DEFINE_QCOM_CC_CLK(ALPHA_PLL, gpll4, 0x76000, 0x52000, BIT(4), "bi_tcxo"); + +DEFINE_QCOM_CC_CLK(ALPHA_PLL_POSTDIV, gpll0_out_even, 0x0, 8, post_div_tab= le_fabia_even, 4, &gpll0.clkr.hw); =20 static const struct parent_map gcc_parent_map_0[] =3D { { P_BI_TCXO, 0 }, --=20 2.34.3