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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id d13-20020adf9c8d000000b0021e4c3b2967sm15244670wre.65.2022.07.26.06.55.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Jul 2022 06:55:20 -0700 (PDT) From: Balsam CHIHI To: rafael@kernel.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, amitk@kernel.org Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, mka@chromium.org, robh+dt@kernel.org, krzk+dt@kernel.org, matthias.bgg@gmail.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, fan.chen@mediatek.com, louis.yu@mediatek.com, rex-bc.chen@mediatek.com, abailon@baylibre.com Subject: [PATCH v8 4/6] thermal: mediatek: Add thermal zone settings for mt8195 Date: Tue, 26 Jul 2022 15:55:04 +0200 Message-Id: <20220726135506.485108-5-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220726135506.485108-1-bchihi@baylibre.com> References: <20220726135506.485108-1-bchihi@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add thermal zone settings for mt8195 Signed-off-by: Michael Kao Signed-off-by: Ben Tseng Signed-off-by: Alexandre Bailon Signed-off-by: Balsam CHIHI --- drivers/thermal/mediatek/Kconfig | 12 ++ drivers/thermal/mediatek/Makefile | 1 + drivers/thermal/mediatek/lvts_mt8195.c | 253 +++++++++++++++++++++++ drivers/thermal/mediatek/soc_temp_lvts.h | 1 + 4 files changed, 267 insertions(+) create mode 100644 drivers/thermal/mediatek/lvts_mt8195.c diff --git a/drivers/thermal/mediatek/Kconfig b/drivers/thermal/mediatek/Kc= onfig index 7fc04237dd50..df3b4a033fc2 100644 --- a/drivers/thermal/mediatek/Kconfig +++ b/drivers/thermal/mediatek/Kconfig @@ -47,4 +47,16 @@ config LVTS_MT8192 configures LVTS thermal controllers to collect temperatures via ASIF. =20 +config LVTS_MT8195 + tristate "LVTS driver for MediaTek MT8195 SoC" + depends on HAS_IOMEM + depends on NVMEM + depends on RESET_TI_SYSCON + depends on MTK_SOC_THERMAL_LVTS + help + Enable this option if you want to get SoC temperature + information for MT8195. This driver + configures LVTS thermal controllers to collect temperatures + via ASIF. + endif diff --git a/drivers/thermal/mediatek/Makefile b/drivers/thermal/mediatek/M= akefile index 5ff1197e80ab..dada1bf13110 100644 --- a/drivers/thermal/mediatek/Makefile +++ b/drivers/thermal/mediatek/Makefile @@ -1,3 +1,4 @@ obj-$(CONFIG_MTK_SOC_THERMAL) +=3D soc_temp.o obj-$(CONFIG_MTK_SOC_THERMAL_LVTS) +=3D soc_temp_lvts.o obj-$(CONFIG_LVTS_MT8192) +=3D lvts_mt8192.o +obj-$(CONFIG_LVTS_MT8195) +=3D lvts_mt8195.o diff --git a/drivers/thermal/mediatek/lvts_mt8195.c b/drivers/thermal/media= tek/lvts_mt8195.c new file mode 100644 index 000000000000..df69e2e79115 --- /dev/null +++ b/drivers/thermal/mediatek/lvts_mt8195.c @@ -0,0 +1,253 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 MediaTek Inc. + */ + +#include +#include +#include "soc_temp_lvts.h" + +enum mt8195_lvts_mcu_sensor_enum { + MT8195_TS1_0, // cpu_big1 + MT8195_TS1_1, // cpu_big2 + MT8195_TS2_0, // cpu_big3 + MT8195_TS2_1, // cpu_big4 + MT8195_TS3_0, // cpu_little1 + MT8195_TS3_1, // cpu_little2 + MT8195_TS3_2, // cpu_little3 + MT8195_TS3_3, // cpu_little4 + MT8195_NUM_TS_MCU +}; + +enum mt8195_lvts_ap_sensor_enum { + MT8195_TS4_0, // vpu1 + MT8195_TS4_1, // vpu2 + MT8195_TS5_0, // gpu1 + MT8195_TS5_1, // gpu2 + MT8195_TS6_0, // vdec + MT8195_TS6_1, // img + MT8195_TS6_2, // infra + MT8195_TS7_0, // cam1 + MT8195_TS7_1, // cam2 + MT8195_NUM_TS_AP +}; + +static void mt8195_mcu_efuse_to_cal_data(struct lvts_data *lvts_data) +{ + struct lvts_sensor_cal_data *cal_data =3D &lvts_data->cal_data; + + cal_data->golden_temp =3D GET_CAL_DATA_BITMASK(0, lvts_data, 31, 24); + + cal_data->count_r[MT8195_TS1_0] =3D GET_CAL_DATA_BITMASK(1, lvts_data, 23= , 0); + cal_data->count_r[MT8195_TS1_1] =3D (GET_CAL_DATA_BITMASK(2, lvts_data, 1= 5, 0) << 8) + + GET_CAL_DATA_BITMASK(1, lvts_data, 31, 24); + cal_data->count_r[MT8195_TS2_0] =3D GET_CAL_DATA_BITMASK(3, lvts_data, 31= , 8); + cal_data->count_r[MT8195_TS2_1] =3D GET_CAL_DATA_BITMASK(4, lvts_data, 23= , 0); + cal_data->count_r[MT8195_TS3_0] =3D (GET_CAL_DATA_BITMASK(6, lvts_data, 7= , 0) << 16) + + GET_CAL_DATA_BITMASK(5, lvts_data, 31, 16); + cal_data->count_r[MT8195_TS3_1] =3D GET_CAL_DATA_BITMASK(6, lvts_data, 31= , 8); + cal_data->count_r[MT8195_TS3_2] =3D GET_CAL_DATA_BITMASK(7, lvts_data, 23= , 0); + cal_data->count_r[MT8195_TS3_3] =3D (GET_CAL_DATA_BITMASK(8, lvts_data, 1= 5, 0) << 8) + + GET_CAL_DATA_BITMASK(7, lvts_data, 31, 24); + + cal_data->count_rc[MT8195_TS1_0] =3D (GET_CAL_DATA_BITMASK(3, lvts_data, = 7, 0) << 16) + + GET_CAL_DATA_BITMASK(2, lvts_data, 31, 16); + cal_data->count_rc[MT8195_TS2_0] =3D (GET_CAL_DATA_BITMASK(5, lvts_data, = 15, 0) << 8) + + GET_CAL_DATA_BITMASK(4, lvts_data, 31, 24); + cal_data->count_rc[MT8195_TS3_0] =3D (GET_CAL_DATA_BITMASK(9, lvts_data, = 7, 0) << 16) + + GET_CAL_DATA_BITMASK(8, lvts_data, 31, 16); +} + +static void mt8195_ap_efuse_to_cal_data(struct lvts_data *lvts_data) +{ + struct lvts_sensor_cal_data *cal_data =3D &lvts_data->cal_data; + + cal_data->golden_temp =3D GET_CAL_DATA_BITMASK(0, lvts_data, 31, 24); + + cal_data->count_r[MT8195_TS4_0] =3D GET_CAL_DATA_BITMASK(9, lvts_data, 31= , 8); + cal_data->count_r[MT8195_TS4_1] =3D GET_CAL_DATA_BITMASK(10, lvts_data, 2= 3, 0); + cal_data->count_r[MT8195_TS5_0] =3D (GET_CAL_DATA_BITMASK(12, lvts_data, = 7, 0) << 16) + + GET_CAL_DATA_BITMASK(11, lvts_data, 31, 16); + cal_data->count_r[MT8195_TS5_1] =3D GET_CAL_DATA_BITMASK(12, lvts_data, 3= 1, 8); + cal_data->count_r[MT8195_TS6_0] =3D (GET_CAL_DATA_BITMASK(14, lvts_data, = 15, 0) << 8) + + GET_CAL_DATA_BITMASK(13, lvts_data, 31, 24); + cal_data->count_r[MT8195_TS6_1] =3D (GET_CAL_DATA_BITMASK(15, lvts_data, = 7, 0) << 16) + + GET_CAL_DATA_BITMASK(14, lvts_data, 31, 16); + cal_data->count_r[MT8195_TS6_2] =3D GET_CAL_DATA_BITMASK(15, lvts_data, 3= 1, 8); + cal_data->count_r[MT8195_TS7_0] =3D (GET_CAL_DATA_BITMASK(17, lvts_data, = 15, 0) << 8) + + GET_CAL_DATA_BITMASK(16, lvts_data, 31, 24); + cal_data->count_r[MT8195_TS7_1] =3D (GET_CAL_DATA_BITMASK(18, lvts_data, = 7, 0) << 16) + + GET_CAL_DATA_BITMASK(17, lvts_data, 31, 16); + + cal_data->count_rc[MT8195_TS4_0] =3D (GET_CAL_DATA_BITMASK(11, lvts_data,= 15, 0) << 8) + + GET_CAL_DATA_BITMASK(10, lvts_data, 31, 24); + cal_data->count_rc[MT8195_TS5_0] =3D GET_CAL_DATA_BITMASK(13, lvts_data, = 23, 0); + cal_data->count_rc[MT8195_TS6_0] =3D GET_CAL_DATA_BITMASK(16, lvts_data, = 23, 0); + cal_data->count_rc[MT8195_TS7_0] =3D GET_CAL_DATA_BITMASK(18, lvts_data, = 31, 8); +} + +static struct lvts_speed_settings tc_speed_mt8195 =3D { + .period_unit =3D PERIOD_UNIT, + .group_interval_delay =3D GROUP_INTERVAL_DELAY, + .filter_interval_delay =3D FILTER_INTERVAL_DELAY, + .sensor_interval_delay =3D SENSOR_INTERVAL_DELAY, +}; + +static const struct lvts_tc_settings mt8195_tc_mcu_settings[] =3D { + [0] =3D { + .dev_id =3D 0x81, + .addr_offset =3D 0x0, + .num_sensor =3D 2, + .sensor_map =3D {MT8195_TS1_0, MT8195_TS1_1}, + .tc_speed =3D &tc_speed_mt8195, + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT1, + .hw_reboot_trip_point =3D HW_REBOOT_TRIP_POINT, + .irq_bit =3D BIT(3), + }, + [1] =3D { + .dev_id =3D 0x82, + .addr_offset =3D 0x100, + .num_sensor =3D 2, + .sensor_map =3D {MT8195_TS2_0, MT8195_TS2_1}, + .tc_speed =3D &tc_speed_mt8195, + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT0, + .hw_reboot_trip_point =3D HW_REBOOT_TRIP_POINT, + .irq_bit =3D BIT(4), + }, + [2] =3D { + .dev_id =3D 0x83, + .addr_offset =3D 0x200, + .num_sensor =3D 4, + .sensor_map =3D {MT8195_TS3_0, MT8195_TS3_1, MT8195_TS3_2, MT8195_TS3_3}, + .tc_speed =3D &tc_speed_mt8195, + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT0, + .hw_reboot_trip_point =3D HW_REBOOT_TRIP_POINT, + .irq_bit =3D BIT(5), + } +}; + +static const struct lvts_tc_settings mt8195_tc_ap_settings[] =3D { + [0] =3D { + .dev_id =3D 0x84, + .addr_offset =3D 0x0, + .num_sensor =3D 2, + .sensor_map =3D {MT8195_TS4_0, MT8195_TS4_1}, + .tc_speed =3D &tc_speed_mt8195, + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT0, + .hw_reboot_trip_point =3D HW_REBOOT_TRIP_POINT, + .irq_bit =3D BIT(3), + }, + [1] =3D { + .dev_id =3D 0x85, + .addr_offset =3D 0x100, + .num_sensor =3D 2, + .sensor_map =3D {MT8195_TS5_0, MT8195_TS5_1}, + .tc_speed =3D &tc_speed_mt8195, + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT1, + .hw_reboot_trip_point =3D HW_REBOOT_TRIP_POINT, + .irq_bit =3D BIT(4), + }, + [2] =3D { + .dev_id =3D 0x86, + .addr_offset =3D 0x200, + .num_sensor =3D 3, + .sensor_map =3D {MT8195_TS6_0, MT8195_TS6_1, MT8195_TS6_2}, + .tc_speed =3D &tc_speed_mt8195, + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT1, + .hw_reboot_trip_point =3D HW_REBOOT_TRIP_POINT, + .irq_bit =3D BIT(5), + }, + [3] =3D { + .dev_id =3D 0x87, + .addr_offset =3D 0x300, + .num_sensor =3D 2, + .sensor_map =3D {MT8195_TS7_0, MT8195_TS7_1}, + .tc_speed =3D &tc_speed_mt8195, + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT0, + .hw_reboot_trip_point =3D HW_REBOOT_TRIP_POINT, + .irq_bit =3D BIT(6), + } +}; + +static const struct lvts_data mt8195_lvts_mcu_data =3D { + .num_tc =3D (ARRAY_SIZE(mt8195_tc_mcu_settings)), + .tc =3D mt8195_tc_mcu_settings, + .num_sensor =3D MT8195_NUM_TS_MCU, + .ops =3D { + .efuse_to_cal_data =3D mt8195_mcu_efuse_to_cal_data, + .device_enable_and_init =3D lvts_device_enable_and_init_v4, + .device_enable_auto_rck =3D lvts_device_enable_auto_rck_v4, + .device_read_count_rc_n =3D lvts_device_read_count_rc_n_v4, + .set_cal_data =3D lvts_set_calibration_data_v4, + .init_controller =3D lvts_init_controller_v4, + }, + .feature_bitmap =3D FEATURE_DEVICE_AUTO_RCK, + .num_efuse_addr =3D NUM_EFUSE_ADDR, + .num_efuse_block =3D NUM_EFUSE_BLOCK_MT8195, + .cal_data =3D { + .default_golden_temp =3D DEFAULT_GOLDEN_TEMP, + .default_count_r =3D DEFAULT_CUONT_R, + .default_count_rc =3D DEFAULT_CUONT_RC, + }, + .coeff =3D { + .a =3D COEFF_A, + .b =3D COEFF_B, + }, +}; + +static const struct lvts_data mt8195_lvts_ap_data =3D { + .num_tc =3D (ARRAY_SIZE(mt8195_tc_ap_settings)), + .tc =3D mt8195_tc_ap_settings, + .num_sensor =3D MT8195_NUM_TS_AP, + .ops =3D { + .efuse_to_cal_data =3D mt8195_ap_efuse_to_cal_data, + .device_enable_and_init =3D lvts_device_enable_and_init_v4, + .device_enable_auto_rck =3D lvts_device_enable_auto_rck_v4, + .device_read_count_rc_n =3D lvts_device_read_count_rc_n_v4, + .set_cal_data =3D lvts_set_calibration_data_v4, + .init_controller =3D lvts_init_controller_v4, + }, + .feature_bitmap =3D FEATURE_DEVICE_AUTO_RCK, + .num_efuse_addr =3D NUM_EFUSE_ADDR, + .num_efuse_block =3D NUM_EFUSE_BLOCK_MT8195, + .cal_data =3D { + .default_golden_temp =3D DEFAULT_GOLDEN_TEMP, + .default_count_r =3D DEFAULT_CUONT_R, + .default_count_rc =3D DEFAULT_CUONT_RC, + }, + .coeff =3D { + .a =3D COEFF_A, + .b =3D COEFF_B, + }, +}; + +static const struct of_device_id lvts_of_match[] =3D { + { .compatible =3D "mediatek,mt8195-lvts-mcu", .data =3D &mt8195_lvts_mcu_= data, }, + { .compatible =3D "mediatek,mt8195-lvts-ap", .data =3D &mt8195_lvts_ap_da= ta, }, + {}, +}; +MODULE_DEVICE_TABLE(of, lvts_of_match); + +static struct platform_driver soc_temp_lvts =3D { + .probe =3D lvts_probe, + .remove =3D lvts_remove, + .suspend =3D lvts_suspend, + .resume =3D lvts_resume, + .driver =3D { + .name =3D "mtk-soc-temp-lvts-mt8195", + .of_match_table =3D lvts_of_match, + }, +}; +module_platform_driver(soc_temp_lvts); + +MODULE_AUTHOR("Yu-Chia Chang "); +MODULE_AUTHOR("Michael Kao "); +MODULE_DESCRIPTION("MediaTek soc temperature driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/thermal/mediatek/soc_temp_lvts.h b/drivers/thermal/med= iatek/soc_temp_lvts.h index 6f8b6e3af98c..c4acb7e26e5e 100644 --- a/drivers/thermal/mediatek/soc_temp_lvts.h +++ b/drivers/thermal/mediatek/soc_temp_lvts.h @@ -16,6 +16,7 @@ #define FEATURE_DEVICE_AUTO_RCK BIT(0) #define NUM_EFUSE_ADDR 22 #define NUM_EFUSE_BLOCK_MT8192 1 +#define NUM_EFUSE_BLOCK_MT8195 2 #define DEFAULT_GOLDEN_TEMP 50 #define DEFAULT_CUONT_R 35000 #define DEFAULT_CUONT_RC 2750 --=20 2.34.1