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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id d13-20020adf9c8d000000b0021e4c3b2967sm15244670wre.65.2022.07.26.06.55.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Jul 2022 06:55:17 -0700 (PDT) From: Balsam CHIHI To: rafael@kernel.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, amitk@kernel.org Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, mka@chromium.org, robh+dt@kernel.org, krzk+dt@kernel.org, matthias.bgg@gmail.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, fan.chen@mediatek.com, louis.yu@mediatek.com, rex-bc.chen@mediatek.com, abailon@baylibre.com Subject: [PATCH v8 1/6] thermal: mediatek: Relocate driver to mediatek folder Date: Tue, 26 Jul 2022 15:55:01 +0200 Message-Id: <20220726135506.485108-2-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220726135506.485108-1-bchihi@baylibre.com> References: <20220726135506.485108-1-bchihi@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add Mediatek proprietary folder to upstream more thermal zone and cooler drivers. Relocate the original thermal controller driver to it and rename as soc_temp.c to show its purpose more clearly. Signed-off-by: Michael Kao Signed-off-by: Ben Tseng Reviewed-by: Matthias Brugger Signed-off-by: Balsam CHIHI Reviewed-by: AngeloGioacchino Del Regno --- drivers/thermal/Kconfig | 14 ++++------- drivers/thermal/Makefile | 2 +- drivers/thermal/mediatek/Kconfig | 23 +++++++++++++++++++ drivers/thermal/mediatek/Makefile | 1 + .../{mtk_thermal.c =3D> mediatek/soc_temp.c} | 0 5 files changed, 29 insertions(+), 11 deletions(-) create mode 100644 drivers/thermal/mediatek/Kconfig create mode 100644 drivers/thermal/mediatek/Makefile rename drivers/thermal/{mtk_thermal.c =3D> mediatek/soc_temp.c} (100%) diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 0e5cc948373c..ecba8d6e313b 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -412,16 +412,10 @@ config DA9062_THERMAL zone. Compatible with the DA9062 and DA9061 PMICs. =20 -config MTK_THERMAL - tristate "Temperature sensor driver for mediatek SoCs" - depends on ARCH_MEDIATEK || COMPILE_TEST - depends on HAS_IOMEM - depends on NVMEM || NVMEM=3Dn - depends on RESET_CONTROLLER - default y - help - Enable this option if you want to have support for thermal management - controller present in Mediatek SoCs +menu "Mediatek thermal drivers" +depends on ARCH_MEDIATEK || COMPILE_TEST +source "drivers/thermal/mediatek/Kconfig" +endmenu =20 config AMLOGIC_THERMAL tristate "Amlogic Thermal Support" diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index def8e1a0399c..3c00e864ad55 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -55,7 +55,7 @@ obj-y +=3D st/ obj-$(CONFIG_QCOM_TSENS) +=3D qcom/ obj-y +=3D tegra/ obj-$(CONFIG_HISI_THERMAL) +=3D hisi_thermal.o -obj-$(CONFIG_MTK_THERMAL) +=3D mtk_thermal.o +obj-$(CONFIG_MTK_THERMAL) +=3D mediatek/ obj-$(CONFIG_GENERIC_ADC_THERMAL) +=3D thermal-generic-adc.o obj-$(CONFIG_UNIPHIER_THERMAL) +=3D uniphier_thermal.o obj-$(CONFIG_AMLOGIC_THERMAL) +=3D amlogic_thermal.o diff --git a/drivers/thermal/mediatek/Kconfig b/drivers/thermal/mediatek/Kc= onfig new file mode 100644 index 000000000000..9c41e9079fc3 --- /dev/null +++ b/drivers/thermal/mediatek/Kconfig @@ -0,0 +1,23 @@ +config MTK_THERMAL + tristate "MediaTek thermal drivers" + depends on THERMAL_OF + help + This is the option for MediaTek thermal software + solutions. Please enable corresponding options to + get temperature information from thermal sensors or + turn on throttle mechaisms for thermal mitigation. + +if MTK_THERMAL + +config MTK_SOC_THERMAL + tristate "Temperature sensor driver for MediaTek SoCs" + depends on HAS_IOMEM + depends on NVMEM + depends on RESET_CONTROLLER + help + Enable this option if you want to get SoC temperature + information for MediaTek platforms. This driver + configures thermal controllers to collect temperature + via AUXADC interface. + +endif diff --git a/drivers/thermal/mediatek/Makefile b/drivers/thermal/mediatek/M= akefile new file mode 100644 index 000000000000..4b4cb04a358f --- /dev/null +++ b/drivers/thermal/mediatek/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_MTK_SOC_THERMAL) +=3D soc_temp.o diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mediatek/soc_t= emp.c similarity index 100% rename from drivers/thermal/mtk_thermal.c rename to drivers/thermal/mediatek/soc_temp.c --=20 2.34.1 From nobody Sat Sep 21 20:11:47 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3EA35C00140 for ; Tue, 26 Jul 2022 13:55:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239121AbiGZNzb (ORCPT ); Tue, 26 Jul 2022 09:55:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37794 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229634AbiGZNzV (ORCPT ); Tue, 26 Jul 2022 09:55:21 -0400 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 637CF7672 for ; Tue, 26 Jul 2022 06:55:20 -0700 (PDT) Received: by mail-wr1-x42d.google.com with SMTP id u5so20268869wrm.4 for ; Tue, 26 Jul 2022 06:55:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4UyB6UT6ks0HkEwyd3qTKWT7a722IA4Qy0x6ECfS6JA=; b=fnElU9WVkp/hVhjv7YThd5aslfssg97RW5Tc1Htc8AR/9ztHH0xlHj+E1ANhlATIin NpCigtCYkQPtAt4+998IITLVdULV+9ilkjQuyB4FpACY69+gQUDL+lk1KY0Hz5J08+/i EGLxVbqfCUgGEZPemzqKYJrQnXKYjSqzX/IaA+l5DSyONvBo9iMEgdrUP0hv7aEMNuDp gNkUWDOt0MNHSQhzapmSD0z5p3VdS+nnLAnMW3FEz8Qz/DmsCYXtwjCYZHOSKeYn2RXg G7rHqkqafxEz0fBrB5x8+lUwJTD54xUirg6le322OaUZyQoPvPGiucsZPUp1b2luQ2DN +MfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4UyB6UT6ks0HkEwyd3qTKWT7a722IA4Qy0x6ECfS6JA=; b=FYSWG52D7axPwaBnDX1kDH/wiHB7KsD6Jq77ioCnD4iwflTrC2Nbnf5/47sNgPve2E m+hS5V9PzB+py+P4Tqu6ZBfMn2drZVHySvGoKgBZE8W0PV/xzjAOkAhCRjFb4P0C+EIZ y6qvexNmxbhFjOV8fUFr4MqAxlySJ8FS2v4uPWlXxUROFSjJkVPfnDU9NeB1AzkB/vaq NJnfXQE/QwUt6BSSLCj8rqNgT4mt9hev7MYgCWq+m5+iEbE1sA9az1pbo9FGcvIbu96H eKPl2SodXyHWzgEdCsrmVX50OC3v6MsNkabTK90COBZy+OcgjmhnxdJG/VTdE9+6UAnO k/6w== X-Gm-Message-State: AJIora/8GHjcLmrputaZ4avKImlC8kuvRjN8d/4FvnTOrHVVxIbokR3P /jcGIP4U2dM1uPF5sNdp5mWWNg== X-Google-Smtp-Source: AGRyM1tNOSDyHTzrF4a7MTg/xELPN/dHSfVWdPLkjj7I/TNbUJeJJG9NgzCR6U44gB8fwRp4KDsO2A== X-Received: by 2002:adf:f492:0:b0:21d:89d5:9443 with SMTP id l18-20020adff492000000b0021d89d59443mr10608607wro.201.1658843718871; Tue, 26 Jul 2022 06:55:18 -0700 (PDT) Received: from Balsam-ThinkPad-T480.baylibre (laubervilliers-658-1-213-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id d13-20020adf9c8d000000b0021e4c3b2967sm15244670wre.65.2022.07.26.06.55.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Jul 2022 06:55:18 -0700 (PDT) From: Balsam CHIHI To: rafael@kernel.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, amitk@kernel.org Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, mka@chromium.org, robh+dt@kernel.org, krzk+dt@kernel.org, matthias.bgg@gmail.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, fan.chen@mediatek.com, louis.yu@mediatek.com, rex-bc.chen@mediatek.com, abailon@baylibre.com Subject: [PATCH v8 2/6] dt-bindings: thermal: Add binding document for LVTS thermal controllers Date: Tue, 26 Jul 2022 15:55:02 +0200 Message-Id: <20220726135506.485108-3-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220726135506.485108-1-bchihi@baylibre.com> References: <20220726135506.485108-1-bchihi@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch adds dt-binding documents for mt8192 and mt8195 thermal controll= ers. Signed-off-by: Alexandre Bailon Signed-off-by: Balsam CHIHI --- .../thermal/mediatek,mt8192-lvts.yaml | 73 ++++++++++++++++++ .../thermal/mediatek,mt8195-lvts.yaml | 75 +++++++++++++++++++ 2 files changed, 148 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/mediatek,mt81= 92-lvts.yaml create mode 100644 Documentation/devicetree/bindings/thermal/mediatek,mt81= 95-lvts.yaml diff --git a/Documentation/devicetree/bindings/thermal/mediatek,mt8192-lvts= .yaml b/Documentation/devicetree/bindings/thermal/mediatek,mt8192-lvts.yaml new file mode 100644 index 000000000000..8c5a02eb97c5 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/mediatek,mt8192-lvts.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/mediatek,mt8192-lvts.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek SoC LVTS thermal controller + +maintainers: + - Yu-Chia Chang + - Ben Tseng + +properties: + compatible: + enum: + - mediatek,mt8192-lvts-ap + - mediatek,mt8192-lvts-mcu + + "#thermal-sensor-cells": + const: 1 + + reg: + maxItems: 2 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + items: + - description: SW reset HW AP/MCU domain for clean temporary data wh= en HW initialization and resume. + + nvmem-cells: + items: + - description: LVTS calibration data for thermal sensors + + nvmem-cell-names: + items: + - const: lvts_calib_data + +required: + - compatible + - '#thermal-sensor-cells' + - reg + - interrupts + - clocks + - resets + - nvmem-cells + - nvmem-cell-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + lvtsmcu: thermal-sensor@11278000 { + compatible =3D "mediatek,mt8192-lvts-mcu"; + #thermal-sensor-cells =3D <1>; + reg =3D <0 0x11278000 0 0x400>; + interrupts =3D ; + clocks =3D <&infracfg_ao CLK_INFRA_THERM>; + resets =3D <&infracfg_ao MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST>; + nvmem-cells =3D <&lvts_efuse_data>; + nvmem-cell-names =3D "lvts_calib_data"; + }; + +... diff --git a/Documentation/devicetree/bindings/thermal/mediatek,mt8195-lvts= .yaml b/Documentation/devicetree/bindings/thermal/mediatek,mt8195-lvts.yaml new file mode 100644 index 000000000000..6b0b53a33272 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/mediatek,mt8195-lvts.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/mediatek,mt8195-lvts.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek SoC LVTS thermal controller + +maintainers: + - Yu-Chia Chang + - Ben Tseng + +properties: + compatible: + enum: + - mediatek,mt8195-lvts-ap + - mediatek,mt8195-lvts-mcu + + "#thermal-sensor-cells": + const: 1 + + reg: + maxItems: 2 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + items: + - description: SW reset HW AP/MCU domain for clean temporary data wh= en HW initialization and resume. + + nvmem-cells: + items: + - description: LVTS calibration data 1 for thermal sensors + - description: LVTS calibration data 2 for thermal sensors + + nvmem-cell-names: + items: + - const: lvts_calib_data1 + - const: lvts_calib_data2 + +required: + - compatible + - '#thermal-sensor-cells' + - reg + - interrupts + - clocks + - resets + - nvmem-cells + - nvmem-cell-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + lvtsmcu: thermal-sensor@11278000 { + compatible =3D "mediatek,mt8195-lvts-mcu"; + #thermal-sensor-cells =3D <1>; + reg =3D <0 0x11278000 0 0x400>; + interrupts =3D ; + clocks =3D <&infracfg_ao CLK_INFRA_AO_THERM>; + resets =3D <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>; + nvmem-cells =3D <&lvts_efuse_data1 &lvts_efuse_data2>; + nvmem-cell-names =3D "lvts_calib_data1", "lvts_calib_data2"; + }; + +... --=20 2.34.1 From nobody Sat Sep 21 20:11:47 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76B2FC00140 for ; Tue, 26 Jul 2022 13:57:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239244AbiGZN4C (ORCPT ); Tue, 26 Jul 2022 09:56:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38056 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239134AbiGZNzb (ORCPT ); Tue, 26 Jul 2022 09:55:31 -0400 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C8742BC88 for ; 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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id d13-20020adf9c8d000000b0021e4c3b2967sm15244670wre.65.2022.07.26.06.55.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Jul 2022 06:55:19 -0700 (PDT) From: Balsam CHIHI To: rafael@kernel.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, amitk@kernel.org Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, mka@chromium.org, robh+dt@kernel.org, krzk+dt@kernel.org, matthias.bgg@gmail.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, fan.chen@mediatek.com, louis.yu@mediatek.com, rex-bc.chen@mediatek.com, abailon@baylibre.com Subject: [PATCH v8 3/6] thermal: mediatek: Add LVTS drivers for SoC theraml zones for mt8192 Date: Tue, 26 Jul 2022 15:55:03 +0200 Message-Id: <20220726135506.485108-4-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220726135506.485108-1-bchihi@baylibre.com> References: <20220726135506.485108-1-bchihi@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a LVTS (Low voltage thermal sensor) driver to report junction temperatures in Mediatek SoC mt8192 and register the maximum temperature of sensors and each sensor as a thermal zone. Signed-off-by: Yu-Chia Chang Signed-off-by: Michael Kao Signed-off-by: Ben Tseng Signed-off-by: Alexandre Bailon Signed-off-by: Balsam CHIHI --- drivers/thermal/mediatek/Kconfig | 27 + drivers/thermal/mediatek/Makefile | 2 + drivers/thermal/mediatek/lvts_mt8192.c | 241 ++++++ drivers/thermal/mediatek/soc_temp.c | 2 +- drivers/thermal/mediatek/soc_temp_lvts.c | 928 +++++++++++++++++++++++ drivers/thermal/mediatek/soc_temp_lvts.h | 365 +++++++++ 6 files changed, 1564 insertions(+), 1 deletion(-) create mode 100644 drivers/thermal/mediatek/lvts_mt8192.c create mode 100644 drivers/thermal/mediatek/soc_temp_lvts.c create mode 100644 drivers/thermal/mediatek/soc_temp_lvts.h diff --git a/drivers/thermal/mediatek/Kconfig b/drivers/thermal/mediatek/Kc= onfig index 9c41e9079fc3..7fc04237dd50 100644 --- a/drivers/thermal/mediatek/Kconfig +++ b/drivers/thermal/mediatek/Kconfig @@ -20,4 +20,31 @@ config MTK_SOC_THERMAL configures thermal controllers to collect temperature via AUXADC interface. =20 +config MTK_SOC_THERMAL_LVTS + tristate "LVTS (Low voltage thermal sensor) driver for Mediatek SoCs" + depends on HAS_IOMEM + depends on NVMEM + depends on RESET_TI_SYSCON + help + Enable this option if you want to get SoC temperature + information for MediaTek platforms. This driver + configures LVTS thermal controllers to collect temperatures + via Analog Serial Interface(ASIF). + +endif + +if MTK_SOC_THERMAL_LVTS + +config LVTS_MT8192 + tristate "LVTS driver for MediaTek MT8192 SoC" + depends on HAS_IOMEM + depends on NVMEM + depends on RESET_TI_SYSCON + depends on MTK_SOC_THERMAL_LVTS + help + Enable this option if you want to get SoC temperature + information for MT8192. This driver + configures LVTS thermal controllers to collect temperatures + via ASIF. + endif diff --git a/drivers/thermal/mediatek/Makefile b/drivers/thermal/mediatek/M= akefile index 4b4cb04a358f..5ff1197e80ab 100644 --- a/drivers/thermal/mediatek/Makefile +++ b/drivers/thermal/mediatek/Makefile @@ -1 +1,3 @@ obj-$(CONFIG_MTK_SOC_THERMAL) +=3D soc_temp.o +obj-$(CONFIG_MTK_SOC_THERMAL_LVTS) +=3D soc_temp_lvts.o +obj-$(CONFIG_LVTS_MT8192) +=3D lvts_mt8192.o diff --git a/drivers/thermal/mediatek/lvts_mt8192.c b/drivers/thermal/media= tek/lvts_mt8192.c new file mode 100644 index 000000000000..19e4e82c410b --- /dev/null +++ b/drivers/thermal/mediatek/lvts_mt8192.c @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 MediaTek Inc. + */ + +#include +#include +#include "soc_temp_lvts.h" + +enum mt8192_lvts_mcu_sensor_enum { + MT8192_TS1_0, + MT8192_TS1_1, + MT8192_TS2_0, + MT8192_TS2_1, + MT8192_TS3_0, + MT8192_TS3_1, + MT8192_TS3_2, + MT8192_TS3_3, + MT8192_NUM_TS_MCU +}; + +enum mt8192_lvts_ap_sensor_enum { + MT8192_TS4_0, + MT8192_TS4_1, + MT8192_TS5_0, + MT8192_TS5_1, + MT8192_TS6_0, + MT8192_TS6_1, + MT8192_TS7_0, + MT8192_TS7_1, + MT8192_TS7_2, + MT8192_NUM_TS_AP +}; + +static void mt8192_mcu_efuse_to_cal_data(struct lvts_data *lvts_data) +{ + struct lvts_sensor_cal_data *cal_data =3D &lvts_data->cal_data; + unsigned int i, j; + const unsigned int mt8192_TS[] =3D {MT8192_TS2_0, MT8192_TS3_0}; + + cal_data->golden_temp =3D GET_CAL_DATA_BITMASK(0, lvts_data, 31, 24); + + for (i =3D 0; i < MT8192_NUM_TS_MCU; i++) + cal_data->count_r[i] =3D GET_CAL_DATA_BITMASK(i + 1, lvts_data, 23, 0); + + cal_data->count_rc[MT8192_TS1_0] =3D GET_CAL_DATA_BITMASK(21, lvts_data, = 23, 0); + + for (i =3D 0; i < (ARRAY_SIZE(mt8192_TS)); i++) { + for (j =3D 1; j <=3D 18; j++) { + cal_data->count_rc[mt8192_TS[i]] =3D (GET_CAL_DATA_BITMASK(j, lvts_data= , 31, 24) << 16) + + (GET_CAL_DATA_BITMASK(j, lvts_data, 31, 24) << 8) + + GET_CAL_DATA_BITMASK(j, lvts_data, 31, 24); + } + } +} + +static void mt8192_ap_efuse_to_cal_data(struct lvts_data *lvts_data) +{ + struct lvts_sensor_cal_data *cal_data =3D &lvts_data->cal_data; + unsigned int i, j; + const unsigned int mt8192_TS[] =3D {MT8192_TS4_0, MT8192_TS5_0, MT8192_TS= 6_0, MT8192_TS7_0}; + + cal_data->golden_temp =3D GET_CAL_DATA_BITMASK(0, lvts_data, 31, 24); + + for (i =3D 0; i < MT8192_NUM_TS_AP; i++) + cal_data->count_r[i] =3D GET_CAL_DATA_BITMASK(i + 1, lvts_data, 23, 0); + + for (i =3D 0; i < (ARRAY_SIZE(mt8192_TS)); i++) { + for (j =3D 1; j <=3D 18; j++) { + cal_data->count_rc[mt8192_TS[i]] =3D (GET_CAL_DATA_BITMASK(j, lvts_data= , 31, 24) << 16) + + (GET_CAL_DATA_BITMASK(j, lvts_data, 31, 24) << 8) + + GET_CAL_DATA_BITMASK(j, lvts_data, 31, 24); + } + } +} + +static struct lvts_speed_settings tc_speed_mt8192 =3D { + .period_unit =3D PERIOD_UNIT, + .group_interval_delay =3D GROUP_INTERVAL_DELAY, + .filter_interval_delay =3D FILTER_INTERVAL_DELAY, + .sensor_interval_delay =3D SENSOR_INTERVAL_DELAY, +}; + +static const struct lvts_tc_settings mt8192_tc_mcu_settings[] =3D { + [0] =3D { + .dev_id =3D 0x81, + .addr_offset =3D 0x0, + .num_sensor =3D 2, + .sensor_map =3D {MT8192_TS1_0, MT8192_TS1_1}, + .tc_speed =3D &tc_speed_mt8192, + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT1, + .hw_reboot_trip_point =3D HW_REBOOT_TRIP_POINT, + .irq_bit =3D BIT(3), + }, + [1] =3D { + .dev_id =3D 0x82, + .addr_offset =3D 0x100, + .num_sensor =3D 2, + .sensor_map =3D {MT8192_TS2_0, MT8192_TS2_1}, + .tc_speed =3D &tc_speed_mt8192, + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT0, + .hw_reboot_trip_point =3D HW_REBOOT_TRIP_POINT, + .irq_bit =3D BIT(4), + }, + [2] =3D { + .dev_id =3D 0x83, + .addr_offset =3D 0x200, + .num_sensor =3D 4, + .sensor_map =3D {MT8192_TS3_0, MT8192_TS3_1, MT8192_TS3_2, MT8192_TS3_3}, + .tc_speed =3D &tc_speed_mt8192, + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT0, + .hw_reboot_trip_point =3D HW_REBOOT_TRIP_POINT, + .irq_bit =3D BIT(5), + } +}; + +static const struct lvts_tc_settings mt8192_tc_ap_settings[] =3D { + [0] =3D { + .dev_id =3D 0x84, + .addr_offset =3D 0x0, + .num_sensor =3D 2, + .sensor_map =3D {MT8192_TS4_0, MT8192_TS4_1}, + .tc_speed =3D &tc_speed_mt8192, + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT0, + .hw_reboot_trip_point =3D HW_REBOOT_TRIP_POINT, + .irq_bit =3D BIT(3), + }, + [1] =3D { + .dev_id =3D 0x85, + .addr_offset =3D 0x100, + .num_sensor =3D 2, + .sensor_map =3D {MT8192_TS5_0, MT8192_TS5_1}, + .tc_speed =3D &tc_speed_mt8192, + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT1, + .hw_reboot_trip_point =3D HW_REBOOT_TRIP_POINT, + .irq_bit =3D BIT(4), + }, + [2] =3D { + .dev_id =3D 0x86, + .addr_offset =3D 0x200, + .num_sensor =3D 2, + .sensor_map =3D {MT8192_TS6_0, MT8192_TS6_1}, + .tc_speed =3D &tc_speed_mt8192, + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT1, + .hw_reboot_trip_point =3D HW_REBOOT_TRIP_POINT, + .irq_bit =3D BIT(5), + }, + [3] =3D { + .dev_id =3D 0x87, + .addr_offset =3D 0x300, + .num_sensor =3D 3, + .sensor_map =3D {MT8192_TS7_0, MT8192_TS7_1, MT8192_TS7_2}, + .tc_speed =3D &tc_speed_mt8192, + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT2, + .hw_reboot_trip_point =3D HW_REBOOT_TRIP_POINT, + .irq_bit =3D BIT(6), + } +}; + +static const struct lvts_data mt8192_lvts_mcu_data =3D { + .num_tc =3D (ARRAY_SIZE(mt8192_tc_mcu_settings)), + .tc =3D mt8192_tc_mcu_settings, + .num_sensor =3D MT8192_NUM_TS_MCU, + .ops =3D { + .efuse_to_cal_data =3D mt8192_mcu_efuse_to_cal_data, + .device_enable_and_init =3D lvts_device_enable_and_init_v4, + .device_enable_auto_rck =3D lvts_device_enable_auto_rck_v4, + .device_read_count_rc_n =3D lvts_device_read_count_rc_n_v4, + .set_cal_data =3D lvts_set_calibration_data_v4, + .init_controller =3D lvts_init_controller_v4, + }, + .feature_bitmap =3D FEATURE_DEVICE_AUTO_RCK, + .num_efuse_addr =3D NUM_EFUSE_ADDR, + .num_efuse_block =3D NUM_EFUSE_BLOCK_MT8192, + .cal_data =3D { + .default_golden_temp =3D DEFAULT_GOLDEN_TEMP, + .default_count_r =3D DEFAULT_CUONT_R, + .default_count_rc =3D DEFAULT_CUONT_RC, + }, + .coeff =3D { + .a =3D COEFF_A, + .b =3D COEFF_B, + }, +}; + +static const struct lvts_data mt8192_lvts_ap_data =3D { + .num_tc =3D (ARRAY_SIZE(mt8192_tc_ap_settings)), + .tc =3D mt8192_tc_ap_settings, + .num_sensor =3D MT8192_NUM_TS_AP, + .ops =3D { + .efuse_to_cal_data =3D mt8192_ap_efuse_to_cal_data, + .device_enable_and_init =3D lvts_device_enable_and_init_v4, + .device_enable_auto_rck =3D lvts_device_enable_auto_rck_v4, + .device_read_count_rc_n =3D lvts_device_read_count_rc_n_v4, + .set_cal_data =3D lvts_set_calibration_data_v4, + .init_controller =3D lvts_init_controller_v4, + }, + .feature_bitmap =3D FEATURE_DEVICE_AUTO_RCK, + .num_efuse_addr =3D NUM_EFUSE_ADDR, + .num_efuse_block =3D NUM_EFUSE_BLOCK_MT8192, + .cal_data =3D { + .default_golden_temp =3D DEFAULT_GOLDEN_TEMP, + .default_count_r =3D DEFAULT_CUONT_R, + .default_count_rc =3D DEFAULT_CUONT_RC, + }, + .coeff =3D { + .a =3D COEFF_A, + .b =3D COEFF_B, + }, +}; + +static const struct of_device_id lvts_of_match[] =3D { + { .compatible =3D "mediatek,mt8192-lvts-mcu", .data =3D &mt8192_lvts_mcu_= data, }, + { .compatible =3D "mediatek,mt8192-lvts-ap", .data =3D &mt8192_lvts_ap_da= ta, }, + {}, +}; +MODULE_DEVICE_TABLE(of, lvts_of_match); + +static struct platform_driver soc_temp_lvts =3D { + .probe =3D lvts_probe, + .remove =3D lvts_remove, + .suspend =3D lvts_suspend, + .resume =3D lvts_resume, + .driver =3D { + .name =3D "mtk-soc-temp-lvts-mt8192", + .of_match_table =3D lvts_of_match, + }, +}; +module_platform_driver(soc_temp_lvts); + +MODULE_AUTHOR("Yu-Chia Chang "); +MODULE_AUTHOR("Michael Kao "); +MODULE_DESCRIPTION("MediaTek soc temperature driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/thermal/mediatek/soc_temp.c b/drivers/thermal/mediatek= /soc_temp.c index ede94eadddda..60924f8f98e9 100644 --- a/drivers/thermal/mediatek/soc_temp.c +++ b/drivers/thermal/mediatek/soc_temp.c @@ -23,7 +23,7 @@ #include #include =20 -#include "thermal_hwmon.h" +#include "../thermal_hwmon.h" =20 /* AUXADC Registers */ #define AUXADC_CON1_SET_V 0x008 diff --git a/drivers/thermal/mediatek/soc_temp_lvts.c b/drivers/thermal/med= iatek/soc_temp_lvts.c new file mode 100644 index 000000000000..ee7efc0de65f --- /dev/null +++ b/drivers/thermal/mediatek/soc_temp_lvts.c @@ -0,0 +1,928 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "soc_temp_lvts.h" + +static int lvts_raw_to_temp(struct lvts_formula_coeff *co, unsigned int ms= r_raw) +{ + /* This function returns degree mC */ + + int temp; + + temp =3D (co->a * ((unsigned long long)msr_raw)) >> 14; + temp =3D temp + co->golden_temp * 500 + co->b; + + return temp; +} + +static unsigned int lvts_temp_to_raw(struct lvts_formula_coeff *co, int te= mp) +{ + unsigned int msr_raw; + + msr_raw =3D div_s64((s64)((co->golden_temp * 500 + co->b - temp)) << 14, + (-1 * co->a)); + + return msr_raw; +} + +static int soc_temp_lvts_read_temp(void *data, int *temperature) +{ + struct soc_temp_tz *lvts_tz =3D (struct soc_temp_tz *)data; + struct lvts_data *lvts_data =3D lvts_tz->lvts_data; + unsigned int msr_raw; + + msr_raw =3D readl(lvts_data->reg[lvts_tz->id]) & MRS_RAW_MASK; + if (msr_raw =3D=3D 0) + return -EINVAL; + + *temperature =3D lvts_raw_to_temp(&lvts_data->coeff, msr_raw); + + return 0; +} + +static const struct thermal_zone_of_device_ops soc_temp_lvts_ops =3D { + .get_temp =3D soc_temp_lvts_read_temp, +}; + +static void lvts_write_device(struct lvts_data *lvts_data, unsigned int da= ta, + int tc_id) +{ + void __iomem *base =3D GET_BASE_ADDR(lvts_data, tc_id); + + writel(DEVICE_WRITE | data, LVTS_CONFIG_0 + base); + + usleep_range(5, 15); +} + +static unsigned int lvts_read_device(struct lvts_data *lvts_data, + unsigned int reg_idx, int tc_id) +{ + struct device *dev =3D lvts_data->dev; + void __iomem *base =3D GET_BASE_ADDR(lvts_data, tc_id); + unsigned int data; + int ret; + + writel(READ_DEVICE_REG(reg_idx), LVTS_CONFIG_0 + base); + + usleep_range(5, 15); + + ret =3D readl_poll_timeout(LVTS_CONFIG_0 + base, data, + !(data & DEVICE_ACCESS_STARTUS), 2, 200); + if (ret) + dev_err(dev, + "Error: LVTS %d DEVICE_ACCESS_START is not ready\n", tc_id); + + data =3D readl(LVTSRDATA0_0 + base); + + return data; +} + +static const char * const lvts_error_table[] =3D {"IDLE", "Write transacti= on", + "Waiting for read after Write", "Disable Continue fetching on Device", + "Read transaction", "Set Device special Register for Voltage threshold", + "Set TSMCU number for Fetch"}; + +static void wait_all_tc_sensing_point_idle(struct lvts_data *lvts_data) +{ + struct device *dev =3D lvts_data->dev; + unsigned int mask, error_code, is_error; + void __iomem *base; + int i, cnt, ret; + + mask =3D BIT(10) | BIT(7) | BIT(0); + + for (cnt =3D 0; cnt < 2; cnt++) { + is_error =3D 0; + for (i =3D 0; i < lvts_data->num_tc; i++) { + base =3D GET_BASE_ADDR(lvts_data, i); + ret =3D readl_poll_timeout(LVTSMSRCTL1_0 + base, error_code, + !(error_code & mask), 2, 200); + + error_code =3D ((error_code & BIT(10)) >> 8) + + ((error_code & BIT(7)) >> 6) + + (error_code & BIT(0)); + + if (ret) + dev_err(dev, "LVTS %d error: %s\n", + i, lvts_error_table[error_code]); + + if (error_code !=3D 0) + is_error =3D 1; + } + + if (is_error =3D=3D 0) + break; + } +} + +static void lvts_reset(struct lvts_data *lvts_data) +{ + if (lvts_data->reset) + reset_control_assert(lvts_data->reset); + if (lvts_data->reset) + reset_control_deassert(lvts_data->reset); +} + +static void device_identification(struct lvts_data *lvts_data) +{ + struct device *dev =3D lvts_data->dev; + unsigned int i, data; + void __iomem *base; + + for (i =3D 0; i < lvts_data->num_tc; i++) { + base =3D GET_BASE_ADDR(lvts_data, i); + + writel(ENABLE_LVTS_CTRL_CLK, LVTSCLKEN_0 + base); + lvts_write_device(lvts_data, RESET_ALL_DEVICES, i); + writel(READ_BACK_DEVICE_ID, LVTS_CONFIG_0 + base); + + usleep_range(5, 15); + + /* Check LVTS device ID */ + data =3D (readl(LVTS_ID_0 + base) & DEVICE_REG_DATA); + if (data !=3D (lvts_data->tc->dev_id + i)) + dev_err(dev, "LVTS_TC_%d, Device ID should be 0x%x, but 0x%x\n", + i, (lvts_data->tc->dev_id + i), data); + } +} + +static void disable_all_sensing_points(struct lvts_data *lvts_data) +{ + unsigned int i; + void __iomem *base; + + for (i =3D 0; i < lvts_data->num_tc; i++) { + base =3D GET_BASE_ADDR(lvts_data, i); + writel(DISABLE_SENSING_POINT, LVTSMONCTL0_0 + base); + } +} + +static void enable_all_sensing_points(struct lvts_data *lvts_data) +{ + struct device *dev =3D lvts_data->dev; + const struct lvts_tc_settings *tc =3D lvts_data->tc; + unsigned int i, num; + void __iomem *base; + + for (i =3D 0; i < lvts_data->num_tc; i++) { + base =3D GET_BASE_ADDR(lvts_data, i); + num =3D tc[i].num_sensor; + + if (num > ALL_SENSING_POINTS) { + dev_err(dev, + "%s, LVTS%d, illegal number of sensors: %d\n", + __func__, i, tc[i].num_sensor); + continue; + } + + writel(ENABLE_SENSING_POINT(num), LVTSMONCTL0_0 + base); + } +} + +static void set_polling_speed(struct lvts_data *lvts_data, int tc_id) +{ + struct device *dev =3D lvts_data->dev; + const struct lvts_tc_settings *tc =3D lvts_data->tc; + unsigned int lvts_mon_ctl_1, lvts_mon_ctl_2; + void __iomem *base; + + base =3D GET_BASE_ADDR(lvts_data, tc_id); + + lvts_mon_ctl_1 =3D ((tc[tc_id].tc_speed->group_interval_delay << 20) & GE= NMASK(29, 20)) | + (tc[tc_id].tc_speed->period_unit & GENMASK(9, 0)); + lvts_mon_ctl_2 =3D ((tc[tc_id].tc_speed->filter_interval_delay << 16) & G= ENMASK(25, 16)) | + (tc[tc_id].tc_speed->sensor_interval_delay & GENMASK(9, 0)); + /* + * Clock source of LVTS thermal controller is 26MHz. + * Period unit is a base for all interval delays + * All interval delays must multiply it to convert a setting to time. + * Filter interval delay is a delay between two samples of the same sensor + * Sensor interval delay is a delay between two samples of differnet sens= ors + * Group interval delay is a delay between different rounds. + * For example: + * If Period unit =3D C, filter delay =3D 1, sensor delay =3D 2, grou= p delay =3D 1, + * and two sensors, TS1 and TS2, are in a LVTS thermal controller + * and then + * Period unit =3D C * 1/26M * 256 =3D 12 * 38.46ns * 256 =3D 118.149= us + * Filter interval delay =3D 1 * Period unit =3D 118.149us + * Sensor interval delay =3D 2 * Period unit =3D 236.298us + * Group interval delay =3D 1 * Period unit =3D 118.149us + * + * TS1 TS1 ... TS1 TS2 TS2 ... TS2 TS1... + * <--> Filter interval delay + * <--> Sensor interval delay + * <--> Group interval delay + */ + writel(lvts_mon_ctl_1, LVTSMONCTL1_0 + base); + writel(lvts_mon_ctl_2, LVTSMONCTL2_0 + base); + + dev_dbg(dev, "LVTS_TC_%d, LVTSMONCTL1_0=3D 0x%x, LVTSMONCTL2_0=3D 0x%x\n", + tc_id, readl(LVTSMONCTL1_0 + base), + readl(LVTSMONCTL2_0 + base)); +} + +static void set_hw_filter(struct lvts_data *lvts_data, int tc_id) +{ + struct device *dev =3D lvts_data->dev; + const struct lvts_tc_settings *tc =3D lvts_data->tc; + unsigned int option; + void __iomem *base; + + base =3D GET_BASE_ADDR(lvts_data, tc_id); + option =3D tc[tc_id].hw_filter & 0x7; + /* + * hw filter + * 000: Get one sample + * 001: Get 2 samples and average them + * 010: Get 4 samples, drop max and min, then average the rest of 2 sampl= es + * 011: Get 6 samples, drop max and min, then average the rest of 4 sampl= es + * 100: Get 10 samples, drop max and min, then average the rest of 8 samp= les + * 101: Get 18 samples, drop max and min, then average the rest of 16 sam= ples + */ + option =3D (option << 9) | (option << 6) | (option << 3) | option; + + writel(option, LVTSMSRCTL0_0 + base); + dev_dbg(dev, "LVTS_TC_%d, LVTSMSRCTL0_0=3D 0x%x\n", + tc_id, readl(LVTSMSRCTL0_0 + base)); +} + +static int get_dominator_index(struct lvts_data *lvts_data, int tc_id) +{ + struct device *dev =3D lvts_data->dev; + const struct lvts_tc_settings *tc =3D lvts_data->tc; + int d_index; + + if (tc[tc_id].dominator_sensing_point =3D=3D ALL_SENSING_POINTS) { + d_index =3D ALL_SENSING_POINTS; + } else if (tc[tc_id].dominator_sensing_point < + tc[tc_id].num_sensor){ + d_index =3D tc[tc_id].dominator_sensing_point; + } else { + dev_err(dev, + "Error: LVTS%d, dominator_sensing_point=3D %d should smaller than num_s= ensor=3D %d\n", + tc_id, tc[tc_id].dominator_sensing_point, + tc[tc_id].num_sensor); + + dev_err(dev, "Use the sensing point 0 as the dominated sensor\n"); + d_index =3D SENSING_POINT0; + } + + return d_index; +} + +static void disable_hw_reboot_interrupt(struct lvts_data *lvts_data, int t= c_id) +{ + unsigned int temp; + void __iomem *base; + + base =3D GET_BASE_ADDR(lvts_data, tc_id); + + /* + * LVTS thermal controller has two interrupts for thermal HW reboot + * One is for AP SW and the other is for RGU + * The interrupt of AP SW can turn off by a bit of a register, but + * the other for RGU cannot. + * To prevent rebooting device accidentally, we are going to add + * a huge offset to LVTS and make LVTS always report extremely low + * temperature. + */ + + /* + * After adding the huge offset 0x3FFF, LVTS alawys adds the + * offset to MSR_RAW. + * When MSR_RAW is larger, SW will convert lower temperature/ + */ + temp =3D readl(LVTSPROTCTL_0 + base); + writel(temp | 0x3FFF, LVTSPROTCTL_0 + base); + + /* Disable the interrupt of AP SW */ + temp =3D readl(LVTSMONINT_0 + base); + writel(temp & ~(STAGE3_INT_EN), LVTSMONINT_0 + base); +} + +static void enable_hw_reboot_interrupt(struct lvts_data *lvts_data, int tc= _id) +{ + unsigned int temp; + void __iomem *base; + + base =3D GET_BASE_ADDR(lvts_data, tc_id); + + /* Enable the interrupt of AP SW */ + temp =3D readl(LVTSMONINT_0 + base); + writel(temp | STAGE3_INT_EN, LVTSMONINT_0 + base); + /* Clear the offset */ + temp =3D readl(LVTSPROTCTL_0 + base); + writel(temp & ~PROTOFFSET, LVTSPROTCTL_0 + base); +} + +static void set_tc_hw_reboot_threshold(struct lvts_data *lvts_data, + int trip_point, int tc_id) +{ + struct device *dev =3D lvts_data->dev; + unsigned int msr_raw, temp, config, d_index; + void __iomem *base; + + base =3D GET_BASE_ADDR(lvts_data, tc_id); + d_index =3D get_dominator_index(lvts_data, tc_id); + + dev_info(dev, "lvts_tc_%d: dominator sensing point =3D %d\n", tc_id, d_in= dex); + + disable_hw_reboot_interrupt(lvts_data, tc_id); + + temp =3D readl(LVTSPROTCTL_0 + base); + if (d_index =3D=3D ALL_SENSING_POINTS) { + /* Maximum of 4 sensing points */ + config =3D (0x1 << 16); + writel(config | temp, LVTSPROTCTL_0 + base); + } else { + /* Select protection sensor */ + config =3D ((d_index << 2) + 0x2) << 16; + writel(config | temp, LVTSPROTCTL_0 + base); + } + + msr_raw =3D lvts_temp_to_raw(&lvts_data->coeff, trip_point); + writel(msr_raw, LVTSPROTTC_0 + base); + + enable_hw_reboot_interrupt(lvts_data, tc_id); +} + +static void set_all_tc_hw_reboot(struct lvts_data *lvts_data) +{ + const struct lvts_tc_settings *tc =3D lvts_data->tc; + int i, trip_point; + + for (i =3D 0; i < lvts_data->num_tc; i++) { + trip_point =3D tc[i].hw_reboot_trip_point; + + if (tc[i].num_sensor =3D=3D 0) + continue; + + if (trip_point =3D=3D THERMAL_TEMP_INVALID) + continue; + + set_tc_hw_reboot_threshold(lvts_data, trip_point, i); + } +} + +static int lvts_init(struct lvts_data *lvts_data) +{ + struct platform_ops *ops =3D &lvts_data->ops; + struct device *dev =3D lvts_data->dev; + int ret; + + ret =3D clk_prepare_enable(lvts_data->clk); + if (ret) { + dev_err(dev, + "Error: Failed to enable lvts controller clock: %d\n", + ret); + return ret; + } + + lvts_reset(lvts_data); + + device_identification(lvts_data); + if (ops->device_enable_and_init) + ops->device_enable_and_init(lvts_data); + + if (HAS_FEATURE(lvts_data, FEATURE_DEVICE_AUTO_RCK)) { + if (ops->device_enable_auto_rck) + ops->device_enable_auto_rck(lvts_data); + } else { + if (ops->device_read_count_rc_n) + ops->device_read_count_rc_n(lvts_data); + } + + if (ops->set_cal_data) + ops->set_cal_data(lvts_data); + + disable_all_sensing_points(lvts_data); + wait_all_tc_sensing_point_idle(lvts_data); + if (ops->init_controller) + ops->init_controller(lvts_data); + enable_all_sensing_points(lvts_data); + + set_all_tc_hw_reboot(lvts_data); + + return 0; +} + +static int prepare_calibration_data(struct lvts_data *lvts_data) +{ + struct device *dev =3D lvts_data->dev; + struct lvts_sensor_cal_data *cal_data =3D &lvts_data->cal_data; + struct platform_ops *ops =3D &lvts_data->ops; + int i, offset; + char buffer[512]; + + cal_data->count_r =3D devm_kcalloc(dev, lvts_data->num_sensor, + sizeof(*cal_data->count_r), GFP_KERNEL); + if (!cal_data->count_r) + return -ENOMEM; + + cal_data->count_rc =3D devm_kcalloc(dev, lvts_data->num_sensor, + sizeof(*cal_data->count_rc), GFP_KERNEL); + if (!cal_data->count_rc) + return -ENOMEM; + + if (ops->efuse_to_cal_data && !cal_data->use_fake_efuse) + ops->efuse_to_cal_data(lvts_data); + if (cal_data->golden_temp =3D=3D 0 || cal_data->golden_temp > GOLDEN_TEMP= _MAX) + cal_data->use_fake_efuse =3D 1; + + if (cal_data->use_fake_efuse) { + /* It means all efuse data are equal to 0 */ + dev_err(dev, + "%s: This sample is not calibrated, fake !!\n", __func__); + + cal_data->golden_temp =3D cal_data->default_golden_temp; + for (i =3D 0; i < lvts_data->num_sensor; i++) { + cal_data->count_r[i] =3D cal_data->default_count_r; + cal_data->count_rc[i] =3D cal_data->default_count_rc; + } + } + + lvts_data->coeff.golden_temp =3D cal_data->golden_temp; + + dev_dbg(dev, "golden_temp =3D %d\n", cal_data->golden_temp); + + offset =3D snprintf(buffer, sizeof(buffer), "[lvts_cal] num:g_count:g_cou= nt_rc "); + for (i =3D 0; i < lvts_data->num_sensor; i++) + offset +=3D snprintf(buffer + offset, sizeof(buffer) - offset, "%d:%d:%d= ", + i, cal_data->count_r[i], cal_data->count_rc[i]); + + buffer[offset] =3D '\0'; + + return 0; +} + +static int get_calibration_data(struct lvts_data *lvts_data) +{ + struct device *dev =3D lvts_data->dev; + char cell_name[32]; + struct nvmem_cell *cell; + u32 *buf; + size_t len; + int i, j, index =3D 0, ret; + + lvts_data->efuse =3D devm_kcalloc(dev, lvts_data->num_efuse_addr, + sizeof(*lvts_data->efuse), GFP_KERNEL); + if (!lvts_data->efuse) + return -ENOMEM; + + for (i =3D 0; i < lvts_data->num_efuse_block; i++) { + snprintf(cell_name, sizeof(cell_name), "lvts_calib_data%d", i + 1); + cell =3D nvmem_cell_get(dev, cell_name); + if (IS_ERR(cell)) { + dev_err(dev, "Error: Failed to get nvmem cell %s\n", cell_name); + return PTR_ERR(cell); + } + + buf =3D (u32 *)nvmem_cell_read(cell, &len); + nvmem_cell_put(cell); + + if (IS_ERR(buf)) + return PTR_ERR(buf); + + for (j =3D 0; j < (len / sizeof(u32)); j++) { + if (index >=3D lvts_data->num_efuse_addr) { + dev_err(dev, "Array efuse is going to overflow"); + kfree(buf); + return -EINVAL; + } + + lvts_data->efuse[index] =3D buf[j]; + index++; + } + + kfree(buf); + } + + ret =3D prepare_calibration_data(lvts_data); + + return ret; +} + +static int lvts_init_tc_regs(struct device *dev, struct lvts_data *lvts_da= ta) +{ + const struct lvts_tc_settings *tc =3D lvts_data->tc; + unsigned int i, j, s_index; + void __iomem *base; + + lvts_data->reg =3D devm_kcalloc(dev, lvts_data->num_sensor, + sizeof(*lvts_data->reg), GFP_KERNEL); + if (!lvts_data->reg) + return -ENOMEM; + + for (i =3D 0; i < lvts_data->num_tc; i++) { + base =3D GET_BASE_ADDR(lvts_data, i); + for (j =3D 0; j < tc[i].num_sensor; j++) { + s_index =3D tc[i].sensor_map[j]; + lvts_data->reg[s_index] =3D LVTSMSR0_0 + base + 0x4 * j; + } + } + + return 0; +} + +static int of_update_lvts_data(struct lvts_data *lvts_data, + struct platform_device *pdev) +{ + struct device *dev =3D lvts_data->dev; + struct resource *res; + int ret; + + lvts_data->clk =3D devm_clk_get(dev, NULL); + if (IS_ERR(lvts_data->clk)) + return PTR_ERR(lvts_data->clk); + + /* Get base address */ + res =3D platform_get_mem_or_io(pdev, 0); + if (!res) { + dev_err(dev, "No IO resource\n"); + return -ENXIO; + } + + lvts_data->base =3D devm_ioremap_resource(dev, res); + if (IS_ERR(lvts_data->base)) { + dev_err(dev, "Failed to remap io\n"); + return PTR_ERR(lvts_data->base); + } + + /* Get interrupt number */ + ret =3D platform_get_irq(pdev, 0); + if (ret < 0) { + dev_err(dev, "No irq resource\n"); + return -EINVAL; + } + lvts_data->irq_num =3D ret; + + /* Get reset control */ + lvts_data->reset =3D devm_reset_control_get_by_index(dev, 0); + if (IS_ERR(lvts_data->reset)) { + dev_err(dev, "Failed to get reset control\n"); + return PTR_ERR(lvts_data->reset); + } + + ret =3D lvts_init_tc_regs(dev, lvts_data); + if (ret) + return ret; + + ret =3D get_calibration_data(lvts_data); + if (ret) + return ret; + + return 0; +} + +static void lvts_device_close(struct lvts_data *lvts_data) +{ + unsigned int i; + void __iomem *base; + + for (i =3D 0; i < lvts_data->num_tc; i++) { + base =3D GET_BASE_ADDR(lvts_data, i); + lvts_write_device(lvts_data, RESET_ALL_DEVICES, i); + writel(DISABLE_LVTS_CTRL_CLK, LVTSCLKEN_0 + base); + } +} + +static void lvts_close(struct lvts_data *lvts_data) +{ + disable_all_sensing_points(lvts_data); + wait_all_tc_sensing_point_idle(lvts_data); + lvts_device_close(lvts_data); + clk_disable_unprepare(lvts_data->clk); +} + +static void tc_irq_handler(struct lvts_data *lvts_data, int tc_id) +{ + const struct device *dev =3D lvts_data->dev; + unsigned int ret =3D 0; + void __iomem *base; + + base =3D GET_BASE_ADDR(lvts_data, tc_id); + + ret =3D readl(LVTSMONINTSTS_0 + base); + /* Write back to clear interrupt status */ + writel(ret, LVTSMONINTSTS_0 + base); + + dev_dbg(dev, "LVTS thermal controller %d, LVTSMONINTSTS=3D0x%08x\n", tc_i= d, ret); + + if (ret & THERMAL_PROTECTION_STAGE_3) + dev_dbg(dev, "Thermal protection stage 3 interrupt triggered\n"); +} + +static irqreturn_t irq_handler(int irq, void *dev_id) +{ + struct lvts_data *lvts_data =3D (struct lvts_data *)dev_id; + struct device *dev =3D lvts_data->dev; + const struct lvts_tc_settings *tc =3D lvts_data->tc; + unsigned int i, *irq_bitmap; + void __iomem *base; + + irq_bitmap =3D kcalloc(1, sizeof(*irq_bitmap), GFP_ATOMIC); + + if (!irq_bitmap) + return IRQ_NONE; + + base =3D lvts_data->base; + *irq_bitmap =3D readl(THERMINTST + base); + dev_dbg(dev, "THERMINTST =3D 0x%x\n", *irq_bitmap); + + for (i =3D 0; i < lvts_data->num_tc; i++) { + if (tc[i].irq_bit =3D=3D 0) + tc_irq_handler(lvts_data, i); + } + + kfree(irq_bitmap); + + return IRQ_HANDLED; +} + +static int lvts_register_irq_handler(struct lvts_data *lvts_data) +{ + struct device *dev =3D lvts_data->dev; + int ret; + + ret =3D devm_request_irq(dev, lvts_data->irq_num, irq_handler, + IRQF_TRIGGER_HIGH, "mtk_lvts", lvts_data); + + if (ret) { + dev_err(dev, "Failed to register LVTS IRQ, ret %d, irq_num %d\n", + ret, lvts_data->irq_num); + lvts_close(lvts_data); + return ret; + } + + return 0; +} + +static int lvts_register_thermal_zones(struct lvts_data *lvts_data) +{ + struct device *dev =3D lvts_data->dev; + struct thermal_zone_device *tzdev; + struct soc_temp_tz *lvts_tz; + int i, ret; + + for (i =3D 0; i < lvts_data->num_sensor; i++) { + lvts_tz =3D devm_kzalloc(dev, sizeof(*lvts_tz), GFP_KERNEL); + if (!lvts_tz) { + lvts_close(lvts_data); + return -ENOMEM; + } + + lvts_tz->id =3D i; + lvts_tz->lvts_data =3D lvts_data; + + tzdev =3D devm_thermal_zone_of_sensor_register(dev, lvts_tz->id, + lvts_tz, &soc_temp_lvts_ops); + + if (IS_ERR(tzdev)) { + if (lvts_tz->id !=3D 0) + return 0; + + ret =3D PTR_ERR(tzdev); + dev_err(dev, "Error: Failed to register lvts tz %d, ret =3D %d\n", + lvts_tz->id, ret); + lvts_close(lvts_data); + return ret; + } + } + + return 0; +} + +void lvts_device_enable_and_init_v4(struct lvts_data *lvts_data) +{ + unsigned int i; + + for (i =3D 0; i < lvts_data->num_tc; i++) { + lvts_write_device(lvts_data, STOP_COUNTING_V4, i); + lvts_write_device(lvts_data, SET_RG_TSFM_LPDLY_V4, i); + lvts_write_device(lvts_data, SET_COUNTING_WINDOW_20US1_V4, i); + lvts_write_device(lvts_data, SET_COUNTING_WINDOW_20US2_V4, i); + lvts_write_device(lvts_data, TSV2F_CHOP_CKSEL_AND_TSV2F_EN_V4, i); + lvts_write_device(lvts_data, TSBG_DEM_CKSEL_X_TSBG_CHOP_EN_V4, i); + lvts_write_device(lvts_data, SET_TS_RSV_V4, i); + lvts_write_device(lvts_data, SET_TS_EN_V4, i); + lvts_write_device(lvts_data, TOGGLE_RG_TSV2F_VCO_RST1_V4, i); + lvts_write_device(lvts_data, TOGGLE_RG_TSV2F_VCO_RST2_V4, i); + } + + lvts_data->counting_window_us =3D 20; +} +EXPORT_SYMBOL_GPL(lvts_device_enable_and_init_v4); + +void lvts_device_enable_auto_rck_v4(struct lvts_data *lvts_data) +{ + unsigned int i; + + for (i =3D 0; i < lvts_data->num_tc; i++) + lvts_write_device(lvts_data, SET_LVTS_AUTO_RCK_V4, i); +} +EXPORT_SYMBOL_GPL(lvts_device_enable_auto_rck_v4); + +int lvts_device_read_count_rc_n_v4(struct lvts_data *lvts_data) +{ + /* Resistor-Capacitor Calibration */ + /* count_RC_N: count RC now */ + struct device *dev =3D lvts_data->dev; + const struct lvts_tc_settings *tc =3D lvts_data->tc; + struct lvts_sensor_cal_data *cal_data =3D &lvts_data->cal_data; + unsigned int offset, size, s_index, data; + void __iomem *base; + int ret, i, j; + char buffer[512]; + + cal_data->count_rc_now =3D devm_kcalloc(dev, lvts_data->num_sensor, + sizeof(*cal_data->count_rc_now), GFP_KERNEL); + if (!cal_data->count_rc_now) + return -ENOMEM; + + for (i =3D 0; i < lvts_data->num_tc; i++) { + base =3D GET_BASE_ADDR(lvts_data, i); + for (j =3D 0; j < tc[i].num_sensor; j++) { + s_index =3D tc[i].sensor_map[j]; + + lvts_write_device(lvts_data, SELECT_SENSOR_RCK_V4(j), i); + lvts_write_device(lvts_data, SET_DEVICE_SINGLE_MODE_V4, i); + usleep_range(10, 20); + + lvts_write_device(lvts_data, KICK_OFF_RCK_COUNTING_V4, i); + usleep_range(30, 40); + + ret =3D readl_poll_timeout(LVTS_CONFIG_0 + base, data, + !(data & DEVICE_SENSING_STATUS), 2, 200); + if (ret) + dev_err(dev, + "Error: LVTS %d DEVICE_SENSING_STATUS didn't ready\n", i); + + data =3D lvts_read_device(lvts_data, 0x00, i); + + cal_data->count_rc_now[s_index] =3D (data & GENMASK(23, 0)); + } + + /* Recover Setting for Normal Access on + * temperature fetch + */ + lvts_write_device(lvts_data, SET_SENSOR_NO_RCK_V4, i); + lvts_write_device(lvts_data, SET_DEVICE_LOW_POWER_SINGLE_MODE_V4, i); + } + + size =3D sizeof(buffer); + offset =3D snprintf(buffer, size, "[COUNT_RC_NOW] "); + for (i =3D 0; i < lvts_data->num_sensor; i++) + offset +=3D snprintf(buffer + offset, size - offset, "%d:%d ", + i, cal_data->count_rc_now[i]); + + buffer[offset] =3D '\0'; + dev_dbg(dev, "%s\n", buffer); + + return 0; +} +EXPORT_SYMBOL_GPL(lvts_device_read_count_rc_n_v4); + +void lvts_set_calibration_data_v4(struct lvts_data *lvts_data) +{ + const struct lvts_tc_settings *tc =3D lvts_data->tc; + struct lvts_sensor_cal_data *cal_data =3D &lvts_data->cal_data; + unsigned int i, j, s_index, lvts_calib_data; + void __iomem *base; + + for (i =3D 0; i < lvts_data->num_tc; i++) { + base =3D GET_BASE_ADDR(lvts_data, i); + + for (j =3D 0; j < tc[i].num_sensor; j++) { + s_index =3D tc[i].sensor_map[j]; + if (HAS_FEATURE(lvts_data, FEATURE_DEVICE_AUTO_RCK)) + lvts_calib_data =3D cal_data->count_r[s_index]; + else + lvts_calib_data =3D (((unsigned long long) + cal_data->count_rc_now[s_index]) * + cal_data->count_r[s_index]) >> 14; + + writel(lvts_calib_data, LVTSEDATA00_0 + base + 0x4 * j); + } + } +} +EXPORT_SYMBOL_GPL(lvts_set_calibration_data_v4); + +void lvts_init_controller_v4(struct lvts_data *lvts_data) +{ + struct device *dev =3D lvts_data->dev; + unsigned int i; + void __iomem *base; + + for (i =3D 0; i < lvts_data->num_tc; i++) { + base =3D GET_BASE_ADDR(lvts_data, i); + + lvts_write_device(lvts_data, SET_DEVICE_LOW_POWER_SINGLE_MODE_V4, i); + + writel(SET_SENSOR_INDEX, LVTSTSSEL_0 + base); + writel(SET_CALC_SCALE_RULES, LVTSCALSCALE_0 + base); + + set_polling_speed(lvts_data, i); + set_hw_filter(lvts_data, i); + + dev_info(dev, "lvts_tc_%d: read all %d sensors in %d us, one in %d us\n", + i, GET_TC_SENSOR_NUM(lvts_data, i), GROUP_LATENCY_US(i), SENSOR_LATENCY= _US(i)); + } +} +EXPORT_SYMBOL_GPL(lvts_init_controller_v4); + +int lvts_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct lvts_data *lvts_data; + int ret; + + lvts_data =3D (struct lvts_data *)of_device_get_match_data(dev); + + if (!lvts_data) { + dev_err(dev, "Error: Failed to get lvts platform data\n"); + return -ENODATA; + } + + lvts_data->dev =3D &pdev->dev; + + ret =3D of_update_lvts_data(lvts_data, pdev); + if (ret) + return ret; + + platform_set_drvdata(pdev, lvts_data); + + ret =3D lvts_init(lvts_data); + if (ret) + return ret; + + ret =3D lvts_register_irq_handler(lvts_data); + if (ret) + return ret; + + ret =3D lvts_register_thermal_zones(lvts_data); + if (ret) + return ret; + + return 0; +} + +int lvts_remove(struct platform_device *pdev) +{ + struct lvts_data *lvts_data; + + lvts_data =3D (struct lvts_data *)platform_get_drvdata(pdev); + + lvts_close(lvts_data); + + return 0; +} + +int lvts_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct lvts_data *lvts_data; + + lvts_data =3D (struct lvts_data *)platform_get_drvdata(pdev); + + lvts_close(lvts_data); + + return 0; +} + +int lvts_resume(struct platform_device *pdev) +{ + int ret; + struct lvts_data *lvts_data; + + lvts_data =3D (struct lvts_data *)platform_get_drvdata(pdev); + + ret =3D lvts_init(lvts_data); + if (ret) + return ret; + + return 0; +} + +MODULE_AUTHOR("Yu-Chia Chang "); +MODULE_AUTHOR("Michael Kao "); +MODULE_DESCRIPTION("MediaTek soc temperature driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/thermal/mediatek/soc_temp_lvts.h b/drivers/thermal/med= iatek/soc_temp_lvts.h new file mode 100644 index 000000000000..6f8b6e3af98c --- /dev/null +++ b/drivers/thermal/mediatek/soc_temp_lvts.h @@ -0,0 +1,365 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 MediaTek Inc. + */ + +#ifndef __MTK_SOC_TEMP_LVTS_H__ +#define __MTK_SOC_TEMP_LVTS_H__ + +#define PERIOD_UNIT 12 +#define GROUP_INTERVAL_DELAY 1 +#define FILTER_INTERVAL_DELAY 1 +#define SENSOR_INTERVAL_DELAY 1 + +#define HW_REBOOT_TRIP_POINT 117000 + +#define FEATURE_DEVICE_AUTO_RCK BIT(0) +#define NUM_EFUSE_ADDR 22 +#define NUM_EFUSE_BLOCK_MT8192 1 +#define DEFAULT_GOLDEN_TEMP 50 +#define DEFAULT_CUONT_R 35000 +#define DEFAULT_CUONT_RC 2750 +#define COEFF_A -250460 +#define COEFF_B 250460 + +#define CLOCK_26MHZ_CYCLE_NS 38 +#define BUS_ACCESS_US 2 +#define GOLDEN_TEMP_MAX 62 + +/* LVTS device register */ +#define RG_TSFM_DATA_0 0x00 +#define RG_TSFM_DATA_1 0x01 +#define RG_TSFM_DATA_2 0x02 +#define RG_TSFM_CTRL_0 0x03 +#define RG_TSFM_CTRL_1 0x04 +#define RG_TSFM_CTRL_2 0x05 +#define RG_TSFM_CTRL_3 0x06 +#define RG_TSFM_CTRL_4 0x07 +#define RG_TSV2F_CTRL_0 0x08 +#define RG_TSV2F_CTRL_1 0x09 +#define RG_TSV2F_CTRL_2 0x0A +#define RG_TSV2F_CTRL_3 0x0B +#define RG_TSV2F_CTRL_4 0x0C +#define RG_TSV2F_CTRL_5 0x0D +#define RG_TSV2F_CTRL_6 0x0E +#define RG_TEMP_DATA_0 0x10 +#define RG_TEMP_DATA_1 0x11 +#define RG_TEMP_DATA_2 0x12 +#define RG_TEMP_DATA_3 0x13 +#define RG_RC_DATA_0 0x14 +#define RG_RC_DATA_1 0x15 +#define RG_RC_DATA_2 0x16 +#define RG_RC_DATA_3 0x17 +#define RG_DIV_DATA_0 0x18 +#define RG_DIV_DATA_1 0x19 +#define RG_DIV_DATA_2 0x1A +#define RG_DIV_DATA_3 0x1B +#define RG_TST_DATA_0 0x70 +#define RG_TST_DATA_1 0x71 +#define RG_TST_DATA_2 0x72 +#define RG_TST_CTRL 0x73 +#define RG_DBG_FQMTR 0xF0 +#define RG_DBG_LPSEQ 0xF1 +#define RG_DBG_STATE 0xF2 +#define RG_DBG_CHKSUM 0xF3 +#define RG_DID_LVTS 0xFC +#define RG_DID_REV 0xFD +#define RG_TSFM_RST 0xFF + +/* LVTS controller register */ +#define LVTSMONCTL0_0 0x000 +#define ENABLE_SENSING_POINT(num) (LVTS_SINGLE_SENSE | GENMASK(((num) - 1)= , 0)) +#define DISABLE_SENSING_POINT (LVTS_SINGLE_SENSE | 0x0) +#define LVTSMONCTL1_0 0x004 +#define LVTSMONCTL2_0 0x008 +#define LVTSMONINT_0 0x00C +#define STAGE3_INT_EN BIT(31) +#define LVTSMONINTSTS_0 0x010 +#define LVTSMONIDET0_0 0x014 +#define LVTSMONIDET1_0 0x018 +#define LVTSMONIDET2_0 0x01C +#define LVTSMONIDET3_0 0x020 +#define LVTSH2NTHRE_0 0x024 +#define LVTSHTHRE_0 0x028 +#define LVTSCTHRE_0 0x02C +#define LVTSOFFSETH_0 0x030 +#define LVTSOFFSETL_0 0x034 +#define LVTSMSRCTL0_0 0x038 +#define LVTSMSRCTL1_0 0x03C +#define LVTSTSSEL_0 0x040 +#define SET_SENSOR_INDEX 0x13121110 +#define LVTSDEVICETO_0 0x044 +#define LVTSCALSCALE_0 0x048 +#define SET_CALC_SCALE_RULES 0x00000300 +#define LVTS_ID_0 0x04C +#define LVTS_CONFIG_0 0x050 + +#define SCK_ONLY BIT(31) +#define BROADCAST_ID_UPDATE BIT(26) +#define DEVICE_SENSING_STATUS BIT(25) +#define DEVICE_ACCESS_STARTUS BIT(24) +#define READ_32BIT_ACCESS BIT(17) +#define WRITE_ACCESS BIT(16) +#define LVTS_SINGLE_SENSE BIT(9) +#define FEATURE_CK26M_ACTIVE BIT(1) +#define DEVICE_REG_DATA GENMASK(7, 0) + +#define LVTSEDATA00_0 0x054 +#define LVTSEDATA01_0 0x058 +#define LVTSEDATA02_0 0x05C +#define LVTSEDATA03_0 0x060 +#define LVTSMSR0_0 0x090 +#define MRS_RAW_MASK GENMASK(15, 0) +#define MRS_RAW_VALID_BIT BIT(16) +#define LVTSMSR1_0 0x094 +#define LVTSMSR2_0 0x098 +#define LVTSMSR3_0 0x09C +#define LVTSIMMD0_0 0x0A0 +#define LVTSIMMD1_0 0x0A4 +#define LVTSIMMD2_0 0x0A8 +#define LVTSIMMD3_0 0x0AC +#define LVTSRDATA0_0 0x0B0 +#define LVTSRDATA1_0 0x0B4 +#define LVTSRDATA2_0 0x0B8 +#define LVTSRDATA3_0 0x0BC +#define LVTSPROTCTL_0 0x0C0 +#define PROTOFFSET GENMASK(15, 0) +#define LVTSPROTTA_0 0x0C4 +#define LVTSPROTTB_0 0x0C8 +#define LVTSPROTTC_0 0x0CC +#define LVTSCLKEN_0 0x0E4 +#define ENABLE_LVTS_CTRL_CLK (1) +#define DISABLE_LVTS_CTRL_CLK (0) +#define LVTSDBGSEL_0 0x0E8 +#define LVTSDBGSIG_0 0x0EC +#define LVTSSPARE0_0 0x0F0 +#define LVTSSPARE1_0 0x0F4 +#define LVTSSPARE2_0 0x0F8 +#define LVTSSPARE3_0 0x0FC +#define THERMINTST 0xF04 + +/* LVTS register mask */ +#define THERMAL_COLD_INTERRUPT_0 BIT(0) +#define THERMAL_HOT_INTERRUPT_0 BIT(1) +#define THERMAL_LOW_OFFSET_INTERRUPT_0 BIT(2) +#define THERMAL_HIGH_OFFSET_INTERRUPT_0 BIT(3) +#define THERMAL_HOT2NORMAL_INTERRUPT_0 BIT(4) +#define THERMAL_COLD_INTERRUPT_1 BIT(5) +#define THERMAL_HOT_INTERRUPT_1 BIT(6) +#define THERMAL_LOW_OFFSET_INTERRUPT_1 BIT(7) +#define THERMAL_HIGH_OFFSET_INTERRUPT_1 BIT(8) +#define THERMAL_HOT2NORMAL_INTERRUPT_1 BIT(9) +#define THERMAL_COLD_INTERRUPT_2 BIT(10) +#define THERMAL_HOT_INTERRUPT_2 BIT(11) +#define THERMAL_LOW_OFFSET_INTERRUPT_2 BIT(12) +#define THERMAL_HIGH_OFFSET_INTERRUPT_2 BIT(13) +#define THERMAL_HOT2NORMAL_INTERRUPT_2 BIT(14) +#define THERMAL_AHB_TIMEOUT_INTERRUPT BIT(15) +#define THERMAL_DEVICE_TIMEOUT_INTERRUPT BIT(15) +#define THERMAL_IMMEDIATE_INTERRUPT_0 BIT(16) +#define THERMAL_IMMEDIATE_INTERRUPT_1 BIT(17) +#define THERMAL_IMMEDIATE_INTERRUPT_2 BIT(18) +#define THERMAL_FILTER_INTERRUPT_0 BIT(19) +#define THERMAL_FILTER_INTERRUPT_1 BIT(20) +#define THERMAL_FILTER_INTERRUPT_2 BIT(21) +#define THERMAL_COLD_INTERRUPT_3 BIT(22) +#define THERMAL_HOT_INTERRUPT_3 BIT(23) +#define THERMAL_LOW_OFFSET_INTERRUPT_3 BIT(24) +#define THERMAL_HIGH_OFFSET_INTERRUPT_3 BIT(25) +#define THERMAL_HOT2NORMAL_INTERRUPT_3 BIT(26) +#define THERMAL_IMMEDIATE_INTERRUPT_3 BIT(27) +#define THERMAL_FILTER_INTERRUPT_3 BIT(28) +#define THERMAL_PROTECTION_STAGE_1 BIT(29) +#define THERMAL_PROTECTION_STAGE_2 BIT(30) +#define THERMAL_PROTECTION_STAGE_3 BIT(31) + +#define CFG_REGISTER(reg, value) (reg << 8 | value) +#define STOP_COUNTING_V4 CFG_REGISTER(RG_TSFM_CTRL_0, 0x00) +#define SET_RG_TSFM_LPDLY_V4 CFG_REGISTER(RG_TSFM_CTRL_4, 0xA6) +#define SET_COUNTING_WINDOW_20US1_V4 CFG_REGISTER(RG_TSFM_CTRL_2, 0x00) +#define SET_COUNTING_WINDOW_20US2_V4 CFG_REGISTER(RG_TSFM_CTRL_1, 0x20) +#define TSV2F_CHOP_CKSEL_AND_TSV2F_EN_V4 CFG_REGISTER(RG_TSV2F_CTRL_2, 0x8= 4) +#define TSBG_DEM_CKSEL_X_TSBG_CHOP_EN_V4 CFG_REGISTER(RG_TSV2F_CTRL_4, 0x7= C) +#define SET_TS_RSV_V4 CFG_REGISTER(RG_TSV2F_CTRL_1, 0x8D) +#define SET_TS_EN_V4 CFG_REGISTER(RG_TSV2F_CTRL_0, 0xF4) +#define TOGGLE_RG_TSV2F_VCO_RST1_V4 CFG_REGISTER(RG_TSV2F_CTRL_0, 0xFC) +#define TOGGLE_RG_TSV2F_VCO_RST2_V4 CFG_REGISTER(RG_TSV2F_CTRL_0, 0xF4) + +#define SET_LVTS_AUTO_RCK_V4 CFG_REGISTER(RG_TSV2F_CTRL_6, 0x01) +#define SELECT_SENSOR_RCK_V4(id) CFG_REGISTER(RG_TSV2F_CTRL_5, (id)) +#define SET_DEVICE_SINGLE_MODE_V4 CFG_REGISTER(RG_TSFM_CTRL_3, 0x78) +#define KICK_OFF_RCK_COUNTING_V4 CFG_REGISTER(RG_TSFM_CTRL_0, 0x02) +#define SET_SENSOR_NO_RCK_V4 CFG_REGISTER(RG_TSV2F_CTRL_5, 0x10) +#define SET_DEVICE_LOW_POWER_SINGLE_MODE_V4 CFG_REGISTER(RG_TSFM_CTRL_3, 0= xB8) + +#define HAS_FEATURE(lvts_data, feature) (lvts_data->feature_bitmap & (fea= ture)) +#define GET_BASE_ADDR(lvts_data, tc_id) (lvts_data->base + lvts_data->tc[= tc_id].addr_offset) +#define GET_CAL_DATA_BITMASK(index, lvts_data, h, l) (((index) < lvts_data= ->num_efuse_addr) \ + ? ((lvts_data->efuse[(index)] & GENMASK(h, l)) >> l) : 0) + +#define GET_TC_SENSOR_NUM(lvts_data, tc_id) (lvts_data->tc[tc_id].num_sen= sor) +#define ONE_SAMPLE (lvts_data->counting_window_us + 2 * BUS_ACCESS_US) +#define NUM_OF_SAMPLE(tc_id) ((lvts_data->tc[tc_id].hw_filter < LVTS_FILTE= R_2) ? 1 : \ + ((lvts_data->tc[tc_id].hw_filter > LVTS_FILTER_16_OF_18) ? 1 : \ + ((lvts_data->tc[tc_id].hw_filter =3D=3D LVTS_FILTER_16_OF_18) ? 18 : \ + ((lvts_data->tc[tc_id].hw_filter =3D=3D LVTS_FILTER_8_OF_10) ? 10 : \ + (lvts_data->tc[tc_id].hw_filter * 2))))) + +#define PERIOD_UNIT_US(tc_id) ((lvts_data->tc[tc_id].tc_speed->period_unit= * 256 * \ + CLOCK_26MHZ_CYCLE_NS) / 1000) +#define FILTER_INT_US(tc_id) (lvts_data->tc[tc_id].tc_speed->filter_interv= al_delay * \ + PERIOD_UNIT_US(tc_id)) +#define SENSOR_INT_US(tc_id) (lvts_data->tc[tc_id].tc_speed->sensor_interv= al_delay * \ + PERIOD_UNIT_US(tc_id)) +#define GROUP_INT_US(tc_id) (lvts_data->tc[tc_id].tc_speed->group_interva= l_delay * \ + PERIOD_UNIT_US(tc_id)) +#define SENSOR_LATENCY_US(tc_id) ((NUM_OF_SAMPLE(tc_id) - 1) * FILTER_INT_= US(tc_id) + \ + NUM_OF_SAMPLE(tc_id) * ONE_SAMPLE) +#define GROUP_LATENCY_US(tc_id) (GET_TC_SENSOR_NUM(lvts_data, tc_id) * \ + SENSOR_LATENCY_US(tc_id) + (GET_TC_SENSOR_NUM(lvts_data, tc_id) - 1) * SE= NSOR_INT_US(tc_id) + \ + GROUP_INT_US(tc_id)) + +#define CK26M_ACTIVE(lvts_data) (((lvts_data->feature_bitmap & FEATURE_CK2= 6M_ACTIVE) ? 1 : 0) << 30) +#define DEVICE_ACCESS (SCK_ONLY | DEVICE_ACCESS_STARTUS | READ_32BIT_ACC= ESS) +#define DEVICE_READ (CK26M_ACTIVE(lvts_data) | DEVICE_ACCESS) +#define DEVICE_WRITE (CK26M_ACTIVE(lvts_data) | DEVICE_ACCESS | WRITE_AC= CESS) +#define READ_BACK_DEVICE_ID (CK26M_ACTIVE(lvts_data) | DEVICE_ACCESS | BR= OADCAST_ID_UPDATE | \ + RG_DID_LVTS << 8) +#define READ_DEVICE_REG(reg_idx) (DEVICE_READ | (reg_idx) << 8 | 0x00) +#define RESET_ALL_DEVICES (DEVICE_WRITE | RG_TSFM_RST << 8 | 0xFF) + +/* + * LVTS HW filter settings + * 000: Get one sample + * 001: Get 2 samples and average them + * 010: Get 4 samples, drop max and min, then average the rest of 2 samples + * 011: Get 6 samples, drop max and min, then average the rest of 4 samples + * 100: Get 10 samples, drop max and min, then average the rest of 8 sampl= es + * 101: Get 18 samples, drop max and min, then average the rest of 16 samp= les + */ +enum lvts_hw_filter { + LVTS_FILTER_1, + LVTS_FILTER_2, + LVTS_FILTER_2_OF_4, + LVTS_FILTER_4_OF_6, + LVTS_FILTER_8_OF_10, + LVTS_FILTER_16_OF_18 +}; + +enum lvts_sensing_point { + SENSING_POINT0, + SENSING_POINT1, + SENSING_POINT2, + SENSING_POINT3, + ALL_SENSING_POINTS +}; + +struct lvts_data; + +/** + * struct lvts_speed_settings - A structure to hold the data related to po= lling rate + * @period_unit: Period unit is a base for all interval delays + * @group_interval_delay: Delay between different rounds + * @filter_interval_delay: Delay between two samples of the same sensor + * @sensor_interval_delay: Delay between two samples of differnet sensors + * + * Calculation is achieved with the following equations: + * For the period unit: (period_us * 1000) / (256 * clock_26mhz_cycle_ns) + * For the interval delays: delay / period_us + */ +struct lvts_speed_settings { + unsigned int period_unit; + unsigned int group_interval_delay; + unsigned int filter_interval_delay; + unsigned int sensor_interval_delay; +}; + +struct lvts_tc_settings { + unsigned int dev_id; + unsigned int addr_offset; + unsigned int num_sensor; + unsigned int sensor_map[ALL_SENSING_POINTS]; /* In sensor ID */ + struct lvts_speed_settings *tc_speed; + /* + * HW filter setting + * 000: Get one sample + * 001: Get 2 samples and average them + * 010: Get 4 samples, drop max and min, then average the rest of 2 sampl= es + * 011: Get 6 samples, drop max and min, then average the rest of 4 sampl= es + * 100: Get 10 samples, drop max and min, then average the rest of 8 samp= les + * 101: Get 18 samples, drop max and min, then average the rest of 16 sam= ples + */ + unsigned int hw_filter; + /* + * Dominator_sensing point is used to select a sensing point + * and reference its temperature to trigger Thermal HW Reboot + * When it is ALL_SENSING_POINTS, it will select all sensing points + */ + int dominator_sensing_point; + int hw_reboot_trip_point; /* -274000: Disable HW reboot */ + unsigned int irq_bit; +}; + +struct lvts_formula_coeff { + int a; + int b; + unsigned int golden_temp; +}; + +struct lvts_sensor_cal_data { + int use_fake_efuse; /* 1: Use fake efuse, 0: Use real efuse */ + unsigned int golden_temp; + unsigned int *count_r; + unsigned int *count_rc; + unsigned int *count_rc_now; + unsigned int default_golden_temp; + unsigned int default_count_r; + unsigned int default_count_rc; +}; + +struct platform_ops { + void (*efuse_to_cal_data)(struct lvts_data *lvts_data); + void (*device_enable_and_init)(struct lvts_data *lvts_data); + void (*device_enable_auto_rck)(struct lvts_data *lvts_data); + int (*device_read_count_rc_n)(struct lvts_data *lvts_data); + void (*set_cal_data)(struct lvts_data *lvts_data); + void (*init_controller)(struct lvts_data *lvts_data); +}; + +struct lvts_data { + struct device *dev; + struct clk *clk; + void __iomem *base; /* LVTS base addresses */ + unsigned int irq_num; /* LVTS interrupt numbers */ + struct reset_control *reset; + int num_tc; /* Number of LVTS thermal controllers */ + const struct lvts_tc_settings *tc; + int counting_window_us; /* LVTS device counting window */ + int num_sensor; /* Number of sensors in this platform */ + void __iomem **reg; + struct platform_ops ops; + int feature_bitmap; /* Show what features are enabled */ + unsigned int num_efuse_addr; + unsigned int *efuse; + unsigned int num_efuse_block; /* Number of contiguous efuse indexes */ + struct lvts_sensor_cal_data cal_data; + struct lvts_formula_coeff coeff; +}; + +struct soc_temp_tz { + unsigned int id; + struct lvts_data *lvts_data; +}; + +extern void lvts_device_enable_and_init_v4(struct lvts_data *lvts_data); +extern void lvts_device_enable_auto_rck_v4(struct lvts_data *lvts_data); +extern int lvts_device_read_count_rc_n_v4(struct lvts_data *lvts_data); +extern void lvts_set_calibration_data_v4(struct lvts_data *lvts_data); +extern void lvts_init_controller_v4(struct lvts_data *lvts_data); + +extern int lvts_probe(struct platform_device *pdev); +extern int lvts_remove(struct platform_device *pdev); +extern int lvts_suspend(struct platform_device *pdev, pm_message_t state); +extern int lvts_resume(struct platform_device *pdev); + +#endif /* __MTK_SOC_TEMP_LVTS_H__ */ --=20 2.34.1 From nobody Sat Sep 21 20:11:47 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CA41C00140 for ; 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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id d13-20020adf9c8d000000b0021e4c3b2967sm15244670wre.65.2022.07.26.06.55.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Jul 2022 06:55:20 -0700 (PDT) From: Balsam CHIHI To: rafael@kernel.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, amitk@kernel.org Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, mka@chromium.org, robh+dt@kernel.org, krzk+dt@kernel.org, matthias.bgg@gmail.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, fan.chen@mediatek.com, louis.yu@mediatek.com, rex-bc.chen@mediatek.com, abailon@baylibre.com Subject: [PATCH v8 4/6] thermal: mediatek: Add thermal zone settings for mt8195 Date: Tue, 26 Jul 2022 15:55:04 +0200 Message-Id: <20220726135506.485108-5-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220726135506.485108-1-bchihi@baylibre.com> References: <20220726135506.485108-1-bchihi@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add thermal zone settings for mt8195 Signed-off-by: Michael Kao Signed-off-by: Ben Tseng Signed-off-by: Alexandre Bailon Signed-off-by: Balsam CHIHI --- drivers/thermal/mediatek/Kconfig | 12 ++ drivers/thermal/mediatek/Makefile | 1 + drivers/thermal/mediatek/lvts_mt8195.c | 253 +++++++++++++++++++++++ drivers/thermal/mediatek/soc_temp_lvts.h | 1 + 4 files changed, 267 insertions(+) create mode 100644 drivers/thermal/mediatek/lvts_mt8195.c diff --git a/drivers/thermal/mediatek/Kconfig b/drivers/thermal/mediatek/Kc= onfig index 7fc04237dd50..df3b4a033fc2 100644 --- a/drivers/thermal/mediatek/Kconfig +++ b/drivers/thermal/mediatek/Kconfig @@ -47,4 +47,16 @@ config LVTS_MT8192 configures LVTS thermal controllers to collect temperatures via ASIF. =20 +config LVTS_MT8195 + tristate "LVTS driver for MediaTek MT8195 SoC" + depends on HAS_IOMEM + depends on NVMEM + depends on RESET_TI_SYSCON + depends on MTK_SOC_THERMAL_LVTS + help + Enable this option if you want to get SoC temperature + information for MT8195. This driver + configures LVTS thermal controllers to collect temperatures + via ASIF. + endif diff --git a/drivers/thermal/mediatek/Makefile b/drivers/thermal/mediatek/M= akefile index 5ff1197e80ab..dada1bf13110 100644 --- a/drivers/thermal/mediatek/Makefile +++ b/drivers/thermal/mediatek/Makefile @@ -1,3 +1,4 @@ obj-$(CONFIG_MTK_SOC_THERMAL) +=3D soc_temp.o obj-$(CONFIG_MTK_SOC_THERMAL_LVTS) +=3D soc_temp_lvts.o obj-$(CONFIG_LVTS_MT8192) +=3D lvts_mt8192.o +obj-$(CONFIG_LVTS_MT8195) +=3D lvts_mt8195.o diff --git a/drivers/thermal/mediatek/lvts_mt8195.c b/drivers/thermal/media= tek/lvts_mt8195.c new file mode 100644 index 000000000000..df69e2e79115 --- /dev/null +++ b/drivers/thermal/mediatek/lvts_mt8195.c @@ -0,0 +1,253 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 MediaTek Inc. + */ + +#include +#include +#include "soc_temp_lvts.h" + +enum mt8195_lvts_mcu_sensor_enum { + MT8195_TS1_0, // cpu_big1 + MT8195_TS1_1, // cpu_big2 + MT8195_TS2_0, // cpu_big3 + MT8195_TS2_1, // cpu_big4 + MT8195_TS3_0, // cpu_little1 + MT8195_TS3_1, // cpu_little2 + MT8195_TS3_2, // cpu_little3 + MT8195_TS3_3, // cpu_little4 + MT8195_NUM_TS_MCU +}; + +enum mt8195_lvts_ap_sensor_enum { + MT8195_TS4_0, // vpu1 + MT8195_TS4_1, // vpu2 + MT8195_TS5_0, // gpu1 + MT8195_TS5_1, // gpu2 + MT8195_TS6_0, // vdec + MT8195_TS6_1, // img + MT8195_TS6_2, // infra + MT8195_TS7_0, // cam1 + MT8195_TS7_1, // cam2 + MT8195_NUM_TS_AP +}; + +static void mt8195_mcu_efuse_to_cal_data(struct lvts_data *lvts_data) +{ + struct lvts_sensor_cal_data *cal_data =3D &lvts_data->cal_data; + + cal_data->golden_temp =3D GET_CAL_DATA_BITMASK(0, lvts_data, 31, 24); + + cal_data->count_r[MT8195_TS1_0] =3D GET_CAL_DATA_BITMASK(1, lvts_data, 23= , 0); + cal_data->count_r[MT8195_TS1_1] =3D (GET_CAL_DATA_BITMASK(2, lvts_data, 1= 5, 0) << 8) + + GET_CAL_DATA_BITMASK(1, lvts_data, 31, 24); + cal_data->count_r[MT8195_TS2_0] =3D GET_CAL_DATA_BITMASK(3, lvts_data, 31= , 8); + cal_data->count_r[MT8195_TS2_1] =3D GET_CAL_DATA_BITMASK(4, lvts_data, 23= , 0); + cal_data->count_r[MT8195_TS3_0] =3D (GET_CAL_DATA_BITMASK(6, lvts_data, 7= , 0) << 16) + + GET_CAL_DATA_BITMASK(5, lvts_data, 31, 16); + cal_data->count_r[MT8195_TS3_1] =3D GET_CAL_DATA_BITMASK(6, lvts_data, 31= , 8); + cal_data->count_r[MT8195_TS3_2] =3D GET_CAL_DATA_BITMASK(7, lvts_data, 23= , 0); + cal_data->count_r[MT8195_TS3_3] =3D (GET_CAL_DATA_BITMASK(8, lvts_data, 1= 5, 0) << 8) + + GET_CAL_DATA_BITMASK(7, lvts_data, 31, 24); + + cal_data->count_rc[MT8195_TS1_0] =3D (GET_CAL_DATA_BITMASK(3, lvts_data, = 7, 0) << 16) + + GET_CAL_DATA_BITMASK(2, lvts_data, 31, 16); + cal_data->count_rc[MT8195_TS2_0] =3D (GET_CAL_DATA_BITMASK(5, lvts_data, = 15, 0) << 8) + + GET_CAL_DATA_BITMASK(4, lvts_data, 31, 24); + cal_data->count_rc[MT8195_TS3_0] =3D (GET_CAL_DATA_BITMASK(9, lvts_data, = 7, 0) << 16) + + GET_CAL_DATA_BITMASK(8, lvts_data, 31, 16); +} + +static void mt8195_ap_efuse_to_cal_data(struct lvts_data *lvts_data) +{ + struct lvts_sensor_cal_data *cal_data =3D &lvts_data->cal_data; + + cal_data->golden_temp =3D GET_CAL_DATA_BITMASK(0, lvts_data, 31, 24); + + cal_data->count_r[MT8195_TS4_0] =3D GET_CAL_DATA_BITMASK(9, lvts_data, 31= , 8); + cal_data->count_r[MT8195_TS4_1] =3D GET_CAL_DATA_BITMASK(10, lvts_data, 2= 3, 0); + cal_data->count_r[MT8195_TS5_0] =3D (GET_CAL_DATA_BITMASK(12, lvts_data, = 7, 0) << 16) + + GET_CAL_DATA_BITMASK(11, lvts_data, 31, 16); + cal_data->count_r[MT8195_TS5_1] =3D GET_CAL_DATA_BITMASK(12, lvts_data, 3= 1, 8); + cal_data->count_r[MT8195_TS6_0] =3D (GET_CAL_DATA_BITMASK(14, lvts_data, = 15, 0) << 8) + + GET_CAL_DATA_BITMASK(13, lvts_data, 31, 24); + cal_data->count_r[MT8195_TS6_1] =3D (GET_CAL_DATA_BITMASK(15, lvts_data, = 7, 0) << 16) + + GET_CAL_DATA_BITMASK(14, lvts_data, 31, 16); + cal_data->count_r[MT8195_TS6_2] =3D GET_CAL_DATA_BITMASK(15, lvts_data, 3= 1, 8); + cal_data->count_r[MT8195_TS7_0] =3D (GET_CAL_DATA_BITMASK(17, lvts_data, = 15, 0) << 8) + + GET_CAL_DATA_BITMASK(16, lvts_data, 31, 24); + cal_data->count_r[MT8195_TS7_1] =3D (GET_CAL_DATA_BITMASK(18, lvts_data, = 7, 0) << 16) + + GET_CAL_DATA_BITMASK(17, lvts_data, 31, 16); + + cal_data->count_rc[MT8195_TS4_0] =3D (GET_CAL_DATA_BITMASK(11, lvts_data,= 15, 0) << 8) + + GET_CAL_DATA_BITMASK(10, lvts_data, 31, 24); + cal_data->count_rc[MT8195_TS5_0] =3D GET_CAL_DATA_BITMASK(13, lvts_data, = 23, 0); + cal_data->count_rc[MT8195_TS6_0] =3D GET_CAL_DATA_BITMASK(16, lvts_data, = 23, 0); + cal_data->count_rc[MT8195_TS7_0] =3D GET_CAL_DATA_BITMASK(18, lvts_data, = 31, 8); +} + +static struct lvts_speed_settings tc_speed_mt8195 =3D { + .period_unit =3D PERIOD_UNIT, + .group_interval_delay =3D GROUP_INTERVAL_DELAY, + .filter_interval_delay =3D FILTER_INTERVAL_DELAY, + .sensor_interval_delay =3D SENSOR_INTERVAL_DELAY, +}; + +static const struct lvts_tc_settings mt8195_tc_mcu_settings[] =3D { + [0] =3D { + .dev_id =3D 0x81, + .addr_offset =3D 0x0, + .num_sensor =3D 2, + .sensor_map =3D {MT8195_TS1_0, MT8195_TS1_1}, + .tc_speed =3D &tc_speed_mt8195, + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT1, + .hw_reboot_trip_point =3D HW_REBOOT_TRIP_POINT, + .irq_bit =3D BIT(3), + }, + [1] =3D { + .dev_id =3D 0x82, + .addr_offset =3D 0x100, + .num_sensor =3D 2, + .sensor_map =3D {MT8195_TS2_0, MT8195_TS2_1}, + .tc_speed =3D &tc_speed_mt8195, + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT0, + .hw_reboot_trip_point =3D HW_REBOOT_TRIP_POINT, + .irq_bit =3D BIT(4), + }, + [2] =3D { + .dev_id =3D 0x83, + .addr_offset =3D 0x200, + .num_sensor =3D 4, + .sensor_map =3D {MT8195_TS3_0, MT8195_TS3_1, MT8195_TS3_2, MT8195_TS3_3}, + .tc_speed =3D &tc_speed_mt8195, + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT0, + .hw_reboot_trip_point =3D HW_REBOOT_TRIP_POINT, + .irq_bit =3D BIT(5), + } +}; + +static const struct lvts_tc_settings mt8195_tc_ap_settings[] =3D { + [0] =3D { + .dev_id =3D 0x84, + .addr_offset =3D 0x0, + .num_sensor =3D 2, + .sensor_map =3D {MT8195_TS4_0, MT8195_TS4_1}, + .tc_speed =3D &tc_speed_mt8195, + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT0, + .hw_reboot_trip_point =3D HW_REBOOT_TRIP_POINT, + .irq_bit =3D BIT(3), + }, + [1] =3D { + .dev_id =3D 0x85, + .addr_offset =3D 0x100, + .num_sensor =3D 2, + .sensor_map =3D {MT8195_TS5_0, MT8195_TS5_1}, + .tc_speed =3D &tc_speed_mt8195, + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT1, + .hw_reboot_trip_point =3D HW_REBOOT_TRIP_POINT, + .irq_bit =3D BIT(4), + }, + [2] =3D { + .dev_id =3D 0x86, + .addr_offset =3D 0x200, + .num_sensor =3D 3, + .sensor_map =3D {MT8195_TS6_0, MT8195_TS6_1, MT8195_TS6_2}, + .tc_speed =3D &tc_speed_mt8195, + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT1, + .hw_reboot_trip_point =3D HW_REBOOT_TRIP_POINT, + .irq_bit =3D BIT(5), + }, + [3] =3D { + .dev_id =3D 0x87, + .addr_offset =3D 0x300, + .num_sensor =3D 2, + .sensor_map =3D {MT8195_TS7_0, MT8195_TS7_1}, + .tc_speed =3D &tc_speed_mt8195, + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT0, + .hw_reboot_trip_point =3D HW_REBOOT_TRIP_POINT, + .irq_bit =3D BIT(6), + } +}; + +static const struct lvts_data mt8195_lvts_mcu_data =3D { + .num_tc =3D (ARRAY_SIZE(mt8195_tc_mcu_settings)), + .tc =3D mt8195_tc_mcu_settings, + .num_sensor =3D MT8195_NUM_TS_MCU, + .ops =3D { + .efuse_to_cal_data =3D mt8195_mcu_efuse_to_cal_data, + .device_enable_and_init =3D lvts_device_enable_and_init_v4, + .device_enable_auto_rck =3D lvts_device_enable_auto_rck_v4, + .device_read_count_rc_n =3D lvts_device_read_count_rc_n_v4, + .set_cal_data =3D lvts_set_calibration_data_v4, + .init_controller =3D lvts_init_controller_v4, + }, + .feature_bitmap =3D FEATURE_DEVICE_AUTO_RCK, + .num_efuse_addr =3D NUM_EFUSE_ADDR, + .num_efuse_block =3D NUM_EFUSE_BLOCK_MT8195, + .cal_data =3D { + .default_golden_temp =3D DEFAULT_GOLDEN_TEMP, + .default_count_r =3D DEFAULT_CUONT_R, + .default_count_rc =3D DEFAULT_CUONT_RC, + }, + .coeff =3D { + .a =3D COEFF_A, + .b =3D COEFF_B, + }, +}; + +static const struct lvts_data mt8195_lvts_ap_data =3D { + .num_tc =3D (ARRAY_SIZE(mt8195_tc_ap_settings)), + .tc =3D mt8195_tc_ap_settings, + .num_sensor =3D MT8195_NUM_TS_AP, + .ops =3D { + .efuse_to_cal_data =3D mt8195_ap_efuse_to_cal_data, + .device_enable_and_init =3D lvts_device_enable_and_init_v4, + .device_enable_auto_rck =3D lvts_device_enable_auto_rck_v4, + .device_read_count_rc_n =3D lvts_device_read_count_rc_n_v4, + .set_cal_data =3D lvts_set_calibration_data_v4, + .init_controller =3D lvts_init_controller_v4, + }, + .feature_bitmap =3D FEATURE_DEVICE_AUTO_RCK, + .num_efuse_addr =3D NUM_EFUSE_ADDR, + .num_efuse_block =3D NUM_EFUSE_BLOCK_MT8195, + .cal_data =3D { + .default_golden_temp =3D DEFAULT_GOLDEN_TEMP, + .default_count_r =3D DEFAULT_CUONT_R, + .default_count_rc =3D DEFAULT_CUONT_RC, + }, + .coeff =3D { + .a =3D COEFF_A, + .b =3D COEFF_B, + }, +}; + +static const struct of_device_id lvts_of_match[] =3D { + { .compatible =3D "mediatek,mt8195-lvts-mcu", .data =3D &mt8195_lvts_mcu_= data, }, + { .compatible =3D "mediatek,mt8195-lvts-ap", .data =3D &mt8195_lvts_ap_da= ta, }, + {}, +}; +MODULE_DEVICE_TABLE(of, lvts_of_match); + +static struct platform_driver soc_temp_lvts =3D { + .probe =3D lvts_probe, + .remove =3D lvts_remove, + .suspend =3D lvts_suspend, + .resume =3D lvts_resume, + .driver =3D { + .name =3D "mtk-soc-temp-lvts-mt8195", + .of_match_table =3D lvts_of_match, + }, +}; +module_platform_driver(soc_temp_lvts); + +MODULE_AUTHOR("Yu-Chia Chang "); +MODULE_AUTHOR("Michael Kao "); +MODULE_DESCRIPTION("MediaTek soc temperature driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/thermal/mediatek/soc_temp_lvts.h b/drivers/thermal/med= iatek/soc_temp_lvts.h index 6f8b6e3af98c..c4acb7e26e5e 100644 --- a/drivers/thermal/mediatek/soc_temp_lvts.h +++ b/drivers/thermal/mediatek/soc_temp_lvts.h @@ -16,6 +16,7 @@ #define FEATURE_DEVICE_AUTO_RCK BIT(0) #define NUM_EFUSE_ADDR 22 #define NUM_EFUSE_BLOCK_MT8192 1 +#define NUM_EFUSE_BLOCK_MT8195 2 #define DEFAULT_GOLDEN_TEMP 50 #define DEFAULT_CUONT_R 35000 #define DEFAULT_CUONT_RC 2750 --=20 2.34.1 From nobody Sat Sep 21 20:11:47 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4067CC00140 for ; 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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id d13-20020adf9c8d000000b0021e4c3b2967sm15244670wre.65.2022.07.26.06.55.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Jul 2022 06:55:21 -0700 (PDT) From: Balsam CHIHI To: rafael@kernel.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, amitk@kernel.org Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, mka@chromium.org, robh+dt@kernel.org, krzk+dt@kernel.org, matthias.bgg@gmail.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, fan.chen@mediatek.com, louis.yu@mediatek.com, rex-bc.chen@mediatek.com, abailon@baylibre.com Subject: [PATCH v8 5/6] arm64: dts: mt8195: Add efuse node to mt8195 Date: Tue, 26 Jul 2022 15:55:05 +0200 Message-Id: <20220726135506.485108-6-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220726135506.485108-1-bchihi@baylibre.com> References: <20220726135506.485108-1-bchihi@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds the efuse node. This will be required by the thermal driver to get the calibration data. Signed-off-by: Alexandre Bailon Signed-off-by: Balsam CHIHI --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 0ff34edcf8c8..4fbf24b5d202 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1236,6 +1236,22 @@ nor_flash: spi@1132c000 { status =3D "disabled"; }; =20 + efuse: efuse@11c10000 { + compatible =3D "mediatek,efuse"; + reg =3D <0 0x11c10000 0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + lvts_efuse_data1: lvts1-calib@1bc { + reg =3D <0x1bc 0x14>; + }; + lvts_efuse_data2: lvts2-calib@1d0 { + reg =3D <0x1d0 0x38>; + }; + svs_calibration: calib@580 { + reg =3D <0x580 0x64>; + }; + }; + u3phy2: t-phy@11c40000 { compatible =3D "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; #address-cells =3D <1>; --=20 2.34.1 From nobody Sat Sep 21 20:11:47 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 068A6C00140 for ; Tue, 26 Jul 2022 13:55:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239176AbiGZNzt (ORCPT ); Tue, 26 Jul 2022 09:55:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38058 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239131AbiGZNzb (ORCPT ); Tue, 26 Jul 2022 09:55:31 -0400 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A7A51CE39 for ; Tue, 26 Jul 2022 06:55:24 -0700 (PDT) Received: by mail-wm1-x32a.google.com with SMTP id id17so8803162wmb.1 for ; Tue, 26 Jul 2022 06:55:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=N02ENN8wREPX4veIj3cGqV28PXqeQzl2/6jGMwhV5k4=; b=vO9zvYPT5F1jd3WhvAXktLAz6qcb8YZgGeLh1fXmtfpqcsBFp8Js3hB+qnqryJRuBl 2tV1KtKbEj+iw2CLAXaujRN8QpTGItj84cZdY3YIt8Wqcxrq1Y9Tqqf0XdvmBml1R99U MVrxwDL2oeW8hl/hZs/K4zffKdBlG573cIGBw0SoXvP78XIxAg7fGITYYjJfOFl7NLZj Sv+SuVeq9vsL5XPjan/wzSLX4NWjqAoRiTF4uXqC1huzb6719k+s+RsdiBN7mKdU0vlk AxQnUwdaAbm/Bi5jSow290CBHv1JEdr0DF4WeHltdnDaKon0HvytQGi+Q3w5aqyJ8ZvY 4jCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=N02ENN8wREPX4veIj3cGqV28PXqeQzl2/6jGMwhV5k4=; b=YZW0kQqkDM/aJRKkoXg9myHgTva1laeSOaOUzJIChGpVzMptkEO857ojHu97CN8LeH dRxfvmvmsdukU4x3mP+zyVBVFuIHmx0tR43oBvajzBKPWSnSJuGnXIcD8MhnE/tZvXlb VtpUFWhT+CWrZQXMPfDpWHi+ZhaYVW7uuls6IdLfem8q+vNDjixiCnXR6GDFtKZF/xW8 jDD4V7YypnZHSuIeM42kaeq58IEN13YIlo7txdG378UAU1Et+nw4xNsRjFDPAa9r8AsO nmSb9tgcX215wRnzBO1xKls7oJxdjuY8iGohr385JCmaw2g/qEvJVTn9kHnL+0+8SglV Jriw== X-Gm-Message-State: AJIora+XUwkShI8Ke6qmAObwo5WiMur+CDH7qNgq/rlpXmUW5eh1bZrx xlWMq3H50r8jg8IY35UleBEXhg== X-Google-Smtp-Source: AGRyM1vhX7RgKC8IGy97eICF/591FulDH1b+GwMaL7So30RUVSvED/g4XVgQWTuECYQ6Gn9vbOzMZQ== X-Received: by 2002:a1c:2783:0:b0:3a2:fd82:bf46 with SMTP id n125-20020a1c2783000000b003a2fd82bf46mr24814709wmn.29.1658843723039; Tue, 26 Jul 2022 06:55:23 -0700 (PDT) Received: from Balsam-ThinkPad-T480.baylibre (laubervilliers-658-1-213-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id d13-20020adf9c8d000000b0021e4c3b2967sm15244670wre.65.2022.07.26.06.55.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Jul 2022 06:55:22 -0700 (PDT) From: Balsam CHIHI To: rafael@kernel.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, amitk@kernel.org Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, mka@chromium.org, robh+dt@kernel.org, krzk+dt@kernel.org, matthias.bgg@gmail.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, fan.chen@mediatek.com, louis.yu@mediatek.com, rex-bc.chen@mediatek.com, abailon@baylibre.com Subject: [PATCH v8 6/6] arm64: dts: mt8195: Add thermal zone Date: Tue, 26 Jul 2022 15:55:06 +0200 Message-Id: <20220726135506.485108-7-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220726135506.485108-1-bchihi@baylibre.com> References: <20220726135506.485108-1-bchihi@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds the thermal zone for the mt8195. Signed-off-by: Tinghan Shen Signed-off-by: Ben Tseng Signed-off-by: Alexandre Bailon Signed-off-by: Balsam CHIHI --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 115 ++++++++++++++++++++++- 1 file changed, 114 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 4fbf24b5d202..78017224930c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) /* - * Copyright (c) 2021 MediaTek Inc. + * Copyright (c) 2022 MediaTek Inc. * Author: Seiya Wang */ =20 @@ -11,6 +11,9 @@ #include #include #include +#include +#include +#include =20 / { compatible =3D "mediatek,mt8195"; @@ -810,6 +813,28 @@ spi0: spi@1100a000 { status =3D "disabled"; }; =20 + lvtsap: thermal-sensor@1100b000 { + compatible =3D "mediatek,mt8195-lvts-ap"; + #thermal-sensor-cells =3D <1>; + reg =3D <0 0x1100b000 0 0x400>; + interrupts =3D ; + clocks =3D <&infracfg_ao CLK_INFRA_AO_THERM>; + resets =3D <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>; + nvmem-cells =3D <&lvts_efuse_data1 &lvts_efuse_data2>; + nvmem-cell-names =3D "lvts_calib_data1", "lvts_calib_data2"; + }; + + lvtsmcu: thermal-sensor@11278000 { + compatible =3D "mediatek,mt8195-lvts-mcu"; + #thermal-sensor-cells =3D <1>; + reg =3D <0 0x11278000 0 0x400>; + interrupts =3D ; + clocks =3D <&infracfg_ao CLK_INFRA_AO_THERM>; + resets =3D <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>; + nvmem-cells =3D <&lvts_efuse_data1 &lvts_efuse_data2>; + nvmem-cell-names =3D "lvts_calib_data1", "lvts_calib_data2"; + }; + spi1: spi@11010000 { compatible =3D "mediatek,mt8195-spi", "mediatek,mt6765-spi"; @@ -1613,4 +1638,92 @@ vencsys_core1: clock-controller@1b000000 { #clock-cells =3D <1>; }; }; + + thermal_zones: thermal-zones { + cpu-big1-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsmcu 0>; + }; + cpu-big2-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsmcu 1>; + }; + cpu-big3-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsmcu 2>; + }; + cpu-big4-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsmcu 3>; + }; + cpu-little1-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsmcu 4>; + }; + cpu-little2-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsmcu 5>; + }; + cpu-little3-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsmcu 6>; + }; + cpu-little4-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsmcu 7>; + }; + vpu1-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsap 0>; + }; + vpu2-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsap 1>; + }; + gpu1-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsap 2>; + }; + gpu2-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsap 3>; + }; + vdec-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsap 4>; + }; + img-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsap 5>; + }; + infra-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsap 6>; + }; + cam1-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsap 7>; + }; + cam2-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvtsap 8>; + }; + }; }; --=20 2.34.1