From nobody Wed Apr 15 04:16:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9326DC19F2B for ; Tue, 26 Jul 2022 13:45:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239063AbiGZNoc (ORCPT ); Tue, 26 Jul 2022 09:44:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55944 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239065AbiGZNoR (ORCPT ); Tue, 26 Jul 2022 09:44:17 -0400 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2075.outbound.protection.outlook.com [40.107.223.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 34E461F2EA for ; Tue, 26 Jul 2022 06:44:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=hw7DQnJX1jjEzyYZy4NM9CU9Wc4zTcXUjbIXfyJLwmME8C8TOz/etCzxH9+1qy4hg8yYYRJ/JbusCEwmQlRKhwpOUws+MugyCzuB5dt6VJV3CC85u3LQ9Tzm40x6YUr6fzWdgMXam3CBOnG4QugAgHJu7z5wBzCiCw+DvPQOd810jOc4RZ1JqD3Ygu4Tc/FhojfOjXaUQDzk6GzU2Xs4AI71H3lLCxabZWpPvIhTmTZG8h1pPFMEQ5iYrWA5sXwxCMCWGDXOqeXpdVPCFDyCJaQxUZ59a1/Q7jW1uQ+mpEi3wgTTfHQgSJqnje/7cgjyNkrNFfzVNL9ivLTWCOiKAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=1pvtjB5E5Wn0Em+4gJKN7YBwHfcjrAOHNdv6qXT7ZI0=; b=R68kXfp00H8vraQ819TbKyXjJuO3qXuvb3RtSgLWrU3+VphNP4rpdQeE5HP+c6hJYbDvJAeXmTTtLWrPB0TlIkZXWJclKDjINlv0dYCUWBXuil6vIdzCZUJVJp6rvBEEpnZGHPKbE8ACwZODbVmGaWJqr78r8QW+d4L6C0H3SzmmNnFn8XwJiWUR4Gu6kAyW0Y3ZF2gbdfRatk+9SXhphKAvHfQ4VhzaEjBFMEeK9c4c2tQzNWCqXBp04p3IV84Bq1pKJuKqXgA5j8F6/huRFWpH9GenMjWZMfNvLkAEsnqi3k4jQGEPNVC3NFb86xL+A9Z7KQZ35q8VGGwdyyoP2Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=1pvtjB5E5Wn0Em+4gJKN7YBwHfcjrAOHNdv6qXT7ZI0=; b=GUU8Ax6ekp5JEM5WkY/uwrYZNsB9cBGOKLKhFSd21vNMQgw/eWYqeyhh2LLY7sNzxAQLVA/4x+uHIGND4o/k9pU0nvgqkZmwWo3kAg68MgScoNB99230NxParbaA23sFvXyXBK+n5rATjqYBc+GfXRr7Gln8aVkUKSzi8N1/El0= Received: from MW4PR03CA0183.namprd03.prod.outlook.com (2603:10b6:303:b8::8) by CY4PR1201MB2517.namprd12.prod.outlook.com (2603:10b6:903:da::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5458.21; Tue, 26 Jul 2022 13:44:14 +0000 Received: from CO1NAM11FT005.eop-nam11.prod.protection.outlook.com (2603:10b6:303:b8:cafe::ec) by MW4PR03CA0183.outlook.office365.com (2603:10b6:303:b8::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5458.18 via Frontend Transport; Tue, 26 Jul 2022 13:44:14 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT005.mail.protection.outlook.com (10.13.174.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5458.17 via Frontend Transport; Tue, 26 Jul 2022 13:44:13 +0000 Received: from ruby-95f9host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Tue, 26 Jul 2022 08:44:11 -0500 From: Suravee Suthikulpanit To: , CC: , , , , , Suravee Suthikulpanit , Maxim Levitsky Subject: [PATCH 1/2] iommu/amd: Simplify and Consolidate Virtual APIC (AVIC) Enablement Date: Tue, 26 Jul 2022 08:43:47 -0500 Message-ID: <20220726134348.6438-2-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220726134348.6438-1-suravee.suthikulpanit@amd.com> References: <20220726134348.6438-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f2471759-cbea-43f0-ec58-08da6f0ced6d X-MS-TrafficTypeDiagnostic: CY4PR1201MB2517:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: yC3eKPqgDaU+H5UJf2D1nmfzzKJo+vB2OuY4l0W7nJWN4dbjQ8unbm32iz/9+fyNaNywey/P5YEzofNoF/bIl450OmeDXIe/SnWUW6rQ4+i8NMfy0vVId3oO//Zz9XFO1aDPUbfl0p6dSaVkj3YbPePadpWG3ogcO0/AXUV6Ss5xNOQAgz2fcbtGWrjsWtvqbwmkomPbnvZgFFMKsq9Pxcmw+THxaVG9yT0mncNQqlZrFYKmKY/2TWq3KON2ErhyrA7EQpfkIcy0cj5o1POxTI5J/oCEdq2TGx4d3Dl3LNb72zRSpkhUkrcQd39dgL2juXXthGlfG9+HaXPXWgWnbTf1y7s3R/ybJFOHq7ZW/+fojaq6+rf4KfgdIaaXZMET1fhB6Pqpdlq2uQ1YVG8kH89Lglh3RdYnEl5kCwUH+P7FqXj2V64DN+y8vpl8QhQYNENAr6H8xbmEB/HXUKHdGxa5vUmZida67QNZeOYdvgBX+kMj1BnPoUYQwFQbDM8O7SyPGBhHcwUoAqcfJWmvUsnobA/VZlD+YCGn6ygcxEuB3yhtMoK+rIIDq+99jq3t2Es2Y0dm5778gqoEjNSNi40awXLZCTOWU+Zl8tvcBv5FZsCcPJV80EtGpq4G4msIQzkhD3vf5X5JyPvq+MOCimrwpTBUkgAu1M4aszdRhF5dMoC/6bwV+Dwl6jHuNgzowduP/TgFl1bplVQQzmuRK0p/bU1fR4VacBNgZ+8gv3PnI9yY2BRpvs5g3Ssz52YbOiynGkLVsNzzljZcFA9Dt7dCiywfG2ZuoIDYbuKU/uokpYASd3RQosTS5aOG1opOqNCmJww5ENolo+AhZAVThQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230016)(4636009)(346002)(136003)(39860400002)(396003)(376002)(46966006)(40470700004)(36840700001)(82740400003)(356005)(8936002)(45080400002)(47076005)(426003)(336012)(41300700001)(36756003)(83380400001)(6666004)(86362001)(5660300002)(16526019)(186003)(54906003)(478600001)(110136005)(4326008)(70586007)(1076003)(8676002)(70206006)(40460700003)(82310400005)(2616005)(36860700001)(7696005)(40480700001)(81166007)(44832011)(26005)(2906002)(316002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jul 2022 13:44:13.8166 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f2471759-cbea-43f0-ec58-08da6f0ced6d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT005.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR1201MB2517 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently, enabling AVIC requires individually detect and enable GAM and GALOG features on each IOMMU, which is difficult to keep track on multi-IOMMU system, where the features needs to be enabled system-wide. In addition, these features do not need to be enabled in early stage.=20 It can be delayed until after amd_iommu_init_pci(). Therefore, consolidate logic for detecting and enabling IOMMU GAM and GALOG features into a helper function, enable_iommus_vapic(), which uses the check_feature_on_all_iommus() helper function to ensure system-wide support of the features before enabling them, and postpone until after amd_iommu_init_pci(). The new function also check and clean up feature enablement residue from previous boot (e.g. in case of booting into kdump kernel), which triggers a WARN_ON (shown below) introduced by the commit a8d4a37d1bb9 ("iommu/amd: Restore GA log/tail pointer on host resume") in iommu_ga_log_enable(). [ 7.731955] ------------[ cut here ]------------ [ 7.736575] WARNING: CPU: 0 PID: 1 at drivers/iommu/amd/init.c:829 iommu= _ga_log_enable.isra.0+0x16f/0x190 [ 7.746135] Modules linked in: [ 7.749193] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W ---= ----- --- 5.19.0-0.rc7.53.eln120.x86_64 #1 [ 7.759706] Hardware name: Dell Inc. PowerEdge R7525/04D5GJ, BIOS 2.1.6 = 03/09/2021 [ 7.767274] RIP: 0010:iommu_ga_log_enable.isra.0+0x16f/0x190 [ 7.772931] Code: 20 20 00 00 8b 00 f6 c4 01 74 da 48 8b 44 24 08 65 48 = 2b 04 25 28 00 00 00 75 13 48 83 c4 10 5b 5d e9 f5 00 72 00 0f 0b eb e1 <0f= > 0b eb dd e8 f8 66 42 00 48 8b 15 f1 85 53 01 e9 29 ff ff ff 48 [ 7.791679] RSP: 0018:ffffc90000107d20 EFLAGS: 00010206 [ 7.796905] RAX: ffffc90000780000 RBX: 0000000000000100 RCX: ffffc900007= 80000 [ 7.804038] RDX: 0000000000000001 RSI: ffffc90000780000 RDI: ffff8880451= f9800 [ 7.811170] RBP: ffff8880451f9800 R08: ffffffffffffffff R09: 00000000000= 00000 [ 7.818303] R10: 0000000000000000 R11: 0000000000000000 R12: 00080000000= 00000 [ 7.825435] R13: ffff8880462ea900 R14: 0000000000000021 R15: 00000000000= 00000 [ 7.832572] FS: 0000000000000000(0000) GS:ffff888054a00000(0000) knlGS:= 0000000000000000 [ 7.840657] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 7.846400] CR2: ffff888054dff000 CR3: 0000000053210000 CR4: 00000000003= 50eb0 [ 7.853533] Call Trace: [ 7.855979] [ 7.858085] amd_iommu_enable_interrupts+0x180/0x270 [ 7.863051] ? iommu_setup+0x271/0x271 [ 7.866803] state_next+0x197/0x2c0 [ 7.870295] ? iommu_setup+0x271/0x271 [ 7.874049] iommu_go_to_state+0x24/0x2c [ 7.877976] amd_iommu_init+0xf/0x29 [ 7.881554] pci_iommu_init+0xe/0x36 [ 7.885133] do_one_initcall+0x44/0x200 [ 7.888975] do_initcalls+0xc8/0xe1 [ 7.892466] kernel_init_freeable+0x14c/0x199 [ 7.896826] ? rest_init+0xd0/0xd0 [ 7.900231] kernel_init+0x16/0x130 [ 7.903723] ret_from_fork+0x22/0x30 [ 7.907306] [ 7.909497] ---[ end trace 0000000000000000 ]--- Fixes: commit a8d4a37d1bb9 ("iommu/amd: Restore GA log/tail pointer on host= resume") Reported-by: Jerry Snitselaar Cc: Joerg Roedel Cc: Maxim Levitsky Cc: Will Deacon (maintainer:IOMMU DRIVERS) Signed-off-by: Suravee Suthikulpanit Reviewed-by: Jerry Snitselaar --- drivers/iommu/amd/init.c | 85 ++++++++++++++++++++++++++-------------- 1 file changed, 55 insertions(+), 30 deletions(-) diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index d86496114ca5..4cd94d716122 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -908,11 +908,6 @@ static int iommu_ga_log_enable(struct amd_iommu *iommu) if (!iommu->ga_log) return -EINVAL; =20 - /* Check if already running */ - status =3D readl(iommu->mmio_base + MMIO_STATUS_OFFSET); - if (WARN_ON(status & (MMIO_STATUS_GALOG_RUN_MASK))) - return 0; - entry =3D iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512; memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET, &entry, sizeof(entry)); @@ -2068,10 +2063,6 @@ static int __init iommu_init_pci(struct amd_iommu *i= ommu) if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu)) return -ENOMEM; =20 - ret =3D iommu_init_ga_log(iommu); - if (ret) - return ret; - if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) { pr_info("Using strict mode due to virtualization\n"); iommu_set_dma_strict(); @@ -2155,8 +2146,6 @@ static void print_iommu_info(void) } if (irq_remapping_enabled) { pr_info("Interrupt remapping enabled\n"); - if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) - pr_info("Virtual APIC enabled\n"); if (amd_iommu_xt_mode =3D=3D IRQ_REMAP_X2APIC_MODE) pr_info("X2APIC enabled\n"); } @@ -2446,9 +2435,6 @@ static int iommu_init_irq(struct amd_iommu *iommu) =20 if (iommu->ppr_log !=3D NULL) iommu_feature_enable(iommu, CONTROL_PPRINT_EN); - - iommu_ga_log_enable(iommu); - return 0; } =20 @@ -2678,8 +2664,6 @@ static void iommu_enable_ga(struct amd_iommu *iommu) #ifdef CONFIG_IRQ_REMAP switch (amd_iommu_guest_ir) { case AMD_IOMMU_GUEST_IR_VAPIC: - iommu_feature_enable(iommu, CONTROL_GAM_EN); - fallthrough; case AMD_IOMMU_GUEST_IR_LEGACY_GA: iommu_feature_enable(iommu, CONTROL_GA_EN); iommu->irte_ops =3D &irte_128_ops; @@ -2759,19 +2743,6 @@ static void early_enable_iommus(void) iommu_flush_all_caches(iommu); } } - -#ifdef CONFIG_IRQ_REMAP - /* - * Note: We have already checked GASup from IVRS table. - * Now, we need to make sure that GAMSup is set. - */ - if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) && - !check_feature_on_all_iommus(FEATURE_GAM_VAPIC)) - amd_iommu_guest_ir =3D AMD_IOMMU_GUEST_IR_LEGACY_GA; - - if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) - amd_iommu_irq_ops.capability |=3D (1 << IRQ_POSTING_CAP); -#endif } =20 static void enable_iommus_v2(void) @@ -2784,10 +2755,63 @@ static void enable_iommus_v2(void) } } =20 +static void enable_iommus_vapic(void) +{ +#ifdef CONFIG_IRQ_REMAP + u32 status, i; + struct amd_iommu *iommu; + + for_each_iommu(iommu) { + /* + * Disable GALog if already running. It could have been enabled + * in the previous boot before kdump. + */ + status =3D readl(iommu->mmio_base + MMIO_STATUS_OFFSET); + if (!(status & MMIO_STATUS_GALOG_RUN_MASK)) + continue; + + iommu_feature_disable(iommu, CONTROL_GALOG_EN); + iommu_feature_disable(iommu, CONTROL_GAINT_EN); + + /* + * Need to set and poll check the GALOGRun bit to zero before + * we can set/ modify GA Log registers safely. + */ + for (i =3D 0; i < LOOP_TIMEOUT; ++i) { + status =3D readl(iommu->mmio_base + MMIO_STATUS_OFFSET); + if (!(status & MMIO_STATUS_GALOG_RUN_MASK)) + break; + udelay(10); + } + + if (WARN_ON(i >=3D LOOP_TIMEOUT)) + return; + } + + if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) && + !check_feature_on_all_iommus(FEATURE_GAM_VAPIC)) { + amd_iommu_guest_ir =3D AMD_IOMMU_GUEST_IR_LEGACY_GA; + return; + } + + /* Enabling GAM support */ + for_each_iommu(iommu) { + if (iommu_init_ga_log(iommu) || + iommu_ga_log_enable(iommu)) + return; + + iommu_feature_enable(iommu, CONTROL_GAM_EN); + } + + amd_iommu_irq_ops.capability |=3D (1 << IRQ_POSTING_CAP); + pr_info("Virtual APIC enabled\n"); +#endif +} + static void enable_iommus(void) { early_enable_iommus(); - + enable_iommus_vapic(); enable_iommus_v2(); } =20 @@ -3126,6 +3150,7 @@ static int __init state_next(void) register_syscore_ops(&amd_iommu_syscore_ops); ret =3D amd_iommu_init_pci(); init_state =3D ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT; + enable_iommus_vapic(); enable_iommus_v2(); break; case IOMMU_PCI_INIT: --=20 2.34.1 From nobody Wed Apr 15 04:16:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BBF7C282E7 for ; Tue, 26 Jul 2022 13:45:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237447AbiGZNo0 (ORCPT ); Tue, 26 Jul 2022 09:44:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55948 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239073AbiGZNoR (ORCPT ); Tue, 26 Jul 2022 09:44:17 -0400 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2071.outbound.protection.outlook.com [40.107.237.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 89A251FCD6 for ; Tue, 26 Jul 2022 06:44:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Hy0enKK09e5BfSVbAsVk8v8ix++A6Zc7W/1m9NR4wkJ7BtduyOCc1Vw+KsAAyi95P+LkI97KyKG4JltoVtcTAXW4q9aW2uzJWSvnZ++aQzxBBhc4X+AiYabpHMGOKyhGWYoeu4ZNGzJlBSKfoIV1vKQ8nxQyJ4VV4RHeFqUNKbLxdATRO7f8Ayotu5KL/+W8qkrq8LXvwjn/sANP9D/jouj6fR6Z2EvhDhtKtKp/eIvPWQNb6pf7Cvh1Y5FYtSSo4Tv73NenAM+XCFIpC+y/GYh+gdyoebJIOrW+I8j9bEXwSYe4ojZ5tdxV0z7ehLaHFIc+1e7MD4pgo7m7WXhG5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=JewnuYvYkE+G1d5/s7qzbpzMIipsOKHs8rUG70UpspI=; b=IP5dccM+ZtTBiMsT1IzbnGsI/+ySz9BKLY3Jgt0ZAbKQ/j6RX+a6vmQXka/mnSXNLlx/00cLTisprgtkI40Mo6K/eS6hbrqNZT3tLDrvgBfYnVnjHMCtHTbgRQZsNkam7MNR9xt3ATB6oJzxHtDzFNkgTRTu4FeL3g0qywUt0YMGtvIne+mDrNlZat4usO03OoVoMbA+Ug+sjLDR7V3736OXppHiVWv+ur99ouzq7VmhCdUwazapd3yuIdTK0hOjAWEQ6BuNCxKiDDBXqr7qR6E2EKxuNGwkDizA5jWecH7LX+1khq0DAOFVjssvCBEsWbDb19uZAs2C6/wLLWwomw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=JewnuYvYkE+G1d5/s7qzbpzMIipsOKHs8rUG70UpspI=; b=H5hEtTAthGMNiEnYdsFbwaM1Q7gg/ahFZ3Lwt6NWWSmRMcB3BN7C5TXJkFLaItZ3qsq7dVse6K7KQCyYPIQn7XRGZ2k+hqZfzYrKVO+gfh1pYr6ojHy7adydvQY+e/bmT4etqPXEFEhnJ+TDiXVPxXOshZmRvcdWkU7n3EUu1vM= Received: from MW4PR03CA0183.namprd03.prod.outlook.com (2603:10b6:303:b8::8) by BY5PR12MB4147.namprd12.prod.outlook.com (2603:10b6:a03:205::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5458.19; Tue, 26 Jul 2022 13:44:14 +0000 Received: from CO1NAM11FT005.eop-nam11.prod.protection.outlook.com (2603:10b6:303:b8:cafe::63) by MW4PR03CA0183.outlook.office365.com (2603:10b6:303:b8::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5458.18 via Frontend Transport; Tue, 26 Jul 2022 13:44:14 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT005.mail.protection.outlook.com (10.13.174.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5458.17 via Frontend Transport; Tue, 26 Jul 2022 13:44:14 +0000 Received: from ruby-95f9host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Tue, 26 Jul 2022 08:44:12 -0500 From: Suravee Suthikulpanit To: , CC: , , , , , Suravee Suthikulpanit Subject: [PATCH 2/2] iommu/amd: Add support for AVIC when SNP is enabled Date: Tue, 26 Jul 2022 08:43:48 -0500 Message-ID: <20220726134348.6438-3-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220726134348.6438-1-suravee.suthikulpanit@amd.com> References: <20220726134348.6438-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 200eba34-e695-4500-48b4-08da6f0cedcd X-MS-TrafficTypeDiagnostic: BY5PR12MB4147:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: gIkYbY5ZkvuHsvToaHe8OETG3WjwQ4gK38HiF7kGBIsb0QcBAYG2yuflA5XCwfzzpZI2HAh5iF4B95SLRAIhEJy4AaQ2ntEoiMcCpDjfGc1hcLTotY1wdrFSpICH8ZFETWRWQAJbMOF+O5oj/muj8k6gpBYARhe3AUFVAmMcpkJut2YCmwymB59xwdcvFK/hKMMl4yAYuUynaOGg1ZQkSbqn2z6oG+TMnHKhN0BDGvQYmXF1eHN3b+h9D2Es59vD9elK5CBR68lSuGsKiYoK/CZj8lUIEuJi/vq7zUiXyIkAC11pyTRomqSbMdSu4P8L8MnjQPkkz2b9mlaAQvp/oOvoR3+hdmcQVUFwYW26cTrng7UX7lc6wmaQtl0AjmAeQB/wlvsUMmATasU6lwV7ByymR+Jru3ARlcWTyRz6GJfd745UcTDE+t0pfaQAkaNqoKN+xByzYG67IiWQXwEi2Oitxvbb24+vHWVIKEoXiIH9TfhNp/iv+WMQ0ELR4qUgdiQ2FNfyt+B/w8Z11J9KZKBTvNxMpGerDuu17GZdUYWj7XKfYLtdY2QOsVMpruvRwLeJkkwrLdy0tny8JFlhKIw5AXeNwWqEqG1BMTgnyZts6Sg5zdnzYnnt+n/Q/qN5M0VsxNyKdumht+LBZN75MN6y2ROYDz3cFWNIT1ACnn3fcmhZRr5uYk+BBiwKEsJbIHyeOgRC7S1NjheTmtXzDtbmZnfo6NQ7Z1EK41z9RTSbGENrQi5/HG6HzH246WTXGMxskl/e+EV9b1ez14r3klAj/mAmM958IiXtpxLec41sO0t4rrjFSz0mBqD9uMFRUL2st9HAQsEfpEyvQensS14mKV2d7bMCJGAHe/CrANSFR720HE9phn9fHD7rene9 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230016)(4636009)(396003)(346002)(136003)(376002)(39860400002)(36840700001)(40470700004)(46966006)(6666004)(41300700001)(2906002)(7696005)(26005)(336012)(186003)(44832011)(5660300002)(40460700003)(86362001)(47076005)(426003)(16526019)(2616005)(83380400001)(1076003)(478600001)(8936002)(36860700001)(110136005)(36756003)(82310400005)(316002)(54906003)(8676002)(82740400003)(40480700001)(70206006)(70586007)(356005)(4326008)(81166007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jul 2022 13:44:14.4259 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 200eba34-e695-4500-48b4-08da6f0cedcd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT005.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4147 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In order to support AVIC on SNP-enabled system, The IOMMU driver needs to check EFR2[SNPAVICSup] and enables the support by setting SNPAVICEn bit in the IOMMU control register (MMIO offset 18h). For detail, please see section "SEV-SNP Guest Virtual APIC Support" of the AMD I/O Virtualization Technology (IOMMU) Specification. (https://www.amd.com/system/files/TechDocs/48882_IOMMU.pdf) Signed-off-by: Suravee Suthikulpanit Reviewed-by: Jerry Snitselaar --- drivers/iommu/amd/amd_iommu_types.h | 7 +++++++ drivers/iommu/amd/init.c | 11 ++++++++++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 3c1205ba636a..5b1019dab328 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -103,6 +103,12 @@ #define FEATURE_GLXVAL_SHIFT 14 #define FEATURE_GLXVAL_MASK (0x03ULL << FEATURE_GLXVAL_SHIFT) =20 +/* Extended Feature 2 Bits */ +#define FEATURE_SNPAVICSUP_SHIFT 5 +#define FEATURE_SNPAVICSUP_MASK (0x07ULL << FEATURE_SNPAVICSUP_SHIFT) +#define FEATURE_SNPAVICSUP_GAM(x) \ + ((x & FEATURE_SNPAVICSUP_MASK) >> FEATURE_SNPAVICSUP_SHIFT =3D=3D 0x1) + /* Note: * The current driver only support 16-bit PASID. * Currently, hardware only implement upto 16-bit PASID @@ -165,6 +171,7 @@ #define CONTROL_GAINT_EN 29 #define CONTROL_XT_EN 50 #define CONTROL_INTCAPXT_EN 51 +#define CONTROL_SNPAVIC_EN 61 =20 #define CTRL_INV_TO_MASK (7 << CONTROL_INV_TIMEOUT) #define CTRL_INV_TO_NONE 0 diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 4cd94d716122..6bbaf6b971e8 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -2794,13 +2794,22 @@ static void enable_iommus_vapic(void) return; } =20 - /* Enabling GAM support */ + if (amd_iommu_snp_en && + !FEATURE_SNPAVICSUP_GAM(amd_iommu_efr2)) { + pr_warn("Force to disable Virtual APIC due to SNP\n"); + amd_iommu_guest_ir =3D AMD_IOMMU_GUEST_IR_LEGACY_GA; + return; + } + + /* Enabling GAM and SNPAVIC support */ for_each_iommu(iommu) { if (iommu_init_ga_log(iommu) || iommu_ga_log_enable(iommu)) return; =20 iommu_feature_enable(iommu, CONTROL_GAM_EN); + if (amd_iommu_snp_en) + iommu_feature_enable(iommu, CONTROL_SNPAVIC_EN); } =20 amd_iommu_irq_ops.capability |=3D (1 << IRQ_POSTING_CAP); --=20 2.34.1