From nobody Wed May 15 21:36:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C508C433EF for ; Tue, 26 Jul 2022 06:29:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238065AbiGZG3I (ORCPT ); Tue, 26 Jul 2022 02:29:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237717AbiGZG27 (ORCPT ); Tue, 26 Jul 2022 02:28:59 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9795623F; Mon, 25 Jul 2022 23:28:57 -0700 (PDT) X-UUID: b90dd3d6a44843dd9249f7a24c599351-20220726 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8,REQID:0d4748df-4bba-482e-bd9e-e508d97c9f26,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:-5 X-CID-META: VersionHash:0f94e32,CLOUDID:5012f4d3-912a-458b-a623-74f605a77e93,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: b90dd3d6a44843dd9249f7a24c599351-20220726 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1321559032; Tue, 26 Jul 2022 14:28:49 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Tue, 26 Jul 2022 14:28:47 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 26 Jul 2022 14:28:45 +0800 From: Axe Yang To: Ulf Hansson , Rob Herring , Chaotian Jing , Matthias Brugger , Adrian Hunter CC: Yoshihiro Shimoda , Satya Tangirala , Andy Shevchenko , Wolfram Sang , Axe Yang , Lucas Stach , Eric Biggers , Andrew Jeffery , Stephen Boyd , Kiwoong Kim , Yue Hu , Tian Tao , , , , , , , , Rob Herring Subject: [PATCH v14 1/3] dt-bindings: mmc: mtk-sd: extend interrupts and pinctrls properties Date: Tue, 26 Jul 2022 14:28:40 +0800 Message-ID: <20220726062842.18846-2-axe.yang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220726062842.18846-1-axe.yang@mediatek.com> References: <20220726062842.18846-1-axe.yang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Extend interrupts and pinctrls for SDIO wakeup interrupt feature. This feature allow SDIO devices alarm asynchronous interrupt to host even when host stop providing clock to SDIO card. An extra wakeup interrupt and pinctrl states for SDIO DAT1 pin state switching are required in this scenario. Reviewed-by: Rob Herring Signed-off-by: Axe Yang Reviewed-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/mmc/mtk-sd.yaml | 50 ++++++++++++++++++- 1 file changed, 49 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentat= ion/devicetree/bindings/mmc/mtk-sd.yaml index be366cefffc2..083d1ec2f661 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml @@ -70,12 +70,27 @@ properties: - const: ahb_cg =20 interrupts: - maxItems: 1 + description: + Should at least contain MSDC GIC interrupt. To support SDIO in-band = wakeup, an extended + interrupt is required and be configured as wakeup source irq. + minItems: 1 + maxItems: 2 + + interrupt-names: + items: + - const: msdc + - const: sdio_wakeup =20 pinctrl-names: + description: + Should at least contain default and state_uhs. To support SDIO in-ba= nd wakeup, dat1 pin + will be switched between GPIO mode and SDIO DAT1 mode, state_eint is= mandatory in this + scenario. + minItems: 2 items: - const: default - const: state_uhs + - const: state_eint =20 pinctrl-0: description: @@ -87,6 +102,11 @@ properties: should contain uhs mode pin ctrl. maxItems: 1 =20 + pinctrl-2: + description: + should switch dat1 pin to GPIO mode. + maxItems: 1 + assigned-clocks: description: PLL of the source clock. @@ -206,4 +226,32 @@ examples: mediatek,hs400-cmd-resp-sel-rising; }; =20 + mmc3: mmc@11260000 { + compatible =3D "mediatek,mt8173-mmc"; + reg =3D <0x11260000 0x1000>; + clock-names =3D "source", "hclk"; + clocks =3D <&pericfg CLK_PERI_MSDC30_3>, + <&topckgen CLK_TOP_MSDC50_2_H_SEL>; + interrupt-names =3D "msdc", "sdio_wakeup"; + interrupts-extended =3D <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_LOW 0>, + <&pio 23 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default", "state_uhs", "state_eint"; + pinctrl-0 =3D <&mmc2_pins_default>; + pinctrl-1 =3D <&mmc2_pins_uhs>; + pinctrl-2 =3D <&mmc2_pins_eint>; + bus-width =3D <4>; + max-frequency =3D <200000000>; + cap-sd-highspeed; + sd-uhs-sdr104; + keep-power-in-suspend; + wakeup-source; + cap-sdio-irq; + no-mmc; + no-sd; + non-removable; + vmmc-supply =3D <&sdio_fixed_3v3>; + vqmmc-supply =3D <&mt6397_vgp3_reg>; + mmc-pwrseq =3D <&wifi_pwrseq>; + }; + ... --=20 2.25.1 From nobody Wed May 15 21:36:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32FBDC433EF for ; Tue, 26 Jul 2022 06:29:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237640AbiGZG3E (ORCPT ); Tue, 26 Jul 2022 02:29:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237541AbiGZG26 (ORCPT ); Tue, 26 Jul 2022 02:28:58 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C5845BA; Mon, 25 Jul 2022 23:28:56 -0700 (PDT) X-UUID: 043c1f77d86644dd90201672843001df-20220726 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8,REQID:4f505ee3-9bd3-4a87-a829-6a97538d13c5,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:-5 X-CID-META: VersionHash:0f94e32,CLOUDID:4e12f4d3-912a-458b-a623-74f605a77e93,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: 043c1f77d86644dd90201672843001df-20220726 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 758254670; Tue, 26 Jul 2022 14:28:50 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Tue, 26 Jul 2022 14:28:49 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 26 Jul 2022 14:28:47 +0800 From: Axe Yang To: Ulf Hansson , Rob Herring , Chaotian Jing , Matthias Brugger , Adrian Hunter CC: Yoshihiro Shimoda , Satya Tangirala , Andy Shevchenko , Wolfram Sang , Axe Yang , Lucas Stach , Eric Biggers , Andrew Jeffery , Stephen Boyd , Kiwoong Kim , Yue Hu , Tian Tao , , , , , , , Subject: [PATCH v14 2/3] mmc: core: Add support for SDIO wakeup interrupt Date: Tue, 26 Jul 2022 14:28:41 +0800 Message-ID: <20220726062842.18846-3-axe.yang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220726062842.18846-1-axe.yang@mediatek.com> References: <20220726062842.18846-1-axe.yang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If wakeup-source flag is set in host dts node, parse EAI information from SDIO CCCR interrupt externsion segment for in-band wakeup. If async interrupt is supported by SDIO card then enable it and set enable_async_irq flag in sdio_cccr structure to 1. The parse flow is implemented in sdio_read_cccr(). Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Axe Yang --- drivers/mmc/core/sdio.c | 14 ++++++++++++++ include/linux/mmc/card.h | 8 +++++++- include/linux/mmc/sdio.h | 5 +++++ 3 files changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/core/sdio.c b/drivers/mmc/core/sdio.c index b589df1c35e0..0b682a31cd3e 100644 --- a/drivers/mmc/core/sdio.c +++ b/drivers/mmc/core/sdio.c @@ -226,6 +226,20 @@ static int sdio_read_cccr(struct mmc_card *card, u32 o= cr) card->sw_caps.sd3_drv_type |=3D SD_DRIVER_TYPE_C; if (data & SDIO_DRIVE_SDTD) card->sw_caps.sd3_drv_type |=3D SD_DRIVER_TYPE_D; + + ret =3D mmc_io_rw_direct(card, 0, 0, SDIO_CCCR_INTERRUPT_EXT, 0, &data); + if (ret) + goto out; + + if (data & SDIO_INTERRUPT_EXT_SAI) { + data |=3D SDIO_INTERRUPT_EXT_EAI; + ret =3D mmc_io_rw_direct(card, 1, 0, SDIO_CCCR_INTERRUPT_EXT, + data, NULL); + if (ret) + goto out; + + card->cccr.enable_async_irq =3D 1; + } } =20 /* if no uhs mode ensure we check for high speed */ diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h index 156a7b673a28..8a30de08e913 100644 --- a/include/linux/mmc/card.h +++ b/include/linux/mmc/card.h @@ -219,7 +219,8 @@ struct sdio_cccr { wide_bus:1, high_power:1, high_speed:1, - disable_cd:1; + disable_cd:1, + enable_async_irq:1; }; =20 struct sdio_cis { @@ -343,6 +344,11 @@ static inline bool mmc_large_sector(struct mmc_card *c= ard) return card->ext_csd.data_sector_size =3D=3D 4096; } =20 +static inline int mmc_card_enable_async_irq(struct mmc_card *card) +{ + return card->cccr.enable_async_irq; +} + bool mmc_card_is_blockaddr(struct mmc_card *card); =20 #define mmc_card_mmc(c) ((c)->type =3D=3D MMC_TYPE_MMC) diff --git a/include/linux/mmc/sdio.h b/include/linux/mmc/sdio.h index 2a05d1ac4f0e..1ef400f28642 100644 --- a/include/linux/mmc/sdio.h +++ b/include/linux/mmc/sdio.h @@ -159,6 +159,11 @@ #define SDIO_DTSx_SET_TYPE_A (1 << SDIO_DRIVE_DTSx_SHIFT) #define SDIO_DTSx_SET_TYPE_C (2 << SDIO_DRIVE_DTSx_SHIFT) #define SDIO_DTSx_SET_TYPE_D (3 << SDIO_DRIVE_DTSx_SHIFT) + +#define SDIO_CCCR_INTERRUPT_EXT 0x16 +#define SDIO_INTERRUPT_EXT_SAI (1 << 0) +#define SDIO_INTERRUPT_EXT_EAI (1 << 1) + /* * Function Basic Registers (FBR) */ --=20 2.25.1 From nobody Wed May 15 21:36:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5976EC43334 for ; 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Tue, 26 Jul 2022 14:28:52 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Tue, 26 Jul 2022 14:28:51 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 26 Jul 2022 14:28:48 +0800 From: Axe Yang To: Ulf Hansson , Rob Herring , Chaotian Jing , Matthias Brugger , Adrian Hunter CC: Yoshihiro Shimoda , Satya Tangirala , Andy Shevchenko , Wolfram Sang , Axe Yang , Lucas Stach , Eric Biggers , Andrew Jeffery , Stephen Boyd , Kiwoong Kim , Yue Hu , Tian Tao , , , , , , , , Yong Mao , Linus Walleij Subject: [PATCH v14 3/3] mmc: mediatek: add support for SDIO eint wakup IRQ Date: Tue, 26 Jul 2022 14:28:42 +0800 Message-ID: <20220726062842.18846-4-axe.yang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220726062842.18846-1-axe.yang@mediatek.com> References: <20220726062842.18846-1-axe.yang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for eint IRQ when MSDC is used as an SDIO host. This feature requires SDIO device support async IRQ function. With this feature, SDIO host can be awakened by SDIO card in suspend state, without additional pin. MSDC driver will time-share the SDIO DAT1 pin. During suspend, MSDC turn off clock and switch SDIO DAT1 pin to GPIO mode. And during resume, switch GPIO function back to DAT1 mode then turn on clock. Some device tree property should be added or modified in MSDC node to support SDIO eint IRQ. Pinctrls "state_eint" is mandatory. Since this feature depends on asynchronous interrupts, "wakeup-source", "keep-power-in-suspend" and "cap-sdio-irq" flags are necessary, and the interrupts list should be extended(the interrupt named with sdio_wakeup): &mmcX { ... interrupt-names =3D "msdc", "sdio_wakeup"; interrupts-extended =3D <...>, <&pio xxx IRQ_TYPE_LEVEL_LOW>; ... pinctrl-names =3D "default", "state_uhs", "state_eint"; ... pinctrl-2 =3D <&mmc2_pins_eint>; ... cap-sdio-irq; keep-power-in-suspend; wakeup-source; ... }; Co-developed-by: Yong Mao Signed-off-by: Yong Mao Reviewed-by: Chaotian Jing Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Linus Walleij Signed-off-by: Axe Yang --- drivers/mmc/host/mtk-sd.c | 86 ++++++++++++++++++++++++++++++++++++--- 1 file changed, 80 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index a4954b200d87..4ff73d1883de 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2014-2015 MediaTek Inc. + * Copyright (c) 2014-2015, 2022 MediaTek Inc. * Author: Chaotian.Jing */ =20 @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -440,8 +441,10 @@ struct msdc_host { struct pinctrl *pinctrl; struct pinctrl_state *pins_default; struct pinctrl_state *pins_uhs; + struct pinctrl_state *pins_eint; struct delayed_work req_timeout; int irq; /* host interrupt */ + int eint_irq; /* interrupt from sdio device for waking up system */ struct reset_control *reset; =20 struct clk *src_clk; /* msdc source clock */ @@ -1521,17 +1524,46 @@ static void __msdc_enable_sdio_irq(struct msdc_host= *host, int enb) =20 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) { - unsigned long flags; struct msdc_host *host =3D mmc_priv(mmc); + unsigned long flags; + int ret; =20 spin_lock_irqsave(&host->lock, flags); __msdc_enable_sdio_irq(host, enb); spin_unlock_irqrestore(&host->lock, flags); =20 - if (enb) - pm_runtime_get_noresume(host->dev); - else - pm_runtime_put_noidle(host->dev); + if (mmc_card_enable_async_irq(mmc->card) && host->pins_eint) { + if (enb) { + /* + * In dev_pm_set_dedicated_wake_irq_reverse(), eint pin will be set to + * GPIO mode. We need to restore it to SDIO DAT1 mode after that. + * Since the current pinstate is pins_uhs, to ensure pinctrl select take + * affect successfully, we change the pinstate to pins_eint firstly. + */ + pinctrl_select_state(host->pinctrl, host->pins_eint); + ret =3D dev_pm_set_dedicated_wake_irq_reverse(host->dev, host->eint_irq= ); + + if (ret) { + dev_err(host->dev, "Failed to register SDIO wakeup irq!\n"); + host->pins_eint =3D NULL; + pm_runtime_get_noresume(host->dev); + } else { + dev_dbg(host->dev, "SDIO eint irq: %d!\n", host->eint_irq); + } + + pinctrl_select_state(host->pinctrl, host->pins_uhs); + } else { + dev_pm_clear_wake_irq(host->dev); + } + } else { + if (enb) { + /* Ensure host->pins_eint is NULL */ + host->pins_eint =3D NULL; + pm_runtime_get_noresume(host->dev); + } else { + pm_runtime_put_noidle(host->dev); + } + } } =20 static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts) @@ -2635,6 +2667,20 @@ static int msdc_drv_probe(struct platform_device *pd= ev) goto host_free; } =20 + /* Support for SDIO eint irq ? */ + if ((mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ) && (mmc->pm_caps & MMC_PM_KEEP_= POWER)) { + host->eint_irq =3D platform_get_irq_byname(pdev, "sdio_wakeup"); + if (host->eint_irq > 0) { + host->pins_eint =3D pinctrl_lookup_state(host->pinctrl, "state_eint"); + if (IS_ERR(host->pins_eint)) { + dev_err(&pdev->dev, "Cannot find pinctrl eint!\n"); + host->pins_eint =3D NULL; + } else { + device_init_wakeup(&pdev->dev, true); + } + } + } + msdc_of_property_parse(pdev, host); =20 host->dev =3D &pdev->dev; @@ -2849,6 +2895,15 @@ static int __maybe_unused msdc_runtime_suspend(struc= t device *dev) struct msdc_host *host =3D mmc_priv(mmc); =20 msdc_save_reg(host); + + if (sdio_irq_claimed(mmc)) { + if (host->pins_eint) { + disable_irq(host->irq); + pinctrl_select_state(host->pinctrl, host->pins_eint); + } + + __msdc_enable_sdio_irq(host, 0); + } msdc_gate_clock(host); return 0; } @@ -2864,12 +2919,18 @@ static int __maybe_unused msdc_runtime_resume(struc= t device *dev) return ret; =20 msdc_restore_reg(host); + + if (sdio_irq_claimed(mmc) && host->pins_eint) { + pinctrl_select_state(host->pinctrl, host->pins_uhs); + enable_irq(host->irq); + } return 0; } =20 static int __maybe_unused msdc_suspend(struct device *dev) { struct mmc_host *mmc =3D dev_get_drvdata(dev); + struct msdc_host *host =3D mmc_priv(mmc); int ret; =20 if (mmc->caps2 & MMC_CAP2_CQE) { @@ -2878,11 +2939,24 @@ static int __maybe_unused msdc_suspend(struct devic= e *dev) return ret; } =20 + /* + * Bump up runtime PM usage counter otherwise dev->power.needs_force_resu= me will + * not be marked as 1, pm_runtime_force_resume() will go out directly. + */ + if (sdio_irq_claimed(mmc) && host->pins_eint) + pm_runtime_get_noresume(dev); + return pm_runtime_force_suspend(dev); } =20 static int __maybe_unused msdc_resume(struct device *dev) { + struct mmc_host *mmc =3D dev_get_drvdata(dev); + struct msdc_host *host =3D mmc_priv(mmc); + + if (sdio_irq_claimed(mmc) && host->pins_eint) + pm_runtime_put_noidle(dev); + return pm_runtime_force_resume(dev); } =20 --=20 2.25.1