From nobody Sat Sep 21 19:38:01 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 589F7C433EF for ; Mon, 25 Jul 2022 08:19:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232941AbiGYIT0 (ORCPT ); Mon, 25 Jul 2022 04:19:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37524 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232149AbiGYITM (ORCPT ); Mon, 25 Jul 2022 04:19:12 -0400 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 626A213CF7 for ; Mon, 25 Jul 2022 01:19:10 -0700 (PDT) Received: by mail-wm1-x329.google.com with SMTP id j29-20020a05600c1c1d00b003a2fdafdefbso5872101wms.2 for ; Mon, 25 Jul 2022 01:19:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1uBINhkXj5CiEZH5/8Pm1Qj/TstsEH9+dcozESvLJgY=; b=4VWKR6bZmkYqrWq3HipPRaTMH3acCvx2/KBXfW0kxl0JLH2/QaFB5eScM72+FYuodm 1Ps0q3GVeNhtTBshvFoBo3Tg+luJAwRx41Xw2WtnWBJxDGW50QVjM//ZZ7wJvEAAosnM +Cpv9WmVQCiCmjmJ29j2Y2wEiCmig/9I5iyCVcpCZU1JQbrbcqLFkcPaZk6vTFVvSO4k r8HNjXFoAY4onmMo4mvQFeERGQPpAGzZMSpw4mwbD9NsJwuInYdD0TxA5EmnAe/IvGxy VFPQIIeLE0FjcUp5Z8aNVQnik0SGEXiA3bBapqYfkjetq4LhdY5qx9raqdGyxVn92K0p hIIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1uBINhkXj5CiEZH5/8Pm1Qj/TstsEH9+dcozESvLJgY=; b=5UjJR2o5A+/Myg6GqLlZBEVsZMLzNUwkhf9tQCHIHdLpstk5RE6faLmbnO0XVOxTFl GX/UaEWSZo3JFanCXXHM7lUEaIfTwrzdYVRVQ3GB0YfqA7dxPEDZu1Wlc/CmxDFrHlnN lGfSoYSi+cv8WEWuKTTdwIdn4W5M7ltCq40ReNEE6F0FDsRKUmRSWsyIY7QyFq+ilmIq Ejfg3KMaan8xtIH2D7VSOiaIixoaTA4yHiCLeCun1jO3CAb4HUwB7/O/A6+EJLhuP4E+ AnQ43Z1c8sIMFNe+G61ZZosbenR14BeUz87lmOsKmcgUY+eyNlPS1f/NMc7XDS3AsDRI HcfQ== X-Gm-Message-State: AJIora8ioGqmWAHNE1oevA71Ft8Re0K0IsYsf7Z4A44qSW/w76C7GFEG Ipo7ws1O3kn9Nejbp4KTxFKzfQ== X-Google-Smtp-Source: AGRyM1vVJst7/Aus6G68zbPeB5sjlhQjFaxS3scwhOLz5W4CplCDcGNlIQKvOud+yzBrYFf/TaeraA== X-Received: by 2002:a7b:c851:0:b0:3a3:19df:2673 with SMTP id c17-20020a7bc851000000b003a319df2673mr7533079wml.75.1658737148896; Mon, 25 Jul 2022 01:19:08 -0700 (PDT) Received: from blmsp.fritz.box ([2001:4090:a243:806e:25e7:daa:8208:ceb]) by smtp.gmail.com with ESMTPSA id x3-20020a05600c420300b003a3200bc788sm16695264wmh.33.2022.07.25.01.19.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Jul 2022 01:19:08 -0700 (PDT) From: Markus Schneider-Pargmann To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Weiyi Lu Cc: Fabien Parent , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Fabien Parent , Markus Schneider-Pargmann Subject: [PATCH v2 1/4] dt-bindings: power: Add MT8365 power domains Date: Mon, 25 Jul 2022 10:18:50 +0200 Message-Id: <20220725081853.1636444-2-msp@baylibre.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220725081853.1636444-1-msp@baylibre.com> References: <20220725081853.1636444-1-msp@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Fabien Parent Add power domains dt-bindings for MT8365. Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann --- Notes: Changes in v2: - Made include/dt-bindings/power/mt8365-power.h dual-license. .../power/mediatek,power-controller.yaml | 2 ++ include/dt-bindings/power/mt8365-power.h | 19 +++++++++++++++++++ 2 files changed, 21 insertions(+) create mode 100644 include/dt-bindings/power/mt8365-power.h diff --git a/Documentation/devicetree/bindings/power/mediatek,power-control= ler.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controlle= r.yaml index 135c6f722091..2c6d3e4246b2 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -29,6 +29,7 @@ properties: - mediatek,mt8186-power-controller - mediatek,mt8192-power-controller - mediatek,mt8195-power-controller + - mediatek,mt8365-power-controller =20 '#power-domain-cells': const: 1 @@ -67,6 +68,7 @@ patternProperties: "include/dt-bindings/power/mt8183-power.h" - for MT8183 type= power domain. "include/dt-bindings/power/mt8192-power.h" - for MT8192 type= power domain. "include/dt-bindings/power/mt8195-power.h" - for MT8195 type= power domain. + "include/dt-bindings/power/mt8365-power.h" - for MT8365 type= power domain. maxItems: 1 =20 clocks: diff --git a/include/dt-bindings/power/mt8365-power.h b/include/dt-bindings= /power/mt8365-power.h new file mode 100644 index 000000000000..e6cfd0ec7871 --- /dev/null +++ b/include/dt-bindings/power/mt8365-power.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2022 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_POWER_MT8365_POWER_H +#define _DT_BINDINGS_POWER_MT8365_POWER_H + +#define MT8365_POWER_DOMAIN_MM 0 +#define MT8365_POWER_DOMAIN_CONN 1 +#define MT8365_POWER_DOMAIN_MFG 2 +#define MT8365_POWER_DOMAIN_AUDIO 3 +#define MT8365_POWER_DOMAIN_CAM 4 +#define MT8365_POWER_DOMAIN_DSP 5 +#define MT8365_POWER_DOMAIN_VDEC 6 +#define MT8365_POWER_DOMAIN_VENC 7 +#define MT8365_POWER_DOMAIN_APU 8 + +#endif /* _DT_BINDINGS_POWER_MT8365_POWER_H */ --=20 2.36.1 From nobody Sat Sep 21 19:38:01 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F277FC433EF for ; Mon, 25 Jul 2022 08:19:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233877AbiGYITf (ORCPT ); Mon, 25 Jul 2022 04:19:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37536 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232879AbiGYITN (ORCPT ); Mon, 25 Jul 2022 04:19:13 -0400 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D3E5813CFA for ; Mon, 25 Jul 2022 01:19:11 -0700 (PDT) Received: by mail-wm1-x32e.google.com with SMTP id ay11-20020a05600c1e0b00b003a3013da120so8853057wmb.5 for ; Mon, 25 Jul 2022 01:19:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rREHSjcfjpQHk4UrVZdBRlfSt+1lfTPjdekI0y3kZ04=; b=D56mAjLu+4DO0gYwFOIfTQoMPShxKAu9iqoLUzuAHDtYvr96HxZ4K8nWVi0emxOsdC GdOmL7lPLnAfs9ijm+KFBpT6tbGjfIZuapL0IxrUTXZ1V/o10UgD28U8tT70XTOPJdik fv5akro7XWCv7tF5D7GELbMONuk9HIBGFTZ3oLBMgVfQnX5qaagIMxyfnsiYuyBHHvFa bznbRwgn+gGqKgP1JxhjDVtw+2qcinXU7LuImk9iiRKU4iDX2DEt3T+SF2H0iYfPd8pI hkCNprZYObiZbtnZHTTRp0pS2SsI2xNWoTa/UTiDTz+dN/FNAPIf5W8jpuz/fRnjnTT7 wMjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rREHSjcfjpQHk4UrVZdBRlfSt+1lfTPjdekI0y3kZ04=; b=4tC5Gr5gN58GSQBPRSQbhIvyV5MqVpzX/oYXomlLu9UfaiMi9efibTJ8VNWQMqNih7 ITvKOx8nSx8aZKl0ug3mBLyriWCr6CvnWiPuWuE7zwrUASbHioKuec99TFwuAKkAvwjG qnY9uYh1asN9iTeQYx5BMhCZCffY3PTdU/bmJZfBbo45Ydr2/Pv7dbRc76aJbO4KkfR1 EnHptTJPB+EpxQUCaXQdmpcAx2Q/w69UteJWtGWqAzlJIObqWdQO32LA98Ld7Dq0hqel VCwNNPoc5jAhKlreGJxaYFQZL3m/VrhzJ5U8kb+yk8fsNA8iTl/d9Rp3JahYpN9NlqJ9 F/Ww== X-Gm-Message-State: AJIora+PhURO/tbfYTXUBJwMthlsnUjWyx+D5P4n4WVYEJu9dXpvEWFG q26l6+RyHOghd1+TrEaYmFVX9mlUqL+atA== X-Google-Smtp-Source: AGRyM1vqDUKigQoG3ZcH0lsHrxYYImD6MOwA/s7sNlVJpsXootKiw4xE/A7jZKRVkC3sldrBKnN6rg== X-Received: by 2002:a05:600c:c6:b0:3a3:ea8:7995 with SMTP id u6-20020a05600c00c600b003a30ea87995mr7653425wmm.135.1658737150258; Mon, 25 Jul 2022 01:19:10 -0700 (PDT) Received: from blmsp.fritz.box ([2001:4090:a243:806e:25e7:daa:8208:ceb]) by smtp.gmail.com with ESMTPSA id x3-20020a05600c420300b003a3200bc788sm16695264wmh.33.2022.07.25.01.19.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Jul 2022 01:19:09 -0700 (PDT) From: Markus Schneider-Pargmann To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Weiyi Lu Cc: Fabien Parent , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Alexandre Bailon , Fabien Parent , Markus Schneider-Pargmann Subject: [PATCH v2 2/4] soc: mediatek: Add support of WAY_EN operations Date: Mon, 25 Jul 2022 10:18:51 +0200 Message-Id: <20220725081853.1636444-3-msp@baylibre.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220725081853.1636444-1-msp@baylibre.com> References: <20220725081853.1636444-1-msp@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Alexandre Bailon This updates the power domain to support WAY_EN operations. These operations enable a path between different units of the chip and are labeled as 'way_en' in the register descriptions. This operation is required by the mt8365 for the MM power domain. Signed-off-by: Alexandre Bailon Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann --- Notes: Changes in v2: - some minor style fixes. - Renamed 'wayen' to 'way_en' to clarify the meaning - Updated commit message drivers/soc/mediatek/mtk-pm-domains.c | 64 +++++++++++++++++++++------ drivers/soc/mediatek/mtk-pm-domains.h | 28 +++++++----- 2 files changed, 68 insertions(+), 24 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/m= tk-pm-domains.c index 5ced254b082b..d0eae2227813 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -44,6 +44,7 @@ struct scpsys_domain { struct clk_bulk_data *subsys_clks; struct regmap *infracfg; struct regmap *smi; + struct regmap *infracfg_nao; struct regulator *supply; }; =20 @@ -116,23 +117,38 @@ static int scpsys_sram_disable(struct scpsys_domain *= pd) MTK_POLL_TIMEOUT); } =20 -static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *b= pd, struct regmap *regmap) +static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *b= pd, + struct regmap *regmap, struct regmap *infracfg_nao) { int i, ret; =20 for (i =3D 0; i < SPM_MAX_BUS_PROT_DATA; i++) { - u32 val, mask =3D bpd[i].bus_prot_mask; + u32 mask =3D bpd[i].bus_prot_mask; + u32 val =3D mask, sta_mask =3D mask; + struct regmap *ack_regmap =3D regmap; =20 if (!mask) break; =20 + if (bpd[i].way_en) { + if (!infracfg_nao) + return -ENODEV; + + val =3D 0; + sta_mask =3D bpd[i].bus_prot_sta_mask; + ack_regmap =3D infracfg_nao; + } + if (bpd[i].bus_prot_reg_update) - regmap_set_bits(regmap, bpd[i].bus_prot_set, mask); + regmap_update_bits(regmap, bpd[i].bus_prot_set, mask, val); else regmap_write(regmap, bpd[i].bus_prot_set, mask); =20 - ret =3D regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta, - val, (val & mask) =3D=3D mask, + if (bpd[i].ignore_clr_ack) + continue; + + ret =3D regmap_read_poll_timeout(ack_regmap, bpd[i].bus_prot_sta, + val, (val & sta_mask) =3D=3D sta_mask, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); if (ret) return ret; @@ -145,34 +161,49 @@ static int scpsys_bus_protect_enable(struct scpsys_do= main *pd) { int ret; =20 - ret =3D _scpsys_bus_protect_enable(pd->data->bp_infracfg, pd->infracfg); + ret =3D _scpsys_bus_protect_enable(pd->data->bp_infracfg, + pd->infracfg, pd->infracfg_nao); if (ret) return ret; =20 - return _scpsys_bus_protect_enable(pd->data->bp_smi, pd->smi); + return _scpsys_bus_protect_enable(pd->data->bp_smi, pd->smi, NULL); } =20 +#define mask_cond(way_en, val, mask) \ + ((way_en && ((val & mask) =3D=3D mask)) || (!way_en && !(val & mask))) + static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *= bpd, - struct regmap *regmap) + struct regmap *regmap, struct regmap *infracfg_nao) { int i, ret; =20 for (i =3D SPM_MAX_BUS_PROT_DATA - 1; i >=3D 0; i--) { - u32 val, mask =3D bpd[i].bus_prot_mask; + u32 val =3D 0, mask =3D bpd[i].bus_prot_mask; + u32 sta_mask =3D mask; + struct regmap *ack_regmap =3D regmap; =20 if (!mask) continue; =20 + if (bpd[i].way_en) { + if (!infracfg_nao) + return -ENODEV; + + val =3D mask; + sta_mask =3D bpd[i].bus_prot_sta_mask; + ack_regmap =3D infracfg_nao; + } + if (bpd[i].bus_prot_reg_update) - regmap_clear_bits(regmap, bpd[i].bus_prot_clr, mask); + regmap_update_bits(regmap, bpd[i].bus_prot_clr, mask, val); else regmap_write(regmap, bpd[i].bus_prot_clr, mask); =20 if (bpd[i].ignore_clr_ack) continue; =20 - ret =3D regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta, - val, !(val & mask), + ret =3D regmap_read_poll_timeout(ack_regmap, bpd[i].bus_prot_sta, + val, mask_cond(bpd[i].way_en, val, sta_mask), MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); if (ret) return ret; @@ -185,11 +216,12 @@ static int scpsys_bus_protect_disable(struct scpsys_d= omain *pd) { int ret; =20 - ret =3D _scpsys_bus_protect_disable(pd->data->bp_smi, pd->smi); + ret =3D _scpsys_bus_protect_disable(pd->data->bp_smi, pd->smi, NULL); if (ret) return ret; =20 - return _scpsys_bus_protect_disable(pd->data->bp_infracfg, pd->infracfg); + return _scpsys_bus_protect_disable(pd->data->bp_infracfg, + pd->infracfg, pd->infracfg_nao); } =20 static int scpsys_regulator_enable(struct regulator *supply) @@ -363,6 +395,10 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys= *scpsys, struct device_no return ERR_CAST(pd->smi); } =20 + pd->infracfg_nao =3D syscon_regmap_lookup_by_phandle_optional(node, "medi= atek,infracfg_nao"); + if (IS_ERR(pd->infracfg_nao)) + return ERR_CAST(pd->infracfg_nao); + num_clks =3D of_clk_get_parent_count(node); if (num_clks > 0) { /* Calculate number of subsys_clks */ diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/m= tk-pm-domains.h index daa24e890dd4..e788d6bdde9d 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -39,23 +39,29 @@ =20 #define SPM_MAX_BUS_PROT_DATA 6 =20 -#define _BUS_PROT(_mask, _set, _clr, _sta, _update, _ignore) { \ - .bus_prot_mask =3D (_mask), \ - .bus_prot_set =3D _set, \ - .bus_prot_clr =3D _clr, \ - .bus_prot_sta =3D _sta, \ - .bus_prot_reg_update =3D _update, \ - .ignore_clr_ack =3D _ignore, \ +#define _BUS_PROT(_mask, _sta_mask, _set, _clr, _sta, _update, _ignore, _w= ay_en) { \ + .bus_prot_mask =3D (_mask), \ + .bus_prot_set =3D _set, \ + .bus_prot_clr =3D _clr, \ + .bus_prot_sta =3D _sta, \ + .bus_prot_sta_mask =3D _sta_mask, \ + .bus_prot_reg_update =3D _update, \ + .ignore_clr_ack =3D _ignore, \ + .way_en =3D _way_en, \ } =20 #define BUS_PROT_WR(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _sta, false, false) + _BUS_PROT(_mask, _mask, _set, _clr, _sta, false, false, false) =20 #define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _sta, false, true) + _BUS_PROT(_mask, _mask, _set, _clr, _sta, false, true, false) =20 #define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _sta, true, false) + _BUS_PROT(_mask, _mask, _set, _clr, _sta, true, false, false) + +#define BUS_PROT_WAY_EN(_en_mask, _sta_mask, _set, _sta) \ + _BUS_PROT(_en_mask, _sta_mask, _set, _set, _sta, true, false, \ + true) =20 #define BUS_PROT_UPDATE_TOPAXI(_mask) \ BUS_PROT_UPDATE(_mask, \ @@ -68,8 +74,10 @@ struct scpsys_bus_prot_data { u32 bus_prot_set; u32 bus_prot_clr; u32 bus_prot_sta; + u32 bus_prot_sta_mask; bool bus_prot_reg_update; bool ignore_clr_ack; + bool way_en; }; =20 /** --=20 2.36.1 From nobody Sat Sep 21 19:38:01 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E89FC433EF for ; Mon, 25 Jul 2022 08:19:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233897AbiGYITi (ORCPT ); Mon, 25 Jul 2022 04:19:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37556 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233495AbiGYITO (ORCPT ); Mon, 25 Jul 2022 04:19:14 -0400 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DF22513CD6 for ; Mon, 25 Jul 2022 01:19:12 -0700 (PDT) Received: by mail-wr1-x435.google.com with SMTP id u5so14853751wrm.4 for ; Mon, 25 Jul 2022 01:19:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=usxsP0K1Xc8cmseqwIYE6ZqiT92s9j11+9Dz8i0YM0g=; b=lv+HXPVhjb50QOdFMwn/gpk7Lionrt4BCfECLdNR9Hspn3noeqcc93vGQPMcdCDUTx qhnFcrQhGvnS3RekfHFvbZ5LXn2YhfxVLjbNmDuL/QLLOFsgVH7NM/iUcDAzLrKqrG5c 2uvAOHu9IZDbNHdLNyoL5SS+k2cT7yZqdrUxLVa5T6kZTc0LgBVj52D7HNHCG5ycTthB NNdU+vF33FmkBJcwTvSBgPi0quhj2q4o+aUvXloYBnyYITv0pzHOQCEtx/rXjFKGrmE9 cqwC2qKlWAF+zm3ZRW+vQcobEzJ+oz2tGh70NQwKumhg2KDi2izOik2P9vIfO7MkSzyI 3qPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=usxsP0K1Xc8cmseqwIYE6ZqiT92s9j11+9Dz8i0YM0g=; b=DALoMTHfWV3EXohd7bPK7VuJ2LHUCTn6P+5FPSpm+knYcK0BJqW+Ty4aMWCgZhyd5l 9hMhtSy92npDrGPu6b2aiNrvU43+IGsGkCh/QrfiGi0QGRC5TuivziZeoXeYc7JH4Lbm 8O7leRjHf+0WIRm1PZj91s5ppv7iRLj+/R5GT/nWnqCNyJNzZqMCOHyyCgNEm7hNrqXg 4WnY7GN3CZcsD0iJfF37olvy9Uk6qADHQHD0LCg7TeUKxNwXfRyDqp8Tr1UYi/FWicP2 FXL4Ln2tTu6p1sCteGTdYQ9uO4v/w57Oxg2yPWywLVn/3vN5EIq2Ri31faTOSVBZXbnB uhbA== X-Gm-Message-State: AJIora/58/jvAc5mq1cm9RT58whPUaTkwgdPSqqzLNChqaGwRWg4Q/s1 0TAHSf2LBJpVObIiS8B6AU5dJQ== X-Google-Smtp-Source: AGRyM1uyqjH/4hgu+UdZWfQezOgf1LqnW80TfiBg5gxjZZ5SFJbrEh87S3uipSb8IG/IhExuSyQQrA== X-Received: by 2002:adf:fbc3:0:b0:21e:3c88:2aa1 with SMTP id d3-20020adffbc3000000b0021e3c882aa1mr7168379wrs.84.1658737151472; Mon, 25 Jul 2022 01:19:11 -0700 (PDT) Received: from blmsp.fritz.box ([2001:4090:a243:806e:25e7:daa:8208:ceb]) by smtp.gmail.com with ESMTPSA id x3-20020a05600c420300b003a3200bc788sm16695264wmh.33.2022.07.25.01.19.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Jul 2022 01:19:11 -0700 (PDT) From: Markus Schneider-Pargmann To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Weiyi Lu Cc: Fabien Parent , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Alexandre Bailon , Fabien Parent , Markus Schneider-Pargmann Subject: [PATCH v2 3/4] soc: mediatek: add support of MTK_SCPD_STRICT_BUSP cap Date: Mon, 25 Jul 2022 10:18:52 +0200 Message-Id: <20220725081853.1636444-4-msp@baylibre.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220725081853.1636444-1-msp@baylibre.com> References: <20220725081853.1636444-1-msp@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Alexandre Bailon This adds support for MTK_SCPD_STRICT_BUSP capability. It is a strict bus protection policy that requires the bus protection to be disabled before accessing the bus. This is required by the mt8365, for the MM power domain. Signed-off-by: Alexandre Bailon Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann --- Notes: Changes in v2: - Fixup error handling path. drivers/soc/mediatek/mtk-pm-domains.c | 29 +++++++++++++++++++++++---- drivers/soc/mediatek/mtk-pm-domains.h | 1 + 2 files changed, 26 insertions(+), 4 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/m= tk-pm-domains.c index d0eae2227813..94ca8981f45e 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -240,6 +240,7 @@ static int scpsys_power_on(struct generic_pm_domain *ge= npd) struct scpsys *scpsys =3D pd->scpsys; bool tmp; int ret; + bool strict_busprotect; =20 ret =3D scpsys_regulator_enable(pd->supply); if (ret) @@ -263,9 +264,18 @@ static int scpsys_power_on(struct generic_pm_domain *g= enpd) regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT); regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); =20 - ret =3D clk_bulk_prepare_enable(pd->num_subsys_clks, pd->subsys_clks); - if (ret) - goto err_pwr_ack; + /* + * In few Mediatek platforms(e.g. MT6779), the bus protect policy is + * stricter, which leads to bus protect release must be prior to bus + * access. + */ + strict_busprotect =3D MTK_SCPD_CAPS(pd, MTK_SCPD_STRICT_BUSP); + if (!strict_busprotect) { + ret =3D clk_bulk_prepare_enable(pd->num_subsys_clks, + pd->subsys_clks); + if (ret) + goto err_pwr_ack; + } =20 ret =3D scpsys_sram_enable(pd); if (ret < 0) @@ -275,12 +285,23 @@ static int scpsys_power_on(struct generic_pm_domain *= genpd) if (ret < 0) goto err_disable_sram; =20 + if (strict_busprotect) { + ret =3D clk_bulk_prepare_enable(pd->num_subsys_clks, + pd->subsys_clks); + if (ret) + goto err_enable_bus_protect; + } + return 0; =20 +err_enable_bus_protect: + scpsys_bus_protect_enable(pd); err_disable_sram: scpsys_sram_disable(pd); err_disable_subsys_clks: - clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks); + if (!strict_busprotect) + clk_bulk_disable_unprepare(pd->num_subsys_clks, + pd->subsys_clks); err_pwr_ack: clk_bulk_disable_unprepare(pd->num_clks, pd->clks); err_reg: diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/m= tk-pm-domains.h index e788d6bdde9d..a50cfb926d22 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -8,6 +8,7 @@ #define MTK_SCPD_SRAM_ISO BIT(2) #define MTK_SCPD_KEEP_DEFAULT_OFF BIT(3) #define MTK_SCPD_DOMAIN_SUPPLY BIT(4) +#define MTK_SCPD_STRICT_BUSP BIT(5) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) =20 #define SPM_VDE_PWR_CON 0x0210 --=20 2.36.1 From nobody Sat Sep 21 19:38:01 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0503C433EF for ; Mon, 25 Jul 2022 08:19:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233905AbiGYITk (ORCPT ); Mon, 25 Jul 2022 04:19:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37568 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233597AbiGYITO (ORCPT ); Mon, 25 Jul 2022 04:19:14 -0400 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2DB1413CEF for ; Mon, 25 Jul 2022 01:19:13 -0700 (PDT) Received: by mail-wr1-x42f.google.com with SMTP id b26so14859395wrc.2 for ; Mon, 25 Jul 2022 01:19:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dbr3JQtMMaGq7OcYmkim964lJBjU8ButDLGYuZUJvkQ=; b=1iX+J+7nnRoL4osklN5L2LUeP86CSAeIYvLvha6uu8625huekLS5PAQNiiSQSSgjbd hg8jFLOfRzxZHiqHGrHV+C9MOlgVQrh8kVwLyxc9nZiQY+MJffzX2BXOep2otgwlWNxg 20iGzsG0QkHignxDaI+oCH7C75cWPVJfJ/dvbQ/i7zK9JEqqqJrxkO+B0a26edIhgwdI n2xhCwnHWySeGktv9L3a57V37OAJwZYgiSqe4F/kLCRTH2dsejT5fBAx7UocdUijAFAQ UmG1q8SjHOfh92ULDZsh0A+0Oe1CnXfWB646JEoQQnrig7A6JDG42YlSOr0NnqKEtZm7 x18w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dbr3JQtMMaGq7OcYmkim964lJBjU8ButDLGYuZUJvkQ=; b=ZOYbMsvnpS1UVmy3Txs3HXwJ/wgXQlRcoyweZfD7ZnwIu1hQSia5rwK71qQ8qZP6Bl DeQt1Miehn/w+TLKR4uBG4DBd5I+8Hy0YM8ig39ymCLoM+h74ja2rEiYj40nE1qG8siF FPvXb06wW+l78v9GITqghJE+2DkbanOU+/zbSpCYv7i6l0oG+PuiQB2XLU47VL/qPKW6 N7dL7iJ/397togVaT8qzwiA4rDlAv2b+MPw12pxnZyf+43uGx+8JABj7SQZMdSadBqvO /lN4qGgiSsOmFof4Gn0fyRNB+ysvlSwQtiraEsaurkYGOhRGuCKxwHG12bo8SIAOxO39 a5Zg== X-Gm-Message-State: AJIora+/j2nPOSRlJrfa46j1R0bCfuJ3OxRqN0LFgwI/1cSl2ViMiKNm BhJNGUhIkBkdToC9WCyFr+XtUg== X-Google-Smtp-Source: AGRyM1vrWcAbv6Sym5GPPlbiU+33ImFsuhdvIyZygsVu4w5jWmunJuEg11Fyb/W1Hr8BQkejekHRXw== X-Received: by 2002:a5d:6e8e:0:b0:21d:ea5:710f with SMTP id k14-20020a5d6e8e000000b0021d0ea5710fmr6828170wrz.48.1658737152701; Mon, 25 Jul 2022 01:19:12 -0700 (PDT) Received: from blmsp.fritz.box ([2001:4090:a243:806e:25e7:daa:8208:ceb]) by smtp.gmail.com with ESMTPSA id x3-20020a05600c420300b003a3200bc788sm16695264wmh.33.2022.07.25.01.19.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Jul 2022 01:19:12 -0700 (PDT) From: Markus Schneider-Pargmann To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Weiyi Lu Cc: Fabien Parent , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Fabien Parent , Markus Schneider-Pargmann Subject: [PATCH v2 4/4] soc: mediatek: pm-domains: Add support for MT8365 Date: Mon, 25 Jul 2022 10:18:53 +0200 Message-Id: <20220725081853.1636444-5-msp@baylibre.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220725081853.1636444-1-msp@baylibre.com> References: <20220725081853.1636444-1-msp@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Fabien Parent Add the needed board data to support MT8365 SoC. Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann --- drivers/soc/mediatek/mt8365-pm-domains.h | 147 +++++++++++++++++++++++ drivers/soc/mediatek/mtk-pm-domains.c | 5 + 2 files changed, 152 insertions(+) create mode 100644 drivers/soc/mediatek/mt8365-pm-domains.h diff --git a/drivers/soc/mediatek/mt8365-pm-domains.h b/drivers/soc/mediate= k/mt8365-pm-domains.h new file mode 100644 index 000000000000..011049d64bb2 --- /dev/null +++ b/drivers/soc/mediatek/mt8365-pm-domains.h @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8365_PM_DOMAINS_H +#define __SOC_MEDIATEK_MT8365_PM_DOMAINS_H + +#include "mtk-pm-domains.h" +#include + +/* + * MT8365 power domain support + */ + +static const struct scpsys_domain_data scpsys_domain_data_mt8365[] =3D { + [MT8365_POWER_DOMAIN_MM] =3D { + .name =3D "mm", + .sta_mask =3D PWR_STATUS_DISP, + .ctl_offs =3D 0x30c, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(8, 8), + .sram_pdn_ack_bits =3D GENMASK(12, 12), + .caps =3D MTK_SCPD_STRICT_BUSP, + .bp_infracfg =3D { + BUS_PROT_WR(BIT(16) | BIT(17), 0x2a8, 0x2ac, 0x258), + BUS_PROT_WR(BIT(1) | BIT(2) | BIT(10) | BIT(11), 0x2a0, 0x2a4, 0x228), + BUS_PROT_WAY_EN(BIT(6), BIT(24), 0x200, 0x0), + BUS_PROT_WAY_EN(BIT(5), BIT(14), 0x234, 0x28), + BUS_PROT_WR(BIT(6), 0x2a0, 0x2a4, 0x228), + }, + }, + [MT8365_POWER_DOMAIN_VENC] =3D { + .name =3D "venc", + .sta_mask =3D PWR_STATUS_VENC, + .ctl_offs =3D 0x0304, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(8, 8), + .sram_pdn_ack_bits =3D GENMASK(12, 12), + .bp_smi =3D { + BUS_PROT_WR(BIT(1), 0x3c4, 0x3c8, 0x3c0), + }, + }, + [MT8365_POWER_DOMAIN_AUDIO] =3D { + .name =3D "audio", + .sta_mask =3D PWR_STATUS_AUDIO, + .ctl_offs =3D 0x0314, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(12, 8), + .sram_pdn_ack_bits =3D GENMASK(17, 13), + .bp_infracfg =3D { + BUS_PROT_WR(BIT(27) | BIT(28), 0x2a8, 0x2ac, 0x258), + }, + .caps =3D MTK_SCPD_ACTIVE_WAKEUP, + }, + [MT8365_POWER_DOMAIN_CONN] =3D { + .name =3D "conn", + .sta_mask =3D PWR_STATUS_CONN, + .ctl_offs =3D 0x032c, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D 0, + .sram_pdn_ack_bits =3D 0, + .bp_infracfg =3D { + BUS_PROT_WR(BIT(13), 0x2a0, 0x2a4, 0x228), + BUS_PROT_WR(BIT(18), 0x2a8, 0x2ac, 0x258), + BUS_PROT_WR(BIT(14), 0x2a0, 0x2a4, 0x228), + BUS_PROT_WR(BIT(21), 0x2a8, 0x2ac, 0x258), + }, + .caps =3D MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8365_POWER_DOMAIN_MFG] =3D { + .name =3D "mfg", + .sta_mask =3D PWR_STATUS_MFG, + .ctl_offs =3D 0x0338, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(9, 8), + .sram_pdn_ack_bits =3D GENMASK(13, 12), + .bp_infracfg =3D { + BUS_PROT_WR(BIT(25), 0x2a0, 0x2a4, 0x228), + BUS_PROT_WR(BIT(21) | BIT(22), 0x2a0, 0x2a4, 0x228), + }, + }, + [MT8365_POWER_DOMAIN_CAM] =3D { + .name =3D "cam", + .sta_mask =3D BIT(25), + .ctl_offs =3D 0x0344, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(9, 8), + .sram_pdn_ack_bits =3D GENMASK(13, 12), + .bp_infracfg =3D { + BUS_PROT_WR(BIT(19), 0x2a8, 0x2ac, 0x258), + }, + .bp_smi =3D { + BUS_PROT_WR(BIT(2), 0x3c4, 0x3c8, 0x3c0), + }, + }, + [MT8365_POWER_DOMAIN_VDEC] =3D { + .name =3D "vdec", + .sta_mask =3D BIT(31), + .ctl_offs =3D 0x0370, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(8, 8), + .sram_pdn_ack_bits =3D GENMASK(12, 12), + .bp_smi =3D { + BUS_PROT_WR(BIT(3), 0x3c4, 0x3c8, 0x3c0), + }, + }, + [MT8365_POWER_DOMAIN_APU] =3D { + .name =3D "apu", + .sta_mask =3D BIT(16), + .ctl_offs =3D 0x0378, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(14, 8), + .sram_pdn_ack_bits =3D GENMASK(21, 15), + .bp_infracfg =3D { + BUS_PROT_WR(BIT(2) | BIT(20), 0x2a8, 0x2ac, 0x258), + }, + .bp_smi =3D { + BUS_PROT_WR(BIT(4), 0x3c4, 0x3c8, 0x3c0), + }, + }, + [MT8365_POWER_DOMAIN_DSP] =3D { + .name =3D "dsp", + .sta_mask =3D BIT(17), + .ctl_offs =3D 0x037C, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(11, 8), + .sram_pdn_ack_bits =3D GENMASK(15, 12), + .bp_infracfg =3D { + BUS_PROT_WR(BIT(24) | BIT(30) | BIT(31), 0x2a8, 0x2ac, 0x258), + }, + .caps =3D MTK_SCPD_ACTIVE_WAKEUP, + }, +}; + +static const struct scpsys_soc_data mt8365_scpsys_data =3D { + .domains_data =3D scpsys_domain_data_mt8365, + .num_domains =3D ARRAY_SIZE(scpsys_domain_data_mt8365), +}; + +#endif /* __SOC_MEDIATEK_MT8365_PM_DOMAINS_H */ diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/m= tk-pm-domains.c index 94ca8981f45e..7bfadc8dee7e 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -22,6 +22,7 @@ #include "mt8186-pm-domains.h" #include "mt8192-pm-domains.h" #include "mt8195-pm-domains.h" +#include "mt8365-pm-domains.h" =20 #define MTK_POLL_DELAY_US 10 #define MTK_POLL_TIMEOUT USEC_PER_SEC @@ -636,6 +637,10 @@ static const struct of_device_id scpsys_of_match[] =3D= { .compatible =3D "mediatek,mt8195-power-controller", .data =3D &mt8195_scpsys_data, }, + { + .compatible =3D "mediatek,mt8365-power-controller", + .data =3D &mt8365_scpsys_data, + }, { } }; =20 --=20 2.36.1