From nobody Fri Apr 17 10:27:39 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D3C0C43334 for ; Fri, 22 Jul 2022 22:44:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237145AbiGVWoX (ORCPT ); Fri, 22 Jul 2022 18:44:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38770 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236881AbiGVWoP (ORCPT ); Fri, 22 Jul 2022 18:44:15 -0400 Received: from mail-pl1-x649.google.com (mail-pl1-x649.google.com [IPv6:2607:f8b0:4864:20::649]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AE819BE11 for ; Fri, 22 Jul 2022 15:44:14 -0700 (PDT) Received: by mail-pl1-x649.google.com with SMTP id k11-20020a170902ce0b00b0016a15fe2627so3315331plg.22 for ; Fri, 22 Jul 2022 15:44:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=reply-to:date:in-reply-to:message-id:mime-version:references :subject:from:to:cc; bh=WN/xY6gOj1e2WnlDEa/rBl2RMeNZSHfOPPkC15IuT+I=; b=dFdqM1GImgHSmfrpMtWX2mFjGG/F4k4bC4JDEKFNocnSz4yh7wq90o7YCEvOBKVl0B LaVkYJCQtVQTaAb+JOmTBlrOkKUoZM0brfVL9P93bw6wiIpzBIAcw69Y8JBPW3+vro2A gvRPVFz7etzVTFpeiAsagZz0Ia2ssLUTxxpEr1mho987VPLniFmBjsi16ur28R8gYxjh G9FLE93SXKfFsbiQvB5eVEKM10Mikz7owdgIhJGp8aP0+wqTcjbnFqLECiMPmcaLZyF0 S8wObyB7+xzi7lf4ZxGD9idq8djA58qN1NNMhIiJeaepPmoHTtlDulurF8uw8LTxNO8N TZ6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:reply-to:date:in-reply-to:message-id :mime-version:references:subject:from:to:cc; bh=WN/xY6gOj1e2WnlDEa/rBl2RMeNZSHfOPPkC15IuT+I=; b=F0hfrHMtuFBPbf2HKDUfzRb3CHhiGytZd2VKZrpO8JUoXC91c4xvOs7UwMENUuG8le Q9SYsvumHn8COsR0+rJJGmFHrBDXFNkVi6dGgGqtJ2zIOElDQ339ipT7Gl9tDhXZ7t/z o/k588sA64yh/4mvgJleQiUTm6W7Z0eIehDZ79Skjo0jbo7MGc3rBQQBbbBDFDklDKgL ibngMP8q8RXKKOEXY28U3WZ80zoKKyuXlh38nRkn90NFMp/tDfFBqmVMa3fyCPw9gOJ7 NqYFQsom4MM27CAhl6z/e8ZzWgSBZR4OorqNSlxfgwWrqorspbW4N+M0u+oshxSqy8y2 9dgA== X-Gm-Message-State: AJIora/x225Yxmq0tYFQZ2s/GjzM+arZerv7r/aFIqpVE2E+S5P6deF6 aQ31615uT5Cz0IYgqr6Pgmzkgp8CdWs= X-Google-Smtp-Source: AGRyM1tVHf2nBEKhoB+GuOB6GF7HefI8tK4cljRmv+pNdm37LTjAtoSL298ZmzoSg/lMvhUp8MSNeGdFClA= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a05:6a00:158e:b0:52a:e628:8b3b with SMTP id u14-20020a056a00158e00b0052ae6288b3bmr2164120pfk.80.1658529854264; Fri, 22 Jul 2022 15:44:14 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 22 Jul 2022 22:44:05 +0000 In-Reply-To: <20220722224409.1336532-1-seanjc@google.com> Message-Id: <20220722224409.1336532-2-seanjc@google.com> Mime-Version: 1.0 References: <20220722224409.1336532-1-seanjc@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH 1/5] Revert "Revert "KVM: nVMX: Expose load IA32_PERF_GLOBAL_CTRL VM-{Entry,Exit} control"" From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This reverts commit 00590a3844086384b584eb9e7c8155baa6e33e49. Intended to be fixup, not a standalone revert. --- arch/x86/kvm/vmx/nested.c | 26 +++++++++++++++++++++++--- arch/x86/kvm/vmx/nested.h | 2 ++ arch/x86/kvm/vmx/pmu_intel.c | 3 +++ 3 files changed, 28 insertions(+), 3 deletions(-) diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index b9425b142028..451cbb9c56c3 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -2623,7 +2623,6 @@ static int prepare_vmcs02(struct kvm_vcpu *vcpu, stru= ct vmcs12 *vmcs12, } =20 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) && - vmcs12->guest_ia32_perf_global_ctrl !=3D vcpu_to_pmu(vcpu)->global_ct= rl && WARN_ON_ONCE(kvm_set_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL, vmcs12->guest_ia32_perf_global_ctrl))) { *entry_failure_code =3D ENTRY_FAIL_DEFAULT; @@ -4334,8 +4333,7 @@ static void load_vmcs12_host_state(struct kvm_vcpu *v= cpu, vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat); vcpu->arch.pat =3D vmcs12->host_ia32_pat; } - if ((vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) - && vmcs12->host_ia32_perf_global_ctrl !=3D vcpu_to_pmu(vcpu)->global_= ctrl) + if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) WARN_ON_ONCE(kvm_set_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL, vmcs12->host_ia32_perf_global_ctrl)); =20 @@ -4824,6 +4822,28 @@ int get_vmx_mem_address(struct kvm_vcpu *vcpu, unsig= ned long exit_qualification, return 0; } =20 +void nested_vmx_pmu_refresh(struct kvm_vcpu *vcpu, + bool vcpu_has_perf_global_ctrl) +{ + struct vcpu_vmx *vmx; + + if (!nested_vmx_allowed(vcpu)) + return; + + vmx =3D to_vmx(vcpu); + if (vcpu_has_perf_global_ctrl) { + vmx->nested.msrs.entry_ctls_high |=3D + VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; + vmx->nested.msrs.exit_ctls_high |=3D + VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; + } else { + vmx->nested.msrs.entry_ctls_high &=3D + ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; + vmx->nested.msrs.exit_ctls_high &=3D + ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; + } +} + static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer, int *ret) { diff --git a/arch/x86/kvm/vmx/nested.h b/arch/x86/kvm/vmx/nested.h index 88b00a7359e4..129ae4e01f7c 100644 --- a/arch/x86/kvm/vmx/nested.h +++ b/arch/x86/kvm/vmx/nested.h @@ -32,6 +32,8 @@ int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index,= u64 data); int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdat= a); int get_vmx_mem_address(struct kvm_vcpu *vcpu, unsigned long exit_qualific= ation, u32 vmx_instruction_info, bool wr, int len, gva_t *ret); +void nested_vmx_pmu_refresh(struct kvm_vcpu *vcpu, + bool vcpu_has_perf_global_ctrl); void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu); bool nested_vmx_check_io_bitmaps(struct kvm_vcpu *vcpu, unsigned int port, int size); diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index cfcb590afaa7..4bc098fbec31 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -590,6 +590,9 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) bitmap_set(pmu->all_valid_pmc_idx, INTEL_PMC_MAX_GENERIC, pmu->nr_arch_fixed_counters); =20 + nested_vmx_pmu_refresh(vcpu, + intel_is_valid_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL)); + if (cpuid_model_is_consistent(vcpu)) x86_perf_get_lbr(&lbr_desc->records); else --=20 2.37.1.359.gd136c6c3e2-goog From nobody Fri Apr 17 10:27:39 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B6E4C433EF for ; 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Fri, 22 Jul 2022 15:44:15 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 22 Jul 2022 22:44:06 +0000 In-Reply-To: <20220722224409.1336532-1-seanjc@google.com> Message-Id: <20220722224409.1336532-3-seanjc@google.com> Mime-Version: 1.0 References: <20220722224409.1336532-1-seanjc@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH 2/5] KVM: VMX: Mark all PERF_GLOBAL_(OVF)_CTRL bits reserved if there's no vPMU From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Mark all MSR_CORE_PERF_GLOBAL_CTRL and MSR_CORE_PERF_GLOBAL_OVF_CTRL bits as reserved if there is no guest vPMU. The nVMX VM-Entry consistency checks do not check for a valid vPMU prior to consuming the masks via kvm_valid_perf_global_ctrl(), i.e. may incorrectly allow a non-zero mask to be loaded via VM-Enter or VM-Exit (well, attempted to be loaded, the actual MSR load will be rejected by intel_is_valid_msr()). Fixes: f5132b01386b ("KVM: Expose a version 2 architectural PMU to a guests= ") Cc: stable@vger.kernel.org Signed-off-by: Sean Christopherson --- arch/x86/kvm/vmx/pmu_intel.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 4bc098fbec31..6e355c5d2f40 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -527,6 +527,8 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) pmu->version =3D 0; pmu->reserved_bits =3D 0xffffffff00200000ull; pmu->raw_event_mask =3D X86_RAW_EVENT_MASK; + pmu->global_ctrl_mask =3D ~0ull; + pmu->global_ovf_ctrl_mask =3D ~0ull; pmu->fixed_ctr_ctrl_mask =3D ~0ull; pmu->pebs_enable_mask =3D ~0ull; pmu->pebs_data_cfg_mask =3D ~0ull; --=20 2.37.1.359.gd136c6c3e2-goog From nobody Fri Apr 17 10:27:39 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91706C43334 for ; Fri, 22 Jul 2022 22:44:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237091AbiGVWob (ORCPT ); Fri, 22 Jul 2022 18:44:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38818 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236928AbiGVWoS (ORCPT ); Fri, 22 Jul 2022 18:44:18 -0400 Received: from mail-pl1-x649.google.com (mail-pl1-x649.google.com [IPv6:2607:f8b0:4864:20::649]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D209FDFC5 for ; Fri, 22 Jul 2022 15:44:17 -0700 (PDT) Received: by mail-pl1-x649.google.com with SMTP id d10-20020a170902ceca00b0016bea2dc145so3285079plg.7 for ; Fri, 22 Jul 2022 15:44:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=reply-to:date:in-reply-to:message-id:mime-version:references :subject:from:to:cc; bh=nQbI7mgbPu76BJJTxIKbUpy3vK9Oikhk2MGU8S06ItM=; b=gs/mLRrabGlmhxpkstmEAULa3o8l9S4Z63InD53IX0DUsxaV8IDtM/l44DSpaEr4s1 6IfW58DBfkAq4r0eKePk6jfemH3i6C1r5H2gXBgm5U4hlWK00pCLJ2a7s+0kxUfnT3eD ztg633DDoUaIEzb4XEtL5we+/SWkZSxIgcT3vMoVhfsaCTGcdGyxX5x1IPlEOEn5AF8R hm0JMYYzR+6/s20i1cGEKzocN4a1JIchljVAiFJOJDWQYcPR9NffUdUQgpX7ETAgbuU3 fyWIdnOAxyJDVCGCTYBC38h3mKgKkP9XggQJpiin0is3kP5zr3itK6oj1UqwhAsnoq9L znWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:reply-to:date:in-reply-to:message-id :mime-version:references:subject:from:to:cc; bh=nQbI7mgbPu76BJJTxIKbUpy3vK9Oikhk2MGU8S06ItM=; b=w158TVgAt0R40Dnb+gMhDQNs+nooud2c3llKzZTQy2laE5qA6wxHF6dWuqzHxybtrh ljd/PPP0+MPyN7UbeK1l+ST+WLFL83LgNdRSsF3H/oIxOpO1/aHMzZ6cwDrlpxZBh+lW SBadqjrSUDsrDAtYDMUy6rUJMgjWxTfEUIaloXON8EigSvRf8jCdyfA5kkWYvE1caiod VDD9Skgq4ZKJQKYgFYHTlzoUOw0mCr4voY4skazdY2ovMeIE12Cmac+9gyfGX3mgNzhZ nt8IR6ogUdqDUIYyUj8LDB6llo/DlTvJ2l0uQF2Lj4ZzXtBLvmrcaxfclSjKSVKz/6HA 591g== X-Gm-Message-State: AJIora8phFbvRCb2kAvRr7at7M7J9FP+NVkZbecjpzPBQjgfpwxoAP/L cCE8wRUQMXS6Ij4iGM/gWCP4Lxd4hFc= X-Google-Smtp-Source: AGRyM1uMN9Bq8o664JObQs8A6sS3uPBc5ZuDgDK4I/bo2w4Ex/gpGwWdxLKgnS090UlnEcme99TIC85j/Gs= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a05:6a00:8c5:b0:510:6eae:6fa1 with SMTP id s5-20020a056a0008c500b005106eae6fa1mr2093741pfu.12.1658529857442; Fri, 22 Jul 2022 15:44:17 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 22 Jul 2022 22:44:07 +0000 In-Reply-To: <20220722224409.1336532-1-seanjc@google.com> Message-Id: <20220722224409.1336532-4-seanjc@google.com> Mime-Version: 1.0 References: <20220722224409.1336532-1-seanjc@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH 3/5] KVM: VMX: Add helper to check if the guest PMU has PERF_GLOBAL_CTRL From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a helper to check of the guest PMU has PERF_GLOBAL_CTRL, which is unintuitive _and_ diverges from Intel's architecturally defined behavior. Even worse, KVM currently implements the check using two different (but equivalent) checks, _and_ there has been at least one attempt to add a _third_ flavor. Cc: stable@vger.kernel.org Signed-off-by: Sean Christopherson --- arch/x86/kvm/vmx/pmu_intel.c | 4 ++-- arch/x86/kvm/vmx/vmx.h | 12 ++++++++++++ 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 6e355c5d2f40..78f2800fd850 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -111,7 +111,7 @@ static bool intel_pmc_is_enabled(struct kvm_pmc *pmc) { struct kvm_pmu *pmu =3D pmc_to_pmu(pmc); =20 - if (pmu->version < 2) + if (!intel_pmu_has_perf_global_ctrl(pmu)) return true; =20 return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl); @@ -207,7 +207,7 @@ static bool intel_is_valid_msr(struct kvm_vcpu *vcpu, u= 32 msr) case MSR_CORE_PERF_GLOBAL_STATUS: case MSR_CORE_PERF_GLOBAL_CTRL: case MSR_CORE_PERF_GLOBAL_OVF_CTRL: - ret =3D pmu->version > 1; + return intel_pmu_has_perf_global_ctrl(pmu); break; case MSR_IA32_PEBS_ENABLE: ret =3D vcpu_get_perf_capabilities(vcpu) & PERF_CAP_PEBS_FORMAT; diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h index 286c88e285ea..2a0b94e0fda7 100644 --- a/arch/x86/kvm/vmx/vmx.h +++ b/arch/x86/kvm/vmx/vmx.h @@ -91,6 +91,18 @@ union vmx_exit_reason { u32 full; }; =20 +static inline bool intel_pmu_has_perf_global_ctrl(struct kvm_pmu *pmu) +{ + /* + * Architecturally, Intel's SDM states that IA32_PERF_GLOBAL_CTRL is + * supported if "CPUID.0AH: EAX[7:0] > 0", i.e. if the PMU version is + * greater than zero. However, KVM only exposes and emulates the MSR + * to/for the guest if the guest PMU supports at least "Architectural + * Performance Monitoring Version 2". + */ + return pmu->version > 1; +} + #define vcpu_to_lbr_desc(vcpu) (&to_vmx(vcpu)->lbr_desc) #define vcpu_to_lbr_records(vcpu) (&to_vmx(vcpu)->lbr_desc.records) =20 --=20 2.37.1.359.gd136c6c3e2-goog From nobody Fri Apr 17 10:27:39 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F758C433EF for ; Fri, 22 Jul 2022 22:44:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237112AbiGVWod (ORCPT ); Fri, 22 Jul 2022 18:44:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237025AbiGVWoU (ORCPT ); Fri, 22 Jul 2022 18:44:20 -0400 Received: from mail-pj1-x1049.google.com (mail-pj1-x1049.google.com [IPv6:2607:f8b0:4864:20::1049]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7AEE015A1F for ; Fri, 22 Jul 2022 15:44:19 -0700 (PDT) Received: by mail-pj1-x1049.google.com with SMTP id rm8-20020a17090b3ec800b001f07b25d636so4498401pjb.1 for ; Fri, 22 Jul 2022 15:44:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=reply-to:date:in-reply-to:message-id:mime-version:references :subject:from:to:cc; bh=ZY+tUE4rZ+sUQOkiCezCy7txeAhXNX+dCy+Lqq1rkD4=; b=OSW3LvDdoeGIwZPNx8kr9+XrS21Q+ytT7VjmU2P3X6LwHhKBk99ebVSfxt32kvJYap nZOpxA2OCVkHZIXEj/sETQykOSKs9OcNXH59oNJIFBKHgqWrLvsRvGX1VZr6U09S935x z1D4BzsbQjjhCDKBKDVu9VzUwXYu3tVs1z3qn2/EZk9BrAoozhqUyoCT6g7leU7LwiGS 7BGsNQ7dM5WKuiAXIO8VAVHFGFMr5ucfMR0l/uQ3eBS2NXfitjmbE0zpHwNTuU3bCcoO n0wY8is0EUkCX/2IlyOibwgbuOsRE3Sc3O437kPCc8I9Wu/y/I8yZ7usie5Us3oDqpAQ P59A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:reply-to:date:in-reply-to:message-id :mime-version:references:subject:from:to:cc; bh=ZY+tUE4rZ+sUQOkiCezCy7txeAhXNX+dCy+Lqq1rkD4=; b=IwhLRqKgN2ZA90MZYIHfX3+K/88W7uyPOYd2S5o76jHBKMSdzylZkNd82CTPFerQ+g Prxvtchi3dY8eMzRgCGTWrtZAZpjS1QJ+YqqDSHduVA2bbGaGMfC6u/lCcohWKYxYJMx TmU1oXM9W13+L5JqX9nlyTcTmIMFPapaqnI1NBB9ok5BYUAgo/75LV3k0DzIt7QbhxcS U3R8sfSZUeWuWwuTQB1yr3u4D9l026YjidqfBRLYrRKT1GSTK5kp7qBpHAWGKUeUS178 T3YDWLbkjxdlyNsiafa8las0IacJfwh7HOIsJFzpT75SjeUGWxSeZjpRC8DUYr/gkQnZ my5Q== X-Gm-Message-State: AJIora+EyTiyGLlVRPVqurmREEmLseNGBu1TZAhagB8+QV/19262kpuQ rUMOHbQsGL/Quxmxs5pw8oISt27/fD4= X-Google-Smtp-Source: AGRyM1tHsO7GYWir9NMkM91Dbxrg8Fwutg92d7z6lsJLR/uW6wheeqtHfTkKncraswX+5s/dyWDlbiGR2Wg= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a63:8743:0:b0:41a:6f6b:db7b with SMTP id i64-20020a638743000000b0041a6f6bdb7bmr1688976pge.594.1658529859008; Fri, 22 Jul 2022 15:44:19 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 22 Jul 2022 22:44:08 +0000 In-Reply-To: <20220722224409.1336532-1-seanjc@google.com> Message-Id: <20220722224409.1336532-5-seanjc@google.com> Mime-Version: 1.0 References: <20220722224409.1336532-1-seanjc@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH 4/5] KVM: nVMX: Attempt to load PERF_GLOBAL_CTRL on nVMX xfer iff it exists From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Attempt to load PERF_GLOBAL_CTRL during nested VM-Enter/VM-Exit if and only if the MSR exists (according to the guest vCPU model). KVM has very misguided handling of VM_{ENTRY,EXIT}_LOAD_IA32_PERF_GLOBAL_CTRL and attempts to force the nVMX MSR settings to match the vPMU model, i.e. to hide/expose the control based on whether or not the MSR exists from the guest's perspective. KVM's modifications fail to handle the scenario where the vPMU is hidden from the guest _after_ being exposed to the guest, e.g. by userspace doing multiple KVM_SET_CPUID2 calls, which is allowed if done before any KVM_RUN. nested_vmx_pmu_refresh() is called if and only if there's a recognized vPMU, i.e. KVM will leave the bits in the allow state and then ultimately reject the MSR load and WARN. KVM should not force the VMX MSRs in the first place. KVM taking control of the MSRs was a misguided attempt at mimicking what commit 5f76f6f5ff96 ("KVM: nVMX: Do not expose MPX VMX controls when guest MPX disabled", 2018-10-01) did for MPX. However, the MPX commit was a workaround for another KVM bug and not something that should be imitated (and it should never been done in the first place). In other words, KVM's ABI _should_ be that userspace has full control over the MSRs, at which point triggering the WARN that loading the MSR must not fail is trivial. The intent of the WARN is still valid; KVM has consistency checks to ensure that vmcs12->{guest,host}_ia32_perf_global_ctrl is valid. The problem is that '0' must be considered a valid value at all times, and so the simple/obvious solution is to just not actually load the MSR when it does not exist. It is userspace's responsibility to provide a sane vCPU model, i.e. KVM is well within its ABI and Intel's VMX architecture to skip the loads if the MSR does not exist. Fixes: 03a8871add95 ("KVM: nVMX: Expose load IA32_PERF_GLOBAL_CTRL VM-{Entr= y,Exit} control") Cc: stable@vger.kernel.org Signed-off-by: Sean Christopherson --- arch/x86/kvm/vmx/nested.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index 451cbb9c56c3..52fb45e23910 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -2623,6 +2623,7 @@ static int prepare_vmcs02(struct kvm_vcpu *vcpu, stru= ct vmcs12 *vmcs12, } =20 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) && + intel_pmu_has_perf_global_ctrl(vcpu_to_pmu(vcpu)) && WARN_ON_ONCE(kvm_set_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL, vmcs12->guest_ia32_perf_global_ctrl))) { *entry_failure_code =3D ENTRY_FAIL_DEFAULT; @@ -4333,7 +4334,8 @@ static void load_vmcs12_host_state(struct kvm_vcpu *v= cpu, vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat); vcpu->arch.pat =3D vmcs12->host_ia32_pat; } - if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) + if ((vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) && + intel_pmu_has_perf_global_ctrl(vcpu_to_pmu(vcpu))) WARN_ON_ONCE(kvm_set_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL, vmcs12->host_ia32_perf_global_ctrl)); =20 --=20 2.37.1.359.gd136c6c3e2-goog From nobody Fri Apr 17 10:27:39 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25D50C43334 for ; Fri, 22 Jul 2022 22:44:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237127AbiGVWof (ORCPT ); Fri, 22 Jul 2022 18:44:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237067AbiGVWoY (ORCPT ); Fri, 22 Jul 2022 18:44:24 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CA18912765 for ; Fri, 22 Jul 2022 15:44:21 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id m123-20020a253f81000000b0066ff6484995so4650476yba.22 for ; Fri, 22 Jul 2022 15:44:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=reply-to:date:in-reply-to:message-id:mime-version:references :subject:from:to:cc; bh=jRW5b1AwRLqsPtLiYdI940KWFJTYfsllVCwerR050ZU=; b=D8eIyfatj63AATbuT4yK79CYNRpWCdlOFFTNSBorLgJO+q/hJ5nV89U5TjLw6DZBZZ qw+N5RXkL/TGUd+1cYEDYJfZfJ1AWJFeMKxTIb00mThzxHet/1RgARY04VEHNqLmYSWX P2cNe2aAyLEUZOJc22aeJZUYhpxV9x3pSTGMi8iNhERx3oxKjnlAUOPUrqZULVLK0Qh+ +o6epHrYJGiXBedHgTkMzJFOMzbuJiZu8ZlNg5A2jiSGrnjBYfwIkkt+XNpy8B7oURAr baXlL9zKk5DNkNQD2mrVduTSgty+4A5cI/vBON56KOqXnzWIT+3V9LvtTzAK2OoWC968 3Lqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:reply-to:date:in-reply-to:message-id :mime-version:references:subject:from:to:cc; bh=jRW5b1AwRLqsPtLiYdI940KWFJTYfsllVCwerR050ZU=; b=wyQaZo1c6Ls9IbBCDrDMsk4PxdzbQaDDcRhy942GYi+PorON1hh0smgadZLseqQuVe 4vMf6xZ09XkiHXSNYIfDj2Fd1CUg/7GAOk/4Biksdsg0c5rdkifimkGieUNLG6bIkvWv nGP1ncOhaOi8P3tCrC+cUGQhhJ8UnDQ53sztLF6a8CPY0XFSx357VgQGCp6haTvrlaeZ +xMPSEU2/oP7VP44tKVqauIgSupT/hyj4ChOz9pMn7HVp3ML3YH3C5y0L3zT7n72NsrD O+e+tl89s5piwxnshOpXKtxzeg5/h1Bv7UrleKslh5LaHST+Us7vgg8jNCxp3GdydkVB O9fA== X-Gm-Message-State: AJIora/vo2qKbZnWQpxtQnkZjxczvHRQCZa2Dt5CpV7aT7DTkiBiau/t Byq0CEtII74NFISsZgzqalF7D9DaRJE= X-Google-Smtp-Source: AGRyM1sgw9WQOgJabF3Ug/th0ONJN646sekDkdkEtGqcxujSgR7CN8sF2pu2CMtToTgmyEy4btnnimQLJU0= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a0d:fcc5:0:b0:31e:7544:9806 with SMTP id m188-20020a0dfcc5000000b0031e75449806mr1806701ywf.193.1658529860663; Fri, 22 Jul 2022 15:44:20 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 22 Jul 2022 22:44:09 +0000 In-Reply-To: <20220722224409.1336532-1-seanjc@google.com> Message-Id: <20220722224409.1336532-6-seanjc@google.com> Mime-Version: 1.0 References: <20220722224409.1336532-1-seanjc@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH 5/5] Revert "KVM: nVMX: Expose load IA32_PERF_GLOBAL_CTRL VM-{Entry,Exit} control" From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Paolo Bonzini This reverts commit 03a8871add95213827e2bea84c12133ae5df952e. Since commit 03a8871add95 ("KVM: nVMX: Expose load IA32_PERF_GLOBAL_CTRL VM-{Entry,Exit} control"), KVM has taken ownership of the "load IA32_PERF_GLOBAL_CTRL" VMX entry/exit control bits, trying to set these bits in the IA32_VMX_TRUE_{ENTRY,EXIT}_CTLS MSRs if the guest's CPUID supports the architectural PMU (CPUID[EAX=3D0Ah].EAX[7:0]=3D1), and clear otherwise. This was a misguided attempt at mimicking what commit 5f76f6f5ff96 ("KVM: nVMX: Do not expose MPX VMX controls when guest MPX disabled", 2018-10-01) did for MPX. However, that commit was a workaround for another KVM bug and not something that should be imitated. Mucking with the VMX MSRs creates a subtle, difficult to maintain ABI as KVM must ensure that any internal changes, e.g. to how KVM handles _any_ guest CPUID changes, yield the same functional result. Therefore, KVM's policy is to let userspace have full control of the guest vCPU model so long as the host kernel is not at risk. Now that KVM really truly ensures kvm_set_msr() will succeed by loading PERF_GLOBAL_CTRL if and only if it exists, revert KVM's misguided and roundabout behavior. Signed-off-by: Paolo Bonzini [sean: make it a pure revert] Signed-off-by: Sean Christopherson --- arch/x86/kvm/vmx/nested.c | 22 ---------------------- arch/x86/kvm/vmx/nested.h | 2 -- arch/x86/kvm/vmx/pmu_intel.c | 3 --- 3 files changed, 27 deletions(-) diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index 52fb45e23910..ed247a121325 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -4824,28 +4824,6 @@ int get_vmx_mem_address(struct kvm_vcpu *vcpu, unsig= ned long exit_qualification, return 0; } =20 -void nested_vmx_pmu_refresh(struct kvm_vcpu *vcpu, - bool vcpu_has_perf_global_ctrl) -{ - struct vcpu_vmx *vmx; - - if (!nested_vmx_allowed(vcpu)) - return; - - vmx =3D to_vmx(vcpu); - if (vcpu_has_perf_global_ctrl) { - vmx->nested.msrs.entry_ctls_high |=3D - VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; - vmx->nested.msrs.exit_ctls_high |=3D - VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; - } else { - vmx->nested.msrs.entry_ctls_high &=3D - ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; - vmx->nested.msrs.exit_ctls_high &=3D - ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; - } -} - static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer, int *ret) { diff --git a/arch/x86/kvm/vmx/nested.h b/arch/x86/kvm/vmx/nested.h index 129ae4e01f7c..88b00a7359e4 100644 --- a/arch/x86/kvm/vmx/nested.h +++ b/arch/x86/kvm/vmx/nested.h @@ -32,8 +32,6 @@ int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index,= u64 data); int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdat= a); int get_vmx_mem_address(struct kvm_vcpu *vcpu, unsigned long exit_qualific= ation, u32 vmx_instruction_info, bool wr, int len, gva_t *ret); -void nested_vmx_pmu_refresh(struct kvm_vcpu *vcpu, - bool vcpu_has_perf_global_ctrl); void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu); bool nested_vmx_check_io_bitmaps(struct kvm_vcpu *vcpu, unsigned int port, int size); diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 78f2800fd850..862c1a4d971b 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -592,9 +592,6 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) bitmap_set(pmu->all_valid_pmc_idx, INTEL_PMC_MAX_GENERIC, pmu->nr_arch_fixed_counters); =20 - nested_vmx_pmu_refresh(vcpu, - intel_is_valid_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL)); - if (cpuid_model_is_consistent(vcpu)) x86_perf_get_lbr(&lbr_desc->records); else --=20 2.37.1.359.gd136c6c3e2-goog