From nobody Sat Sep 21 21:26:44 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B109C43334 for ; Thu, 21 Jul 2022 14:50:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231790AbiGUOuk (ORCPT ); Thu, 21 Jul 2022 10:50:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36086 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230291AbiGUOuc (ORCPT ); Thu, 21 Jul 2022 10:50:32 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 79DC026549; Thu, 21 Jul 2022 07:50:31 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 5DDAB6601AAF; Thu, 21 Jul 2022 15:50:29 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1658415029; bh=iCe3nCCYP+CXI4lEolJz5G4aPJpz8Pwnh2r8Gx2Y2to=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=awtLGO2z/IVaa/9TR30oGf/O6xtPL8RZe/1QTAELT4kg6HOyl/GK/K8De+8jQRqMd znBpAK/DD7dehom2b5bfcZCprsbz0O96KiUNMt/7CIdX8Ixn6qLO42tmvhtlsOmxF2 ebGndDoSoRar6bxJW9kGf/F6+COboH9SJ9mFS1rMN1tqJWcPgEalEDH31Y/nPTGa3U yGnQMXFrGKpGlqJg4D3bHR78taYD8ZXG5polIVwxQxXrKhFdYYykfI7YgtLCe0bjG2 wskXi9GCrIj5NTPxSQecHiq9765t0L86yZqXSHAMTAhSNM+iBx2zczvvjA+oAxomPP 10U7x0jvPfKEA== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno Subject: [PATCH v2 2/8] arm64: dts: mediatek: cherry: Wire up the ChromeOS EC and GSC Date: Thu, 21 Jul 2022 16:50:11 +0200 Message-Id: <20220721145017.918102-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220721145017.918102-1-angelogioacchino.delregno@collabora.com> References: <20220721145017.918102-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Wire up the ChromeOS Embedded Controller on SPI0 and its communication channel via SCP RPMSG along with all of the offered functionality, including Keyboard, Smart Battery Metrics (SBS), PWM controller, I2C tunnel, regulators and Type-C connector management. While at it, also add support for the Cr50 Google Security Chip (GSC) found on this platform on I2C3 to support TPM and also use it as an entropy source for the kernel. Signed-off-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8195-cherry.dtsi | 93 +++++++++++++++++++ 1 file changed, 93 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/b= oot/dts/mediatek/mt8195-cherry.dtsi index feebbe367e93..87ac2b4f9814 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -149,6 +149,14 @@ &i2c3 { clock-frequency =3D <400000>; pinctrl-names =3D "default"; pinctrl-0 =3D <&i2c3_pins>; + + cr50@50 { + compatible =3D "google,cr50"; + reg =3D <0x50>; + interrupts-extended =3D <&pio 88 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cr50_int>; + }; }; =20 &i2c4 { @@ -426,6 +434,21 @@ &pio { "AP_SPI_FLASH_MOSI", "AP_SPI_FLASH_MISO"; =20 + cr50_int: cr50-irq-default-pins { + pins-gsc-ap-int-odl { + pinmux =3D ; + input-enable; + }; + }; + + cros_ec_int: cros-ec-irq-default-pins { + pins-ec-ap-int-odl { + pinmux =3D ; + bias-pull-up =3D ; + input-enable; + }; + }; + i2c0_pins: i2c0-default-pins { pins-bus { pinmux =3D , @@ -669,6 +692,11 @@ &scp { memory-region =3D <&scp_mem>; pinctrl-names =3D "default"; pinctrl-0 =3D <&scp_pins>; + + cros-ec-rpmsg { + compatible =3D "google,cros-ec-rpmsg"; + mediatek,rpmsg-name =3D "cros-ec-rpmsg"; + }; }; =20 &spi0 { @@ -677,6 +705,68 @@ &spi0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&spi0_pins>; mediatek,pad-select =3D <0>; + + cros_ec: ec@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + compatible =3D "google,cros-ec-spi"; + reg =3D <0>; + interrupts-extended =3D <&pio 4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cros_ec_int>; + spi-max-frequency =3D <3000000>; + + cros_ec_pwm: ec-pwm { + compatible =3D "google,cros-ec-pwm"; + #pwm-cells =3D <1>; + }; + + i2c_tunnel: i2c-tunnel { + compatible =3D "google,cros-ec-i2c-tunnel"; + google,remote-bus =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mt_pmic_vmc_ldo_reg: regulator@0 { + compatible =3D "google,cros-ec-regulator"; + reg =3D <0>; + regulator-name =3D "mt_pmic_vmc_ldo"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <3600000>; + }; + + mt_pmic_vmch_ldo_reg: regulator@1 { + compatible =3D "google,cros-ec-regulator"; + reg =3D <1>; + regulator-name =3D "mt_pmic_vmch_ldo"; + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <3600000>; + }; + + typec { + compatible =3D "google,cros-ec-typec"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + usb_c0: connector@0 { + compatible =3D "usb-c-connector"; + reg =3D <0>; + power-role =3D "dual"; + data-role =3D "host"; + try-power-role =3D "source"; + }; + + usb_c1: connector@1 { + compatible =3D "usb-c-connector"; + reg =3D <1>; + power-role =3D "dual"; + data-role =3D "host"; + try-power-role =3D "source"; + }; + }; + }; }; =20 &u3phy0 { @@ -728,3 +818,6 @@ &xhci3 { vusb33-supply =3D <&mt6359_vusb_ldo_reg>; vbus-supply =3D <&usb_vbus>; }; + +#include +#include --=20 2.35.1