From nobody Sat Sep 21 23:04:44 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C27F7C433EF for ; Wed, 20 Jul 2022 12:32:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240344AbiGTMcE (ORCPT ); Wed, 20 Jul 2022 08:32:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238038AbiGTMaj (ORCPT ); Wed, 20 Jul 2022 08:30:39 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 204674AD50; Wed, 20 Jul 2022 05:30:36 -0700 (PDT) X-UUID: e3c4a480ed5646e89dd6a05ea44e4357-20220720 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8,REQID:f3ae1d6d-0364-411f-8f70-a745715c6226,OB:0,LO B:0,IP:0,URL:5,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:5 X-CID-META: VersionHash:0f94e32,CLOUDID:9b547d33-b9e4-42b8-b28a-6364427c76bb,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:1,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: e3c4a480ed5646e89dd6a05ea44e4357-20220720 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1471411167; Wed, 20 Jul 2022 20:30:27 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Wed, 20 Jul 2022 20:30:26 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 20 Jul 2022 20:30:26 +0800 From: Tinghan Shen To: Yong Wu , Joerg Roedel , "Will Deacon" , Robin Murphy , Rob Herring , Krzysztof Kozlowski , Lee Jones , Matthias Brugger , Tinghan Shen , AngeloGioacchino Del Regno , MandyJH Liu CC: , , , , , , Weiyi Lu Subject: [PATCH v3 13/21] arm64: dts: mt8195: Add power domains controller Date: Wed, 20 Jul 2022 20:30:15 +0800 Message-ID: <20220720123023.13500-14-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220720123023.13500-1-tinghan.shen@mediatek.com> References: <20220720123023.13500-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add power domains controller node for mt8195. Signed-off-by: Weiyi Lu Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 326 +++++++++++++++++++++++ 1 file changed, 326 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 8d59a7da3271..7e77aecb1296 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include =20 / { compatible =3D "mediatek,mt8195"; @@ -338,6 +339,331 @@ #interrupt-cells =3D <2>; }; =20 + scpsys: syscon@10006000 { + compatible =3D "mediatek,mt8195-scpsys", "syscon", "simple-mfd"; + reg =3D <0 0x10006000 0 0x1000>; + + /* System Power Manager */ + spm: power-controller { + compatible =3D "mediatek,mt8195-power-controller"; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + /* power domain of the SoC */ + mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 { + reg =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8195_POWER_DOMAIN_MFG1 { + reg =3D ; + clocks =3D <&apmixedsys CLK_APMIXED_MFGPLL>; + clock-names =3D "mfg"; + mediatek,infracfg =3D <&infracfg_ao>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8195_POWER_DOMAIN_MFG2 { + reg =3D ; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_MFG3 { + reg =3D ; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_MFG4 { + reg =3D ; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_MFG5 { + reg =3D ; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_MFG6 { + reg =3D ; + #power-domain-cells =3D <0>; + }; + }; + }; + + power-domain@MT8195_POWER_DOMAIN_VPPSYS0 { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_VPP>, + <&topckgen CLK_TOP_CAM>, + <&topckgen CLK_TOP_CCU>, + <&topckgen CLK_TOP_IMG>, + <&topckgen CLK_TOP_VENC>, + <&topckgen CLK_TOP_VDEC>, + <&topckgen CLK_TOP_WPE_VPP>, + <&topckgen CLK_TOP_CFG_VPP0>, + <&vppsys0 CLK_VPP0_SMI_COMMON>, + <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>, + <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>, + <&vppsys0 CLK_VPP0_GALS_VENCSYS>, + <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>, + <&vppsys0 CLK_VPP0_GALS_INFRA>, + <&vppsys0 CLK_VPP0_GALS_CAMSYS>, + <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>, + <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>, + <&vppsys0 CLK_VPP0_SMI_REORDER>, + <&vppsys0 CLK_VPP0_SMI_IOMMU>, + <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, + <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, + <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, + <&vppsys0 CLK_VPP0_SMI_RSI>, + <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, + <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, + <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, + <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; + clock-names =3D "vppsys", "vppsys1", "vppsys2", "vppsys3", + "vppsys4", "vppsys5", "vppsys6", "vppsys7", + "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3", + "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7", + "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11", + "vppsys0-12", "vppsys0-13", "vppsys0-14", + "vppsys0-15", "vppsys0-16", "vppsys0-17", + "vppsys0-18"; + mediatek,infracfg =3D <&infracfg_ao>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8195_POWER_DOMAIN_VDEC1 { + reg =3D ; + clocks =3D <&vdecsys CLK_VDEC_LARB1>; + clock-names =3D "vdec1-0"; + mediatek,infracfg =3D <&infracfg_ao>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 { + reg =3D ; + mediatek,infracfg =3D <&infracfg_ao>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_VDOSYS0 { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_CFG_VDO0>, + <&vdosys0 CLK_VDO0_SMI_GALS>, + <&vdosys0 CLK_VDO0_SMI_COMMON>, + <&vdosys0 CLK_VDO0_SMI_EMI>, + <&vdosys0 CLK_VDO0_SMI_IOMMU>, + <&vdosys0 CLK_VDO0_SMI_LARB>, + <&vdosys0 CLK_VDO0_SMI_RSI>; + clock-names =3D "vdosys0", "vdosys0-0", "vdosys0-1", + "vdosys0-2", "vdosys0-3", + "vdosys0-4", "vdosys0-5"; + mediatek,infracfg =3D <&infracfg_ao>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8195_POWER_DOMAIN_VPPSYS1 { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_CFG_VPP1>, + <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, + <&vppsys1 CLK_VPP1_VPPSYS1_LARB>; + clock-names =3D "vppsys1", "vppsys1-0", + "vppsys1-1"; + mediatek,infracfg =3D <&infracfg_ao>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_WPESYS { + reg =3D ; + clocks =3D <&wpesys CLK_WPE_SMI_LARB7>, + <&wpesys CLK_WPE_SMI_LARB8>, + <&wpesys CLK_WPE_SMI_LARB7_P>, + <&wpesys CLK_WPE_SMI_LARB8_P>; + clock-names =3D "wepsys-0", "wepsys-1", "wepsys-2", + "wepsys-3"; + mediatek,infracfg =3D <&infracfg_ao>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_VDEC0 { + reg =3D ; + clocks =3D <&vdecsys_soc CLK_VDEC_SOC_LARB1>; + clock-names =3D "vdec0-0"; + mediatek,infracfg =3D <&infracfg_ao>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_VDEC2 { + reg =3D ; + clocks =3D <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; + clock-names =3D "vdec2-0"; + mediatek,infracfg =3D <&infracfg_ao>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_VENC { + reg =3D ; + mediatek,infracfg =3D <&infracfg_ao>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_VDOSYS1 { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_CFG_VDO1>, + <&vdosys1 CLK_VDO1_SMI_LARB2>, + <&vdosys1 CLK_VDO1_SMI_LARB3>, + <&vdosys1 CLK_VDO1_GALS>; + clock-names =3D "vdosys1", "vdosys1-0", + "vdosys1-1", "vdosys1-2"; + mediatek,infracfg =3D <&infracfg_ao>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8195_POWER_DOMAIN_DP_TX { + reg =3D ; + mediatek,infracfg =3D <&infracfg_ao>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_EPD_TX { + reg =3D ; + mediatek,infracfg =3D <&infracfg_ao>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_HDMI_TX { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_HDMI_APB>; + clock-names =3D "hdmi_tx"; + #power-domain-cells =3D <0>; + }; + }; + + power-domain@MT8195_POWER_DOMAIN_IMG { + reg =3D ; + clocks =3D <&imgsys CLK_IMG_LARB9>, + <&imgsys CLK_IMG_GALS>; + clock-names =3D "img-0", "img-1"; + mediatek,infracfg =3D <&infracfg_ao>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8195_POWER_DOMAIN_DIP { + reg =3D ; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_IPE { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_IPE>, + <&imgsys CLK_IMG_IPE>, + <&ipesys CLK_IPE_SMI_LARB12>; + clock-names =3D "ipe", "ipe-0", "ipe-1"; + mediatek,infracfg =3D <&infracfg_ao>; + #power-domain-cells =3D <0>; + }; + }; + + power-domain@MT8195_POWER_DOMAIN_CAM { + reg =3D ; + clocks =3D <&camsys CLK_CAM_LARB13>, + <&camsys CLK_CAM_LARB14>, + <&camsys CLK_CAM_CAM2MM0_GALS>, + <&camsys CLK_CAM_CAM2MM1_GALS>, + <&camsys CLK_CAM_CAM2SYS_GALS>; + clock-names =3D "cam-0", "cam-1", "cam-2", "cam-3", + "cam-4"; + mediatek,infracfg =3D <&infracfg_ao>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8195_POWER_DOMAIN_CAM_RAWA { + reg =3D ; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_CAM_RAWB { + reg =3D ; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_CAM_MRAW { + reg =3D ; + #power-domain-cells =3D <0>; + }; + }; + }; + }; + + power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 { + reg =3D ; + mediatek,infracfg =3D <&infracfg_ao>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 { + reg =3D ; + mediatek,infracfg =3D <&infracfg_ao>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_PCIE_PHY { + reg =3D ; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY { + reg =3D ; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_SENINF>, + <&topckgen CLK_TOP_SENINF2>; + clock-names =3D "csi_rx_top", "csi_rx_top1"; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_ETHER { + reg =3D ; + clocks =3D <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; + clock-names =3D "ether"; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_ADSP { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_ADSP>, + <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>; + clock-names =3D "adsp", "adsp1"; + #address-cells =3D <1>; + #size-cells =3D <0>; + mediatek,infracfg =3D <&infracfg_ao>; + #power-domain-cells =3D <1>; + + power-domain@MT8195_POWER_DOMAIN_AUDIO { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_A1SYS_HP>, + <&topckgen CLK_TOP_AUD_INTBUS>, + <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, + <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>; + clock-names =3D "audio", "audio1", "audio2", + "audio3"; + mediatek,infracfg =3D <&infracfg_ao>; + #power-domain-cells =3D <0>; + }; + }; + }; + }; + watchdog: watchdog@10007000 { compatible =3D "mediatek,mt8195-wdt", "mediatek,mt6589-wdt"; --=20 2.18.0