From nobody Sat Apr 18 02:47:34 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E530C43334 for ; Tue, 19 Jul 2022 05:48:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236754AbiGSFs3 (ORCPT ); Tue, 19 Jul 2022 01:48:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48878 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236715AbiGSFs0 (ORCPT ); Tue, 19 Jul 2022 01:48:26 -0400 Received: from mail-pg1-x533.google.com (mail-pg1-x533.google.com [IPv6:2607:f8b0:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0543D25596 for ; Mon, 18 Jul 2022 22:48:26 -0700 (PDT) Received: by mail-pg1-x533.google.com with SMTP id r186so12566302pgr.2 for ; Mon, 18 Jul 2022 22:48:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1Zv1KPN9JiNDXsrpx/KpRv4jlVQ/XgtQ+la2iBvvbEo=; b=aPmyhgHbEj3yjha+RdH7+WmsgzNU6UK2PdYcjlAmGBwYMtEf1UUTaGFvA/5q3/uqf2 TSB6Pb0KkVqQxl+mHM+p05+aB2P5iNDR4JPwth096jqb6fK+ei29DWXX6/m5v9EsqHiI 4EJ/DM1d9n7Rq270JbzZLvMOQyJDkGEGWn0b9gPk0e8WV0U9tV5+yXOwjV8pN4Ua2ZPA ZX5FKnH5IeeNqaVG+9NH1B6+Sz/m4+M852tl3ArR+1lescplIrffsGg4Y9JW/C4xwctn gGtD4KLl+OQq9rj6VoPFcNUtmF+IrtEbwKLvDpQcEIUsvhbJOXyJwOzd5tEghk+vQCC2 gGGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1Zv1KPN9JiNDXsrpx/KpRv4jlVQ/XgtQ+la2iBvvbEo=; b=rS11YV0Tq0OWeBpNmREMspuR8q5yNipEfyo8U/Gt07XweWQxmXZ4QKF843SHH2Ii9Z GWnYq54mK6o8x4VDwUwlywLRF3omlisDiotYFtmro+y6t/tWzZzbucdgiZdHZbU4iBLC O0/xIorSXz8Ttfzqs9aj3uJsXjhQddeFQQpHx38otDgpvL7SI5fkPEGshRfy62RCU8Yj c6Us7keJQW9rFcuOny+LtWl594h4hGsALE220idZ/XHv0qPN8phTOGAzuiCMRumedBYw KNTuLNBBuQPjdgL5jDH8kgg31s0xHfMC5K5vyp4KPkhH+SwK50AFIg8D0/3OBYwcWG6f XSSg== X-Gm-Message-State: AJIora+8UGvATRDUK3/U2GzOUoh4LL5GkkKvYR8I5TOCVl8u9bAE+JWT aBMQBPkkMY0uE0vbTBUkfTv6sA== X-Google-Smtp-Source: AGRyM1swatdkW28ipNZyiwyjPCdj/wjSf0JTm3UtSlnt0QiJb65SJO6lfU4nMttdr1PWPl6x72yPxg== X-Received: by 2002:aa7:8887:0:b0:52b:17e8:fc7 with SMTP id z7-20020aa78887000000b0052b17e80fc7mr28107122pfe.35.1658209705381; Mon, 18 Jul 2022 22:48:25 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.93.102]) by smtp.gmail.com with ESMTPSA id o186-20020a62cdc3000000b0050dc7628171sm10374129pfg.75.2022.07.18.22.48.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 22:48:24 -0700 (PDT) From: Anup Patel To: Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Daniel Lezcano , Thomas Gleixner Cc: Atish Patra , Samuel Holland , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH 1/2] dt-bindings: riscv: Add optional DT property riscv,timer-always-on Date: Tue, 19 Jul 2022 11:17:28 +0530 Message-Id: <20220719054729.2224766-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220719054729.2224766-1-apatel@ventanamicro.com> References: <20220719054729.2224766-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We add an optional DT property riscv,timer-always-on which if present in CPU DT node then CPU timer is always powered-on and never loses context. Signed-off-by: Anup Patel --- Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentat= ion/devicetree/bindings/riscv/cpus.yaml index d632ac76532e..33832b8dfaab 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -78,6 +78,12 @@ properties: - rv64imac - rv64imafdc =20 + riscv,timer-always-on: + type: boolean + description: + If present, the timer is powered through an always-on power + domain, therefore it never loses context. + # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false =20 --=20 2.34.1 From nobody Sat Apr 18 02:47:34 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ACA2CC433EF for ; Tue, 19 Jul 2022 05:48:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236816AbiGSFsi (ORCPT ); Tue, 19 Jul 2022 01:48:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48974 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236779AbiGSFsa (ORCPT ); Tue, 19 Jul 2022 01:48:30 -0400 Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1779B2CDF8 for ; Mon, 18 Jul 2022 22:48:30 -0700 (PDT) Received: by mail-pj1-x102f.google.com with SMTP id s21so13722308pjq.4 for ; Mon, 18 Jul 2022 22:48:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jlHFWO4BUKOhkSLA3ixeUG8K1wKBWBAz4fLmjE1iQBA=; b=ZBkkCxufH7ydH8OKvcGhQe+q/xQvww1z1TdeoI+35Id+tJRpE/dbzKRO4vJ5pWvPwZ p7sdoPv4pe3n1JOvVjFNLo/7AeFaoKNbq+cvIurPcAx/C7bjAjAoKL295axJKCLcrzPX bBulGkELrm14unIvVSkLLxfAdEGa6DDBDeeHB8NdAC8zAYqfOOaushPnMmqT7cC44Vaj 1FM5Z76yv7FOnMOI8p801088ELpLTMTUY5r6qHN0QunIZtJebSVjCGR/gIZPVmtVMvgw fsVkxX56YVN4t6oXJ+kAvKHWDmvF/scTky3P6ws6shrPyGguRWvpptiBwsOjecnCoFGa c6aQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jlHFWO4BUKOhkSLA3ixeUG8K1wKBWBAz4fLmjE1iQBA=; b=asxYHigXnyduyQW+imWfzEziJxTFtTkv60znGUdDdUZwwsnDnJS0OUlbxXQaWIPaGJ NwlhdqHFgGQDR3dS0kxowIf3pAIE3jzck1IJ5Bp7vrbsooYCGMiOkdiqiKmtaYJtSsrQ gF1qbG1vOH04fnrJOy/SxFxl2x1nWlwgwCFtSsHgf6chDnP5TK7rjjhQPVQ81uYsDXX+ nSDnzujsvQAjp3mL5V0BAM6o8hNMOb66S8FyDRi58d6eDwOpiUkZSmcvMmWyXa1qoeRZ 8u0isf1yfo7p5ZCO49jl8+VybtNWYQdJeVDGgo3ynVGX1mA0zAetr5OCZjH8CJdXO/R6 Jhcg== X-Gm-Message-State: AJIora9l0XmxhwZJR7sJF7CyHOI1sJ1jwdXPbir4CEHccWXhWbCWD1si 5cwhuJ9p1r36lADekKaWsBIJ6A== X-Google-Smtp-Source: AGRyM1tbCDz5SQoHGY0Cz35UcNtVlaAQaLE3yMTc5wyWn7kRDXfNXmJbqvJWzumgav4UYhPSSq5bfQ== X-Received: by 2002:a17:902:ce09:b0:16c:c7b6:8b63 with SMTP id k9-20020a170902ce0900b0016cc7b68b63mr21511826plg.35.1658209709512; Mon, 18 Jul 2022 22:48:29 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.93.102]) by smtp.gmail.com with ESMTPSA id o186-20020a62cdc3000000b0050dc7628171sm10374129pfg.75.2022.07.18.22.48.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 22:48:28 -0700 (PDT) From: Anup Patel To: Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Daniel Lezcano , Thomas Gleixner Cc: Atish Patra , Samuel Holland , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH 2/2] clocksource: timer-riscv: Set CLOCK_EVT_FEAT_C3STOP based on DT property Date: Tue, 19 Jul 2022 11:17:29 +0530 Message-Id: <20220719054729.2224766-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220719054729.2224766-1-apatel@ventanamicro.com> References: <20220719054729.2224766-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We should set CLOCK_EVT_FEAT_C3STOP for a clock_event_device only when riscv,timer-always-on DT property is not present for the corresponding CPU. This way CLOCK_EVT_FEAT_C3STOP feature is set for clock_event_device based on RISC-V platform capabilities rather than having it set for all RISC-V platforms. Signed-off-by: Anup Patel --- drivers/clocksource/timer-riscv.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-= riscv.c index 593d5a957b69..3015324f2b59 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -34,7 +34,7 @@ static int riscv_clock_next_event(unsigned long delta, static unsigned int riscv_clock_event_irq; static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) =3D { .name =3D "riscv_timer_clockevent", - .features =3D CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP, + .features =3D CLOCK_EVT_FEAT_ONESHOT, .rating =3D 100, .set_next_event =3D riscv_clock_next_event, }; @@ -65,9 +65,13 @@ static struct clocksource riscv_clocksource =3D { static int riscv_timer_starting_cpu(unsigned int cpu) { struct clock_event_device *ce =3D per_cpu_ptr(&riscv_clock_event, cpu); + struct device_node *np =3D of_get_cpu_node(cpu, NULL); =20 ce->cpumask =3D cpumask_of(cpu); ce->irq =3D riscv_clock_event_irq; + if (!of_property_read_bool(np, "riscv,timer-always-on")) + ce->features |=3D CLOCK_EVT_FEAT_C3STOP; + of_node_put(np); clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff); =20 enable_percpu_irq(riscv_clock_event_irq, --=20 2.34.1