From nobody Sat Apr 18 07:43:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D7CEC433EF for ; Fri, 15 Jul 2022 14:20:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229951AbiGOOUL (ORCPT ); Fri, 15 Jul 2022 10:20:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45732 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229532AbiGOOUJ (ORCPT ); Fri, 15 Jul 2022 10:20:09 -0400 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.220.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 528A05C9C7; Fri, 15 Jul 2022 07:20:06 -0700 (PDT) Received: from relay2.suse.de (relay2.suse.de [149.44.160.134]) by smtp-out1.suse.de (Postfix) with ESMTP id 2446734DC8; Fri, 15 Jul 2022 14:20:03 +0000 (UTC) Received: from adalid.arch.suse.de (adalid.arch.suse.de [10.161.8.13]) by relay2.suse.de (Postfix) with ESMTP id 0BF6F2C141; Fri, 15 Jul 2022 14:20:03 +0000 (UTC) From: Thomas Bogendoerfer To: Linus Walleij , Bartosz Golaszewski , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [PATCH v3] gpio: remove VR41XX related gpio driver Date: Fri, 15 Jul 2022 16:19:59 +0200 Message-Id: <20220715142000.136855-1-tsbogend@alpha.franken.de> X-Mailer: git-send-email 2.29.2 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Commit d3164e2f3b0a ("MIPS: Remove VR41xx support") removed support for MIPS VR41xx platform, so remove exclusive drivers for this platform, too. Signed-off-by: Thomas Bogendoerfer --- Changes in v3: removed drivers/char changes Changes in v2: sent with correct mail address drivers/gpio/Kconfig | 6 - drivers/gpio/Makefile | 1 - drivers/gpio/gpio-vr41xx.c | 541 ------------------------------------- 3 files changed, 548 deletions(-) delete mode 100644 drivers/gpio/gpio-vr41xx.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index b01961999ced..224d5ead27bd 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -690,12 +690,6 @@ config GPIO_VISCONTI help Say yes here to support GPIO on Tohisba Visconti. =20 -config GPIO_VR41XX - tristate "NEC VR4100 series General-purpose I/O Unit support" - depends on CPU_VR41XX - help - Say yes here to support the NEC VR4100 series General-purpose I/O Unit. - config GPIO_VX855 tristate "VIA VX855/VX875 GPIO" depends on (X86 || COMPILE_TEST) && PCI diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 14352f6dfe8e..9d4805b2b60b 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -169,7 +169,6 @@ obj-$(CONFIG_GPIO_VF610) +=3D gpio-vf610.o obj-$(CONFIG_GPIO_VIPERBOARD) +=3D gpio-viperboard.o obj-$(CONFIG_GPIO_VIRTIO) +=3D gpio-virtio.o obj-$(CONFIG_GPIO_VISCONTI) +=3D gpio-visconti.o -obj-$(CONFIG_GPIO_VR41XX) +=3D gpio-vr41xx.o obj-$(CONFIG_GPIO_VX855) +=3D gpio-vx855.o obj-$(CONFIG_GPIO_WCD934X) +=3D gpio-wcd934x.o obj-$(CONFIG_GPIO_WHISKEY_COVE) +=3D gpio-wcove.o diff --git a/drivers/gpio/gpio-vr41xx.c b/drivers/gpio/gpio-vr41xx.c deleted file mode 100644 index 8d09b619c166..000000000000 --- a/drivers/gpio/gpio-vr41xx.c +++ /dev/null @@ -1,541 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Driver for NEC VR4100 series General-purpose I/O Unit. - * - * Copyright (C) 2002 MontaVista Software Inc. - * Author: Yoichi Yuasa - * Copyright (C) 2003-2009 Yoichi Yuasa - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -MODULE_AUTHOR("Yoichi Yuasa "); -MODULE_DESCRIPTION("NEC VR4100 series General-purpose I/O Unit driver"); -MODULE_LICENSE("GPL"); - -#define GIUIOSELL 0x00 -#define GIUIOSELH 0x02 -#define GIUPIODL 0x04 -#define GIUPIODH 0x06 -#define GIUINTSTATL 0x08 -#define GIUINTSTATH 0x0a -#define GIUINTENL 0x0c -#define GIUINTENH 0x0e -#define GIUINTTYPL 0x10 -#define GIUINTTYPH 0x12 -#define GIUINTALSELL 0x14 -#define GIUINTALSELH 0x16 -#define GIUINTHTSELL 0x18 -#define GIUINTHTSELH 0x1a -#define GIUPODATL 0x1c -#define GIUPODATEN 0x1c -#define GIUPODATH 0x1e - #define PIOEN0 0x0100 - #define PIOEN1 0x0200 -#define GIUPODAT 0x1e -#define GIUFEDGEINHL 0x20 -#define GIUFEDGEINHH 0x22 -#define GIUREDGEINHL 0x24 -#define GIUREDGEINHH 0x26 - -#define GIUUSEUPDN 0x1e0 -#define GIUTERMUPDN 0x1e2 - -#define GPIO_HAS_PULLUPDOWN_IO 0x0001 -#define GPIO_HAS_OUTPUT_ENABLE 0x0002 -#define GPIO_HAS_INTERRUPT_EDGE_SELECT 0x0100 - -enum { - GPIO_INPUT, - GPIO_OUTPUT, -}; - -static DEFINE_SPINLOCK(giu_lock); -static unsigned long giu_flags; - -static void __iomem *giu_base; -static struct gpio_chip vr41xx_gpio_chip; - -#define giu_read(offset) readw(giu_base + (offset)) -#define giu_write(offset, value) writew((value), giu_base + (offset)) - -#define GPIO_PIN_OF_IRQ(irq) ((irq) - GIU_IRQ_BASE) -#define GIUINT_HIGH_OFFSET 16 -#define GIUINT_HIGH_MAX 32 - -static inline u16 giu_set(u16 offset, u16 set) -{ - u16 data; - - data =3D giu_read(offset); - data |=3D set; - giu_write(offset, data); - - return data; -} - -static inline u16 giu_clear(u16 offset, u16 clear) -{ - u16 data; - - data =3D giu_read(offset); - data &=3D ~clear; - giu_write(offset, data); - - return data; -} - -static void ack_giuint_low(struct irq_data *d) -{ - giu_write(GIUINTSTATL, 1 << GPIO_PIN_OF_IRQ(d->irq)); -} - -static void mask_giuint_low(struct irq_data *d) -{ - giu_clear(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(d->irq)); -} - -static void mask_ack_giuint_low(struct irq_data *d) -{ - unsigned int pin; - - pin =3D GPIO_PIN_OF_IRQ(d->irq); - giu_clear(GIUINTENL, 1 << pin); - giu_write(GIUINTSTATL, 1 << pin); -} - -static void unmask_giuint_low(struct irq_data *d) -{ - giu_set(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(d->irq)); -} - -static unsigned int startup_giuint(struct irq_data *data) -{ - int ret; - - ret =3D gpiochip_lock_as_irq(&vr41xx_gpio_chip, irqd_to_hwirq(data)); - if (ret) { - dev_err(vr41xx_gpio_chip.parent, - "unable to lock HW IRQ %lu for IRQ\n", - data->hwirq); - return ret; - } - - /* Satisfy the .enable semantics by unmasking the line */ - unmask_giuint_low(data); - return 0; -} - -static void shutdown_giuint(struct irq_data *data) -{ - mask_giuint_low(data); - gpiochip_unlock_as_irq(&vr41xx_gpio_chip, data->hwirq); -} - -static struct irq_chip giuint_low_irq_chip =3D { - .name =3D "GIUINTL", - .irq_ack =3D ack_giuint_low, - .irq_mask =3D mask_giuint_low, - .irq_mask_ack =3D mask_ack_giuint_low, - .irq_unmask =3D unmask_giuint_low, - .irq_startup =3D startup_giuint, - .irq_shutdown =3D shutdown_giuint, -}; - -static void ack_giuint_high(struct irq_data *d) -{ - giu_write(GIUINTSTATH, - 1 << (GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET)); -} - -static void mask_giuint_high(struct irq_data *d) -{ - giu_clear(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET)); -} - -static void mask_ack_giuint_high(struct irq_data *d) -{ - unsigned int pin; - - pin =3D GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET; - giu_clear(GIUINTENH, 1 << pin); - giu_write(GIUINTSTATH, 1 << pin); -} - -static void unmask_giuint_high(struct irq_data *d) -{ - giu_set(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET)); -} - -static struct irq_chip giuint_high_irq_chip =3D { - .name =3D "GIUINTH", - .irq_ack =3D ack_giuint_high, - .irq_mask =3D mask_giuint_high, - .irq_mask_ack =3D mask_ack_giuint_high, - .irq_unmask =3D unmask_giuint_high, -}; - -static int giu_get_irq(unsigned int irq) -{ - u16 pendl, pendh, maskl, maskh; - int i; - - pendl =3D giu_read(GIUINTSTATL); - pendh =3D giu_read(GIUINTSTATH); - maskl =3D giu_read(GIUINTENL); - maskh =3D giu_read(GIUINTENH); - - maskl &=3D pendl; - maskh &=3D pendh; - - if (maskl) { - for (i =3D 0; i < 16; i++) { - if (maskl & (1 << i)) - return GIU_IRQ(i); - } - } else if (maskh) { - for (i =3D 0; i < 16; i++) { - if (maskh & (1 << i)) - return GIU_IRQ(i + GIUINT_HIGH_OFFSET); - } - } - - printk(KERN_ERR "spurious GIU interrupt: %04x(%04x),%04x(%04x)\n", - maskl, pendl, maskh, pendh); - - return -EINVAL; -} - -void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger, - irq_signal_t signal) -{ - u16 mask; - - if (pin < GIUINT_HIGH_OFFSET) { - mask =3D 1 << pin; - if (trigger !=3D IRQ_TRIGGER_LEVEL) { - giu_set(GIUINTTYPL, mask); - if (signal =3D=3D IRQ_SIGNAL_HOLD) - giu_set(GIUINTHTSELL, mask); - else - giu_clear(GIUINTHTSELL, mask); - if (giu_flags & GPIO_HAS_INTERRUPT_EDGE_SELECT) { - switch (trigger) { - case IRQ_TRIGGER_EDGE_FALLING: - giu_set(GIUFEDGEINHL, mask); - giu_clear(GIUREDGEINHL, mask); - break; - case IRQ_TRIGGER_EDGE_RISING: - giu_clear(GIUFEDGEINHL, mask); - giu_set(GIUREDGEINHL, mask); - break; - default: - giu_set(GIUFEDGEINHL, mask); - giu_set(GIUREDGEINHL, mask); - break; - } - } - irq_set_chip_and_handler(GIU_IRQ(pin), - &giuint_low_irq_chip, - handle_edge_irq); - } else { - giu_clear(GIUINTTYPL, mask); - giu_clear(GIUINTHTSELL, mask); - irq_set_chip_and_handler(GIU_IRQ(pin), - &giuint_low_irq_chip, - handle_level_irq); - } - giu_write(GIUINTSTATL, mask); - } else if (pin < GIUINT_HIGH_MAX) { - mask =3D 1 << (pin - GIUINT_HIGH_OFFSET); - if (trigger !=3D IRQ_TRIGGER_LEVEL) { - giu_set(GIUINTTYPH, mask); - if (signal =3D=3D IRQ_SIGNAL_HOLD) - giu_set(GIUINTHTSELH, mask); - else - giu_clear(GIUINTHTSELH, mask); - if (giu_flags & GPIO_HAS_INTERRUPT_EDGE_SELECT) { - switch (trigger) { - case IRQ_TRIGGER_EDGE_FALLING: - giu_set(GIUFEDGEINHH, mask); - giu_clear(GIUREDGEINHH, mask); - break; - case IRQ_TRIGGER_EDGE_RISING: - giu_clear(GIUFEDGEINHH, mask); - giu_set(GIUREDGEINHH, mask); - break; - default: - giu_set(GIUFEDGEINHH, mask); - giu_set(GIUREDGEINHH, mask); - break; - } - } - irq_set_chip_and_handler(GIU_IRQ(pin), - &giuint_high_irq_chip, - handle_edge_irq); - } else { - giu_clear(GIUINTTYPH, mask); - giu_clear(GIUINTHTSELH, mask); - irq_set_chip_and_handler(GIU_IRQ(pin), - &giuint_high_irq_chip, - handle_level_irq); - } - giu_write(GIUINTSTATH, mask); - } -} -EXPORT_SYMBOL_GPL(vr41xx_set_irq_trigger); - -void vr41xx_set_irq_level(unsigned int pin, irq_level_t level) -{ - u16 mask; - - if (pin < GIUINT_HIGH_OFFSET) { - mask =3D 1 << pin; - if (level =3D=3D IRQ_LEVEL_HIGH) - giu_set(GIUINTALSELL, mask); - else - giu_clear(GIUINTALSELL, mask); - giu_write(GIUINTSTATL, mask); - } else if (pin < GIUINT_HIGH_MAX) { - mask =3D 1 << (pin - GIUINT_HIGH_OFFSET); - if (level =3D=3D IRQ_LEVEL_HIGH) - giu_set(GIUINTALSELH, mask); - else - giu_clear(GIUINTALSELH, mask); - giu_write(GIUINTSTATH, mask); - } -} -EXPORT_SYMBOL_GPL(vr41xx_set_irq_level); - -static int giu_set_direction(struct gpio_chip *chip, unsigned pin, int dir) -{ - u16 offset, mask, reg; - unsigned long flags; - - if (pin >=3D chip->ngpio) - return -EINVAL; - - if (pin < 16) { - offset =3D GIUIOSELL; - mask =3D 1 << pin; - } else if (pin < 32) { - offset =3D GIUIOSELH; - mask =3D 1 << (pin - 16); - } else { - if (giu_flags & GPIO_HAS_OUTPUT_ENABLE) { - offset =3D GIUPODATEN; - mask =3D 1 << (pin - 32); - } else { - switch (pin) { - case 48: - offset =3D GIUPODATH; - mask =3D PIOEN0; - break; - case 49: - offset =3D GIUPODATH; - mask =3D PIOEN1; - break; - default: - return -EINVAL; - } - } - } - - spin_lock_irqsave(&giu_lock, flags); - - reg =3D giu_read(offset); - if (dir =3D=3D GPIO_OUTPUT) - reg |=3D mask; - else - reg &=3D ~mask; - giu_write(offset, reg); - - spin_unlock_irqrestore(&giu_lock, flags); - - return 0; -} - -static int vr41xx_gpio_get(struct gpio_chip *chip, unsigned pin) -{ - u16 reg, mask; - - if (pin >=3D chip->ngpio) - return -EINVAL; - - if (pin < 16) { - reg =3D giu_read(GIUPIODL); - mask =3D 1 << pin; - } else if (pin < 32) { - reg =3D giu_read(GIUPIODH); - mask =3D 1 << (pin - 16); - } else if (pin < 48) { - reg =3D giu_read(GIUPODATL); - mask =3D 1 << (pin - 32); - } else { - reg =3D giu_read(GIUPODATH); - mask =3D 1 << (pin - 48); - } - - if (reg & mask) - return 1; - - return 0; -} - -static void vr41xx_gpio_set(struct gpio_chip *chip, unsigned pin, - int value) -{ - u16 offset, mask, reg; - unsigned long flags; - - if (pin >=3D chip->ngpio) - return; - - if (pin < 16) { - offset =3D GIUPIODL; - mask =3D 1 << pin; - } else if (pin < 32) { - offset =3D GIUPIODH; - mask =3D 1 << (pin - 16); - } else if (pin < 48) { - offset =3D GIUPODATL; - mask =3D 1 << (pin - 32); - } else { - offset =3D GIUPODATH; - mask =3D 1 << (pin - 48); - } - - spin_lock_irqsave(&giu_lock, flags); - - reg =3D giu_read(offset); - if (value) - reg |=3D mask; - else - reg &=3D ~mask; - giu_write(offset, reg); - - spin_unlock_irqrestore(&giu_lock, flags); -} - - -static int vr41xx_gpio_direction_input(struct gpio_chip *chip, unsigned of= fset) -{ - return giu_set_direction(chip, offset, GPIO_INPUT); -} - -static int vr41xx_gpio_direction_output(struct gpio_chip *chip, unsigned o= ffset, - int value) -{ - vr41xx_gpio_set(chip, offset, value); - - return giu_set_direction(chip, offset, GPIO_OUTPUT); -} - -static int vr41xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset) -{ - if (offset >=3D chip->ngpio) - return -EINVAL; - - return GIU_IRQ_BASE + offset; -} - -static struct gpio_chip vr41xx_gpio_chip =3D { - .label =3D "vr41xx", - .owner =3D THIS_MODULE, - .direction_input =3D vr41xx_gpio_direction_input, - .get =3D vr41xx_gpio_get, - .direction_output =3D vr41xx_gpio_direction_output, - .set =3D vr41xx_gpio_set, - .to_irq =3D vr41xx_gpio_to_irq, -}; - -static int giu_probe(struct platform_device *pdev) -{ - unsigned int trigger, i, pin; - struct irq_chip *chip; - int irq; - - switch (pdev->id) { - case GPIO_50PINS_PULLUPDOWN: - giu_flags =3D GPIO_HAS_PULLUPDOWN_IO; - vr41xx_gpio_chip.ngpio =3D 50; - break; - case GPIO_36PINS: - vr41xx_gpio_chip.ngpio =3D 36; - break; - case GPIO_48PINS_EDGE_SELECT: - giu_flags =3D GPIO_HAS_INTERRUPT_EDGE_SELECT; - vr41xx_gpio_chip.ngpio =3D 48; - break; - default: - dev_err(&pdev->dev, "GIU: unknown ID %d\n", pdev->id); - return -ENODEV; - } - - giu_base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(giu_base)) - return PTR_ERR(giu_base); - - vr41xx_gpio_chip.parent =3D &pdev->dev; - - if (gpiochip_add_data(&vr41xx_gpio_chip, NULL)) - return -ENODEV; - - giu_write(GIUINTENL, 0); - giu_write(GIUINTENH, 0); - - trigger =3D giu_read(GIUINTTYPH) << 16; - trigger |=3D giu_read(GIUINTTYPL); - for (i =3D GIU_IRQ_BASE; i <=3D GIU_IRQ_LAST; i++) { - pin =3D GPIO_PIN_OF_IRQ(i); - if (pin < GIUINT_HIGH_OFFSET) - chip =3D &giuint_low_irq_chip; - else - chip =3D &giuint_high_irq_chip; - - if (trigger & (1 << pin)) - irq_set_chip_and_handler(i, chip, handle_edge_irq); - else - irq_set_chip_and_handler(i, chip, handle_level_irq); - - } - - irq =3D platform_get_irq(pdev, 0); - if (irq < 0 || irq >=3D nr_irqs) - return -EBUSY; - - return cascade_irq(irq, giu_get_irq); -} - -static int giu_remove(struct platform_device *pdev) -{ - if (giu_base) { - giu_base =3D NULL; - } - - return 0; -} - -static struct platform_driver giu_device_driver =3D { - .probe =3D giu_probe, - .remove =3D giu_remove, - .driver =3D { - .name =3D "GIU", - }, -}; - -module_platform_driver(giu_device_driver); --=20 2.29.2