From nobody Sat Apr 18 10:53:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 742BEC43334 for ; Thu, 14 Jul 2022 16:56:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239693AbiGNQ4B (ORCPT ); Thu, 14 Jul 2022 12:56:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238624AbiGNQz4 (ORCPT ); Thu, 14 Jul 2022 12:55:56 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 522114B0EF for ; Thu, 14 Jul 2022 09:55:55 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id z12so3368783wrq.7 for ; Thu, 14 Jul 2022 09:55:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ay55aei4xTrkHOP8ZwisRNILeuMCaqkFFuCni3Xut2k=; b=n/n3e8j6bJWOXrP95ItdWQVXPuQ0bCFwqzgIEykBYyxN3XjVeTR1h2M0DL/r3D8+I3 /wlwQamJPhfWq2SMEaES+gscw97bq95Af/SwrUZ2xpihPH0LoDtjSyx5KZ6OX7VHh74Y 2ThjifUbf5gBCXdAxi6cnn/9ECyQgHcx/tFyUwbKgSYON23z/QjPXt+UL4mCPvkiiaZB BfzF+kdEOK7IsC22SKqdZgxtyODLUH00aerRHytO8EVmLyMQvKNSH8tlkSRlFMtdPxel VtKnZSYceBp0ZlmE4s7lh/U+Mu4GNt0iBnfIIbXLxlDhGzjC/okAk+Tc/d5AcgkHDnqB b8Qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ay55aei4xTrkHOP8ZwisRNILeuMCaqkFFuCni3Xut2k=; b=JlfuaIMdlqRjgoQfpioiYl9RnAoaEl7UNO6GmxcH94VWwa99W0fiFlDEHlTDv3Y+92 yFw+dkEWte6ofre/2CDNFeX3t6Hmu7LnNyigTgzMcEAReM9HwmRxvaJJPTg+wlrlsX2M 26Iwv0JggvlUy1WFp0TaC8ykEyEcTmVKKDZzuQTB3yOg/uZ1SGW/7oLDMNL2gPZZ/H/k Ar6weXGpI6Jr6oWm34+6zPazbv7CrbjUg/tZYUg/FFCoQtx3/sxCYpbyjqna/Ws2jwcm RVxpWjTe8BbTIQUrJPQxJtrs3zhqff3pvFHBV3Dh3RPHkIvmX13dwxcI0Ay9hG/A5f2g zUPA== X-Gm-Message-State: AJIora9WRUg2GHGDjPwGVFRLGcAdCxwoMgltMx1z/WLMB1qs5A0PZcZp q5W7pLbHj8WtD1T93JFWxxeZ1oj6qkX17IH+ X-Google-Smtp-Source: AGRyM1vl2oDUNW33308hydkFGVWAVq3Dvpg9TwiwSGovoYQ89wJOF+Z1+82DoJM6Mkt65ij0+18yVw== X-Received: by 2002:a05:6000:381:b0:21d:bb54:ae2c with SMTP id u1-20020a056000038100b0021dbb54ae2cmr8677229wrf.222.1657817753512; Thu, 14 Jul 2022 09:55:53 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id j9-20020a05600c190900b0039db31f6372sm7440915wmq.2.2022.07.14.09.55.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 09:55:53 -0700 (PDT) From: Sam Protsenko To: Marek Szyprowski , Krzysztof Kozlowski Cc: Joerg Roedel , Will Deacon , Robin Murphy , Janghyuck Kim , Cho KyongHo , Daniel Mentz , David Virag , Sumit Semwal , iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/6] iommu/exynos: Reuse SysMMU constants for page size and order Date: Thu, 14 Jul 2022 19:55:45 +0300 Message-Id: <20220714165550.8884-2-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220714165550.8884-1-semen.protsenko@linaro.org> References: <20220714165550.8884-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Using SZ_4K in context of SysMMU driver is better than using PAGE_SIZE, as PAGE_SIZE might have different value on different platforms. Though it would be even better to use more specific constants, already existing in SysMMU driver. Make the code more strict by using SPAGE_ORDER and SPAGE_SIZE constants. It also makes sense, as __sysmmu_tlb_invalidate_entry() also uses SPAGE_* constants for further calculations with num_inv param, so it's logical that num_inv should be previously calculated using also SPAGE_* values. Signed-off-by: Sam Protsenko Reviewed-by: Krzysztof Kozlowski Acked-by: Marek Szyprowski --- Changes in v3: - Added Marek's Acked-by tag - Added Krzysztof's R-b tag Changes in v2: - (none) This patch is new and added in v2 drivers/iommu/exynos-iommu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index 79729892eb48..8f80aaa35092 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -340,7 +340,7 @@ static void __sysmmu_set_ptbase(struct sysmmu_drvdata *= data, phys_addr_t pgd) if (MMU_MAJ_VER(data->version) < 5) writel(pgd, data->sfrbase + REG_PT_BASE_ADDR); else - writel(pgd / SZ_4K, data->sfrbase + REG_V5_PT_BASE_PFN); + writel(pgd >> SPAGE_ORDER, data->sfrbase + REG_V5_PT_BASE_PFN); =20 __sysmmu_tlb_invalidate(data); } @@ -550,7 +550,7 @@ static void sysmmu_tlb_invalidate_entry(struct sysmmu_d= rvdata *data, * 64KB page can be one of 16 consecutive sets. */ if (MMU_MAJ_VER(data->version) =3D=3D 2) - num_inv =3D min_t(unsigned int, size / SZ_4K, 64); + num_inv =3D min_t(unsigned int, size / SPAGE_SIZE, 64); =20 if (sysmmu_block(data)) { __sysmmu_tlb_invalidate_entry(data, iova, num_inv); --=20 2.30.2 From nobody Sat Apr 18 10:53:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16344C43334 for ; Thu, 14 Jul 2022 16:56:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240028AbiGNQ4J (ORCPT ); Thu, 14 Jul 2022 12:56:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56840 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239267AbiGNQz5 (ORCPT ); Thu, 14 Jul 2022 12:55:57 -0400 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B9084F6B8 for ; Thu, 14 Jul 2022 09:55:56 -0700 (PDT) Received: by mail-wr1-x434.google.com with SMTP id a5so3334272wrx.12 for ; Thu, 14 Jul 2022 09:55:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=S2fOwRS7PBfoQ/JKwgWoKuZEaYFo7PU9A3pBuSjiPrw=; b=FJYTZoClCTlgrArGKeLYT8JUYfT6a60vzX4X3MgwAp51q4tyoTeo+z3gFLcTsZ2bEo j5hT5ULynZb3pQJxareXMpi7f4RSaQGIqIRmviSi/4Xus+TNZzAs7hp452FuzBLFcg7w ywRqEzWxw2c5kKbfm7iRwREbZpU/D9Jbff+gcPJmQI20iQSSqv+5mKOSIMME1uH6Csqf 4IHfl34HFOIAJvzJabWhKe77UZiHWzC+CtPvYvqQXckMhS4zPEQZF4UX1Zw1vDU0/CAt dPiIkVHGtob3+NZ66Xeonz4SYNmBVvCx8iC2hnD+CoOV7FIha5uMQbJ52A7oHmZvbs3I 60LA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=S2fOwRS7PBfoQ/JKwgWoKuZEaYFo7PU9A3pBuSjiPrw=; b=xedD29cWNs8NAd4978CAbO+8Blpjn32Guf4F3vfAhqten/Rhob/5oumjQQaI9Vn3vm tKXQqx3SL3iwaISWUZsNu89vPAnajLsoD2EwNHEuySzlY7ZHcwko5uApdukatozkK9Ql qadA9Y62xOp0pBkCO0tsD0426HqG3s5lh/I0aKFGBxln8oMEzxidAVp/ntorFoXzqcxz fddM4dinf4mN2hNx72v1j+DR7Xa3bi0hT8BGNnMShkKe7Pq6ULFzvk8ubTxi8Y3AXPCx f6JaKN4+vULr0yJgC/kRLKIPfP3IfgczPDIQhy77CVVVuVM+Oi0hgVC5L/puTZH5K1qv 8r3A== X-Gm-Message-State: AJIora+7yDnfSH4rsrb+xwKMYBrgNV8Ss1+/A5ldl8fgdwdJbR5TTXzv 4yscl2EkUc1gq4wSc2ACME3OWQ== X-Google-Smtp-Source: AGRyM1uOCE0ebi2E5Ao34myU6FQDDLS+28S7amW2//dWGnRsQjZ0isNECaLLQ5j97W3z0Vyo//ZQ7g== X-Received: by 2002:a5d:6489:0:b0:21d:a9a1:3511 with SMTP id o9-20020a5d6489000000b0021da9a13511mr8725414wri.626.1657817754857; Thu, 14 Jul 2022 09:55:54 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id z8-20020a1c4c08000000b003942a244f40sm5706762wmf.25.2022.07.14.09.55.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 09:55:54 -0700 (PDT) From: Sam Protsenko To: Marek Szyprowski , Krzysztof Kozlowski Cc: Joerg Roedel , Will Deacon , Robin Murphy , Janghyuck Kim , Cho KyongHo , Daniel Mentz , David Virag , Sumit Semwal , iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/6] iommu/exynos: Handle failed IOMMU device registration properly Date: Thu, 14 Jul 2022 19:55:46 +0300 Message-Id: <20220714165550.8884-3-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220714165550.8884-1-semen.protsenko@linaro.org> References: <20220714165550.8884-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If iommu_device_register() fails in exynos_sysmmu_probe(), the previous calls have to be cleaned up. In this case, the iommu_device_sysfs_add() should be cleaned up, by calling its remove counterpart call. Fixes: d2c302b6e8b1 ("iommu/exynos: Make use of iommu_device_register inter= face") Signed-off-by: Sam Protsenko Reviewed-by: Krzysztof Kozlowski Acked-by: Marek Szyprowski --- Changes in v3: - Added Marek's Acked-by tag - Added Krzysztof's R-b tag - Added "Fixes" tag, as suggested by Krzysztof Changes in v2: - (none) This patch is new and added in v2 drivers/iommu/exynos-iommu.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index 8f80aaa35092..c85db9dab851 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -629,7 +629,7 @@ static int exynos_sysmmu_probe(struct platform_device *= pdev) =20 ret =3D iommu_device_register(&data->iommu, &exynos_iommu_ops, dev); if (ret) - return ret; + goto err_iommu_register; =20 platform_set_drvdata(pdev, data); =20 @@ -656,6 +656,10 @@ static int exynos_sysmmu_probe(struct platform_device = *pdev) pm_runtime_enable(dev); =20 return 0; + +err_iommu_register: + iommu_device_sysfs_remove(&data->iommu); + return ret; } =20 static int __maybe_unused exynos_sysmmu_suspend(struct device *dev) --=20 2.30.2 From nobody Sat Apr 18 10:53:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC559C433EF for ; Thu, 14 Jul 2022 16:56:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240245AbiGNQ4O (ORCPT ); Thu, 14 Jul 2022 12:56:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56932 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239150AbiGNQz6 (ORCPT ); Thu, 14 Jul 2022 12:55:58 -0400 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C735852FE0 for ; Thu, 14 Jul 2022 09:55:57 -0700 (PDT) Received: by mail-wm1-x335.google.com with SMTP id h14-20020a1ccc0e000000b0039eff745c53so1565682wmb.5 for ; Thu, 14 Jul 2022 09:55:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IZpjZAr4g1dpDBXrOrcfUkHPeUERh/JliRxp06JVucg=; b=W+Cm9cW/KqhsoUWLtK5lM2En6frOk3DnHTnfxJ1rLk8V1Yy7iqDT/XaD3KJvZtRB2s +wI1V2J9RGVol7di4+23oo12YHUhRPKldPKSV9YjJ5yjRhjrP2WaAN5WBs0dNPgnNpad HuJTHxC2yiT+rhVjRowuYazf0MbDsgo69VCsIM7HubxLF7kelLSkr0esfPhTrUxEUoAj qUDA/f2J+d74jP7aA8vMRl/XbZaIPTTn4CP/4jHqkfLZl09qcxuI9UEK/0ESchYUL1Bo wEKWTz5GNh1u+XnfmJpCtUYZJu5ERLefGE8Eh3Pylxz82X29Qo84Fi4d8pzdT2NYw5FK AGwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IZpjZAr4g1dpDBXrOrcfUkHPeUERh/JliRxp06JVucg=; b=kXPpuJ6iON6RyUXmvc/N+Cp1gtp5AlV3TeLqtxuSKVTN9GgZNnZI/d2YyCOMopPBUk dCLEqTY1z5OJeVEPrBAMj5Cp8+fn0CDvTAgtGSmfsu0bMRBS0fD/ElTW9oEh5GqmVO2v nR/IFgyMrpAPsp5svpvmEja+LdRrQGLc7G4g2kou9z/UXhJmYAPFc49YXjKxBwqdks3x bZWmu51N2dC+wcBgPsjL84NSslBm4e+tB/fGhMCl4RZawanMG+oFXpb8zwS43B0gJNmr gI7gmuT3yyZJXKZnzSnH1eiJWyC/S4ni4AqQsf/UHON9Yqrn8OcgeCSUM+Aeq4os+SJL 2HzQ== X-Gm-Message-State: AJIora+L7g54jdfrrpglwNGJcRMS0osStD+XvpEIcWWd9UkJ+3RXtFJ3 1mLLhklQ1hVlxsRNNKvsHU8kpQ== X-Google-Smtp-Source: AGRyM1s5SKEFz/1UdqSHlysek2UsdEyn9+B60Wl05LPjeSEpx2hr6sr3sPBM4eoFrT1tNuALszo/rg== X-Received: by 2002:a05:600c:1e87:b0:3a2:fd16:5934 with SMTP id be7-20020a05600c1e8700b003a2fd165934mr9028538wmb.25.1657817756378; Thu, 14 Jul 2022 09:55:56 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id l13-20020a05600c2ccd00b003a2f2bb72d5sm5516033wmc.45.2022.07.14.09.55.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 09:55:55 -0700 (PDT) From: Sam Protsenko To: Marek Szyprowski , Krzysztof Kozlowski Cc: Joerg Roedel , Will Deacon , Robin Murphy , Janghyuck Kim , Cho KyongHo , Daniel Mentz , David Virag , Sumit Semwal , iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/6] iommu/exynos: Set correct dma mask for SysMMU v5+ Date: Thu, 14 Jul 2022 19:55:47 +0300 Message-Id: <20220714165550.8884-4-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220714165550.8884-1-semen.protsenko@linaro.org> References: <20220714165550.8884-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SysMMU v5+ supports 36 bit physical address space. Set corresponding DMA mask to avoid falling back to SWTLBIO usage in dma_map_single() because of failed dma_capable() check. The original code for this fix was suggested by Marek. Signed-off-by: Sam Protsenko Co-developed-by: Marek Szyprowski Signed-off-by: Marek Szyprowski Acked-by: Krzysztof Kozlowski --- Changes in v3: - Added Krzysztof's Acked-by tag Changes in v2: - Handled failed dma_set_mask() call - Replaced "Originally-by" tag by "Co-developed-by" + SoB tags drivers/iommu/exynos-iommu.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index c85db9dab851..494f7d7aa9c5 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -646,6 +646,14 @@ static int exynos_sysmmu_probe(struct platform_device = *pdev) } } =20 + if (MMU_MAJ_VER(data->version) >=3D 5) { + ret =3D dma_set_mask(dev, DMA_BIT_MASK(36)); + if (ret) { + dev_err(dev, "Unable to set DMA mask: %d\n", ret); + goto err_dma_set_mask; + } + } + /* * use the first registered sysmmu device for performing * dma mapping operations on iommu page tables (cpu cache flush) @@ -657,6 +665,8 @@ static int exynos_sysmmu_probe(struct platform_device *= pdev) =20 return 0; =20 +err_dma_set_mask: + iommu_device_unregister(&data->iommu); err_iommu_register: iommu_device_sysfs_remove(&data->iommu); return ret; --=20 2.30.2 From nobody Sat Apr 18 10:53:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D43C3C433EF for ; Thu, 14 Jul 2022 16:56:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240284AbiGNQ4R (ORCPT ); Thu, 14 Jul 2022 12:56:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56932 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239555AbiGNQ4B (ORCPT ); Thu, 14 Jul 2022 12:56:01 -0400 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B4514BD2A for ; Thu, 14 Jul 2022 09:55:59 -0700 (PDT) Received: by mail-wm1-x32f.google.com with SMTP id i204-20020a1c3bd5000000b003a2fa488efdso3076183wma.4 for ; Thu, 14 Jul 2022 09:55:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ABbzKk/sxz3POb/Xov9eiP5fUgIWe8jtTJuKOXitFhI=; b=ksSS2xxwNkmUX9p310Z0U9LSRA5cdiAu/XA/HO6LifqxJjYqzLajAN16cai+U8KyfZ Z954IRliopxFweXjmk4TJjz+bnRBrHBhZuMRik4H3U38WYtJ9ONz6QnEKVTbrrJ1kBkI Cr5Aqh6Xd1SDSuo7BVSeekBDQNxggADVXRuqHB0raotCYzBYNzjlCBBhSZIlmrJFbQXE EdJPlOZDPQmkwPMFmil8kFZM14o1j9cX3j3L6nYgoQ/R4vAH2betfrXE/DjIQd4mgTX0 j7EA3ME2aqPCPdY2lsOOCigdcNDdZFQR6q5giFSW+6wWjTwLExeRNDNrZW1DcI9rw7FB eARg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ABbzKk/sxz3POb/Xov9eiP5fUgIWe8jtTJuKOXitFhI=; b=F1g4HtnD2cyUzFitXaxKu5xb0HJIytPdVVTeY3R6zUMj5OvneqANzRwSjUePgQU+hx JFL6O5RSEqWtoVbjos31Wc9GMi/e3RnbcV3K6LgdgpkfBb9iLDmZEndmiE6xMnfpCYo9 aV3vIjQMTQNDI4Yfgt8xATftYaiYUJK/RdtdepwUBPOSceFYD10/9ZtSZj9J+DvClyzb oR9zOqOzLI2/X2+BD+KiIcmPwqp3L69XYzCXz3jFOfSmwDZTsDvhgyWaEsBBPw6Ew7Yz g0BLTIB2EP86t1uWrcOH90i3iIWsq/vkJWVcz9hsNJ2BtHXVBpNq3q/zw6t9iYrVQRZG hBmg== X-Gm-Message-State: AJIora/5BrnjWGu49Hqi1aSiIH5tkaWXjV0llGWuhm83iTEuNV0cc5kH 2JbXc2Dn2Ba0zKEw4QwHK9a+fA== X-Google-Smtp-Source: AGRyM1tJIIY8m1U5Jj1xzKMCWd0QWpH+Rbh3z+j1akm/N/3A1wloek2Honra7mfm8CDl+4dSWMofMQ== X-Received: by 2002:a05:600c:2258:b0:3a1:8cba:646 with SMTP id a24-20020a05600c225800b003a18cba0646mr10224837wmm.7.1657817757705; Thu, 14 Jul 2022 09:55:57 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id k9-20020a05600c1c8900b003974cb37a94sm6209144wms.22.2022.07.14.09.55.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 09:55:57 -0700 (PDT) From: Sam Protsenko To: Marek Szyprowski , Krzysztof Kozlowski Cc: Joerg Roedel , Will Deacon , Robin Murphy , Janghyuck Kim , Cho KyongHo , Daniel Mentz , David Virag , Sumit Semwal , iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 4/6] iommu/exynos: Abstract non-common registers on different variants Date: Thu, 14 Jul 2022 19:55:48 +0300 Message-Id: <20220714165550.8884-5-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220714165550.8884-1-semen.protsenko@linaro.org> References: <20220714165550.8884-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" At the moment the driver supports SysMMU v1..v5 versions. SysMMU v5 has different register layout than SysMMU v1..v3. Instead of checking the version each time before reading/writing the registers, let's create corresponding register structure for each SysMMU version and set the needed structure on init, checking the SysMMU version one single time. This way is faster and more elegant. No behavior changes from the user's point of view, it's only a refactoring patch. Signed-off-by: Sam Protsenko Acked-by: Marek Szyprowski --- Changes in v3: - Added Marek's Acked-by tag - Removed abstracting common regs, used plain readl/writel to access those instead - Used variant struct instead of array to keep non-common register offsets - Removed 0x1 value used as an offset for missing registers - Merged __sysmmu_hw_info() into __sysmmu_get_version() - Refactored __sysmmu_tlb_invalidate_entry() for "num_inv =3D=3D 1" case - Reworked the commit message w.r.t. all changes Changes in v2: - Reworked existing code (SysMMU v1..v5) to use this approach - Extracted v7 registers to the separate patches - Replaced MMU_REG() with corresponding SysMMU read/write functions - Improved the comment for 0x1 offsets triggering an unaligned access exception - Removed support for VMID number, as only VMID=3D0 (default) is used for now - Renamed register index names to reflect the old SysMMU version register names drivers/iommu/exynos-iommu.c | 100 +++++++++++++++++++++-------------- 1 file changed, 60 insertions(+), 40 deletions(-) diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index 494f7d7aa9c5..6a0299fe1722 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -148,26 +148,12 @@ static u32 lv2ent_offset(sysmmu_iova_t iova) #define MAKE_MMU_VER(maj, min) ((((maj) & 0xF) << 7) | ((min) & 0x7F)) =20 /* v1.x - v3.x registers */ -#define REG_MMU_FLUSH 0x00C -#define REG_MMU_FLUSH_ENTRY 0x010 -#define REG_PT_BASE_ADDR 0x014 -#define REG_INT_STATUS 0x018 -#define REG_INT_CLEAR 0x01C - #define REG_PAGE_FAULT_ADDR 0x024 #define REG_AW_FAULT_ADDR 0x028 #define REG_AR_FAULT_ADDR 0x02C #define REG_DEFAULT_SLAVE_ADDR 0x030 =20 /* v5.x registers */ -#define REG_V5_PT_BASE_PFN 0x00C -#define REG_V5_MMU_FLUSH_ALL 0x010 -#define REG_V5_MMU_FLUSH_ENTRY 0x014 -#define REG_V5_MMU_FLUSH_RANGE 0x018 -#define REG_V5_MMU_FLUSH_START 0x020 -#define REG_V5_MMU_FLUSH_END 0x024 -#define REG_V5_INT_STATUS 0x060 -#define REG_V5_INT_CLEAR 0x064 #define REG_V5_FAULT_AR_VA 0x070 #define REG_V5_FAULT_AW_VA 0x080 =20 @@ -250,6 +236,21 @@ struct exynos_iommu_domain { struct iommu_domain domain; /* generic domain data structure */ }; =20 +/* + * SysMMU version specific data. Contains offsets for the registers which = can + * be found in different SysMMU variants, but have different offset values. + */ +struct sysmmu_variant { + u32 pt_base; /* page table base address (physical) */ + u32 flush_all; /* invalidate all TLB entries */ + u32 flush_entry; /* invalidate specific TLB entry */ + u32 flush_range; /* invalidate TLB entries in specified range */ + u32 flush_start; /* start address of range invalidation */ + u32 flush_end; /* end address of range invalidation */ + u32 int_status; /* interrupt status information */ + u32 int_clear; /* clear the interrupt */ +}; + /* * This structure hold all data of a single SYSMMU controller, this includ= es * hw resources like registers and clocks, pointers and list nodes to conn= ect @@ -274,6 +275,30 @@ struct sysmmu_drvdata { unsigned int version; /* our version */ =20 struct iommu_device iommu; /* IOMMU core handle */ + const struct sysmmu_variant *variant; /* version specific data */ +}; + +#define SYSMMU_REG(data, reg) ((data)->sfrbase + (data)->variant->reg) + +/* SysMMU v1..v3 */ +static const struct sysmmu_variant sysmmu_v1_variant =3D { + .flush_all =3D 0x0c, + .flush_entry =3D 0x10, + .pt_base =3D 0x14, + .int_status =3D 0x18, + .int_clear =3D 0x1c, +}; + +/* SysMMU v5 */ +static const struct sysmmu_variant sysmmu_v5_variant =3D { + .pt_base =3D 0x0c, + .flush_all =3D 0x10, + .flush_entry =3D 0x14, + .flush_range =3D 0x18, + .flush_start =3D 0x20, + .flush_end =3D 0x24, + .int_status =3D 0x60, + .int_clear =3D 0x64, }; =20 static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *d= om) @@ -304,10 +329,7 @@ static bool sysmmu_block(struct sysmmu_drvdata *data) =20 static void __sysmmu_tlb_invalidate(struct sysmmu_drvdata *data) { - if (MMU_MAJ_VER(data->version) < 5) - writel(0x1, data->sfrbase + REG_MMU_FLUSH); - else - writel(0x1, data->sfrbase + REG_V5_MMU_FLUSH_ALL); + writel(0x1, SYSMMU_REG(data, flush_all)); } =20 static void __sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data, @@ -315,33 +337,30 @@ static void __sysmmu_tlb_invalidate_entry(struct sysm= mu_drvdata *data, { unsigned int i; =20 - if (MMU_MAJ_VER(data->version) < 5) { + if (MMU_MAJ_VER(data->version) < 5 || num_inv =3D=3D 1) { for (i =3D 0; i < num_inv; i++) { writel((iova & SPAGE_MASK) | 1, - data->sfrbase + REG_MMU_FLUSH_ENTRY); + SYSMMU_REG(data, flush_entry)); iova +=3D SPAGE_SIZE; } } else { - if (num_inv =3D=3D 1) { - writel((iova & SPAGE_MASK) | 1, - data->sfrbase + REG_V5_MMU_FLUSH_ENTRY); - } else { - writel((iova & SPAGE_MASK), - data->sfrbase + REG_V5_MMU_FLUSH_START); - writel((iova & SPAGE_MASK) + (num_inv - 1) * SPAGE_SIZE, - data->sfrbase + REG_V5_MMU_FLUSH_END); - writel(1, data->sfrbase + REG_V5_MMU_FLUSH_RANGE); - } + writel(iova & SPAGE_MASK, SYSMMU_REG(data, flush_start)); + writel((iova & SPAGE_MASK) + (num_inv - 1) * SPAGE_SIZE, + SYSMMU_REG(data, flush_end)); + writel(0x1, SYSMMU_REG(data, flush_range)); } } =20 static void __sysmmu_set_ptbase(struct sysmmu_drvdata *data, phys_addr_t p= gd) { + u32 pt_base; + if (MMU_MAJ_VER(data->version) < 5) - writel(pgd, data->sfrbase + REG_PT_BASE_ADDR); + pt_base =3D pgd; else - writel(pgd >> SPAGE_ORDER, data->sfrbase + REG_V5_PT_BASE_PFN); + pt_base =3D pgd >> SPAGE_ORDER; =20 + writel(pt_base, SYSMMU_REG(data, pt_base)); __sysmmu_tlb_invalidate(data); } =20 @@ -378,6 +397,11 @@ static void __sysmmu_get_version(struct sysmmu_drvdata= *data) dev_dbg(data->sysmmu, "hardware version: %d.%d\n", MMU_MAJ_VER(data->version), MMU_MIN_VER(data->version)); =20 + if (MMU_MAJ_VER(data->version) < 5) + data->variant =3D &sysmmu_v1_variant; + else + data->variant =3D &sysmmu_v5_variant; + __sysmmu_disable_clocks(data); } =20 @@ -405,19 +429,14 @@ static irqreturn_t exynos_sysmmu_irq(int irq, void *d= ev_id) const struct sysmmu_fault_info *finfo; unsigned int i, n, itype; sysmmu_iova_t fault_addr; - unsigned short reg_status, reg_clear; int ret =3D -ENOSYS; =20 WARN_ON(!data->active); =20 if (MMU_MAJ_VER(data->version) < 5) { - reg_status =3D REG_INT_STATUS; - reg_clear =3D REG_INT_CLEAR; finfo =3D sysmmu_faults; n =3D ARRAY_SIZE(sysmmu_faults); } else { - reg_status =3D REG_V5_INT_STATUS; - reg_clear =3D REG_V5_INT_CLEAR; finfo =3D sysmmu_v5_faults; n =3D ARRAY_SIZE(sysmmu_v5_faults); } @@ -426,7 +445,7 @@ static irqreturn_t exynos_sysmmu_irq(int irq, void *dev= _id) =20 clk_enable(data->clk_master); =20 - itype =3D __ffs(readl(data->sfrbase + reg_status)); + itype =3D __ffs(readl(SYSMMU_REG(data, int_status))); for (i =3D 0; i < n; i++, finfo++) if (finfo->bit =3D=3D itype) break; @@ -443,7 +462,7 @@ static irqreturn_t exynos_sysmmu_irq(int irq, void *dev= _id) /* fault is not recovered by fault handler */ BUG_ON(ret !=3D 0); =20 - writel(1 << itype, data->sfrbase + reg_clear); + writel(1 << itype, SYSMMU_REG(data, int_clear)); =20 sysmmu_unblock(data); =20 @@ -622,6 +641,8 @@ static int exynos_sysmmu_probe(struct platform_device *= pdev) data->sysmmu =3D dev; spin_lock_init(&data->lock); =20 + __sysmmu_get_version(data); + ret =3D iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL, dev_name(data->sysmmu)); if (ret) @@ -633,7 +654,6 @@ static int exynos_sysmmu_probe(struct platform_device *= pdev) =20 platform_set_drvdata(pdev, data); =20 - __sysmmu_get_version(data); if (PG_ENT_SHIFT < 0) { if (MMU_MAJ_VER(data->version) < 5) { PG_ENT_SHIFT =3D SYSMMU_PG_ENT_SHIFT; --=20 2.30.2 From nobody Sat Apr 18 10:53:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A82CCCA47B for ; Thu, 14 Jul 2022 16:56:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240344AbiGNQ4T (ORCPT ); Thu, 14 Jul 2022 12:56:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239648AbiGNQ4B (ORCPT ); Thu, 14 Jul 2022 12:56:01 -0400 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CFBE14E851 for ; Thu, 14 Jul 2022 09:55:59 -0700 (PDT) Received: by mail-wm1-x333.google.com with SMTP id y22-20020a7bcd96000000b003a2e2725e89so1591579wmj.0 for ; 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Thu, 14 Jul 2022 09:55:59 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id z18-20020a5d4c92000000b0021d6d18a9f8sm1887563wrs.76.2022.07.14.09.55.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 09:55:58 -0700 (PDT) From: Sam Protsenko To: Marek Szyprowski , Krzysztof Kozlowski Cc: Joerg Roedel , Will Deacon , Robin Murphy , Janghyuck Kim , Cho KyongHo , Daniel Mentz , David Virag , Sumit Semwal , iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 5/6] iommu/exynos: Add SysMMU v7 register set Date: Thu, 14 Jul 2022 19:55:49 +0300 Message-Id: <20220714165550.8884-6-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220714165550.8884-1-semen.protsenko@linaro.org> References: <20220714165550.8884-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SysMMU v7 might have different register layouts (VM capable or non-VM capable). Virtual Machine registers (if present) implement multiple translation domains. If VM registers are not present, the driver shouldn't try to access those. Check which layout is implemented in current SysMMU module (by reading the capability registers) and prepare the corresponding variant structure for further usage. Signed-off-by: Sam Protsenko Acked-by: Marek Szyprowski --- Changes in v3: - Merged "Check if SysMMU v7 has VM registers" patch into this patch - Reworked for using variant struct (instead of array) Changes in v2: - (none) This patch is new and added in v2 drivers/iommu/exynos-iommu.c | 50 +++++++++++++++++++++++++++++++++--- 1 file changed, 47 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index 6a0299fe1722..fc9ef3ff0057 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -135,6 +135,9 @@ static u32 lv2ent_offset(sysmmu_iova_t iova) #define CFG_SYSSEL (1 << 22) /* System MMU 3.2 only */ #define CFG_FLPDCACHE (1 << 20) /* System MMU 3.2+ only */ =20 +#define CAPA0_CAPA1_EXIST BIT(11) +#define CAPA1_VCR_ENABLED BIT(14) + /* common registers */ #define REG_MMU_CTRL 0x000 #define REG_MMU_CFG 0x004 @@ -157,6 +160,10 @@ static u32 lv2ent_offset(sysmmu_iova_t iova) #define REG_V5_FAULT_AR_VA 0x070 #define REG_V5_FAULT_AW_VA 0x080 =20 +/* v7.x registers */ +#define REG_V7_CAPA0 0x870 +#define REG_V7_CAPA1 0x874 + #define has_sysmmu(dev) (dev_iommu_priv_get(dev) !=3D NULL) =20 static struct device *dma_dev; @@ -276,6 +283,9 @@ struct sysmmu_drvdata { =20 struct iommu_device iommu; /* IOMMU core handle */ const struct sysmmu_variant *variant; /* version specific data */ + + /* v7 fields */ + bool has_vcr; /* virtual machine control register */ }; =20 #define SYSMMU_REG(data, reg) ((data)->sfrbase + (data)->variant->reg) @@ -289,7 +299,7 @@ static const struct sysmmu_variant sysmmu_v1_variant = =3D { .int_clear =3D 0x1c, }; =20 -/* SysMMU v5 */ +/* SysMMU v5 and v7 (non-VM capable) */ static const struct sysmmu_variant sysmmu_v5_variant =3D { .pt_base =3D 0x0c, .flush_all =3D 0x10, @@ -301,6 +311,18 @@ static const struct sysmmu_variant sysmmu_v5_variant = =3D { .int_clear =3D 0x64, }; =20 +/* SysMMU v7: VM capable register set */ +static const struct sysmmu_variant sysmmu_v7_vm_variant =3D { + .pt_base =3D 0x800c, + .flush_all =3D 0x8010, + .flush_entry =3D 0x8014, + .flush_range =3D 0x8018, + .flush_start =3D 0x8020, + .flush_end =3D 0x8024, + .int_status =3D 0x60, + .int_clear =3D 0x64, +}; + static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *d= om) { return container_of(dom, struct exynos_iommu_domain, domain); @@ -380,6 +402,20 @@ static void __sysmmu_disable_clocks(struct sysmmu_drvd= ata *data) clk_disable_unprepare(data->clk_master); } =20 +static bool __sysmmu_has_capa1(struct sysmmu_drvdata *data) +{ + u32 capa0 =3D readl(data->sfrbase + REG_V7_CAPA0); + + return capa0 & CAPA0_CAPA1_EXIST; +} + +static void __sysmmu_get_vcr(struct sysmmu_drvdata *data) +{ + u32 capa1 =3D readl(data->sfrbase + REG_V7_CAPA1); + + data->has_vcr =3D capa1 & CAPA1_VCR_ENABLED; +} + static void __sysmmu_get_version(struct sysmmu_drvdata *data) { u32 ver; @@ -397,10 +433,18 @@ static void __sysmmu_get_version(struct sysmmu_drvdat= a *data) dev_dbg(data->sysmmu, "hardware version: %d.%d\n", MMU_MAJ_VER(data->version), MMU_MIN_VER(data->version)); =20 - if (MMU_MAJ_VER(data->version) < 5) + if (MMU_MAJ_VER(data->version) < 5) { data->variant =3D &sysmmu_v1_variant; - else + } else if (MMU_MAJ_VER(data->version) < 7) { data->variant =3D &sysmmu_v5_variant; + } else { + if (__sysmmu_has_capa1(data)) + __sysmmu_get_vcr(data); + if (data->has_vcr) + data->variant =3D &sysmmu_v7_vm_variant; + else + data->variant =3D &sysmmu_v5_variant; + } =20 __sysmmu_disable_clocks(data); } --=20 2.30.2 From nobody Sat Apr 18 10:53:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F53EC43334 for ; Thu, 14 Jul 2022 16:56:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238630AbiGNQ4X (ORCPT ); Thu, 14 Jul 2022 12:56:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57158 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239839AbiGNQ4D (ORCPT ); Thu, 14 Jul 2022 12:56:03 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B9BE54CBD for ; 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Thu, 14 Jul 2022 09:56:00 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id l29-20020a05600c1d1d00b003a2e27fc275sm2797092wms.12.2022.07.14.09.56.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 09:56:00 -0700 (PDT) From: Sam Protsenko To: Marek Szyprowski , Krzysztof Kozlowski Cc: Joerg Roedel , Will Deacon , Robin Murphy , Janghyuck Kim , Cho KyongHo , Daniel Mentz , David Virag , Sumit Semwal , iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 6/6] iommu/exynos: Enable default VM instance on SysMMU v7 Date: Thu, 14 Jul 2022 19:55:50 +0300 Message-Id: <20220714165550.8884-7-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220714165550.8884-1-semen.protsenko@linaro.org> References: <20220714165550.8884-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In order to enable SysMMU v7 with VM register layout, at least the default VM instance (n=3D0) must be enabled, in addition to enabling the SysMMU itself. To do so, add corresponding write to MMU_CTRL_VM[0] register, before writing to MMU_CTRL register. Signed-off-by: Sam Protsenko Acked-by: Marek Szyprowski --- Changes in v3: - Reworked for using plain writel() - Added Marek's Acked-by tag Changes in v2: - Extracted VM enabling code to the separate function - Used new SysMMU read/write functions to access the registers drivers/iommu/exynos-iommu.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index fc9ef3ff0057..8e18984a0c4f 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -135,6 +135,8 @@ static u32 lv2ent_offset(sysmmu_iova_t iova) #define CFG_SYSSEL (1 << 22) /* System MMU 3.2 only */ #define CFG_FLPDCACHE (1 << 20) /* System MMU 3.2+ only */ =20 +#define CTRL_VM_ENABLE BIT(0) +#define CTRL_VM_FAULT_MODE_STALL BIT(3) #define CAPA0_CAPA1_EXIST BIT(11) #define CAPA1_VCR_ENABLED BIT(14) =20 @@ -163,6 +165,7 @@ static u32 lv2ent_offset(sysmmu_iova_t iova) /* v7.x registers */ #define REG_V7_CAPA0 0x870 #define REG_V7_CAPA1 0x874 +#define REG_V7_CTRL_VM 0x8000 =20 #define has_sysmmu(dev) (dev_iommu_priv_get(dev) !=3D NULL) =20 @@ -548,6 +551,18 @@ static void __sysmmu_init_config(struct sysmmu_drvdata= *data) writel(cfg, data->sfrbase + REG_MMU_CFG); } =20 +static void __sysmmu_enable_vid(struct sysmmu_drvdata *data) +{ + u32 ctrl; + + if (MMU_MAJ_VER(data->version) < 7 || !data->has_vcr) + return; + + ctrl =3D readl(data->sfrbase + REG_V7_CTRL_VM); + ctrl |=3D CTRL_VM_ENABLE | CTRL_VM_FAULT_MODE_STALL; + writel(ctrl, data->sfrbase + REG_V7_CTRL_VM); +} + static void __sysmmu_enable(struct sysmmu_drvdata *data) { unsigned long flags; @@ -558,6 +573,7 @@ static void __sysmmu_enable(struct sysmmu_drvdata *data) writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL); __sysmmu_init_config(data); __sysmmu_set_ptbase(data, data->pgtable); + __sysmmu_enable_vid(data); writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL); data->active =3D true; spin_unlock_irqrestore(&data->lock, flags); --=20 2.30.2