From nobody Thu Nov 14 09:19:46 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91C14C43334 for ; Thu, 14 Jul 2022 09:23:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238211AbiGNJXn (ORCPT ); Thu, 14 Jul 2022 05:23:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49030 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238169AbiGNJXP (ORCPT ); Thu, 14 Jul 2022 05:23:15 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D9F9748C8B; Thu, 14 Jul 2022 02:21:59 -0700 (PDT) X-UUID: 95d36ab9f3fc40c5a9aa6d3af7fbd5b0-20220714 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8,REQID:286ff37a-5fc8-491e-8f3a-c614ae993d30,OB:0,LO B:0,IP:0,URL:25,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:25 X-CID-META: VersionHash:0f94e32,CLOUDID:f3fe4964-0b3f-4b2c-b3a6-ed5c044366a0,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:1,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: 95d36ab9f3fc40c5a9aa6d3af7fbd5b0-20220714 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 363682587; Thu, 14 Jul 2022 17:21:56 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Thu, 14 Jul 2022 17:21:54 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 14 Jul 2022 17:21:54 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , "Krzysztof Kozlowski" , Hans Verkuil CC: Chun-Kuang Hu , Rob Landley , Laurent Pinchart , , , , , , Alexandre Courbot , , , , , Benjamin Gaignard , AngeloGioacchino Del Regno , daoyuan huang , Ping-Hsun Wu , , , , , , , , , Subject: [PATCH v22 1/4] dt-binding: mediatek: add bindings for MediaTek MDP3 components Date: Thu, 14 Jul 2022 17:21:50 +0800 Message-ID: <20220714092153.16686-2-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220714092153.16686-1-moudy.ho@mediatek.com> References: <20220714092153.16686-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch adds DT binding documents for Media Data Path 3 (MDP3) a unit in multimedia system combined with several components and used for scaling and color format convert. Signed-off-by: Moudy Ho Reviewed-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno --- .../bindings/media/mediatek,mdp3-rdma.yaml | 95 +++++++++++++++++++ .../bindings/media/mediatek,mdp3-rsz.yaml | 77 +++++++++++++++ .../bindings/media/mediatek,mdp3-wrot.yaml | 80 ++++++++++++++++ 3 files changed, 252 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-r= dma.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-r= sz.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-w= rot.yaml diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yam= l b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml new file mode 100644 index 000000000000..6bbc4dde0393 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek Read Direct Memory Access + +maintainers: + - Matthias Brugger + - Ping-Hsun Wu + +description: | + Mediatek Read Direct Memory Access(RDMA) component used to do read DMA. + It contains one line buffer to store the sufficient pixel data, and + must be siblings to the central MMSYS_CONFIG node. + For a description of the MMSYS_CONFIG binding, see + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml + for details. + +properties: + compatible: + items: + - const: mediatek,mt8183-mdp3-rdma + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + description: The register of client driver can be configured by gce wi= th + 4 arguments defined in this property. Each GCE subsys id is mapping = to + a client defined in the header include/dt-bindings/gce/-gce.h. + + mediatek,gce-events: + description: + The event id which is mapping to the specific hardware event signal + to gce. The event id is defined in the gce header + include/dt-bindings/gce/-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/uint32-array + + power-domains: + maxItems: 1 + + clocks: + items: + - description: RDMA clock + - description: RSZ clock + + iommus: + maxItems: 1 + + mboxes: + items: + - description: used for 1st data pipe from RDMA + - description: used for 2nd data pipe from RDMA + +required: + - compatible + - reg + - mediatek,gce-client-reg + - mediatek,gce-events + - power-domains + - clocks + - iommus + - mboxes + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + mdp3_rdma0: mdp3-rdma0@14001000 { + compatible =3D "mediatek,mt8183-mdp3-rdma"; + reg =3D <0x14001000 0x1000>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x1000 0x1000>; + mediatek,gce-events =3D , + ; + power-domains =3D <&spm MT8183_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_MDP_RDMA0>, + <&mmsys CLK_MM_MDP_RSZ1>; + iommus =3D <&iommu>; + mboxes =3D <&gce 20 CMDQ_THR_PRIO_LOWEST>, + <&gce 21 CMDQ_THR_PRIO_LOWEST>; + }; diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml= b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml new file mode 100644 index 000000000000..b136b3845036 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-rsz.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek Resizer + +maintainers: + - Matthias Brugger + - Ping-Hsun Wu + +description: | + One of Media Data Path 3 (MDP3) components used to do frame resizing. + +properties: + compatible: + items: + - enum: + - mediatek,mt8183-mdp3-rsz + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + description: The register of client driver can be configured by gce wi= th + 4 arguments defined in this property. Each GCE subsys id is mapping = to + a client defined in the header include/dt-bindings/gce/-gce.h. + + mediatek,gce-events: + description: + The event id which is mapping to the specific hardware event signal + to gce. The event id is defined in the gce header + include/dt-bindings/gce/-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/uint32-array + + clocks: + minItems: 1 + +required: + - compatible + - reg + - mediatek,gce-client-reg + - mediatek,gce-events + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + + mdp3_rsz0: mdp3-rsz0@14003000 { + compatible =3D "mediatek,mt8183-mdp3-rsz"; + reg =3D <0x14003000 0x1000>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x3000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&mmsys CLK_MM_MDP_RSZ0>; + }; + + mdp3_rsz1: mdp3-rsz1@14004000 { + compatible =3D "mediatek,mt8183-mdp3-rsz"; + reg =3D <0x14004000 0x1000>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x4000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&mmsys CLK_MM_MDP_RSZ1>; + }; diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yam= l b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml new file mode 100644 index 000000000000..0069b350ee64 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-wrot.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek Write DMA with Rotation + +maintainers: + - Matthias Brugger + - Ping-Hsun Wu + +description: | + One of Media Data Path 3 (MDP3) components used to write DMA with frame = rotation. + +properties: + compatible: + items: + - enum: + - mediatek,mt8183-mdp3-wrot + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + description: The register of client driver can be configured by gce wi= th + 4 arguments defined in this property. Each GCE subsys id is mapping = to + a client defined in the header include/dt-bindings/gce/-gce.h. + + mediatek,gce-events: + description: + The event id which is mapping to the specific hardware event signal + to gce. The event id is defined in the gce header + include/dt-bindings/gce/-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/uint32-array + + power-domains: + maxItems: 1 + + clocks: + minItems: 1 + + iommus: + maxItems: 1 + +required: + - compatible + - reg + - mediatek,gce-client-reg + - mediatek,gce-events + - power-domains + - clocks + - iommus + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + mdp3_wrot0: mdp3-wrot0@14005000 { + compatible =3D "mediatek,mt8183-mdp3-wrot"; + reg =3D <0x14005000 0x1000>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x5000 0x1000>; + mediatek,gce-events =3D , + ; + power-domains =3D <&spm MT8183_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_MDP_WROT0>; + iommus =3D <&iommu>; + }; --=20 2.18.0