From nobody Sat Apr 18 15:44:26 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26C92C433EF for ; Wed, 13 Jul 2022 19:34:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236636AbiGMTeH (ORCPT ); Wed, 13 Jul 2022 15:34:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49436 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231799AbiGMTeC (ORCPT ); Wed, 13 Jul 2022 15:34:02 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 530B9220DA; Wed, 13 Jul 2022 12:33:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1657740839; x=1689276839; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ETKrJvyTarhd9KSSpAx4A8jh8kI6oOjyteuWYEXdd8o=; b=OGzFt/M6zF//setVzAS2qF0Jaz7E+qa+QtePLWC/qxIynGXVyhYYaHnU rj1XAQmRez5/G7+aVNuI9WN0D/A4zthHuUP6aOXxlrYmTRKsnrE1x03tP eXeVYaUj6aMjQgpeZVED3dVJUH/rt9MOCmUwPcTvXB03odvNgjyQmkHu6 9DZMl4BonMgZcc2ObpYAJUpJlhH9Q5kkjTi8/mdOv5+7QG0eGtZpFF+0n fniJs6URIAkIzpPhvOJITC2Z9HiiWn0zK+sA3D5mzsVyPoF7XUT0JSsv9 l+pQu/iNEZEsAtDKTBJ9gD3RlkZvzhHHCwyJYZrJVJwRQ4XqIYXI8cWO9 w==; X-IronPort-AV: E=Sophos;i="5.92,267,1650956400"; d="scan'208";a="167716405" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jul 2022 12:33:56 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Wed, 13 Jul 2022 12:33:54 -0700 Received: from soft-dev3-1.microsemi.net (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Wed, 13 Jul 2022 12:33:52 -0700 From: Horatiu Vultur To: , CC: , , , , , , , , Horatiu Vultur Subject: [PATCH v5 1/2] pinctrl: ocelot: Fix pincfg for lan966x Date: Wed, 13 Jul 2022 21:37:49 +0200 Message-ID: <20220713193750.4079621-2-horatiu.vultur@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220713193750.4079621-1-horatiu.vultur@microchip.com> References: <20220713193750.4079621-1-horatiu.vultur@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The blamed commit introduce support for lan966x which use the same pinconf_ops as sparx5. The problem is that pinconf_ops is specific to sparx5. More precisely the offset of the bits in the pincfg register are different and also lan966x doesn't have support for PIN_CONFIG_INPUT_SCHMITT_ENABLE. Fix this by making pinconf_ops more generic such that it can be also used by lan966x. This is done by introducing 'ocelot_pincfg_data' which contains the offset and what is supported for each SOC. Fixes: 531d6ab36571 ("pinctrl: ocelot: Extend support for lan966x") Signed-off-by: Horatiu Vultur Reviewed-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-ocelot.c | 195 ++++++++++++++++++++----------- 1 file changed, 124 insertions(+), 71 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-oce= lot.c index 5f4a8c5c6650..c6e0232770b7 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -29,19 +29,12 @@ #define ocelot_clrsetbits(addr, clear, set) \ writel((readl(addr) & ~(clear)) | (set), (addr)) =20 -/* PINCONFIG bits (sparx5 only) */ enum { PINCONF_BIAS, PINCONF_SCHMITT, PINCONF_DRIVE_STRENGTH, }; =20 -#define BIAS_PD_BIT BIT(4) -#define BIAS_PU_BIT BIT(3) -#define BIAS_BITS (BIAS_PD_BIT|BIAS_PU_BIT) -#define SCHMITT_BIT BIT(2) -#define DRIVE_BITS GENMASK(1, 0) - /* GPIO standard registers */ #define OCELOT_GPIO_OUT_SET 0x0 #define OCELOT_GPIO_OUT_CLR 0x4 @@ -321,6 +314,13 @@ struct ocelot_pin_caps { unsigned char a_functions[OCELOT_FUNC_PER_PIN]; /* Additional functions */ }; =20 +struct ocelot_pincfg_data { + u8 pd_bit; + u8 pu_bit; + u8 drive_bits; + u8 schmitt_bit; +}; + struct ocelot_pinctrl { struct device *dev; struct pinctrl_dev *pctl; @@ -328,10 +328,16 @@ struct ocelot_pinctrl { struct regmap *map; struct regmap *pincfg; struct pinctrl_desc *desc; + const struct ocelot_pincfg_data *pincfg_data; struct ocelot_pmx_func func[FUNC_MAX]; u8 stride; }; =20 +struct ocelot_match_data { + struct pinctrl_desc desc; + struct ocelot_pincfg_data pincfg_data; +}; + #define LUTON_P(p, f0, f1) \ static struct ocelot_pin_caps luton_pin_##p =3D { \ .pin =3D p, \ @@ -1325,6 +1331,7 @@ static int ocelot_hw_get_value(struct ocelot_pinctrl = *info, int ret =3D -EOPNOTSUPP; =20 if (info->pincfg) { + const struct ocelot_pincfg_data *opd =3D info->pincfg_data; u32 regcfg; =20 ret =3D regmap_read(info->pincfg, pin, ®cfg); @@ -1334,15 +1341,15 @@ static int ocelot_hw_get_value(struct ocelot_pinctr= l *info, ret =3D 0; switch (reg) { case PINCONF_BIAS: - *val =3D regcfg & BIAS_BITS; + *val =3D regcfg & (opd->pd_bit | opd->pu_bit); break; =20 case PINCONF_SCHMITT: - *val =3D regcfg & SCHMITT_BIT; + *val =3D regcfg & opd->schmitt_bit; break; =20 case PINCONF_DRIVE_STRENGTH: - *val =3D regcfg & DRIVE_BITS; + *val =3D regcfg & opd->drive_bits; break; =20 default: @@ -1379,23 +1386,27 @@ static int ocelot_hw_set_value(struct ocelot_pinctr= l *info, int ret =3D -EOPNOTSUPP; =20 if (info->pincfg) { + const struct ocelot_pincfg_data *opd =3D info->pincfg_data; =20 ret =3D 0; switch (reg) { case PINCONF_BIAS: - ret =3D ocelot_pincfg_clrsetbits(info, pin, BIAS_BITS, + ret =3D ocelot_pincfg_clrsetbits(info, pin, + opd->pd_bit | opd->pu_bit, val); break; =20 case PINCONF_SCHMITT: - ret =3D ocelot_pincfg_clrsetbits(info, pin, SCHMITT_BIT, + ret =3D ocelot_pincfg_clrsetbits(info, pin, + opd->schmitt_bit, val); break; =20 case PINCONF_DRIVE_STRENGTH: if (val <=3D 3) ret =3D ocelot_pincfg_clrsetbits(info, pin, - DRIVE_BITS, val); + opd->drive_bits, + val); else ret =3D -EINVAL; break; @@ -1425,17 +1436,20 @@ static int ocelot_pinconf_get(struct pinctrl_dev *p= ctldev, if (param =3D=3D PIN_CONFIG_BIAS_DISABLE) val =3D (val =3D=3D 0); else if (param =3D=3D PIN_CONFIG_BIAS_PULL_DOWN) - val =3D (val & BIAS_PD_BIT ? true : false); + val =3D !!(val & info->pincfg_data->pd_bit); else /* PIN_CONFIG_BIAS_PULL_UP */ - val =3D (val & BIAS_PU_BIT ? true : false); + val =3D !!(val & info->pincfg_data->pu_bit); break; =20 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (!info->pincfg_data->schmitt_bit) + return -EOPNOTSUPP; + err =3D ocelot_hw_get_value(info, pin, PINCONF_SCHMITT, &val); if (err) return err; =20 - val =3D (val & SCHMITT_BIT ? true : false); + val =3D !!(val & info->pincfg_data->schmitt_bit); break; =20 case PIN_CONFIG_DRIVE_STRENGTH: @@ -1479,6 +1493,7 @@ static int ocelot_pinconf_set(struct pinctrl_dev *pct= ldev, unsigned int pin, unsigned long *configs, unsigned int num_configs) { struct ocelot_pinctrl *info =3D pinctrl_dev_get_drvdata(pctldev); + const struct ocelot_pincfg_data *opd =3D info->pincfg_data; u32 param, arg, p; int cfg, err =3D 0; =20 @@ -1491,8 +1506,8 @@ static int ocelot_pinconf_set(struct pinctrl_dev *pct= ldev, unsigned int pin, case PIN_CONFIG_BIAS_PULL_UP: case PIN_CONFIG_BIAS_PULL_DOWN: arg =3D (param =3D=3D PIN_CONFIG_BIAS_DISABLE) ? 0 : - (param =3D=3D PIN_CONFIG_BIAS_PULL_UP) ? BIAS_PU_BIT : - BIAS_PD_BIT; + (param =3D=3D PIN_CONFIG_BIAS_PULL_UP) ? + opd->pu_bit : opd->pd_bit; =20 err =3D ocelot_hw_set_value(info, pin, PINCONF_BIAS, arg); if (err) @@ -1501,7 +1516,10 @@ static int ocelot_pinconf_set(struct pinctrl_dev *pc= tldev, unsigned int pin, break; =20 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: - arg =3D arg ? SCHMITT_BIT : 0; + if (!opd->schmitt_bit) + return -EOPNOTSUPP; + + arg =3D arg ? opd->schmitt_bit : 0; err =3D ocelot_hw_set_value(info, pin, PINCONF_SCHMITT, arg); if (err) @@ -1562,69 +1580,94 @@ static const struct pinctrl_ops ocelot_pctl_ops =3D= { .dt_free_map =3D pinconf_generic_dt_free_map, }; =20 -static struct pinctrl_desc luton_desc =3D { - .name =3D "luton-pinctrl", - .pins =3D luton_pins, - .npins =3D ARRAY_SIZE(luton_pins), - .pctlops =3D &ocelot_pctl_ops, - .pmxops =3D &ocelot_pmx_ops, - .owner =3D THIS_MODULE, +static struct ocelot_match_data luton_desc =3D { + .desc =3D { + .name =3D "luton-pinctrl", + .pins =3D luton_pins, + .npins =3D ARRAY_SIZE(luton_pins), + .pctlops =3D &ocelot_pctl_ops, + .pmxops =3D &ocelot_pmx_ops, + .owner =3D THIS_MODULE, + }, }; =20 -static struct pinctrl_desc serval_desc =3D { - .name =3D "serval-pinctrl", - .pins =3D serval_pins, - .npins =3D ARRAY_SIZE(serval_pins), - .pctlops =3D &ocelot_pctl_ops, - .pmxops =3D &ocelot_pmx_ops, - .owner =3D THIS_MODULE, +static struct ocelot_match_data serval_desc =3D { + .desc =3D { + .name =3D "serval-pinctrl", + .pins =3D serval_pins, + .npins =3D ARRAY_SIZE(serval_pins), + .pctlops =3D &ocelot_pctl_ops, + .pmxops =3D &ocelot_pmx_ops, + .owner =3D THIS_MODULE, + }, }; =20 -static struct pinctrl_desc ocelot_desc =3D { - .name =3D "ocelot-pinctrl", - .pins =3D ocelot_pins, - .npins =3D ARRAY_SIZE(ocelot_pins), - .pctlops =3D &ocelot_pctl_ops, - .pmxops =3D &ocelot_pmx_ops, - .owner =3D THIS_MODULE, +static struct ocelot_match_data ocelot_desc =3D { + .desc =3D { + .name =3D "ocelot-pinctrl", + .pins =3D ocelot_pins, + .npins =3D ARRAY_SIZE(ocelot_pins), + .pctlops =3D &ocelot_pctl_ops, + .pmxops =3D &ocelot_pmx_ops, + .owner =3D THIS_MODULE, + }, }; =20 -static struct pinctrl_desc jaguar2_desc =3D { - .name =3D "jaguar2-pinctrl", - .pins =3D jaguar2_pins, - .npins =3D ARRAY_SIZE(jaguar2_pins), - .pctlops =3D &ocelot_pctl_ops, - .pmxops =3D &ocelot_pmx_ops, - .owner =3D THIS_MODULE, +static struct ocelot_match_data jaguar2_desc =3D { + .desc =3D { + .name =3D "jaguar2-pinctrl", + .pins =3D jaguar2_pins, + .npins =3D ARRAY_SIZE(jaguar2_pins), + .pctlops =3D &ocelot_pctl_ops, + .pmxops =3D &ocelot_pmx_ops, + .owner =3D THIS_MODULE, + }, }; =20 -static struct pinctrl_desc servalt_desc =3D { - .name =3D "servalt-pinctrl", - .pins =3D servalt_pins, - .npins =3D ARRAY_SIZE(servalt_pins), - .pctlops =3D &ocelot_pctl_ops, - .pmxops =3D &ocelot_pmx_ops, - .owner =3D THIS_MODULE, +static struct ocelot_match_data servalt_desc =3D { + .desc =3D { + .name =3D "servalt-pinctrl", + .pins =3D servalt_pins, + .npins =3D ARRAY_SIZE(servalt_pins), + .pctlops =3D &ocelot_pctl_ops, + .pmxops =3D &ocelot_pmx_ops, + .owner =3D THIS_MODULE, + }, }; =20 -static struct pinctrl_desc sparx5_desc =3D { - .name =3D "sparx5-pinctrl", - .pins =3D sparx5_pins, - .npins =3D ARRAY_SIZE(sparx5_pins), - .pctlops =3D &ocelot_pctl_ops, - .pmxops =3D &ocelot_pmx_ops, - .confops =3D &ocelot_confops, - .owner =3D THIS_MODULE, +static struct ocelot_match_data sparx5_desc =3D { + .desc =3D { + .name =3D "sparx5-pinctrl", + .pins =3D sparx5_pins, + .npins =3D ARRAY_SIZE(sparx5_pins), + .pctlops =3D &ocelot_pctl_ops, + .pmxops =3D &ocelot_pmx_ops, + .confops =3D &ocelot_confops, + .owner =3D THIS_MODULE, + }, + .pincfg_data =3D { + .pd_bit =3D BIT(4), + .pu_bit =3D BIT(3), + .drive_bits =3D GENMASK(1, 0), + .schmitt_bit =3D BIT(2), + }, }; =20 -static struct pinctrl_desc lan966x_desc =3D { - .name =3D "lan966x-pinctrl", - .pins =3D lan966x_pins, - .npins =3D ARRAY_SIZE(lan966x_pins), - .pctlops =3D &ocelot_pctl_ops, - .pmxops =3D &lan966x_pmx_ops, - .confops =3D &ocelot_confops, - .owner =3D THIS_MODULE, +static struct ocelot_match_data lan966x_desc =3D { + .desc =3D { + .name =3D "lan966x-pinctrl", + .pins =3D lan966x_pins, + .npins =3D ARRAY_SIZE(lan966x_pins), + .pctlops =3D &ocelot_pctl_ops, + .pmxops =3D &lan966x_pmx_ops, + .confops =3D &ocelot_confops, + .owner =3D THIS_MODULE, + }, + .pincfg_data =3D { + .pd_bit =3D BIT(3), + .pu_bit =3D BIT(2), + .drive_bits =3D GENMASK(1, 0), + }, }; =20 static int ocelot_create_group_func_map(struct device *dev, @@ -1913,6 +1956,7 @@ static struct regmap *ocelot_pinctrl_create_pincfg(st= ruct platform_device *pdev) =20 static int ocelot_pinctrl_probe(struct platform_device *pdev) { + const struct ocelot_match_data *data; struct device *dev =3D &pdev->dev; struct ocelot_pinctrl *info; struct reset_control *reset; @@ -1929,7 +1973,16 @@ static int ocelot_pinctrl_probe(struct platform_devi= ce *pdev) if (!info) return -ENOMEM; =20 - info->desc =3D (struct pinctrl_desc *)device_get_match_data(dev); + data =3D device_get_match_data(dev); + if (!data) + return -EINVAL; + + info->desc =3D devm_kmemdup(dev, &data->desc, sizeof(*info->desc), + GFP_KERNEL); + if (!info->desc) + return -ENOMEM; + + info->pincfg_data =3D &data->pincfg_data; =20 reset =3D devm_reset_control_get_optional_shared(dev, "switch"); if (IS_ERR(reset)) --=20 2.33.0 From nobody Sat Apr 18 15:44:26 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65566C43334 for ; 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X-IronPort-AV: E=Sophos;i="5.92,267,1650956400"; d="scan'208";a="167716423" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jul 2022 12:33:58 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Wed, 13 Jul 2022 12:33:57 -0700 Received: from soft-dev3-1.microsemi.net (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Wed, 13 Jul 2022 12:33:55 -0700 From: Horatiu Vultur To: , CC: , , , , , , , , Horatiu Vultur Subject: [PATCH v5 2/2] pinctrl: ocelot: Fix pincfg Date: Wed, 13 Jul 2022 21:37:50 +0200 Message-ID: <20220713193750.4079621-3-horatiu.vultur@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220713193750.4079621-1-horatiu.vultur@microchip.com> References: <20220713193750.4079621-1-horatiu.vultur@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The blamed commit changed to use regmaps instead of __iomem. But it didn't update the register offsets to be at word offset, so it uses byte offset. Another issue with the same commit is that it has a limit of 32 registers which is incorrect. The sparx5 has 64 while lan966x has 77. Fixes: 076d9e71bcf8 ("pinctrl: ocelot: convert pinctrl to regmap") Acked-by: Colin Foster Reviewed-by: Andy Shevchenko Signed-off-by: Horatiu Vultur --- drivers/pinctrl/pinctrl-ocelot.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-oce= lot.c index c6e0232770b7..dfc8ea9f3843 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -1334,7 +1334,9 @@ static int ocelot_hw_get_value(struct ocelot_pinctrl = *info, const struct ocelot_pincfg_data *opd =3D info->pincfg_data; u32 regcfg; =20 - ret =3D regmap_read(info->pincfg, pin, ®cfg); + ret =3D regmap_read(info->pincfg, + pin * regmap_get_reg_stride(info->pincfg), + ®cfg); if (ret) return ret; =20 @@ -1366,14 +1368,18 @@ static int ocelot_pincfg_clrsetbits(struct ocelot_p= inctrl *info, u32 regaddr, u32 val; int ret; =20 - ret =3D regmap_read(info->pincfg, regaddr, &val); + ret =3D regmap_read(info->pincfg, + regaddr * regmap_get_reg_stride(info->pincfg), + &val); if (ret) return ret; =20 val &=3D ~clrbits; val |=3D setbits; =20 - ret =3D regmap_write(info->pincfg, regaddr, val); + ret =3D regmap_write(info->pincfg, + regaddr * regmap_get_reg_stride(info->pincfg), + val); =20 return ret; } @@ -1933,7 +1939,8 @@ static const struct of_device_id ocelot_pinctrl_of_ma= tch[] =3D { {}, }; =20 -static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device = *pdev) +static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device = *pdev, + const struct ocelot_pinctrl *info) { void __iomem *base; =20 @@ -1941,7 +1948,7 @@ static struct regmap *ocelot_pinctrl_create_pincfg(st= ruct platform_device *pdev) .reg_bits =3D 32, .val_bits =3D 32, .reg_stride =3D 4, - .max_register =3D 32, + .max_register =3D info->desc->npins * 4, .name =3D "pincfg", }; =20 @@ -2009,7 +2016,7 @@ static int ocelot_pinctrl_probe(struct platform_devic= e *pdev) =20 /* Pinconf registers */ if (info->desc->confops) { - pincfg =3D ocelot_pinctrl_create_pincfg(pdev); + pincfg =3D ocelot_pinctrl_create_pincfg(pdev, info); if (IS_ERR(pincfg)) dev_dbg(dev, "Failed to create pincfg regmap\n"); else --=20 2.33.0