From nobody Sat Apr 18 15:43:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53CA0C433EF for ; Tue, 12 Jul 2022 16:41:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232747AbiGLQlV (ORCPT ); Tue, 12 Jul 2022 12:41:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58036 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229592AbiGLQlR (ORCPT ); Tue, 12 Jul 2022 12:41:17 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F124B31F6; Tue, 12 Jul 2022 09:41:16 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 0AF9C6195C; Tue, 12 Jul 2022 16:41:16 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A22DEC341CA; Tue, 12 Jul 2022 16:41:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657644075; bh=ns8dkuWBiA3JnhvLfUhlQSYNSTwyoXAcShXwF7f5Uy0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nOv2/lzuI2/yWB3oTYvNoeVS4pPiwdYzc9Jgod2KHS1M1DR17dQZI5xJcjj7Cs/qe Em7Sqy4FO36W8wEJINtKKrSp6T7wUj8F/cjwQ08lf9G4tmsTaPqBDAa4vME1Ez+UXu 2oKLnc9sSAUObNOrLQRmbXHWS1mIt8BCvQvIrO/n/9a6smCBf91E83fysNRNnIw+tf v8lKOhun3CYSj7Yo1ZH4gItu57Z/ktvRJTSvZfP3if0SqgjdnYZfvXUJSt5D2xgojf ECzWfCIYLPeQNrzJWv1SqoHYh9l5lWz2TDxofIGjz+wv1pEGF4XlKshA7kXzVmvmOl psoaZXTBrgnYQ== From: =?UTF-8?q?Marek=20Beh=C3=BAn?= To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth Cc: Rob Herring , =?UTF-8?q?Pali=20Roh=C3=A1r?= , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Marek=20Beh=C3=BAn?= Subject: [PATCH v2 01/10] ARM: dts: kirkwood: Add definitions for PCIe legacy INTx interrupts Date: Tue, 12 Jul 2022 18:40:59 +0200 Message-Id: <20220712164108.30262-2-kabel@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220712164108.30262-1-kabel@kernel.org> References: <20220712164108.30262-1-kabel@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Pali Roh=C3=A1r Add definitions for PCIe legacy INTx interrupts. This is required for example in a scenario where a driver requests only one of the legacy interrupts (INTA). Without this, the driver would be notified on events on all 4 (INTA, INTB, INTC, INTD), even if it requested only one of them. Signed-off-by: Pali Roh=C3=A1r Signed-off-by: Marek Beh=C3=BAn --- arch/arm/boot/dts/kirkwood-6192.dtsi | 14 ++++++++++-- arch/arm/boot/dts/kirkwood-6281.dtsi | 14 ++++++++++-- arch/arm/boot/dts/kirkwood-6282.dtsi | 28 ++++++++++++++++++++---- arch/arm/boot/dts/kirkwood-98dx4122.dtsi | 14 ++++++++++-- 4 files changed, 60 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/kirkwood-6192.dtsi b/arch/arm/boot/dts/kirkw= ood-6192.dtsi index 396bcba08adb..07f4f7f98c0c 100644 --- a/arch/arm/boot/dts/kirkwood-6192.dtsi +++ b/arch/arm/boot/dts/kirkwood-6192.dtsi @@ -26,12 +26,22 @@ pcie0: pcie@1,0 { ranges =3D <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &intc 9>; + interrupt-names =3D "intx"; + interrupts =3D <9>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; marvell,pcie-port =3D <0>; marvell,pcie-lane =3D <0>; clocks =3D <&gate_clk 2>; status =3D "disabled"; + + pcie_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkw= ood-6281.dtsi index faa05849a40d..d08a9a5ecc26 100644 --- a/arch/arm/boot/dts/kirkwood-6281.dtsi +++ b/arch/arm/boot/dts/kirkwood-6281.dtsi @@ -26,12 +26,22 @@ pcie0: pcie@1,0 { ranges =3D <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &intc 9>; + interrupt-names =3D "intx"; + interrupts =3D <9>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; marvell,pcie-port =3D <0>; marvell,pcie-lane =3D <0>; clocks =3D <&gate_clk 2>; status =3D "disabled"; + + pcie_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkw= ood-6282.dtsi index e84c54b77dea..2eea5b304f47 100644 --- a/arch/arm/boot/dts/kirkwood-6282.dtsi +++ b/arch/arm/boot/dts/kirkwood-6282.dtsi @@ -30,12 +30,22 @@ pcie0: pcie@1,0 { ranges =3D <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &intc 9>; + interrupt-names =3D "intx"; + interrupts =3D <9>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; marvell,pcie-port =3D <0>; marvell,pcie-lane =3D <0>; clocks =3D <&gate_clk 2>; status =3D "disabled"; + + pcie0_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; =20 pcie1: pcie@2,0 { @@ -48,12 +58,22 @@ pcie1: pcie@2,0 { ranges =3D <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &intc 10>; + interrupt-names =3D "intx"; + interrupts =3D <10>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; marvell,pcie-port =3D <1>; marvell,pcie-lane =3D <0>; clocks =3D <&gate_clk 18>; status =3D "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi b/arch/arm/boot/dts/k= irkwood-98dx4122.dtsi index 299c147298c3..070bc13242b8 100644 --- a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi +++ b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi @@ -26,12 +26,22 @@ pcie0: pcie@1,0 { ranges =3D <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &intc 9>; + interrupt-names =3D "intx"; + interrupts =3D <9>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; marvell,pcie-port =3D <0>; marvell,pcie-lane =3D <0>; clocks =3D <&gate_clk 2>; status =3D "disabled"; + + pcie_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; }; }; --=20 2.35.1 From nobody Sat Apr 18 15:43:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3AB64C43334 for ; Tue, 12 Jul 2022 16:41:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233256AbiGLQl0 (ORCPT ); Tue, 12 Jul 2022 12:41:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58076 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230517AbiGLQlT (ORCPT ); Tue, 12 Jul 2022 12:41:19 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 976F1B31F0; Tue, 12 Jul 2022 09:41:18 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 2F0B061943; Tue, 12 Jul 2022 16:41:18 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CE4E0C341C0; Tue, 12 Jul 2022 16:41:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657644077; bh=bnrIiFlK9D2TsTIOY/TJyiBk3yRsU3u0vZgDR+kcVq0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Y1xSwDtpxeoE/xLUlPKH7ydSAMBXzxvWaeLbXp552Q0dDOghmymVemW3r9Q18QaGJ 1D/8AWf45NwJH8+mej3njVbvmTbflWnNWThSIBrAA/jXR+jPEVUO5wzSkEFxMFIfWt R8+KefzI35uQqwwJ+YE4HYwIr2vzR9j5cTa8b68Izu9cOT9G+XEDjk07mWf6npNGQi 8TFJw1dYAM84jZQ5ZJWDn38SNRalDn3srmQX3WZCpeD2gMeG+QFdTsOmFRwl5DeX+C aucQwlL8S9qHRXZvt1WUW9whvnJbBSP9UB09s7WkFKvlVcy7fvzz8oyT9SETJJwReh sZCLpEXU64qZA== From: =?UTF-8?q?Marek=20Beh=C3=BAn?= To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth Cc: Rob Herring , =?UTF-8?q?Pali=20Roh=C3=A1r?= , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Marek=20Beh=C3=BAn?= Subject: [PATCH v2 02/10] ARM: dts: dove: Add definitions for PCIe legacy INTx interrupts Date: Tue, 12 Jul 2022 18:41:00 +0200 Message-Id: <20220712164108.30262-3-kabel@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220712164108.30262-1-kabel@kernel.org> References: <20220712164108.30262-1-kabel@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Pali Roh=C3=A1r Add definitions for PCIe legacy INTx interrupts. This is required for example in a scenario where a driver requests only one of the legacy interrupts (INTA). Without this, the driver would be notified on events on all 4 (INTA, INTB, INTC, INTD), even if it requested only one of them. Signed-off-by: Pali Roh=C3=A1r Signed-off-by: Marek Beh=C3=BAn --- arch/arm/boot/dts/dove.dtsi | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index 89e0bdaf3a85..96ba47c061a7 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -122,8 +122,18 @@ pcie0: pcie@1 { bus-range =3D <0x00 0xff>; =20 #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &intc 16>; + interrupt-names =3D "intx"; + interrupts =3D <16>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; + + pcie0_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; =20 pcie1: pcie@2 { @@ -141,8 +151,18 @@ pcie1: pcie@2 { bus-range =3D <0x00 0xff>; =20 #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &intc 18>; + interrupt-names =3D "intx"; + interrupts =3D <18>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; }; =20 --=20 2.35.1 From nobody Sat Apr 18 15:43:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1119ECCA482 for ; Tue, 12 Jul 2022 16:41:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233268AbiGLQlg (ORCPT ); Tue, 12 Jul 2022 12:41:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58196 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233118AbiGLQlX (ORCPT ); Tue, 12 Jul 2022 12:41:23 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64B0CB38D9; Tue, 12 Jul 2022 09:41:22 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 0305CB817B7; Tue, 12 Jul 2022 16:41:21 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 05F6CC341CA; Tue, 12 Jul 2022 16:41:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657644079; bh=8ejeaiz9hLOtCSMtdSNcLpHTyF5dYkrAAy4F6AZE/M0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HbsJGK/R6lS2CaGYvoq9ZKZPcWcXynNdwq0htw3PDiDjpglAkXJMP/Nh2ke8UvUWF YxEePS8JMmg4zS4bCphP19O3wCNAq8H9iCCZiBkCP2AKWRjkOVw8wzzfFBxLI8r1NJ YF/+bURf+GFQz0NB+5X9VucSaKDLBt3m5BW6uEGFcNu/+bOyAsot9ynGoQ3ojXzyoF Jmm6B+82eWyASAcPqgUf9t8SHaDb8WvNPStrWn7doMarr6ugKgHOJXT/ZoZiQer3u/ nPHxROhJtHCjmKQCZ0u8IehaUC+LxRY7bfO/ZeDOTz5Jj4GztccYGcl/Nag92wsQZz uThkoieEnK5Xg== From: =?UTF-8?q?Marek=20Beh=C3=BAn?= To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth Cc: Rob Herring , =?UTF-8?q?Pali=20Roh=C3=A1r?= , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Marek=20Beh=C3=BAn?= Subject: [PATCH v2 03/10] ARM: dts: armada-370.dtsi: Add definitions for PCIe legacy INTx interrupts Date: Tue, 12 Jul 2022 18:41:01 +0200 Message-Id: <20220712164108.30262-4-kabel@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220712164108.30262-1-kabel@kernel.org> References: <20220712164108.30262-1-kabel@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Pali Roh=C3=A1r Add definitions for PCIe legacy INTx interrupts. This is required for example in a scenario where a driver requests only one of the legacy interrupts (INTA). Without this, the driver would be notified on events on all 4 (INTA, INTB, INTC, INTD), even if it requested only one of them. Signed-off-by: Pali Roh=C3=A1r Signed-off-by: Marek Beh=C3=BAn --- arch/arm/boot/dts/armada-370.dtsi | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-3= 70.dtsi index 46e6d3ed8f35..9dc928859ad3 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -60,16 +60,26 @@ pcie0: pcie@1,0 { reg =3D <0x0800 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&mpic 58>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x1 = 0 1 0 0x81000000 0 0 0x81000000 0x1 0 = 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &mpic 58>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; marvell,pcie-port =3D <0>; marvell,pcie-lane =3D <0>; clocks =3D <&gateclk 5>; status =3D "disabled"; + + pcie0_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; =20 pcie2: pcie@2,0 { @@ -78,16 +88,26 @@ pcie2: pcie@2,0 { reg =3D <0x1000 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&mpic 62>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x2 = 0 1 0 0x81000000 0 0 0x81000000 0x2 0 = 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &mpic 62>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; marvell,pcie-port =3D <1>; marvell,pcie-lane =3D <0>; clocks =3D <&gateclk 9>; status =3D "disabled"; + + pcie2_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; }; =20 --=20 2.35.1 From nobody Sat Apr 18 15:43:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5308CCA47C for ; Tue, 12 Jul 2022 16:41:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233645AbiGLQli (ORCPT ); Tue, 12 Jul 2022 12:41:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58488 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233355AbiGLQlb (ORCPT ); Tue, 12 Jul 2022 12:41:31 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ABBEEB418A; Tue, 12 Jul 2022 09:41:24 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 368FCB81A76; Tue, 12 Jul 2022 16:41:23 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 32318C3411C; Tue, 12 Jul 2022 16:41:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657644082; bh=7SU+lansfxppynvPUzU0yCnCk58FDSjADBXkvGzF/7M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Te8+k4AYnVNYk5zKcs83QylLNIHNwfectxUm5OKwE3DoLurqWrX5UePAWwl+ef3gb JWc/Mym6/jPXxXz0Saktx/6Td1hgqsLrLRPPcWTC7nn63cKe26J+fItsVjynH7toiM RFNFnTc+7p25hpOw4etytbVVVyoNDj7z/MPZbuilfE3/L9q1cRG0vexcReGgm3FoVJ TmHLANiitO1FzMG5E+GjL98wORx1pIwNgUNRdHbOFznvF+XvwJqaQhcZ0AfJQwKB1v vD4tW3PsAOpbNRTx5SX2gWTe9YwDV+zTiUhRN8VuQJWhE5kScb+a/HgN1+6qji6371 SEbjAFyKJHYDg== From: =?UTF-8?q?Marek=20Beh=C3=BAn?= To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth Cc: Rob Herring , =?UTF-8?q?Pali=20Roh=C3=A1r?= , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Marek=20Beh=C3=BAn?= Subject: [PATCH v2 04/10] ARM: dts: armada-xp-98dx3236.dtsi: Add definitions for PCIe legacy INTx interrupts Date: Tue, 12 Jul 2022 18:41:02 +0200 Message-Id: <20220712164108.30262-5-kabel@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220712164108.30262-1-kabel@kernel.org> References: <20220712164108.30262-1-kabel@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Pali Roh=C3=A1r Add definitions for PCIe legacy INTx interrupts. This is required for example in a scenario where a driver requests only one of the legacy interrupts (INTA). Without this, the driver would be notified on events on all 4 (INTA, INTB, INTC, INTD), even if it requested only one of them. Signed-off-by: Pali Roh=C3=A1r Signed-off-by: Marek Beh=C3=BAn --- arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/= armada-xp-98dx3236.dtsi index 38a052a0312d..b21ffb819b1d 100644 --- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi +++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi @@ -76,16 +76,26 @@ pcie1: pcie@1,0 { reg =3D <0x0800 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&mpic 58>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &mpic 58>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; marvell,pcie-port =3D <0>; marvell,pcie-lane =3D <0>; clocks =3D <&gateclk 5>; status =3D "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; }; =20 --=20 2.35.1 From nobody Sat Apr 18 15:43:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5106CC43334 for ; Tue, 12 Jul 2022 16:41:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233747AbiGLQll (ORCPT ); Tue, 12 Jul 2022 12:41:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58460 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230517AbiGLQld (ORCPT ); Tue, 12 Jul 2022 12:41:33 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0BED4BA161; Tue, 12 Jul 2022 09:41:27 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 71D7EB817B7; Tue, 12 Jul 2022 16:41:25 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5DAAEC36AE2; Tue, 12 Jul 2022 16:41:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657644084; bh=YEt9jd46hWyhJgVZ4pcNSjgJG1cZXpwgIBKwaBLiJvw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=W0v4mgPbnMZSQeRIPS4fNHoucTlVHkhNJIhi/MYU73QEGhu51jOveZ3OGy7YUAW0u iMhRQWqbiCLig4J4T96VYazHtuJmysKkW9drgSj7BqT4I2/sUiA0D4RtVNf6lG5e4a XNzbiUj0FFPzxbRU408K6oVfvpkpn+6S5GZH894WOCqq2GUXfpQjrgUdmx00zksBcO IbCJ28lQ1qMq8tXpL57gELX2km44w2M58xlUCwAdubFbm0t8vQ3Kqlua8xwD842kh7 ejUpYBSoh+8Onj24gZvoki7BTk04lslb+bv5vnjSVaySv9AonofEgGyBegCF6Igx8I JU6TSgLklq1PQ== From: =?UTF-8?q?Marek=20Beh=C3=BAn?= To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth Cc: Rob Herring , =?UTF-8?q?Pali=20Roh=C3=A1r?= , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Marek=20Beh=C3=BAn?= Subject: [PATCH v2 05/10] ARM: dts: armada-xp-mv78230.dtsi: Add definitions for PCIe legacy INTx interrupts Date: Tue, 12 Jul 2022 18:41:03 +0200 Message-Id: <20220712164108.30262-6-kabel@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220712164108.30262-1-kabel@kernel.org> References: <20220712164108.30262-1-kabel@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Pali Roh=C3=A1r Add definitions for PCIe legacy INTx interrupts. This is required for example in a scenario where a driver requests only one of the legacy interrupts (INTA). Without this, the driver would be notified on events on all 4 (INTA, INTB, INTC, INTD), even if it requested only one of them. Signed-off-by: Pali Roh=C3=A1r Signed-off-by: Marek Beh=C3=BAn --- arch/arm/boot/dts/armada-xp-mv78230.dtsi | 70 ++++++++++++++++++++---- 1 file changed, 60 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/a= rmada-xp-mv78230.dtsi index 8558bf6bb54c..bf9360f41e0a 100644 --- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi @@ -83,16 +83,26 @@ pcie1: pcie@1,0 { reg =3D <0x0800 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&mpic 58>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &mpic 58>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; marvell,pcie-port =3D <0>; marvell,pcie-lane =3D <0>; clocks =3D <&gateclk 5>; status =3D "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; =20 pcie2: pcie@2,0 { @@ -101,16 +111,26 @@ pcie2: pcie@2,0 { reg =3D <0x1000 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&mpic 59>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &mpic 59>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; marvell,pcie-port =3D <0>; marvell,pcie-lane =3D <1>; clocks =3D <&gateclk 6>; status =3D "disabled"; + + pcie2_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; =20 pcie3: pcie@3,0 { @@ -119,16 +139,26 @@ pcie3: pcie@3,0 { reg =3D <0x1800 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&mpic 60>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &mpic 60>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie3_intc 0>, + <0 0 0 2 &pcie3_intc 1>, + <0 0 0 3 &pcie3_intc 2>, + <0 0 0 4 &pcie3_intc 3>; marvell,pcie-port =3D <0>; marvell,pcie-lane =3D <2>; clocks =3D <&gateclk 7>; status =3D "disabled"; + + pcie3_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; =20 pcie4: pcie@4,0 { @@ -137,16 +167,26 @@ pcie4: pcie@4,0 { reg =3D <0x2000 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&mpic 61>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &mpic 61>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie4_intc 0>, + <0 0 0 2 &pcie4_intc 1>, + <0 0 0 3 &pcie4_intc 2>, + <0 0 0 4 &pcie4_intc 3>; marvell,pcie-port =3D <0>; marvell,pcie-lane =3D <3>; clocks =3D <&gateclk 8>; status =3D "disabled"; + + pcie4_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; =20 pcie5: pcie@5,0 { @@ -155,16 +195,26 @@ pcie5: pcie@5,0 { reg =3D <0x2800 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&mpic 62>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x5 0 1 0 0x81000000 0 0 0x81000000 0x5 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &mpic 62>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie5_intc 0>, + <0 0 0 2 &pcie5_intc 1>, + <0 0 0 3 &pcie5_intc 2>, + <0 0 0 4 &pcie5_intc 3>; marvell,pcie-port =3D <1>; marvell,pcie-lane =3D <0>; clocks =3D <&gateclk 9>; status =3D "disabled"; + + pcie5_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; }; =20 --=20 2.35.1 From nobody Sat Apr 18 15:43:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1FC30C43334 for ; Tue, 12 Jul 2022 16:41:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233870AbiGLQlu (ORCPT ); Tue, 12 Jul 2022 12:41:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58518 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233350AbiGLQle (ORCPT ); Tue, 12 Jul 2022 12:41:34 -0400 Received: from sin.source.kernel.org (sin.source.kernel.org [145.40.73.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77C01C3AFE; Tue, 12 Jul 2022 09:41:30 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 23BDBCE1C9F; Tue, 12 Jul 2022 16:41:28 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8AC12C341CD; Tue, 12 Jul 2022 16:41:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657644086; bh=17y76lSzSc7hAMgtMuJKp71vtfM+9WHafoK+k81GIYQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tBRkSUxYGpA/O42WOco2Rp4+DQ6ckIV3Q16e+CXlKF9Ut6HYNBVhglsDz+VF4UAvZ gAP0chkaOTZWAQU+iEaUZRfIx7Y2U5r3uuklCDK/qZjShWv/fNV3dpFeXbsouq5rIG /xfoA+F/iRrTYBRumksXlmt6ekkz35EaRB5VgQpRs7UtWZbkvz0f42xdAV/t3iIlFB /NavUXhHrwZsvk1KE1mV4Xq08KceoO/ZiD0q5RWxm73tUra7KHtW/OffEbElvGgqBP FUV/aKEG5rHqJSz0tBKNNfBgdD5qPUs1oVdTGsOE3mE0AR970i1c7hU2JXAVZNPyEx vmHyJ47o4RvlA== From: =?UTF-8?q?Marek=20Beh=C3=BAn?= To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth Cc: Rob Herring , =?UTF-8?q?Pali=20Roh=C3=A1r?= , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Marek=20Beh=C3=BAn?= Subject: [PATCH v2 06/10] ARM: dts: armada-xp-mv78260.dtsi: Add definitions for PCIe legacy INTx interrupts Date: Tue, 12 Jul 2022 18:41:04 +0200 Message-Id: <20220712164108.30262-7-kabel@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220712164108.30262-1-kabel@kernel.org> References: <20220712164108.30262-1-kabel@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Pali Roh=C3=A1r Add definitions for PCIe legacy INTx interrupts. This is required for example in a scenario where a driver requests only one of the legacy interrupts (INTA). Without this, the driver would be notified on events on all 4 (INTA, INTB, INTC, INTD), even if it requested only one of them. Signed-off-by: Pali Roh=C3=A1r Signed-off-by: Marek Beh=C3=BAn --- arch/arm/boot/dts/armada-xp-mv78260.dtsi | 126 +++++++++++++++++++---- 1 file changed, 108 insertions(+), 18 deletions(-) diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/a= rmada-xp-mv78260.dtsi index 2d85fe8ac327..0714af52e607 100644 --- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi @@ -98,16 +98,26 @@ pcie1: pcie@1,0 { reg =3D <0x0800 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&mpic 58>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &mpic 58>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; marvell,pcie-port =3D <0>; marvell,pcie-lane =3D <0>; clocks =3D <&gateclk 5>; status =3D "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; =20 pcie2: pcie@2,0 { @@ -116,16 +126,26 @@ pcie2: pcie@2,0 { reg =3D <0x1000 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&mpic 59>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &mpic 59>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; marvell,pcie-port =3D <0>; marvell,pcie-lane =3D <1>; clocks =3D <&gateclk 6>; status =3D "disabled"; + + pcie2_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; =20 pcie3: pcie@3,0 { @@ -134,16 +154,26 @@ pcie3: pcie@3,0 { reg =3D <0x1800 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&mpic 60>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &mpic 60>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie3_intc 0>, + <0 0 0 2 &pcie3_intc 1>, + <0 0 0 3 &pcie3_intc 2>, + <0 0 0 4 &pcie3_intc 3>; marvell,pcie-port =3D <0>; marvell,pcie-lane =3D <2>; clocks =3D <&gateclk 7>; status =3D "disabled"; + + pcie3_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; =20 pcie4: pcie@4,0 { @@ -152,16 +182,26 @@ pcie4: pcie@4,0 { reg =3D <0x2000 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&mpic 61>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &mpic 61>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie4_intc 0>, + <0 0 0 2 &pcie4_intc 1>, + <0 0 0 3 &pcie4_intc 2>, + <0 0 0 4 &pcie4_intc 3>; marvell,pcie-port =3D <0>; marvell,pcie-lane =3D <3>; clocks =3D <&gateclk 8>; status =3D "disabled"; + + pcie4_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; =20 pcie5: pcie@5,0 { @@ -170,16 +210,26 @@ pcie5: pcie@5,0 { reg =3D <0x2800 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&mpic 62>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x5 0 1 0 0x81000000 0 0 0x81000000 0x5 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &mpic 62>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie5_intc 0>, + <0 0 0 2 &pcie5_intc 1>, + <0 0 0 3 &pcie5_intc 2>, + <0 0 0 4 &pcie5_intc 3>; marvell,pcie-port =3D <1>; marvell,pcie-lane =3D <0>; clocks =3D <&gateclk 9>; status =3D "disabled"; + + pcie5_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; =20 pcie6: pcie@6,0 { @@ -188,16 +238,26 @@ pcie6: pcie@6,0 { reg =3D <0x3000 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&mpic 63>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x6 0 1 0 0x81000000 0 0 0x81000000 0x6 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &mpic 63>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie6_intc 0>, + <0 0 0 2 &pcie6_intc 1>, + <0 0 0 3 &pcie6_intc 2>, + <0 0 0 4 &pcie6_intc 3>; marvell,pcie-port =3D <1>; marvell,pcie-lane =3D <1>; clocks =3D <&gateclk 10>; status =3D "disabled"; + + pcie6_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; =20 pcie7: pcie@7,0 { @@ -206,16 +266,26 @@ pcie7: pcie@7,0 { reg =3D <0x3800 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&mpic 64>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x7 0 1 0 0x81000000 0 0 0x81000000 0x7 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &mpic 64>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie7_intc 0>, + <0 0 0 2 &pcie7_intc 1>, + <0 0 0 3 &pcie7_intc 2>, + <0 0 0 4 &pcie7_intc 3>; marvell,pcie-port =3D <1>; marvell,pcie-lane =3D <2>; clocks =3D <&gateclk 11>; status =3D "disabled"; + + pcie7_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; =20 pcie8: pcie@8,0 { @@ -224,16 +294,26 @@ pcie8: pcie@8,0 { reg =3D <0x4000 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&mpic 65>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x8 0 1 0 0x81000000 0 0 0x81000000 0x8 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &mpic 65>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie8_intc 0>, + <0 0 0 2 &pcie8_intc 1>, + <0 0 0 3 &pcie8_intc 2>, + <0 0 0 4 &pcie8_intc 3>; marvell,pcie-port =3D <1>; marvell,pcie-lane =3D <3>; clocks =3D <&gateclk 12>; status =3D "disabled"; + + pcie8_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; =20 pcie9: pcie@9,0 { @@ -242,16 +322,26 @@ pcie9: pcie@9,0 { reg =3D <0x4800 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&mpic 99>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x9 0 1 0 0x81000000 0 0 0x81000000 0x9 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &mpic 99>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie9_intc 0>, + <0 0 0 2 &pcie9_intc 1>, + <0 0 0 3 &pcie9_intc 2>, + <0 0 0 4 &pcie9_intc 3>; marvell,pcie-port =3D <2>; marvell,pcie-lane =3D <0>; clocks =3D <&gateclk 26>; status =3D "disabled"; + + pcie9_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; }; =20 --=20 2.35.1 From nobody Sat Apr 18 15:43:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84118C43334 for ; Tue, 12 Jul 2022 16:41:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233847AbiGLQlr (ORCPT ); Tue, 12 Jul 2022 12:41:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58510 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233505AbiGLQld (ORCPT ); Tue, 12 Jul 2022 12:41:33 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AA4F3BFAF8; Tue, 12 Jul 2022 09:41:29 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 24A906195C; Tue, 12 Jul 2022 16:41:29 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B8492C3411C; Tue, 12 Jul 2022 16:41:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657644088; bh=4WKRmL2FykAWdl6pWbOT0riuyr9bUPG1WRMUEVP7bOU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=M3skOuSd2Sc04Rbu1+S1nWNQei+a1ejS/mKXw67mkTfekp5zp7inI+2+2pqCaUCim KBVfhYIYR020Vpzb9Y0+vS9x7zMPtx7rKB9sjtHv+NTE4BFREoWnuG11bQQCVfKfDV F7duUvZCxLq/IAVyr3xMaCaw8v6O9GUxPEYfjQ1Saw4QcSEbfxhIju/HWvtNB5neRm /vqn0CNu9ixJ0ayI3gEHGD1BUMmBbu5N6MUCOHAhesHEh9oL71a2lvcr89fopasrZI 3tZg6eJqpRQv3d1xBDMrqOTbYpfbgBYg+LJKzR3F6ncuEq7uiWwEaStXtZNEas/OLf bA10SEHlgILVg== From: =?UTF-8?q?Marek=20Beh=C3=BAn?= To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth Cc: Rob Herring , =?UTF-8?q?Pali=20Roh=C3=A1r?= , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Marek=20Beh=C3=BAn?= Subject: [PATCH v2 07/10] ARM: dts: armada-xp-mv78460.dtsi: Add definitions for PCIe legacy INTx interrupts Date: Tue, 12 Jul 2022 18:41:05 +0200 Message-Id: <20220712164108.30262-8-kabel@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220712164108.30262-1-kabel@kernel.org> References: <20220712164108.30262-1-kabel@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Pali Roh=C3=A1r Add definitions for PCIe legacy INTx interrupts. This is required for example in a scenario where a driver requests only one of the legacy interrupts (INTA). Without this, the driver would be notified on events on all 4 (INTA, INTB, INTC, INTD), even if it requested only one of them. Signed-off-by: Pali Roh=C3=A1r Signed-off-by: Marek Beh=C3=BAn --- arch/arm/boot/dts/armada-xp-mv78460.dtsi | 140 +++++++++++++++++++---- 1 file changed, 120 insertions(+), 20 deletions(-) diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/a= rmada-xp-mv78460.dtsi index 230a3fd36b30..16185edf9aa5 100644 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi @@ -119,16 +119,26 @@ pcie1: pcie@1,0 { reg =3D <0x0800 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&mpic 58>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &mpic 58>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; marvell,pcie-port =3D <0>; marvell,pcie-lane =3D <0>; clocks =3D <&gateclk 5>; status =3D "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; =20 pcie2: pcie@2,0 { @@ -137,16 +147,26 @@ pcie2: pcie@2,0 { reg =3D <0x1000 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&mpic 59>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &mpic 59>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; marvell,pcie-port =3D <0>; marvell,pcie-lane =3D <1>; clocks =3D <&gateclk 6>; status =3D "disabled"; + + pcie2_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; =20 pcie3: pcie@3,0 { @@ -155,16 +175,26 @@ pcie3: pcie@3,0 { reg =3D <0x1800 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&mpic 60>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &mpic 60>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie3_intc 0>, + <0 0 0 2 &pcie3_intc 1>, + <0 0 0 3 &pcie3_intc 2>, + <0 0 0 4 &pcie3_intc 3>; marvell,pcie-port =3D <0>; marvell,pcie-lane =3D <2>; clocks =3D <&gateclk 7>; status =3D "disabled"; + + pcie3_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; =20 pcie4: pcie@4,0 { @@ -173,16 +203,26 @@ pcie4: pcie@4,0 { reg =3D <0x2000 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&mpic 61>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &mpic 61>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie4_intc 0>, + <0 0 0 2 &pcie4_intc 1>, + <0 0 0 3 &pcie4_intc 2>, + <0 0 0 4 &pcie4_intc 3>; marvell,pcie-port =3D <0>; marvell,pcie-lane =3D <3>; clocks =3D <&gateclk 8>; status =3D "disabled"; + + pcie4_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; =20 pcie5: pcie@5,0 { @@ -191,16 +231,26 @@ pcie5: pcie@5,0 { reg =3D <0x2800 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&mpic 62>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x5 0 1 0 0x81000000 0 0 0x81000000 0x5 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &mpic 62>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie5_intc 0>, + <0 0 0 2 &pcie5_intc 1>, + <0 0 0 3 &pcie5_intc 2>, + <0 0 0 4 &pcie5_intc 3>; marvell,pcie-port =3D <1>; marvell,pcie-lane =3D <0>; clocks =3D <&gateclk 9>; status =3D "disabled"; + + pcie5_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; =20 pcie6: pcie@6,0 { @@ -209,16 +259,26 @@ pcie6: pcie@6,0 { reg =3D <0x3000 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&mpic 63>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x6 0 1 0 0x81000000 0 0 0x81000000 0x6 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &mpic 63>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie6_intc 0>, + <0 0 0 2 &pcie6_intc 1>, + <0 0 0 3 &pcie6_intc 2>, + <0 0 0 4 &pcie6_intc 3>; marvell,pcie-port =3D <1>; marvell,pcie-lane =3D <1>; clocks =3D <&gateclk 10>; status =3D "disabled"; + + pcie6_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; =20 pcie7: pcie@7,0 { @@ -227,16 +287,26 @@ pcie7: pcie@7,0 { reg =3D <0x3800 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&mpic 64>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x7 0 1 0 0x81000000 0 0 0x81000000 0x7 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &mpic 64>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie7_intc 0>, + <0 0 0 2 &pcie7_intc 1>, + <0 0 0 3 &pcie7_intc 2>, + <0 0 0 4 &pcie7_intc 3>; marvell,pcie-port =3D <1>; marvell,pcie-lane =3D <2>; clocks =3D <&gateclk 11>; status =3D "disabled"; + + pcie7_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; =20 pcie8: pcie@8,0 { @@ -245,16 +315,26 @@ pcie8: pcie@8,0 { reg =3D <0x4000 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&mpic 65>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x8 0 1 0 0x81000000 0 0 0x81000000 0x8 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &mpic 65>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie8_intc 0>, + <0 0 0 2 &pcie8_intc 1>, + <0 0 0 3 &pcie8_intc 2>, + <0 0 0 4 &pcie8_intc 3>; marvell,pcie-port =3D <1>; marvell,pcie-lane =3D <3>; clocks =3D <&gateclk 12>; status =3D "disabled"; + + pcie8_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; =20 pcie9: pcie@9,0 { @@ -263,16 +343,26 @@ pcie9: pcie@9,0 { reg =3D <0x4800 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&mpic 99>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x9 0 1 0 0x81000000 0 0 0x81000000 0x9 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &mpic 99>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie9_intc 0>, + <0 0 0 2 &pcie9_intc 1>, + <0 0 0 3 &pcie9_intc 2>, + <0 0 0 4 &pcie9_intc 3>; marvell,pcie-port =3D <2>; marvell,pcie-lane =3D <0>; clocks =3D <&gateclk 26>; status =3D "disabled"; + + pcie9_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; =20 pcie10: pcie@a,0 { @@ -281,16 +371,26 @@ pcie10: pcie@a,0 { reg =3D <0x5000 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&mpic 103>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0xa 0 1 0 0x81000000 0 0 0x81000000 0xa 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &mpic 103>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie10_intc 0>, + <0 0 0 2 &pcie10_intc 1>, + <0 0 0 3 &pcie10_intc 2>, + <0 0 0 4 &pcie10_intc 3>; marvell,pcie-port =3D <3>; marvell,pcie-lane =3D <0>; clocks =3D <&gateclk 27>; status =3D "disabled"; + + pcie10_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; }; =20 --=20 2.35.1 From nobody Sat Apr 18 15:43:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84A21C433EF for ; Tue, 12 Jul 2022 16:42:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234079AbiGLQmL (ORCPT ); Tue, 12 Jul 2022 12:42:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58492 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233546AbiGLQlg (ORCPT ); Tue, 12 Jul 2022 12:41:36 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C491EB3D51; Tue, 12 Jul 2022 09:41:31 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 48F876195D; Tue, 12 Jul 2022 16:41:31 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E51D5C341D8; Tue, 12 Jul 2022 16:41:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657644090; bh=D0oIMdGF/JP3eXO44e90W+cdHie3mg+K0Kdx1Mi3Xfo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oBc2UYlh1ptv2VXS3JdhyTd6ZmNbsb/sZ2rHFXkfbIfrZLbzlEi8AiuROyzzaOCW2 mu+x/HgxKEZ+C5e91C2QEgCYZUcxvSdsiSk8EnJuDAEq5cf63sXlgPUYslUELbjmcB jsz7Od5DvDXs8ZQNtX35/oGoWB4Y/DNSkSShRoaGH+l+x9+Hw3dvK3KefAiTnjqKeQ OoyUBUJy4hcI5D5JYWXF7qUX/btYYiQl0VNQK8UiatEeCK+t7y3NvahfcUqbanGH5L ZrWV9L+kQgTRCNgokelX5DvsDtOZDydmUTOtnGhrrPXAHWsFx0qgamCICWcp2+D4Zb SGIB1FQFdfz9w== From: =?UTF-8?q?Marek=20Beh=C3=BAn?= To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth Cc: Rob Herring , =?UTF-8?q?Pali=20Roh=C3=A1r?= , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Marek=20Beh=C3=BAn?= Subject: [PATCH v2 08/10] ARM: dts: armada-375.dtsi: Add definitions for PCIe legacy INTx interrupts Date: Tue, 12 Jul 2022 18:41:06 +0200 Message-Id: <20220712164108.30262-9-kabel@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220712164108.30262-1-kabel@kernel.org> References: <20220712164108.30262-1-kabel@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Pali Roh=C3=A1r Add definitions for PCIe legacy INTx interrupts. This is required for example in a scenario where a driver requests only one of the legacy interrupts (INTA). Without this, the driver would be notified on events on all 4 (INTA, INTB, INTC, INTD), even if it requested only one of them. Signed-off-by: Pali Roh=C3=A1r Signed-off-by: Marek Beh=C3=BAn --- arch/arm/boot/dts/armada-375.dtsi | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-3= 75.dtsi index 7f2f24a29e6c..929deaf312a5 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -568,16 +568,26 @@ pcie0: pcie@1,0 { reg =3D <0x0800 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; marvell,pcie-port =3D <0>; marvell,pcie-lane =3D <0>; clocks =3D <&gateclk 5>; status =3D "disabled"; + + pcie0_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; =20 pcie1: pcie@2,0 { @@ -586,16 +596,26 @@ pcie1: pcie@2,0 { reg =3D <0x1000 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; marvell,pcie-port =3D <0>; marvell,pcie-lane =3D <1>; clocks =3D <&gateclk 6>; status =3D "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; =20 }; --=20 2.35.1 From nobody Sat Apr 18 15:43:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99102C43334 for ; Tue, 12 Jul 2022 16:42:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229746AbiGLQmS (ORCPT ); Tue, 12 Jul 2022 12:42:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58584 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233368AbiGLQlj (ORCPT ); Tue, 12 Jul 2022 12:41:39 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 69F17B4199; Tue, 12 Jul 2022 09:41:35 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 2C26DB817B7; Tue, 12 Jul 2022 16:41:34 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1E5D6C3411E; Tue, 12 Jul 2022 16:41:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657644092; bh=SXkMegj1u4GiyrfeNuHSsXbaYZEe6t2/pFH37yNDYX8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=alu4x58Fz3PhWiB+Qs/MMSgBwvZNP1DIRwwl/7s/hODh69772NM1xvjLtC5Hq6c3R e1Cs2p2h744AXGJMoDtwThk7IGNkb8TxwpowQT+ZzT5EMlekaAna/GJB8z2S3kXqqW FGMSHvW2R8zTEjqFIKMXe2wvJ4mFWt87FKB+yjKkyoYb1zM//YHpttgjYdoOuu7ju+ 3egGfmlXUZDUtlg2Vmpv4EfsHu3IGTUekajyIYXsQp7tjquVmTXT45O7bH6PYNqYWA fb0O5DKYJCmu8iAo9T7MPSLyFggytEB7PTZMmg+xyDKHr8YvZbd1kDc8SsIrJFvch4 wzBfZjZBHXFrw== From: =?UTF-8?q?Marek=20Beh=C3=BAn?= To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth Cc: Rob Herring , =?UTF-8?q?Pali=20Roh=C3=A1r?= , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Marek=20Beh=C3=BAn?= Subject: [PATCH v2 09/10] ARM: dts: armada-380.dtsi: Add definitions for PCIe legacy INTx interrupts Date: Tue, 12 Jul 2022 18:41:07 +0200 Message-Id: <20220712164108.30262-10-kabel@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220712164108.30262-1-kabel@kernel.org> References: <20220712164108.30262-1-kabel@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Pali Roh=C3=A1r Add definitions for PCIe legacy INTx interrupts. This is required for example in a scenario where a driver requests only one of the legacy interrupts (INTA). Without this, the driver would be notified on events on all 4 (INTA, INTB, INTC, INTD), even if it requested only one of them. Signed-off-by: Pali Roh=C3=A1r Signed-off-by: Marek Beh=C3=BAn --- arch/arm/boot/dts/armada-380.dtsi | 42 ++++++++++++++++++++++++++----- 1 file changed, 36 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-3= 80.dtsi index cff1269f3fbf..ce1dddb2269b 100644 --- a/arch/arm/boot/dts/armada-380.dtsi +++ b/arch/arm/boot/dts/armada-380.dtsi @@ -64,16 +64,26 @@ pcie@1,0 { reg =3D <0x0800 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; marvell,pcie-port =3D <0>; marvell,pcie-lane =3D <0>; clocks =3D <&gateclk 8>; status =3D "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; =20 /* x1 port */ @@ -83,16 +93,26 @@ pcie@2,0 { reg =3D <0x1000 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; marvell,pcie-port =3D <1>; marvell,pcie-lane =3D <0>; clocks =3D <&gateclk 5>; status =3D "disabled"; + + pcie2_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; =20 /* x1 port */ @@ -102,16 +122,26 @@ pcie@3,0 { reg =3D <0x1800 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie3_intc 0>, + <0 0 0 2 &pcie3_intc 1>, + <0 0 0 3 &pcie3_intc 2>, + <0 0 0 4 &pcie3_intc 3>; marvell,pcie-port =3D <2>; marvell,pcie-lane =3D <0>; clocks =3D <&gateclk 6>; status =3D "disabled"; + + pcie3_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; }; }; --=20 2.35.1 From nobody Sat Apr 18 15:43:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3228EC433EF for ; Tue, 12 Jul 2022 16:42:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233888AbiGLQmV (ORCPT ); Tue, 12 Jul 2022 12:42:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58766 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233369AbiGLQlk (ORCPT ); Tue, 12 Jul 2022 12:41:40 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 176DEB9D89; Tue, 12 Jul 2022 09:41:36 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id A3D2F61957; Tue, 12 Jul 2022 16:41:35 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4A5B0C341C8; Tue, 12 Jul 2022 16:41:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657644095; bh=MLuprfCy4caGLkl1kcFdfe6bnIHmaQdEaRcXPxWeLeE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eVw8br0zwUj0D/nwkC0g33OjQQLsDc5W6PYc/yLVgqZKP/zwrvO7oVrOMig3HBtEj iXFncNbzaXGCz3zTVnyhUWg5wXQ8jc141AGEluzrwsrZLTt2wgR2SrOAqYe0WJkjxu vlBdtjnY6nFKOC32WR5T07f6We4kY8YDEg3x0bbjTFDAzVH7R+ILQLNe63IAvixnfo MudCBWMiT4CIdzjsOU4lO/QhCUNpR3ZGk5tmFfstMJsKhSw1dvr25UgcnZW5taxR7k EqObkIS1pF1/wPuv3DI+dMNwo7Vpg1deLo5CSl/Ls1FmofzOH3grKC9WiBu/81tF8X AKhidmhRadRnA== From: =?UTF-8?q?Marek=20Beh=C3=BAn?= To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth Cc: Rob Herring , =?UTF-8?q?Pali=20Roh=C3=A1r?= , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Marek=20Beh=C3=BAn?= Subject: [PATCH v2 10/10] ARM: dts: armada-39x.dtsi: Add definitions for PCIe legacy INTx interrupts Date: Tue, 12 Jul 2022 18:41:08 +0200 Message-Id: <20220712164108.30262-11-kabel@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220712164108.30262-1-kabel@kernel.org> References: <20220712164108.30262-1-kabel@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Pali Roh=C3=A1r Add definitions for PCIe legacy INTx interrupts. This is required for example in a scenario where a driver requests only one of the legacy interrupts (INTA). Without this, the driver would be notified on events on all 4 (INTA, INTB, INTC, INTD), even if it requested only one of them. Signed-off-by: Pali Roh=C3=A1r Signed-off-by: Marek Beh=C3=BAn --- arch/arm/boot/dts/armada-39x.dtsi | 56 ++++++++++++++++++++++++++----- 1 file changed, 48 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-3= 9x.dtsi index e0b7c2099831..923b035a3ab3 100644 --- a/arch/arm/boot/dts/armada-39x.dtsi +++ b/arch/arm/boot/dts/armada-39x.dtsi @@ -438,16 +438,26 @@ pcie@1,0 { reg =3D <0x0800 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; marvell,pcie-port =3D <0>; marvell,pcie-lane =3D <0>; clocks =3D <&gateclk 8>; status =3D "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; =20 /* x1 port */ @@ -457,16 +467,26 @@ pcie@2,0 { reg =3D <0x1000 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; marvell,pcie-port =3D <1>; marvell,pcie-lane =3D <0>; clocks =3D <&gateclk 5>; status =3D "disabled"; + + pcie2_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; =20 /* x1 port */ @@ -476,16 +496,26 @@ pcie@3,0 { reg =3D <0x1800 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie3_intc 0>, + <0 0 0 2 &pcie3_intc 1>, + <0 0 0 3 &pcie3_intc 2>, + <0 0 0 4 &pcie3_intc 3>; marvell,pcie-port =3D <2>; marvell,pcie-lane =3D <0>; clocks =3D <&gateclk 6>; status =3D "disabled"; + + pcie3_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; =20 /* @@ -498,16 +528,26 @@ pcie@4,0 { reg =3D <0x2000 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; + interrupt-names =3D "intx"; + interrupts-extended =3D <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells =3D <1>; ranges =3D <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie4_intc 0>, + <0 0 0 2 &pcie4_intc 1>, + <0 0 0 3 &pcie4_intc 2>, + <0 0 0 4 &pcie4_intc 3>; marvell,pcie-port =3D <3>; marvell,pcie-lane =3D <0>; clocks =3D <&gateclk 7>; status =3D "disabled"; + + pcie4_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + }; }; }; =20 --=20 2.35.1