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[88.93.169.171]) by smtp.gmail.com with ESMTPSA id w15-20020a05651234cf00b00489e88d6a72sm737577lfr.198.2022.07.12.07.42.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jul 2022 07:42:58 -0700 (PDT) From: Krzysztof Kozlowski To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Bhupesh Sharma , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: Krzysztof Kozlowski , Douglas Anderson Subject: [PATCH v3 1/5] dt-bindings: mmc: sdhci-msm: fix reg-names entries Date: Tue, 12 Jul 2022 16:42:41 +0200 Message-Id: <20220712144245.17417-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220712144245.17417-1-krzysztof.kozlowski@linaro.org> References: <20220712144245.17417-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Bindings before conversion to DT schema expected reg-names without "_mem" suffix. This was used by older DTS files and by the MSM SDHCI driver. Reported-by: Douglas Anderson Fixes: edfbf8c307ff ("dt-bindings: mmc: sdhci-msm: Fix issues in yaml bindi= ngs") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Douglas Anderson --- .../devicetree/bindings/mmc/sdhci-msm.yaml | 24 +++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documen= tation/devicetree/bindings/mmc/sdhci-msm.yaml index 0853d0c32dc7..fc6e5221985a 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -60,22 +60,22 @@ properties: maxItems: 4 oneOf: - items: - - const: hc_mem + - const: hc - items: - - const: hc_mem - - const: core_mem + - const: hc + - const: core - items: - - const: hc_mem - - const: cqe_mem + - const: hc + - const: cqhci - items: - - const: hc_mem - - const: cqe_mem - - const: ice_mem + - const: hc + - const: cqhci + - const: ice - items: - - const: hc_mem - - const: core_mem - - const: cqe_mem - - const: ice_mem + - const: hc + - const: core + - const: cqhci + - const: ice =20 clocks: minItems: 3 --=20 2.34.1 From nobody Sat Apr 18 21:02:47 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B448C43334 for ; Tue, 12 Jul 2022 14:43:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233628AbiGLOnI (ORCPT ); Tue, 12 Jul 2022 10:43:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233540AbiGLOnD (ORCPT ); Tue, 12 Jul 2022 10:43:03 -0400 Received: from mail-lj1-x232.google.com (mail-lj1-x232.google.com [IPv6:2a00:1450:4864:20::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 500FABAA9C for ; Tue, 12 Jul 2022 07:43:02 -0700 (PDT) Received: by mail-lj1-x232.google.com with SMTP id c15so10180981ljr.0 for ; Tue, 12 Jul 2022 07:43:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ya4IX6aXZnfGLTgjCrxYJj58Us6/c6dgWp4HrtPsHjg=; b=FXYsU7ly87F6wYfaTWoiieSaNZcXj4m5ARLB2+oLmk8ZGHhuDeq5p2kADp6tZTS8pf jH231exCwusuketydoCydTEfgKAOaP4JWSUa8qhRKntdxBt0AoJOj/M0kFBRVZ7f+/4Y qN06BX2hrlJsBphFdELj5M9zb5c1NZTBrNQ52NNBkXDTrkf0/tPPbFp2ELrXJHPRvXyX 6xK6c70XGIxZbDsbopIMLNvhNWIHFB148igi+S+jMJOUb/8yC7uhoPD1Dlg0ucKQVcyq UnpvInJev8eIUiqBd+k8EKq+GRHyjHLilRotYperMJIiJCsP1BfBQE2C7QNdXgYjsUYl TblA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ya4IX6aXZnfGLTgjCrxYJj58Us6/c6dgWp4HrtPsHjg=; b=oni+J5Uzf8EOfbjaEafpz8+DyI8COFkIO1RClW3PxkW4tSTeNOc9WGEXX+7DSev4ps qE36q3pdETYW2KnXrIQCgZiNpvgmiooJpDTyXnp7snmPS7bsRgi0AlsKPSo5oX3ujZIT C8E+2U2wgA41Nz9QSiduYivoIiADFguMFwhEbkkazSEgaEHYllVfqL02BjUCCdoqZZzC fNPgBAiohfe4i5zMzLTnShl8M/CzUynA6uU2X9RnlO5n11Oy4PrX7dvFQtWWTg2vro1W GhwpR9luQ7LP7aH0IYMu3TQeM7HX1XWzSjVAeHFq3s+jT7dj1ltyV6v0wgXHBUtZtHLZ 28LA== X-Gm-Message-State: AJIora/FprgQqjRHa43gUvzOTReVW/hQvlTCakc0rhTVTevvRYmz0BEf QLZE7e0+MYyBOWwQPXMgpuZEzg== X-Google-Smtp-Source: AGRyM1u3532cC5WBtGnIdYIeyjGVVbUGQwnn3owEYWqzk8kJyfj5OWr/QzPaDhFTtgk57pgzjO68Kg== X-Received: by 2002:a2e:8501:0:b0:249:17a0:ebf8 with SMTP id j1-20020a2e8501000000b0024917a0ebf8mr13334851lji.125.1657636980684; Tue, 12 Jul 2022 07:43:00 -0700 (PDT) Received: from krzk-bin.. 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[88.93.169.171]) by smtp.gmail.com with ESMTPSA id w15-20020a05651234cf00b00489e88d6a72sm737577lfr.198.2022.07.12.07.42.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jul 2022 07:42:59 -0700 (PDT) From: Krzysztof Kozlowski To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Bhupesh Sharma , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: Krzysztof Kozlowski , Douglas Anderson Subject: [PATCH v3 2/5] dt-bindings: mmc: sdhci-msm: constrain reg-names per variants Date: Tue, 12 Jul 2022 16:42:42 +0200 Message-Id: <20220712144245.17417-3-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220712144245.17417-1-krzysztof.kozlowski@linaro.org> References: <20220712144245.17417-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The entries in arrays must have fixed order, so the bindings and Linux driver expecting various combinations of 'reg' addresses was never actually conforming to guidelines. The 'core' reg entry is valid only for SDCC v4 and lower, so disallow it in SDCC v5. SDCC v4 supports CQE and ICE, so allow them, even though the qcom,sdhci-msm-v4 compatible is used also for earlier SoCs with SDCC v2 or v3, so it is not entirely accurate. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Douglas Anderson --- Changes since v2: 1. Fix commit title typo. 2. Add Rb tag. Changes since v1: 1. Rework the patch based on Doug's feedback. --- .../devicetree/bindings/mmc/sdhci-msm.yaml | 61 ++++++++++++------- 1 file changed, 38 insertions(+), 23 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documen= tation/devicetree/bindings/mmc/sdhci-msm.yaml index fc6e5221985a..2f0fdd65e908 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -49,33 +49,11 @@ properties: =20 reg: minItems: 1 - items: - - description: Host controller register map - - description: SD Core register map - - description: CQE register map - - description: Inline Crypto Engine register map + maxItems: 4 =20 reg-names: minItems: 1 maxItems: 4 - oneOf: - - items: - - const: hc - - items: - - const: hc - - const: core - - items: - - const: hc - - const: cqhci - - items: - - const: hc - - const: cqhci - - const: ice - - items: - - const: hc - - const: core - - const: cqhci - - const: ice =20 clocks: minItems: 3 @@ -177,6 +155,43 @@ required: allOf: - $ref: mmc-controller.yaml# =20 + - if: + properties: + compatible: + contains: + enum: + - qcom,sdhci-msm-v4 + then: + properties: + reg: + minItems: 2 + items: + - description: Host controller register map + - description: SD Core register map + - description: CQE register map + - description: Inline Crypto Engine register map + reg-names: + minItems: 2 + items: + - const: hc + - const: core + - const: cqhci + - const: ice + else: + properties: + reg: + minItems: 1 + items: + - description: Host controller register map + - description: CQE register map + - description: Inline Crypto Engine register map + reg-names: + minItems: 1 + items: + - const: hc + - const: cqhci + - const: ice + unevaluatedProperties: false =20 examples: --=20 2.34.1 From nobody Sat Apr 18 21:02:47 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11B49C433EF for ; Tue, 12 Jul 2022 14:43:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233673AbiGLOnO (ORCPT ); Tue, 12 Jul 2022 10:43:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35056 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233632AbiGLOnF (ORCPT ); Tue, 12 Jul 2022 10:43:05 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0E62CBB7CE for ; Tue, 12 Jul 2022 07:43:03 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id t25so14307462lfg.7 for ; Tue, 12 Jul 2022 07:43:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XRKH8Efyp+7WaOc4hkxLZdMcS/Z3VlGzrmvpw8bwAY8=; b=BRbdomsDxFHOtoR1pKSBtc+JkWGr0hTXZSBEwJphmxjaf3E12XpfYyF++PTjcd5G4e CiF8vU7fW8Zsfyx3fFmUP1k9lar/YwX9slYkh7Fyg71bY+mjGPkJeiTMOCRR9Yqpcslg Jq4MXfBJ9ikZUKD4+dfyY4K3YhcXYljSoLaC8ZNUcqhjPaGQyeZxoth+eO5lngYf4Qyn G6PBH368YJpixAMXBov9uzcjnDXoegf6XHIIrllIfDkoWrWDeeTE6y/ryfLIMQJ2yB3c p2d7PochcgBCieeHmHU3H0DAZqoap2ATGQM/7Fvlv5rm9K8iWfXLoF55acdVsI3UJO0d IYyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XRKH8Efyp+7WaOc4hkxLZdMcS/Z3VlGzrmvpw8bwAY8=; b=oTn1lq/pV5URqwWYuXWDj2sgt0bJ1ElZWASbth0hMuVskl8VsNtYNFGzpA6uL0pETy CBVHOzkg5PmvVHu7/poDwS0z9BWNbohMKuRW4lrSnVMPXiC+ZrMo8uEIkmNw1Eh5UNlY eQR5S4/0xLEQPBbE/OLtg0ouch+5rsH/lcB55+jXKUnym7yzn1uk2JqM/y/z4vaKaVvR NwWoMYZTvoacI2BQJWuq/ntZwtv4WQ3yYGa2CzObdpqmPrOdXnzARqVkaH83mkJYnnK8 RYa0Xi4nIPJt3bLrpc7S04cucGFddslc2e+YyFOISozUVQSvgkRTvDHTJ58Gntsc/hDG NbvQ== X-Gm-Message-State: AJIora9u12rzwkTRttV1j71bhdylePVZCnzpgDBHAAS/AfYvWU77ukqq H0Aq6qjQ7F8nOXBtmSqnn05h/A== X-Google-Smtp-Source: AGRyM1vWK54rOOsp6Y8z7B/A8kPn7tb3dKWCgu3FZRLRPUY2zH6lMOnK9l//YCWg4/hghYpRFrfXYw== X-Received: by 2002:a05:6512:12c8:b0:489:efbf:18d1 with SMTP id p8-20020a05651212c800b00489efbf18d1mr2700825lfg.192.1657636982571; Tue, 12 Jul 2022 07:43:02 -0700 (PDT) Received: from krzk-bin.. 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[88.93.169.171]) by smtp.gmail.com with ESMTPSA id w15-20020a05651234cf00b00489e88d6a72sm737577lfr.198.2022.07.12.07.43.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jul 2022 07:43:02 -0700 (PDT) From: Krzysztof Kozlowski To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Bhupesh Sharma , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: Krzysztof Kozlowski , Douglas Anderson Subject: [PATCH v3 3/5] arm64: dts: qcom: align SDHCI reg-names with DT schema Date: Tue, 12 Jul 2022 16:42:43 +0200 Message-Id: <20220712144245.17417-4-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220712144245.17417-1-krzysztof.kozlowski@linaro.org> References: <20220712144245.17417-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" DT schema requires SDHCI reg names to be hc/core without "_mem" suffix, just like TXT bindings were expecting before the conversion. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Douglas Anderson Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8916.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8953.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8994.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +- 6 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qc= om/ipq8074.dtsi index a6cb0dafcc17..2b9374f61d5b 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -379,7 +379,7 @@ spmi_bus: spmi@200f000 { sdhc_1: mmc@7824900 { compatible =3D "qcom,sdhci-msm-v4"; reg =3D <0x7824900 0x500>, <0x7824000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; =20 interrupts =3D , ; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qc= om/msm8916.dtsi index 48bc2e09128d..0bdf4d39f778 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1469,7 +1469,7 @@ lpass_codec: audio-codec@771c000 { sdhc_1: mmc@7824000 { compatible =3D "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0x07824900 0x11c>, <0x07824000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; =20 interrupts =3D , ; @@ -1487,7 +1487,7 @@ sdhc_1: mmc@7824000 { sdhc_2: mmc@7864000 { compatible =3D "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0x07864900 0x11c>, <0x07864000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; =20 interrupts =3D , ; diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qc= om/msm8953.dtsi index 1bc0ef476cdb..97dde1a429d9 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -799,7 +799,7 @@ sdhc_1: mmc@7824900 { compatible =3D "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; =20 reg =3D <0x7824900 0x500>, <0x7824000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; =20 interrupts =3D , ; @@ -859,7 +859,7 @@ sdhc_2: mmc@7864900 { compatible =3D "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; =20 reg =3D <0x7864900 0x500>, <0x7864000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; =20 interrupts =3D , ; diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qc= om/msm8994.dtsi index 8bc6c070e306..35c1ca080684 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -464,7 +464,7 @@ usb@f9200000 { sdhc1: mmc@f9824900 { compatible =3D "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0xf9824900 0x1a0>, <0xf9824000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; =20 interrupts =3D , ; @@ -487,7 +487,7 @@ sdhc1: mmc@f9824900 { sdhc2: mmc@f98a4900 { compatible =3D "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; =20 interrupts =3D , ; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qc= om/msm8996.dtsi index 25d6b26fab60..9745df5dc007 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2896,7 +2896,7 @@ hsusb_phy2: phy@7412000 { sdhc1: mmc@7464900 { compatible =3D "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0x07464900 0x11c>, <0x07464000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; =20 interrupts =3D , ; @@ -2920,7 +2920,7 @@ sdhc1: mmc@7464900 { sdhc2: mmc@74a4900 { compatible =3D "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0x074a4900 0x314>, <0x074a4000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; =20 interrupts =3D , ; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qc= om/msm8998.dtsi index e263a59d84b0..c98f36f95f3c 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -2078,7 +2078,7 @@ qusb2phy: phy@c012000 { sdhc2: mmc@c0a4900 { compatible =3D "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0x0c0a4900 0x314>, <0x0c0a4000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; =20 interrupts =3D , ; --=20 2.34.1 From nobody Sat Apr 18 21:02:47 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A371C433EF for ; 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[88.93.169.171]) by smtp.gmail.com with ESMTPSA id w15-20020a05651234cf00b00489e88d6a72sm737577lfr.198.2022.07.12.07.43.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jul 2022 07:43:04 -0700 (PDT) From: Krzysztof Kozlowski To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Bhupesh Sharma , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: Krzysztof Kozlowski , Douglas Anderson Subject: [PATCH v3 4/5] ARM: dts: qcom: align SDHCI reg-names with DT schema Date: Tue, 12 Jul 2022 16:42:44 +0200 Message-Id: <20220712144245.17417-5-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220712144245.17417-1-krzysztof.kozlowski@linaro.org> References: <20220712144245.17417-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" DT schema requires SDHCI reg names to be hc/core without "_mem" suffix, just like TXT bindings were expecting before the conversion. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Douglas Anderson Reviewed-by: Konrad Dybcio --- arch/arm/boot/dts/qcom-apq8084.dtsi | 4 ++-- arch/arm/boot/dts/qcom-ipq4019.dtsi | 1 + arch/arm/boot/dts/qcom-msm8226.dtsi | 6 +++--- arch/arm/boot/dts/qcom-msm8974.dtsi | 6 +++--- arch/arm/boot/dts/qcom-sdx65.dtsi | 2 +- 5 files changed, 10 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-a= pq8084.dtsi index 3e8bded2b5c8..45f3cbcf6238 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -422,7 +422,7 @@ blsp2_uart2: serial@f995e000 { mmc@f9824900 { compatible =3D "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0xf9824900 0x11c>, <0xf9824000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; clocks =3D <&gcc GCC_SDCC1_APPS_CLK>, @@ -435,7 +435,7 @@ mmc@f9824900 { mmc@f98a4900 { compatible =3D "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; clocks =3D <&gcc GCC_SDCC2_APPS_CLK>, diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-i= pq4019.dtsi index a2632349cec4..1b98764bab7a 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -224,6 +224,7 @@ vqmmc: regulator@1948000 { sdhci: mmc@7824900 { compatible =3D "qcom,sdhci-msm-v4"; reg =3D <0x7824900 0x11c>, <0x7824000 0x800>; + reg-names =3D "hc", "core"; interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; bus-width =3D <8>; diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-m= sm8226.dtsi index 0b5effdb269a..f711463d22dc 100644 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -137,7 +137,7 @@ apcs: syscon@f9011000 { sdhc_1: mmc@f9824900 { compatible =3D "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0xf9824900 0x11c>, <0xf9824000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; @@ -153,7 +153,7 @@ sdhc_1: mmc@f9824900 { sdhc_2: mmc@f98a4900 { compatible =3D "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; @@ -169,7 +169,7 @@ sdhc_2: mmc@f98a4900 { sdhc_3: mmc@f9864900 { compatible =3D "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0xf9864900 0x11c>, <0xf9864000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-m= sm8974.dtsi index 11b4206036e6..971eceaef3d1 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -439,7 +439,7 @@ acc3: clock-controller@f90b8000 { sdhc_1: mmc@f9824900 { compatible =3D "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0xf9824900 0x11c>, <0xf9824000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; @@ -456,7 +456,7 @@ sdhc_1: mmc@f9824900 { sdhc_3: mmc@f9864900 { compatible =3D "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0xf9864900 0x11c>, <0xf9864000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; @@ -475,7 +475,7 @@ sdhc_3: mmc@f9864900 { sdhc_2: mmc@f98a4900 { compatible =3D "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx= 65.dtsi index 7a193678b4f5..4f3389cb6300 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -334,7 +334,7 @@ glink-edge { sdhc_1: mmc@8804000 { compatible =3D "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; 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[88.93.169.171]) by smtp.gmail.com with ESMTPSA id w15-20020a05651234cf00b00489e88d6a72sm737577lfr.198.2022.07.12.07.43.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jul 2022 07:43:06 -0700 (PDT) From: Krzysztof Kozlowski To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Bhupesh Sharma , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: Krzysztof Kozlowski , Douglas Anderson Subject: [PATCH v3 5/5] ARM: dts: qcom: align SDHCI clocks with DT schema Date: Tue, 12 Jul 2022 16:42:45 +0200 Message-Id: <20220712144245.17417-6-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220712144245.17417-1-krzysztof.kozlowski@linaro.org> References: <20220712144245.17417-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The DT schema expects clocks iface-core order. No functional change. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Douglas Anderson Reviewed-by: Konrad Dybcio --- arch/arm/boot/dts/qcom-apq8084.dtsi | 12 ++++++------ arch/arm/boot/dts/qcom-ipq4019.dtsi | 4 ++-- arch/arm/boot/dts/qcom-msm8226.dtsi | 18 +++++++++--------- arch/arm/boot/dts/qcom-msm8974.dtsi | 18 +++++++++--------- arch/arm/boot/dts/qcom-msm8974pro.dtsi | 6 +++--- 5 files changed, 29 insertions(+), 29 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-a= pq8084.dtsi index 45f3cbcf6238..c887ac5cdd7d 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -425,10 +425,10 @@ mmc@f9824900 { reg-names =3D "hc", "core"; interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; - clocks =3D <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; status =3D "disabled"; }; =20 @@ -438,10 +438,10 @@ mmc@f98a4900 { reg-names =3D "hc", "core"; interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; - clocks =3D <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; status =3D "disabled"; }; =20 diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-i= pq4019.dtsi index 1b98764bab7a..a8a32a5e7e5d 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -228,9 +228,9 @@ sdhci: mmc@7824900 { interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; bus-width =3D <8>; - clocks =3D <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_DCD_XO_CLK>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; status =3D "disabled"; }; =20 diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-m= sm8226.dtsi index f711463d22dc..9d4223bf8fc1 100644 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -141,10 +141,10 @@ sdhc_1: mmc@f9824900 { interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; - clocks =3D <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; pinctrl-names =3D "default"; pinctrl-0 =3D <&sdhc1_default_state>; status =3D "disabled"; @@ -157,10 +157,10 @@ sdhc_2: mmc@f98a4900 { interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; - clocks =3D <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; pinctrl-names =3D "default"; pinctrl-0 =3D <&sdhc2_default_state>; status =3D "disabled"; @@ -173,10 +173,10 @@ sdhc_3: mmc@f9864900 { interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; - clocks =3D <&gcc GCC_SDCC3_APPS_CLK>, - <&gcc GCC_SDCC3_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC3_AHB_CLK>, + <&gcc GCC_SDCC3_APPS_CLK>, <&xo_board>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; pinctrl-names =3D "default"; pinctrl-0 =3D <&sdhc3_default_state>; status =3D "disabled"; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-m= sm8974.dtsi index 971eceaef3d1..1f4baa6ac64d 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -443,10 +443,10 @@ sdhc_1: mmc@f9824900 { interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; - clocks =3D <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; bus-width =3D <8>; non-removable; =20 @@ -460,10 +460,10 @@ sdhc_3: mmc@f9864900 { interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; - clocks =3D <&gcc GCC_SDCC3_APPS_CLK>, - <&gcc GCC_SDCC3_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC3_AHB_CLK>, + <&gcc GCC_SDCC3_APPS_CLK>, <&xo_board>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; bus-width =3D <4>; =20 #address-cells =3D <1>; @@ -479,10 +479,10 @@ sdhc_2: mmc@f98a4900 { interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; - clocks =3D <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; bus-width =3D <4>; =20 #address-cells =3D <1>; diff --git a/arch/arm/boot/dts/qcom-msm8974pro.dtsi b/arch/arm/boot/dts/qco= m-msm8974pro.dtsi index 1e882e16a221..58df6e75ab6d 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974pro.dtsi @@ -10,10 +10,10 @@ &gpu { }; =20 &sdhc_1 { - clocks =3D <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>, <&gcc GCC_SDCC1_CDCCAL_FF_CLK>, <&gcc GCC_SDCC1_CDCCAL_SLEEP_CLK>; - clock-names =3D "core", "iface", "xo", "cal", "sleep"; + clock-names =3D "iface", "core", "xo", "cal", "sleep"; }; --=20 2.34.1