From nobody Sat Apr 25 11:48:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 228C3C433EF for ; Tue, 12 Jul 2022 14:26:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230172AbiGLO0X (ORCPT ); Tue, 12 Jul 2022 10:26:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42580 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233541AbiGLO0J (ORCPT ); Tue, 12 Jul 2022 10:26:09 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E26C3AAB23; Tue, 12 Jul 2022 07:26:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1657635968; x=1689171968; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UGvCmSdLGhHwliGLCezI146iFxUX+rnhWkr8xC90Ykk=; b=S//76q8XD4x9KvIngqdT4FSMn1FxIr1xMs6l9ibX2ye9Ke5nxpW37LIe 313uHujmrKiJZIkZDVk5Opm3Li1Qc99udFAzwQ0z8QatxXSmnyGl6F7aY Sh5h37KZMWH90Kk5F2a0PJAXdFp7CcTXUiGZTCC+zXi/BZi0ohSpZ6+ck WRiiyVutIENlNRRRB23eHb/AfxfM34303AjKrgOLr4AIHZsb7Fw3Dv29W CbznXgqIq7281dj5kinTacwStjhcoRkCEdbgDM+1O0qlJy9W5//TaXPCs XvKQ4gIl5MqCtXvWqi51MHQYLcZr+tQg6ZU5sC1ex5/L9W9RjylXomr7x g==; X-IronPort-AV: E=Sophos;i="5.92,265,1650956400"; d="scan'208";a="181795577" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 12 Jul 2022 07:26:08 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 12 Jul 2022 07:26:08 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 12 Jul 2022 07:26:05 -0700 From: Conor Dooley To: Thierry Reding , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , "Lee Jones" , Rob Herring , "Krzysztof Kozlowski" CC: Daire McNamara , , , , , Conor Dooley , Rob Herring Subject: [PATCH v6 1/4] dt-bindings: pwm: fix microchip corePWM's pwm-cells Date: Tue, 12 Jul 2022 15:25:54 +0100 Message-ID: <20220712142557.1773075-2-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220712142557.1773075-1-conor.dooley@microchip.com> References: <20220712142557.1773075-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" corePWM is capable of inverted operation but the binding requires \#pwm-cells of 2. Expand the binding to support setting the polarity. Fixes: df77f7735786 ("dt-bindings: pwm: add microchip corepwm binding") Acked-by: Rob Herring Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml b= /Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml index a7fae1772a81..cd8e9a8907f8 100644 --- a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml +++ b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml @@ -30,7 +30,9 @@ properties: maxItems: 1 =20 "#pwm-cells": - const: 2 + enum: [2, 3] + description: + The only flag supported by the controller is PWM_POLARITY_INVERTED. =20 microchip,sync-update-mask: description: | --=20 2.36.1 From nobody Sat Apr 25 11:48:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 800C7CCA47C for ; Tue, 12 Jul 2022 14:26:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229605AbiGLO0Z (ORCPT ); Tue, 12 Jul 2022 10:26:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42640 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233185AbiGLO0M (ORCPT ); Tue, 12 Jul 2022 10:26:12 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 29CF3B8E82; Tue, 12 Jul 2022 07:26:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1657635973; x=1689171973; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=E7lc4EnKiZ1cJys8i7k2b1wZuaqqZKmkVBwqdNfKks0=; b=fBXEJbj6BGsqVQCuqb7+PXHfoaAsi78QRz9+h/tLIG7bG5EwRVVU+weU FR56kax1X1/juBSQaXOWsVdDn+yg0x9ls6GhuwUn375VWMoaBOhDf/Bwm YKAU7ZH/cYZiLf8zgcEE5Dn9y1gQXE54aBVgOZGvUBAJhEDQFmfptOsz2 ITbkJ7bTmQq0izHOEaWWI/xzZE6Ygfjzj3r1UPETn5uaxb5vIL1ivXz7i Az+kEb3ppavlUnJ5QPW0Rq4+aoGwFUqFIbHeWcB6DY9iyfbQPkpNq848F oTgUYrS3L/ZvsEr1qZdz6E/VPoK0vOJe9l4OsRmUoDyarQ8Bb2QcA4KLy w==; X-IronPort-AV: E=Sophos;i="5.92,265,1650956400"; d="scan'208";a="164369598" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 12 Jul 2022 07:26:12 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 12 Jul 2022 07:26:11 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 12 Jul 2022 07:26:08 -0700 From: Conor Dooley To: Thierry Reding , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , "Lee Jones" , Rob Herring , "Krzysztof Kozlowski" CC: Daire McNamara , , , , , Conor Dooley Subject: [PATCH v6 2/4] riscv: dts: fix the icicle's #pwm-cells Date: Tue, 12 Jul 2022 15:25:55 +0100 Message-ID: <20220712142557.1773075-3-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220712142557.1773075-1-conor.dooley@microchip.com> References: <20220712142557.1773075-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" \#pwm-cells for the Icicle kit's fabric PWM was incorrectly set to 2 & blindly overridden by the (out of tree) driver anyway. The core can support inverted operation, so update the entry to correctly report its capabilities. Fixes: 72560c6559b8 ("riscv: dts: microchip: add fpga fabric section to ici= cle kit") Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index 0d28858b83f2..e09a13aef268 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -8,7 +8,7 @@ core_pwm0: pwm@41000000 { compatible =3D "microchip,corepwm-rtl-v4"; reg =3D <0x0 0x41000000 0x0 0xF0>; microchip,sync-update-mask =3D /bits/ 32 <0>; - #pwm-cells =3D <2>; + #pwm-cells =3D <3>; clocks =3D <&fabric_clk3>; status =3D "disabled"; }; --=20 2.36.1 From nobody Sat Apr 25 11:48:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8097ECCA482 for ; Tue, 12 Jul 2022 14:26:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233216AbiGLO0n (ORCPT ); Tue, 12 Jul 2022 10:26:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233409AbiGLO0Y (ORCPT ); Tue, 12 Jul 2022 10:26:24 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8102EB8E9E; Tue, 12 Jul 2022 07:26:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1657635974; x=1689171974; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=keWZD2CM+I+EqbORMqNyqkX1JtbHW+MvxGOb+wsJqi0=; b=IVyBplCliDgOFPxvOoEVO++CGUwcx3IZc7+6fKeDoRYe1TeuQ8AX4Vjr Xus8hHN83IbTljhsSl0p11A1hle4EX+DkYnLKfy0AMwgfQt5EnhKr+8pH C/o1ELQ1MbzFLvMlaCk+lLnIH/uTdC6pDtUW8XYzkkhjYRws5BQthCKdF iUx5m9KrsNPDmQbHFjTfIM9k6STSNgnQG434FW2MnfLhdf3PxesM3Oe3A RsD13ASegHaM0xSQiLucvNZnBK39QF9ceGNY1iW0gR4NgKTxH2Joho4n7 ibMjXLuAmzkxs/i+1V/Y5zPWtFOiLSxPMAyahVXG9K16BuwOIMHkhqbcG Q==; X-IronPort-AV: E=Sophos;i="5.92,265,1650956400"; d="scan'208";a="172054810" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 12 Jul 2022 07:26:13 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 12 Jul 2022 07:26:13 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 12 Jul 2022 07:26:11 -0700 From: Conor Dooley To: Thierry Reding , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , "Lee Jones" , Rob Herring , "Krzysztof Kozlowski" CC: Daire McNamara , , , , , Conor Dooley Subject: [PATCH v6 3/4] pwm: add microchip soft ip corePWM driver Date: Tue, 12 Jul 2022 15:25:56 +0100 Message-ID: <20220712142557.1773075-4-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220712142557.1773075-1-conor.dooley@microchip.com> References: <20220712142557.1773075-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a driver that supports the Microchip FPGA "soft" PWM IP core. Signed-off-by: Conor Dooley --- drivers/pwm/Kconfig | 10 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-microchip-core.c | 370 +++++++++++++++++++++++++++++++ 3 files changed, 381 insertions(+) create mode 100644 drivers/pwm/pwm-microchip-core.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 904de8d61828..007ea5750e73 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -383,6 +383,16 @@ config PWM_MEDIATEK To compile this driver as a module, choose M here: the module will be called pwm-mediatek. =20 +config PWM_MICROCHIP_CORE + tristate "Microchip corePWM PWM support" + depends on SOC_MICROCHIP_POLARFIRE || COMPILE_TEST + depends on HAS_IOMEM && OF + help + PWM driver for Microchip FPGA soft IP core. + + To compile this driver as a module, choose M here: the module + will be called pwm-microchip-core. + config PWM_MXS tristate "Freescale MXS PWM support" depends on ARCH_MXS || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 5c08bdb817b4..43feb7cfc66a 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_PWM_LPSS_PCI) +=3D pwm-lpss-pci.o obj-$(CONFIG_PWM_LPSS_PLATFORM) +=3D pwm-lpss-platform.o obj-$(CONFIG_PWM_MESON) +=3D pwm-meson.o obj-$(CONFIG_PWM_MEDIATEK) +=3D pwm-mediatek.o +obj-$(CONFIG_PWM_MICROCHIP_CORE) +=3D pwm-microchip-core.o obj-$(CONFIG_PWM_MTK_DISP) +=3D pwm-mtk-disp.o obj-$(CONFIG_PWM_MXS) +=3D pwm-mxs.o obj-$(CONFIG_PWM_NTXEC) +=3D pwm-ntxec.o diff --git a/drivers/pwm/pwm-microchip-core.c b/drivers/pwm/pwm-microchip-c= ore.c new file mode 100644 index 000000000000..3e28868ee499 --- /dev/null +++ b/drivers/pwm/pwm-microchip-core.c @@ -0,0 +1,370 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * corePWM driver for Microchip "soft" FPGA IP cores. + * + * Copyright (c) 2021-2022 Microchip Corporation. All rights reserved. + * Author: Conor Dooley + * Documentation: + * https://www.microsemi.com/document-portal/doc_download/1245275-corepwm-= hb + * + * Limitations: + * - If the IP block is configured without "shadow registers", all register + * writes will take effect immediately, causing glitches on the output. + * If shadow registers *are* enabled, a write to the "SYNC_UPDATE" regis= ter + * notifies the core that it needs to update the registers defining the + * waveform from the contents of the "shadow registers". + * - The IP block has no concept of a duty cycle, only rising/falling edge= s of + * the waveform. Unfortunately, if the rising & falling edges registers = have + * the same value written to them the IP block will do whichever of a ri= sing + * or a falling edge is possible. I.E. a 50% waveform at twice the reque= sted + * period. Therefore to get a 0% waveform, the output is set the max hig= h/low + * time depending on polarity. + * - The PWM period is set for the whole IP block not per channel. The dri= ver + * will only change the period if no other PWM output is enabled. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PREG_TO_VAL(PREG) ((PREG) + 1) + +#define MCHPCOREPWM_PRESCALE_MAX 0x100 +#define MCHPCOREPWM_PERIOD_STEPS_MAX 0xff +#define MCHPCOREPWM_PERIOD_MAX 0xff00 + +#define MCHPCOREPWM_PRESCALE 0x00 +#define MCHPCOREPWM_PERIOD 0x04 +#define MCHPCOREPWM_EN(i) (0x08 + 0x04 * (i)) /* 0x08, 0x0c */ +#define MCHPCOREPWM_POSEDGE(i) (0x10 + 0x08 * (i)) /* 0x10, 0x18, ..., 0x8= 8 */ +#define MCHPCOREPWM_NEGEDGE(i) (0x14 + 0x08 * (i)) /* 0x14, 0x1c, ..., 0x8= c */ +#define MCHPCOREPWM_SYNC_UPD 0xe4 + +struct mchp_core_pwm_chip { + struct pwm_chip chip; + struct clk *clk; + struct mutex lock; /* protect the shared period */ + void __iomem *base; + u32 sync_update_mask; + u16 channel_enabled; +}; + +static inline struct mchp_core_pwm_chip *to_mchp_core_pwm(struct pwm_chip = *chip) +{ + return container_of(chip, struct mchp_core_pwm_chip, chip); +} + +static void mchp_core_pwm_enable(struct pwm_chip *chip, struct pwm_device = *pwm, + bool enable, u64 period) +{ + struct mchp_core_pwm_chip *mchp_core_pwm =3D to_mchp_core_pwm(chip); + u8 channel_enable, reg_offset, shift; + + /* + * There are two adjacent 8 bit control regs, the lower reg controls + * 0-7 and the upper reg 8-15. Check if the pwm is in the upper reg + * and if so, offset by the bus width. + */ + reg_offset =3D MCHPCOREPWM_EN(pwm->hwpwm >> 3); + shift =3D pwm->hwpwm & 7; + + channel_enable =3D readb_relaxed(mchp_core_pwm->base + reg_offset); + channel_enable &=3D ~(1 << shift); + channel_enable |=3D (enable << shift); + + writel_relaxed(channel_enable, mchp_core_pwm->base + reg_offset); + mchp_core_pwm->channel_enabled &=3D ~BIT(pwm->hwpwm); + mchp_core_pwm->channel_enabled |=3D enable << pwm->hwpwm; + + /* + * Notify the block to update the waveform from the shadow registers. + * The updated values will not appear on the bus until they have been + * applied to the waveform at the beginning of the next period. We must + * write these registers and wait for them to be applied before calling + * enable(). + */ + if (mchp_core_pwm->sync_update_mask & (1 << pwm->hwpwm)) { + writel_relaxed(1U, mchp_core_pwm->base + MCHPCOREPWM_SYNC_UPD); + usleep_range(period, period * 2); + } +} + +static u64 mchp_core_pwm_calc_duty(struct pwm_chip *chip, struct pwm_devic= e *pwm, + const struct pwm_state *state, u8 prescale, u8 period_steps) +{ + struct mchp_core_pwm_chip *mchp_core_pwm =3D to_mchp_core_pwm(chip); + u64 duty_steps, period, tmp; + u16 prescale_val =3D PREG_TO_VAL(prescale); + u8 period_steps_val =3D PREG_TO_VAL(period_steps); + + period =3D period_steps_val * prescale_val * NSEC_PER_SEC; + period =3D DIV64_U64_ROUND_UP(period, clk_get_rate(mchp_core_pwm->clk)); + + /* + * Calculate the duty cycle in multiples of the prescaled period: + * duty_steps =3D duty_in_ns / step_in_ns + * step_in_ns =3D (prescale * NSEC_PER_SEC) / clk_rate + * The code below is rearranged slightly to only divide once. + */ + duty_steps =3D state->duty_cycle * clk_get_rate(mchp_core_pwm->clk); + tmp =3D prescale_val * NSEC_PER_SEC; + return div64_u64(duty_steps, tmp); +} + +static void mchp_core_pwm_apply_duty(struct pwm_chip *chip, struct pwm_dev= ice *pwm, + const struct pwm_state *state, u64 duty_steps, u8 period_steps) +{ + struct mchp_core_pwm_chip *mchp_core_pwm =3D to_mchp_core_pwm(chip); + u8 posedge, negedge; + u8 period_steps_val =3D PREG_TO_VAL(period_steps); + + /* + * Turn the output on unless posedge =3D=3D negedge, in which case the + * duty is intended to be 0, but limitations of the IP block don't + * allow a zero length duty cycle - so just set the max high/low time + * respectively. + */ + if (state->polarity =3D=3D PWM_POLARITY_INVERSED) { + negedge =3D !duty_steps ? period_steps_val : 0u; + posedge =3D duty_steps; + } else { + posedge =3D !duty_steps ? period_steps_val : 0u; + negedge =3D duty_steps; + } + + writel_relaxed(posedge, mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hw= pwm)); + writel_relaxed(negedge, mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hw= pwm)); +} + +static int mchp_core_pwm_calc_period(struct pwm_chip *chip, const struct p= wm_state *state, + u8 *prescale, u8 *period_steps) +{ + struct mchp_core_pwm_chip *mchp_core_pwm =3D to_mchp_core_pwm(chip); + u64 tmp, clk_rate; + + /* + * Calculate the period cycles and prescale values. + * The registers are each 8 bits wide & multiplied to compute the period + * using the formula: + * (clock_period) * (prescale + 1) * (period_steps + 1) + * so the maximum period that can be generated is 0x10000 times the + * period of the input clock. + * However, due to the design of the "hardware", it is not possible to + * attain a 100% duty cycle if the full range of period_steps is used. + * Therefore period_steps is restricted to 0xFE and the maximum multiple + * of the clock period attainable is 0xFF00. + */ + clk_rate =3D clk_get_rate(mchp_core_pwm->clk); + + /* + * If clk_rate is too big, the following multiplication might overflow. + * However this is implausible, as the fabric of current FPGAs cannot + * provide clocks at a rate high enough. + */ + if (clk_rate >=3D NSEC_PER_SEC) + return -EINVAL; + + tmp =3D mul_u64_u64_div_u64(state->period, clk_rate, NSEC_PER_SEC); + + if (tmp >=3D MCHPCOREPWM_PERIOD_MAX) { + *prescale =3D MCHPCOREPWM_PRESCALE_MAX - 1; + *period_steps =3D MCHPCOREPWM_PERIOD_STEPS_MAX - 1; + return 0; + } + + *prescale =3D div_u64(tmp, MCHPCOREPWM_PERIOD_STEPS_MAX); + /* PREG_TO_VAL() can produce a value larger than UINT8_MAX */ + *period_steps =3D div_u64(tmp, PREG_TO_VAL((u32)*prescale)) - 1; + + return 0; +} + +static inline void mchp_core_pwm_apply_period(struct mchp_core_pwm_chip *m= chp_core_pwm, + u8 prescale, u8 period_steps) +{ + writel_relaxed(prescale, mchp_core_pwm->base + MCHPCOREPWM_PRESCALE); + writel_relaxed(period_steps, mchp_core_pwm->base + MCHPCOREPWM_PERIOD); +} + +static int mchp_core_pwm_apply(struct pwm_chip *chip, struct pwm_device *p= wm, + const struct pwm_state *state) +{ + struct mchp_core_pwm_chip *mchp_core_pwm =3D to_mchp_core_pwm(chip); + struct pwm_state current_state =3D pwm->state; + bool period_locked; + u64 duty_steps; + u16 channel_enabled; + u8 prescale, period_steps, hw_prescale, hw_period_steps; + int ret; + + mutex_lock_interruptible(&mchp_core_pwm->lock); + + if (!state->enabled) { + mchp_core_pwm_enable(chip, pwm, false, current_state.period); + mutex_unlock(&mchp_core_pwm->lock); + return 0; + } + + /* + * If the only thing that has changed is the duty cycle or the polarity, + * we can shortcut the calculations and just compute/apply the new duty + * cycle pos & neg edges + * As all the channels share the same period, do not allow it to be + * changed if any other channels are enabled. + * If the period is locked, it may not be possible to use a period + * less than that requested. In that case, we just abort. + */ + period_locked =3D mchp_core_pwm->channel_enabled & ~(1 << pwm->hwpwm); + + if (period_locked) { + mchp_core_pwm_calc_period(chip, state, &prescale, &period_steps); + hw_prescale =3D readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE= ); + hw_period_steps =3D readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERI= OD); + + if ((period_steps * prescale) < (hw_period_steps * hw_prescale)) { + mutex_unlock(&mchp_core_pwm->lock); + return -EINVAL; + } + + prescale =3D hw_prescale; + period_steps =3D hw_period_steps; + } else if (!current_state.enabled || current_state.period !=3D state->per= iod) { + ret =3D mchp_core_pwm_calc_period(chip, state, &prescale, &period_steps); + if (ret) { + mutex_unlock(&mchp_core_pwm->lock); + return ret; + } + mchp_core_pwm_apply_period(mchp_core_pwm, prescale, period_steps); + } else { + prescale =3D readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE); + period_steps =3D readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD); + } + + duty_steps =3D mchp_core_pwm_calc_duty(chip, pwm, state, prescale, period= _steps); + + /* + * Because the period is per channel, it is possible that the requested + * duty cycle is longer than the period, in which case cap it to the + * period, IOW a 100% duty cycle. + */ + if (duty_steps > period_steps) + duty_steps =3D period_steps + 1; + + mchp_core_pwm_apply_duty(chip, pwm, state, duty_steps, period_steps); + + mchp_core_pwm_enable(chip, pwm, true, state->period); + + mutex_unlock(&mchp_core_pwm->lock); + + return 0; +} + +static void mchp_core_pwm_get_state(struct pwm_chip *chip, struct pwm_devi= ce *pwm, + struct pwm_state *state) +{ + struct mchp_core_pwm_chip *mchp_core_pwm =3D to_mchp_core_pwm(chip); + u16 prescale; + u8 period_steps, duty_steps, posedge, negedge; + u16 channel_enabled; + + mutex_lock_interruptible(&mchp_core_pwm->lock); + + channel_enabled =3D mchp_core_pwm->channel_enabled; + + if (channel_enabled & (1 << pwm->hwpwm)) + state->enabled =3D true; + else + state->enabled =3D false; + + prescale =3D PREG_TO_VAL(readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_= PRESCALE)); + + period_steps =3D PREG_TO_VAL(readb_relaxed(mchp_core_pwm->base + MCHPCORE= PWM_PERIOD)); + state->period =3D period_steps * prescale * NSEC_PER_SEC; + state->period =3D DIV64_U64_ROUND_UP(state->period, clk_get_rate(mchp_cor= e_pwm->clk)); + + posedge =3D readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->= hwpwm)); + negedge =3D readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->= hwpwm)); + + if (negedge =3D=3D posedge) { + state->duty_cycle =3D state->period / 2; + } else { + duty_steps =3D abs((s16)posedge - (s16)negedge); + state->duty_cycle =3D duty_steps * prescale * NSEC_PER_SEC; + state->duty_cycle =3D DIV64_U64_ROUND_UP(state->duty_cycle, + clk_get_rate(mchp_core_pwm->clk)); + } + + state->polarity =3D negedge < posedge ? PWM_POLARITY_INVERSED : PWM_POLAR= ITY_NORMAL; + + mutex_unlock(&mchp_core_pwm->lock); +} + +static const struct pwm_ops mchp_core_pwm_ops =3D { + .apply =3D mchp_core_pwm_apply, + .get_state =3D mchp_core_pwm_get_state, + .owner =3D THIS_MODULE, +}; + +static const struct of_device_id mchp_core_of_match[] =3D { + { + .compatible =3D "microchip,corepwm-rtl-v4", + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, mchp_core_of_match); + +static int mchp_core_pwm_probe(struct platform_device *pdev) +{ + struct mchp_core_pwm_chip *mchp_pwm; + struct resource *regs; + int ret; + + mchp_pwm =3D devm_kzalloc(&pdev->dev, sizeof(*mchp_pwm), GFP_KERNEL); + if (!mchp_pwm) + return -ENOMEM; + + mchp_pwm->base =3D devm_platform_get_and_ioremap_resource(pdev, 0, ®s); + if (IS_ERR(mchp_pwm->base)) + return PTR_ERR(mchp_pwm->base); + + mchp_pwm->clk =3D devm_clk_get_enabled(&pdev->dev, NULL); + if (IS_ERR(mchp_pwm->clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(mchp_pwm->clk), + "failed to get PWM clock\n"); + + if (of_property_read_u32(pdev->dev.of_node, "microchip,sync-update-mask", + &mchp_pwm->sync_update_mask)) + mchp_pwm->sync_update_mask =3D 0u; + + mutex_init(&mchp_pwm->lock); + + mchp_pwm->chip.dev =3D &pdev->dev; + mchp_pwm->chip.ops =3D &mchp_core_pwm_ops; + mchp_pwm->chip.npwm =3D 16; + + ret =3D devm_pwmchip_add(&pdev->dev, &mchp_pwm->chip); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n"); + + return 0; +} + +static struct platform_driver mchp_core_pwm_driver =3D { + .driver =3D { + .name =3D "mchp-core-pwm", + .of_match_table =3D mchp_core_of_match, + }, + .probe =3D mchp_core_pwm_probe, +}; +module_platform_driver(mchp_core_pwm_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Conor Dooley "); +MODULE_DESCRIPTION("corePWM driver for Microchip FPGAs"); --=20 2.36.1 From nobody Sat Apr 25 11:48:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F19EBC43334 for ; Tue, 12 Jul 2022 14:27:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233045AbiGLO06 (ORCPT ); Tue, 12 Jul 2022 10:26:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43490 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233308AbiGLO0d (ORCPT ); Tue, 12 Jul 2022 10:26:33 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2142DB93C9; Tue, 12 Jul 2022 07:26:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1657635978; x=1689171978; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0L9J2eXxRU3T3ZDdzxJjwk06pdsoufFKChVyEazSj6I=; b=EH0eAnjCqFzDJuF6HIcqqZQN1Z8Nv8KZsGa3iz+XapXOd5Aj0YnbYrLb y71Rha4fpA2n9uYYw9PQ6mXTaQrllHM8ZmEI5VTcglProTQey90258TKO 0/SkmOjXcSDYVhIxQrT61CYJaGwbR9fQg4YClYzGArOip5I8SFTWPZonC CaONlljf5k59yfWRv8eVW7JD8xs+P/+PK1J7DevMD6LAwovsX5NsnGTNK q1fNGalqBecEh0S6LUPg9ys1LMslwubEvSZ1qYCLA30f/de+FOl1BYO9p q2i7E4dqh7Az9BRV6cuXqz8UliT3B1yetNGfKhOrYVj2YeoIBT5blvId1 g==; X-IronPort-AV: E=Sophos;i="5.92,265,1650956400"; d="scan'208";a="171772480" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 12 Jul 2022 07:26:17 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 12 Jul 2022 07:26:15 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 12 Jul 2022 07:26:13 -0700 From: Conor Dooley To: Thierry Reding , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , "Lee Jones" , Rob Herring , "Krzysztof Kozlowski" CC: Daire McNamara , , , , , Conor Dooley Subject: [PATCH v6 4/4] MAINTAINERS: add pwm to PolarFire SoC entry Date: Tue, 12 Jul 2022 15:25:57 +0100 Message-ID: <20220712142557.1773075-5-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220712142557.1773075-1-conor.dooley@microchip.com> References: <20220712142557.1773075-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the newly introduced pwm driver to the existing PolarFire SoC entry. Signed-off-by: Conor Dooley --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index b5aeaddc9539..99f490a19850 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17468,6 +17468,7 @@ F: drivers/char/hw_random/mpfs-rng.c F: drivers/clk/microchip/clk-mpfs.c F: drivers/mailbox/mailbox-mpfs.c F: drivers/pci/controller/pcie-microchip-host.c +F: drivers/pwm/pwm-microchip-core.c F: drivers/rtc/rtc-mpfs.c F: drivers/soc/microchip/ F: drivers/spi/spi-microchip-core.c --=20 2.36.1