From nobody Thu Nov 14 19:01:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88ACBCCA481 for ; Tue, 12 Jul 2022 11:41:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232696AbiGLLlE (ORCPT ); Tue, 12 Jul 2022 07:41:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232450AbiGLLk5 (ORCPT ); Tue, 12 Jul 2022 07:40:57 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E9F55AD869; Tue, 12 Jul 2022 04:40:56 -0700 (PDT) X-UUID: 86ed2cb90ec942c3b19ff326f5da30c0-20220712 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8,REQID:e1b7f79f-4d28-41ee-a896-694e5f9625c3,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:0f94e32,CLOUDID:1fec1364-0b3f-4b2c-b3a6-ed5c044366a0,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: 86ed2cb90ec942c3b19ff326f5da30c0-20220712 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1580148463; Tue, 12 Jul 2022 19:40:51 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Tue, 12 Jul 2022 19:40:50 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Tue, 12 Jul 2022 19:40:50 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Allen-KH Cheng Subject: [PATCH v3 3/5] arm64: dts: mediatek: Add mmsys #reset-cells property for mt8192 Date: Tue, 12 Jul 2022 19:40:44 +0800 Message-ID: <20220712114046.15574-4-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220712114046.15574-1-allen-kh.cheng@mediatek.com> References: <20220712114046.15574-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To support reset of mmsys, we include mt8192-resets.h and add property of #reset-cells in mmsys. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: N=C3=ADcolas F. R. A. Prado --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index a789b7c9b2af..a997f34cc3ad 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include =20 / { compatible =3D "mediatek,mt8192"; @@ -1187,6 +1188,7 @@ compatible =3D "mediatek,mt8192-mmsys", "syscon"; reg =3D <0 0x14000000 0 0x1000>; #clock-cells =3D <1>; + #reset-cells =3D <1>; }; =20 smi_common: smi@14002000 { --=20 2.18.0