From nobody Sat Sep 21 20:14:10 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87A2BC433EF for ; Tue, 12 Jul 2022 11:41:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232535AbiGLLlC (ORCPT ); Tue, 12 Jul 2022 07:41:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53882 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229776AbiGLLk5 (ORCPT ); Tue, 12 Jul 2022 07:40:57 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F364AE3B5; Tue, 12 Jul 2022 04:40:55 -0700 (PDT) X-UUID: bf2ecc7ab87e4c6c800991a993183c50-20220712 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8,REQID:07db0141-8100-4428-8579-9f4334fdb2ea,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:-5 X-CID-META: VersionHash:0f94e32,CLOUDID:f6eb1364-0b3f-4b2c-b3a6-ed5c044366a0,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: bf2ecc7ab87e4c6c800991a993183c50-20220712 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1856221612; Tue, 12 Jul 2022 19:40:50 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Tue, 12 Jul 2022 19:40:49 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Tue, 12 Jul 2022 19:40:48 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Allen-KH Cheng Subject: [PATCH v3 1/5] arm64: dts: mt8192: Add pwm node Date: Tue, 12 Jul 2022 19:40:42 +0800 Message-ID: <20220712114046.15574-2-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220712114046.15574-1-allen-kh.cheng@mediatek.com> References: <20220712114046.15574-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add pwm node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: N=C3=ADcolas F. R. A. Prado Tested-by: Chen-Yu Tsai Tested-by: N=C3=ADcolas F. R. A. Prado --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index cbae5a5ee4a0..731bdc665b94 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -599,6 +599,17 @@ status =3D "disabled"; }; =20 + pwm0: pwm@1100e000 { + compatible =3D "mediatek,mt8183-disp-pwm"; + reg =3D <0 0x1100e000 0 0x1000>; + interrupts =3D ; + #pwm-cells =3D <2>; + clocks =3D <&topckgen CLK_TOP_DISP_PWM_SEL>, + <&infracfg CLK_INFRA_DISP_PWM>; + clock-names =3D "main", "mm"; + status =3D "disabled"; + }; + spi1: spi@11010000 { compatible =3D "mediatek,mt8192-spi", "mediatek,mt6765-spi"; --=20 2.18.0 From nobody Sat Sep 21 20:14:10 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5FDF0C43334 for ; Tue, 12 Jul 2022 11:41:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232697AbiGLLlI (ORCPT ); Tue, 12 Jul 2022 07:41:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53900 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232503AbiGLLk6 (ORCPT ); Tue, 12 Jul 2022 07:40:58 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0E9D9ADD55; Tue, 12 Jul 2022 04:40:56 -0700 (PDT) X-UUID: 27729a2c025549359d3fd21fdbfb52ad-20220712 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8,REQID:c12c0dbc-a6d5-46bb-a02a-ea69bff460c6,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:0f94e32,CLOUDID:d42d46d7-5d6d-4eaf-a635-828a3ee48b7c,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: 27729a2c025549359d3fd21fdbfb52ad-20220712 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1856016484; Tue, 12 Jul 2022 19:40:50 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Tue, 12 Jul 2022 19:40:49 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Tue, 12 Jul 2022 19:40:49 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Allen-KH Cheng Subject: [PATCH v3 2/5] arm64: dts: mt8192: Add mipi_tx node Date: Tue, 12 Jul 2022 19:40:43 +0800 Message-ID: <20220712114046.15574-3-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220712114046.15574-1-allen-kh.cheng@mediatek.com> References: <20220712114046.15574-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add mipi_tx node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: N=C3=ADcolas F. R. A. Prado Tested-by: Chen-Yu Tsai Tested-by: N=C3=ADcolas F. R. A. Prado --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 731bdc665b94..a789b7c9b2af 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1095,6 +1095,16 @@ }; }; =20 + mipi_tx0: dsi-phy@11e50000 { + compatible =3D "mediatek,mt8183-mipi-tx"; + reg =3D <0 0x11e50000 0 0x1000>; + clocks =3D <&apmixedsys CLK_APMIXED_MIPID26M>; + #clock-cells =3D <0>; + #phy-cells =3D <0>; + clock-output-names =3D "mipi_tx0_pll"; + status =3D "disabled"; + }; + i2c0: i2c@11f00000 { compatible =3D "mediatek,mt8192-i2c"; reg =3D <0 0x11f00000 0 0x1000>, --=20 2.18.0 From nobody Sat Sep 21 20:14:10 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88ACBCCA481 for ; Tue, 12 Jul 2022 11:41:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232696AbiGLLlE (ORCPT ); Tue, 12 Jul 2022 07:41:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232450AbiGLLk5 (ORCPT ); Tue, 12 Jul 2022 07:40:57 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E9F55AD869; Tue, 12 Jul 2022 04:40:56 -0700 (PDT) X-UUID: 86ed2cb90ec942c3b19ff326f5da30c0-20220712 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8,REQID:e1b7f79f-4d28-41ee-a896-694e5f9625c3,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:0f94e32,CLOUDID:1fec1364-0b3f-4b2c-b3a6-ed5c044366a0,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: 86ed2cb90ec942c3b19ff326f5da30c0-20220712 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1580148463; Tue, 12 Jul 2022 19:40:51 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Tue, 12 Jul 2022 19:40:50 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Tue, 12 Jul 2022 19:40:50 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Allen-KH Cheng Subject: [PATCH v3 3/5] arm64: dts: mediatek: Add mmsys #reset-cells property for mt8192 Date: Tue, 12 Jul 2022 19:40:44 +0800 Message-ID: <20220712114046.15574-4-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220712114046.15574-1-allen-kh.cheng@mediatek.com> References: <20220712114046.15574-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To support reset of mmsys, we include mt8192-resets.h and add property of #reset-cells in mmsys. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: N=C3=ADcolas F. R. A. Prado Tested-by: Chen-Yu Tsai Tested-by: N=C3=ADcolas F. R. A. Prado --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index a789b7c9b2af..a997f34cc3ad 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include =20 / { compatible =3D "mediatek,mt8192"; @@ -1187,6 +1188,7 @@ compatible =3D "mediatek,mt8192-mmsys", "syscon"; reg =3D <0 0x14000000 0 0x1000>; #clock-cells =3D <1>; + #reset-cells =3D <1>; }; =20 smi_common: smi@14002000 { --=20 2.18.0 From nobody Sat Sep 21 20:14:10 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E658C433EF for ; Tue, 12 Jul 2022 11:41:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232731AbiGLLlR (ORCPT ); Tue, 12 Jul 2022 07:41:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53962 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232314AbiGLLlA (ORCPT ); Tue, 12 Jul 2022 07:41:00 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 21686AD869; Tue, 12 Jul 2022 04:40:57 -0700 (PDT) X-UUID: 9241ccb2893b4ba2b60ffb7342ae2628-20220712 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8,REQID:7a9c118b-7cad-414f-aa34-6f12c54b3f65,OB:10,L OB:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,AC TION:release,TS:95 X-CID-INFO: VERSION:1.1.8,REQID:7a9c118b-7cad-414f-aa34-6f12c54b3f65,OB:10,LOB :0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,AC TION:quarantine,TS:95 X-CID-META: VersionHash:0f94e32,CLOUDID:f42d46d7-5d6d-4eaf-a635-828a3ee48b7c,C OID:44b38631aa1e,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: 9241ccb2893b4ba2b60ffb7342ae2628-20220712 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 23568853; Tue, 12 Jul 2022 19:40:52 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Tue, 12 Jul 2022 19:40:51 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Tue, 12 Jul 2022 19:40:51 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , Chen-Yu Tsai , Allen-KH Cheng Subject: [PATCH v3 4/5] arm64: dts: mt8192: Add display nodes Date: Tue, 12 Jul 2022 19:40:45 +0800 Message-ID: <20220712114046.15574-5-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220712114046.15574-1-allen-kh.cheng@mediatek.com> References: <20220712114046.15574-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add display nodes and gce info for mt8192 SoC. GCE (Global Command Engine) properties to the display nodes in order to enable the usage of the CMDQ (Command Queue), which is required for operating the display. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: N=C3=ADcolas F. R. A. Prado Tested-by: Chen-Yu Tsai Tested-by: N=C3=ADcolas F. R. A. Prado --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 146 +++++++++++++++++++++++ 1 file changed, 146 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index a997f34cc3ad..92478e57f16f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -6,6 +6,7 @@ =20 /dts-v1/; #include +#include #include #include #include @@ -20,6 +21,14 @@ #address-cells =3D <2>; #size-cells =3D <2>; =20 + aliases { + ovl0 =3D &ovl0; + ovl-2l0 =3D &ovl_2l0; + ovl-2l2 =3D &ovl_2l2; + rdma0 =3D &rdma0; + rdma4 =3D &rdma4; + }; + clk26m: oscillator0 { compatible =3D "fixed-clock"; #clock-cells =3D <0>; @@ -554,6 +563,15 @@ assigned-clock-parents =3D <&topckgen CLK_TOP_OSC_D10>; }; =20 + gce: mailbox@10228000 { + compatible =3D "mediatek,mt8192-gce"; + reg =3D <0 0x10228000 0 0x4000>; + interrupts =3D ; + #mbox-cells =3D <2>; + clocks =3D <&infracfg CLK_INFRA_GCE>; + clock-names =3D "gce"; + }; + scp_adsp: clock-controller@10720000 { compatible =3D "mediatek,mt8192-scp_adsp"; reg =3D <0 0x10720000 0 0x1000>; @@ -1189,6 +1207,19 @@ reg =3D <0 0x14000000 0 0x1000>; #clock-cells =3D <1>; #reset-cells =3D <1>; + mboxes =3D <&gce 0 CMDQ_THR_PRIO_HIGHEST>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0 0x1000>; + }; + + mutex: mutex@14001000 { + compatible =3D "mediatek,mt8192-disp-mutex"; + reg =3D <0 0x14001000 0 0x1000>; + interrupts =3D ; + clocks =3D <&mmsys CLK_MM_DISP_MUTEX0>; + mediatek,gce-events =3D , + ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; }; =20 smi_common: smi@14002000 { @@ -1222,6 +1253,121 @@ power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; }; =20 + ovl0: ovl@14005000 { + compatible =3D "mediatek,mt8192-disp-ovl"; + reg =3D <0 0x14005000 0 0x1000>; + interrupts =3D ; + clocks =3D <&mmsys CLK_MM_DISP_OVL0>; + iommus =3D <&iommu0 M4U_PORT_L0_OVL_RDMA0>, + <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x5000 0x1000>; + }; + + ovl_2l0: ovl@14006000 { + compatible =3D "mediatek,mt8192-disp-ovl-2l"; + reg =3D <0 0x14006000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_OVL0_2L>; + iommus =3D <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x6000 0x1000>; + }; + + rdma0: rdma@14007000 { + compatible =3D "mediatek,mt8192-disp-rdma", + "mediatek,mt8183-disp-rdma"; + reg =3D <0 0x14007000 0 0x1000>; + interrupts =3D ; + clocks =3D <&mmsys CLK_MM_DISP_RDMA0>; + iommus =3D <&iommu0 M4U_PORT_L0_DISP_RDMA0>; + mediatek,rdma-fifo-size =3D <5120>; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x7000 0x1000>; + }; + + color0: color@14009000 { + compatible =3D "mediatek,mt8192-disp-color", + "mediatek,mt8173-disp-color"; + reg =3D <0 0x14009000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_COLOR0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x9000 0x1000>; + }; + + ccorr0: ccorr@1400a000 { + compatible =3D "mediatek,mt8192-disp-ccorr"; + reg =3D <0 0x1400a000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_CCORR0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xa000 0x1000>; + }; + + aal0: aal@1400b000 { + compatible =3D "mediatek,mt8192-disp-aal", + "mediatek,mt8183-disp-aal"; + reg =3D <0 0x1400b000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_AAL0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xb000 0x1000>; + }; + + gamma0: gamma@1400c000 { + compatible =3D "mediatek,mt8192-disp-gamma", + "mediatek,mt8183-disp-gamma"; + reg =3D <0 0x1400c000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_GAMMA0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xc000 0x1000>; + }; + + postmask0: postmask@1400d000 { + compatible =3D "mediatek,mt8192-disp-postmask"; + reg =3D <0 0x1400d000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_POSTMASK0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xd000 0x1000>; + }; + + dither0: dither@1400e000 { + compatible =3D "mediatek,mt8192-disp-dither", + "mediatek,mt8183-disp-dither"; + reg =3D <0 0x1400e000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_DITHER0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xe000 0x1000>; + }; + + ovl_2l2: ovl@14014000 { + compatible =3D "mediatek,mt8192-disp-ovl-2l"; + reg =3D <0 0x14014000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_OVL2_2L>; + iommus =3D <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0x4000 0x1000>; + }; + + rdma4: rdma@14015000 { + compatible =3D "mediatek,mt8192-disp-rdma", + "mediatek,mt8183-disp-rdma"; + reg =3D <0 0x14015000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_RDMA4>; + iommus =3D <&iommu0 M4U_PORT_L1_DISP_RDMA4>; + mediatek,rdma-fifo-size =3D <2048>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0x5000 0x1000>; + }; + dpi0: dpi@14016000 { compatible =3D "mediatek,mt8192-dpi"; reg =3D <0 0x14016000 0 0x1000>; --=20 2.18.0 From nobody Sat Sep 21 20:14:10 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F4D9C43334 for ; Tue, 12 Jul 2022 11:41:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232719AbiGLLlL (ORCPT ); Tue, 12 Jul 2022 07:41:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53910 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232548AbiGLLk6 (ORCPT ); Tue, 12 Jul 2022 07:40:58 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 497F8AE3B5; Tue, 12 Jul 2022 04:40:57 -0700 (PDT) X-UUID: af65d2b188e04f13ab1e8d6c30e29316-20220712 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8,REQID:0bc8c407-d7db-4082-be49-b95e5be60b50,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:-5 X-CID-META: VersionHash:0f94e32,CLOUDID:ff2d46d7-5d6d-4eaf-a635-828a3ee48b7c,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: af65d2b188e04f13ab1e8d6c30e29316-20220712 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 757573389; Tue, 12 Jul 2022 19:40:53 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Tue, 12 Jul 2022 19:40:52 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Tue, 12 Jul 2022 19:40:52 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , Chen-Yu Tsai , Allen-KH Cheng Subject: [PATCH v3 5/5] arm64: dts: mt8192: Add dsi node Date: Tue, 12 Jul 2022 19:40:46 +0800 Message-ID: <20220712114046.15574-6-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220712114046.15574-1-allen-kh.cheng@mediatek.com> References: <20220712114046.15574-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add dsi node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai Tested-by: N=C3=ADcolas F. R. A. Prado --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 92478e57f16f..fcb4f87ad824 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1345,6 +1345,25 @@ mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xe000 0x1000>; }; =20 + dsi0: dsi@14010000 { + compatible =3D "mediatek,mt8183-dsi"; + reg =3D <0 0x14010000 0 0x1000>; + interrupts =3D ; + clocks =3D <&mmsys CLK_MM_DSI0>, + <&mmsys CLK_MM_DSI_DSI0>, + <&mipi_tx0>; + clock-names =3D "engine", "digital", "hs"; + phys =3D <&mipi_tx0>; + phy-names =3D "dphy"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + resets =3D <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>; + status =3D "disabled"; + + port { + dsi_out: endpoint { }; + }; + }; + ovl_2l2: ovl@14014000 { compatible =3D "mediatek,mt8192-disp-ovl-2l"; reg =3D <0 0x14014000 0 0x1000>; --=20 2.18.0