From nobody Sat Sep 21 19:36:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12364C43334 for ; Tue, 12 Jul 2022 11:16:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232353AbiGLLQF (ORCPT ); Tue, 12 Jul 2022 07:16:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60336 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229840AbiGLLPt (ORCPT ); Tue, 12 Jul 2022 07:15:49 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E06B53899; Tue, 12 Jul 2022 04:15:47 -0700 (PDT) X-UUID: 18ec80eaf50443779d82401627b00c1b-20220712 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8,REQID:e23a78a7-eff2-44b3-b4c2-6d9efcb5a771,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:-5 X-CID-META: VersionHash:0f94e32,CLOUDID:20891364-0b3f-4b2c-b3a6-ed5c044366a0,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: 18ec80eaf50443779d82401627b00c1b-20220712 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 22875398; Tue, 12 Jul 2022 19:15:43 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Tue, 12 Jul 2022 19:15:42 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Tue, 12 Jul 2022 19:15:41 +0800 From: Xiangsheng Hou To: , , CC: , , , , , , Xiangsheng Hou , AngeloGioacchino Del Regno Subject: [PATCH V4] dt-bindings: mediatek: Add axi clock in mt8173 dts example Date: Tue, 12 Jul 2022 19:11:07 +0800 Message-ID: <20220712111106.31089-1-xiangsheng.hou@mediatek.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" For mt8173, it is needed to add the axi clock for dma mode. Signed-off-by: Xiangsheng Hou Reviewed-by: AngeloGioacchino Del Regno Acked-by: Rob Herring --- Changes from v3: - fix number of column characters Changes from v2: - remove assigned clocks and parents in dt-binding Changes from v1: - none --- .../devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yam= l b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml index 41e60fe4b09f..d3d7ed4b497b 100644 --- a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml @@ -82,8 +82,9 @@ examples: compatible =3D "mediatek,mt8173-nor"; reg =3D <0 0x1100d000 0 0xe0>; interrupts =3D <1>; - clocks =3D <&pericfg CLK_PERI_SPI>, <&topckgen CLK_TOP_SPINFI_IFR_= SEL>; - clock-names =3D "spi", "sf"; + clocks =3D <&pericfg CLK_PERI_SPI>, <&topckgen CLK_TOP_SPINFI_IFR_= SEL>, + <&pericfg CLK_PERI_NFI>; + clock-names =3D "spi", "sf", "axi"; #address-cells =3D <1>; #size-cells =3D <0>; =20 --=20 2.25.1