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([51.37.234.167]) by smtp.gmail.com with ESMTPSA id j9-20020a05600c410900b003a02cbf862esm7330892wmi.13.2022.07.11.11.44.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jul 2022 11:44:09 -0700 (PDT) From: Conor Dooley To: Emil Renner Berthing , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Conor Dooley Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 1/2] dt-bindings: riscv: document the sifive e24 Date: Mon, 11 Jul 2022 19:43:25 +0100 Message-Id: <20220711184325.1367393-2-mail@conchuod.ie> X-Mailer: git-send-email 2.37.0 In-Reply-To: <20220711184325.1367393-1-mail@conchuod.ie> References: <20220711184325.1367393-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley The SiFive E24 is a 32 bit monitor core present on the JH7100. Signed-off-by: Conor Dooley Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentat= ion/devicetree/bindings/riscv/cpus.yaml index d632ac76532e..195e762094a8 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -29,6 +29,7 @@ properties: - enum: - sifive,rocket0 - sifive,bullet0 + - sifive,e24 - sifive,e5 - sifive,e7 - sifive,e71 @@ -75,6 +76,7 @@ properties: lowercase to simplify parsing. $ref: "/schemas/types.yaml#/definitions/string" enum: + - rv32imafc - rv64imac - rv64imafdc =20 --=20 2.37.0 From nobody Sat Apr 18 19:11:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB6A8C433EF for ; Mon, 11 Jul 2022 18:44:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231274AbiGKSoX (ORCPT ); Mon, 11 Jul 2022 14:44:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33146 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230465AbiGKSoS (ORCPT ); Mon, 11 Jul 2022 14:44:18 -0400 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09CCC23177 for ; Mon, 11 Jul 2022 11:44:12 -0700 (PDT) Received: by mail-wr1-x42e.google.com with SMTP id v16so8133100wrd.13 for ; Mon, 11 Jul 2022 11:44:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=W1IQZ5rMVEddPML6F8h702sg3EwlT7K9zE2hYh3JCeM=; b=Jj+OLkUk2I13jTPtOe9Kyi7VcOuVAPM5BzlQNEypZZQp+NbKf9nMZCCFQ6hHqiqW86 tHABUXE/YfQlNFzH02VLigSQnRyMO6RX68IAt7jTy7bg8wqYs6Pi/wZmk6vanMypaWqE yq3BDMUQEyhYOOs9qMBeoSGec3rKC/acJ0OJlRmVS0NOQz+eWaPudEhyXwtFRoV5VCrU BR6v+4fB9VcyCy5FcimyhsXOn93hng3OBJ82uoQAUeaGQreemb48CXtrir8Vr/lMXfE6 SXvSBmpV63c4EogvWZImFBN6z5sb82Lk06Ak6eG+PCnnbtwgHAdd/ggGETj36Qx8m49v y+lw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=W1IQZ5rMVEddPML6F8h702sg3EwlT7K9zE2hYh3JCeM=; b=WOYGsYbwpdiHTQyvExpk08rmiKSyeynY+njQtdL4VhLexc+qGC499oXVyVPzIK+yn4 0aYutXTfh2l9/SwtHsBTBCEe0v5LAfA45pMZQtifaztUecibiAMvpfudSkOuZwqkwZ73 DPmEjy2Ldfp8NBbkLf0Ke0ILRhFmpYeP0JyuQGpmHH+FABsEGJK0dSBg1G4v9/NjVlf2 JZyiLd2b2ai5izt3RU6JbB/aRLTjiGwBMCdlBhNE0mHvW68I5wqJNfkpuXAcCpbqfGqo oqrge8JG2ywHlKBfVVzSskh1Q8mGzsg2lrQF3kUytZwoFteg8l0g9x9ypBFHj1O3NAEo XX8A== X-Gm-Message-State: AJIora9DyW//oor+uf8+Vi5yCpLO8gKfcMvrJJi88tGrVzj2ZAjiQR+m jJ9rah0FlKlEWuee+22OxO4KDA== X-Google-Smtp-Source: AGRyM1uVjauKfuKiTPMOqOvAQPCUUKMYYNjIBIvYdkM4RZWSrJUmn+aRiqrXVxOF1fvtcHpC/7FBxA== X-Received: by 2002:a5d:4f90:0:b0:21d:a6da:eb6f with SMTP id d16-20020a5d4f90000000b0021da6daeb6fmr5729408wru.283.1657565050659; Mon, 11 Jul 2022 11:44:10 -0700 (PDT) Received: from henark71.. ([51.37.234.167]) by smtp.gmail.com with ESMTPSA id j9-20020a05600c410900b003a02cbf862esm7330892wmi.13.2022.07.11.11.44.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jul 2022 11:44:10 -0700 (PDT) From: Conor Dooley To: Emil Renner Berthing , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Conor Dooley Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/2] riscv: dts: starfive: add the missing monitor core Date: Mon, 11 Jul 2022 19:43:26 +0100 Message-Id: <20220711184325.1367393-3-mail@conchuod.ie> X-Mailer: git-send-email 2.37.0 In-Reply-To: <20220711184325.1367393-1-mail@conchuod.ie> References: <20220711184325.1367393-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley The JH7100 has a 32 bit monitor core that is missing from the device tree. Add it (and its cpu-map entry) to more accurately reflect the actual topology of the SoC. Signed-off-by: Conor Dooley Reviewed-by: Emil Renner Berthing --- arch/riscv/boot/dts/starfive/jh7100.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts= /starfive/jh7100.dtsi index c617a61e26e2..92fce5b66d3d 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -67,6 +67,23 @@ cpu1_intc: interrupt-controller { }; }; =20 + E24: cpu@2 { + compatible =3D "sifive,e24", "riscv"; + reg =3D <2>; + device_type =3D "cpu"; + i-cache-block-size =3D <32>; + i-cache-sets =3D <256>; + i-cache-size =3D <16384>; + riscv,isa =3D "rv32imafc"; + status =3D "disabled"; + + cpu2_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + cpu-map { cluster0 { core0 { @@ -76,6 +93,10 @@ core0 { core1 { cpu =3D <&U74_1>; }; + + core2 { + cpu =3D <&E24>; + }; }; }; }; --=20 2.37.0