From nobody Sat Apr 18 19:11:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 203A3C433EF for ; Mon, 11 Jul 2022 17:46:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230270AbiGKRqy (ORCPT ); Mon, 11 Jul 2022 13:46:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46718 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230006AbiGKRqr (ORCPT ); Mon, 11 Jul 2022 13:46:47 -0400 Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B0EE945F59 for ; Mon, 11 Jul 2022 10:46:44 -0700 (PDT) Received: by mail-pj1-x1033.google.com with SMTP id i8-20020a17090a4b8800b001ef8a65bfbdso5634951pjh.1 for ; Mon, 11 Jul 2022 10:46:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0Sgv21IkQ0c7ss/RxtMygO/Q/cken8+hd9VuAl5/nl8=; b=P89IaPfDJiWRHSo6zBLmhQbd7XMH8r0EWsEPfpbVk058AetLSOhGT4lo6XqgrqrFWb sDdmQ8iv8OQJ+f+UPcasXaE3zwfls6tI8MEJZXBJMzhxKzjmMtl1QyzKQ+2YNdH/H9Op Wse9yuEdi5cG2/XkKhxCaE/RY5qhXxlas2fAx9nbgzmZgBYg15cmGDSGHUVRE4oIbSEn R8AAxy/VJUdjXFuG6uNGt8OrbPltXQ9eT0njiqwzZD6MrOk6JYuWtZHqG6+xhsr1+0XV 0Yh43ZONbPS0WrHxLVMhlu0sEMrKhjQeTyv+mqW8+LgZEQEytI7LCs2Q6aB19a3QKmRt MoPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0Sgv21IkQ0c7ss/RxtMygO/Q/cken8+hd9VuAl5/nl8=; b=fatoO+Q4q2bhtIfiBGazsVI8EYYuUtI8J6XY5wB/uJRyn8pFfiIk2VM3NXJN1UTqCu 4eohD5DMaxUeA1WorTsXP2p7Ho2EQY0Xg4tAk/LKiHx5PJ+budVQ767xxcUCrTHJluiD LAukyyfbv1/ryfOhCHtXTMogtXkk4BSAKb7AcmR0JML20YMtVz9lPNJVq7Jmbl5TeFqB ACBMFzeP2tMdQcYlq7nGRWWj43owel4Y0eqEsQr16l80JVrscrmvfg7ijR9AnjeKh5gn uF/m5TtyB4UwvaS7FY1w+QRAvLRLoh04oQMMlrP20gBsiBoV2XcTK91yczcwcHrQZOWn PlQQ== X-Gm-Message-State: AJIora8+5wF+HyGltjMAJ5wNYAITxDpQ5LQnB/v1LM02bCNyJ/RO3vmV oPMzG6BrhvtD9BtCrdsQGYZ2VyyG/UGiyw== X-Google-Smtp-Source: AGRyM1uwy4SqoGXdZSGU9XupDTj6fIsTxcyHyFsJGzm31lf/2arfzc6EF4NjRqb/sNjEgUsL0zKFFg== X-Received: by 2002:a17:902:ab96:b0:16a:6db6:2715 with SMTP id f22-20020a170902ab9600b0016a6db62715mr20279922plr.141.1657561603713; Mon, 11 Jul 2022 10:46:43 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id p10-20020a170902780a00b0016be9fa6807sm3236866pll.284.2022.07.11.10.46.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jul 2022 10:46:43 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Anup Patel , Atish Patra , Guo Ren , linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Will Deacon Subject: [v3 1/5] RISC-V: Fix counter restart during overflow for RV32 Date: Mon, 11 Jul 2022 10:46:28 -0700 Message-Id: <20220711174632.4186047-2-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220711174632.4186047-1-atishp@rivosinc.com> References: <20220711174632.4186047-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Pass the upper half of the initial value of the counter correctly for RV32. Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support") Signed-off-by: Atish Patra Reviewed-by: Guo Ren --- drivers/perf/riscv_pmu_sbi.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index dca3537a8dcc..0cb694b794ae 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -525,8 +525,13 @@ static inline void pmu_sbi_start_overflow_mask(struct = riscv_pmu *pmu, hwc =3D &event->hw; max_period =3D riscv_pmu_ctr_get_width_mask(event); init_val =3D local64_read(&hwc->prev_count) & max_period; +#if defined(CONFIG_32BIT) + sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1, + flag, init_val, init_val >> 32, 0); +#else sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1, flag, init_val, 0, 0); +#endif } ctr_ovf_mask =3D ctr_ovf_mask >> 1; idx++; --=20 2.25.1 From nobody Sat Apr 18 19:11:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A362C433EF for ; Mon, 11 Jul 2022 17:47:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231174AbiGKRq6 (ORCPT ); Mon, 11 Jul 2022 13:46:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46722 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229986AbiGKRqr (ORCPT ); Mon, 11 Jul 2022 13:46:47 -0400 Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F98C509FC for ; Mon, 11 Jul 2022 10:46:45 -0700 (PDT) Received: by mail-pj1-x1033.google.com with SMTP id o3-20020a17090a744300b001ef8f7f3dddso5622440pjk.3 for ; Mon, 11 Jul 2022 10:46:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YDh5YVCvGcySEdAssqtNk1GISfqzMGhm55Nr/hwr5wA=; b=VKrPvmFHCte+ybcIGCeHbEr1nkOxUZuXHYKbPyClalUQRnUtRYiQPMbKs7VFU5pv3t 6B9RbI7HZfr0cExKC2Rr5FauJpdROREDktC8bopXp7TPTlJEwMoeVAFKhN9eoVgdAMwt hd/JZRe72ROYBr30l9ePQ+Xfdv2KDIAgo2BnVnbKgqAHmROaj3UtEwLbM3p5BVq96iKh H3fhMZyE33b7pcdhLGxXWvb+RDAAlL1P+LqxNHgQaa0Fdi5snAYPZwfF2cTQlzAyAoav YhO2ubCffUa8wv6OxVo/TDJCtKxpdsiXTteySTCA2Vtb3tKcq4y8w5ZkeGIgcPiGtsXL nIAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YDh5YVCvGcySEdAssqtNk1GISfqzMGhm55Nr/hwr5wA=; b=jkxlB3qP88Uw1coO/sKJ+oAMN/0XAeDa73Yk6KUOrT5GmkhSa+VCW0HEG4Iy0b3u62 6DU9U0JZ7uc34MBqsZqVMENRSNDsuaRS/9gRtnM2TfnQU+bvspTBeAEF69nEVDSHI0KA TlJjCwHYhj2K1W0X6sdoAJMmq+e31RlncZ7VNfvrOiAUDZxdwWLaZGC1DLxDroyG5/M5 4eeNfUH+IK9iqp1L2n+vxoTCTuLtmv94cpEyO9rjNRHIg2AmiqbANRLNhTzVaykg7K7L n5yVIWd2f+vcDXgQ4KnW6ZLEOEM2zO9qMVpIaqTN3aNLCEcsCUEsQb5jO1Hoyag8uUkL gHsg== X-Gm-Message-State: AJIora9M9khkaFzFX615BaNbZVQPfmX+kSaUNAsvt9czmBj3CwFoqd59 +pwGgSOGlfhbGj1ym1o9MCpzI/c6L0/MUw== X-Google-Smtp-Source: AGRyM1uUdg0luGzLmisAjzt01bCPhHy3/uI8TPvejk8VYxoPSmO1DV6ej9sDbjQtr8T/9tuzYcmaIQ== X-Received: by 2002:a17:903:2683:b0:16b:f38b:16df with SMTP id jf3-20020a170903268300b0016bf38b16dfmr19945118plb.94.1657561604692; Mon, 11 Jul 2022 10:46:44 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id p10-20020a170902780a00b0016be9fa6807sm3236866pll.284.2022.07.11.10.46.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jul 2022 10:46:44 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Albert Ou , Atish Patra , Guo Ren , linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Will Deacon Subject: [v3 2/5] RISC-V: Update user page mapping only once during start Date: Mon, 11 Jul 2022 10:46:29 -0700 Message-Id: <20220711174632.4186047-3-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220711174632.4186047-1-atishp@rivosinc.com> References: <20220711174632.4186047-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently, riscv_pmu_event_set_period updates the userpage mapping. However, the caller of riscv_pmu_event_set_period should update the userpage mapping because the counter can not be updated/started from set_period function in counter overflow path. Invoke the perf_event_update_userpage at the caller so that it doesn't get invoked twice during counter start path. Fixes: f5bfa23f576f ("RISC-V: Add a perf core library for pmu drivers") Reviewed-by: Anup Patel Signed-off-by: Atish Patra Reviewed-by: Guo Ren --- drivers/perf/riscv_pmu.c | 1 - drivers/perf/riscv_pmu_sbi.c | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/perf/riscv_pmu.c b/drivers/perf/riscv_pmu.c index b2b8d2074ed0..130b9f1a40e0 100644 --- a/drivers/perf/riscv_pmu.c +++ b/drivers/perf/riscv_pmu.c @@ -170,7 +170,6 @@ int riscv_pmu_event_set_period(struct perf_event *event) left =3D (max_period >> 1); =20 local64_set(&hwc->prev_count, (u64)-left); - perf_event_update_userpage(event); =20 return overflow; } diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 0cb694b794ae..3735337a4cfb 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -532,6 +532,7 @@ static inline void pmu_sbi_start_overflow_mask(struct r= iscv_pmu *pmu, sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1, flag, init_val, 0, 0); #endif + perf_event_update_userpage(event); } ctr_ovf_mask =3D ctr_ovf_mask >> 1; idx++; --=20 2.25.1 From nobody Sat Apr 18 19:11:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B87AFC433EF for ; Mon, 11 Jul 2022 17:47:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231237AbiGKRrA (ORCPT ); Mon, 11 Jul 2022 13:47:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46724 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230036AbiGKRqr (ORCPT ); Mon, 11 Jul 2022 13:46:47 -0400 Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E1272AC69 for ; Mon, 11 Jul 2022 10:46:46 -0700 (PDT) Received: by mail-pl1-x62b.google.com with SMTP id r6so2615522plg.3 for ; Mon, 11 Jul 2022 10:46:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vOTmDUkpz+mPbUuokk0QP2W08wgjCdIdsM+mPgDGou0=; b=V3fp0VSk9gvbvNZrW10f40Ews5n1xiSMtpJLcvEJcjL4jfDI8R2TfjOjLurvL4a4Kq asHseIaY3FLyAeWFMiKkq0kSBrv5HX+CVWLg2bcTMK6rqrTNY9ZaT/VnugE9FK6xBpZx gQcwByn7AW4Y130Y5S7itIxIX36fnfT0Oc4UMjhaMyVK0ugJ6+vJ2UipWRSj0sjWCUUm Z5HiKKnYAQDZ7BDFqjV9T5OOyPNvMNnMg/dA0L+ND0cf8DCb1TuPQgSofpxZG3h543tu 4Ln4NjBamXgFyUsiOGtTQsVl8lFrvfSHHlVbqN6VXz2N2850DfkpvZqP/QihGroIj8lQ clmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vOTmDUkpz+mPbUuokk0QP2W08wgjCdIdsM+mPgDGou0=; b=sskKLpwgiDI0jvbbDS1M6rFaJ0jOr+2DIT4wlA2/1+6xnyWGW0w2Af+W0zlIswk3ym 0xQph2pr5LZzGk1XgMQmpTGA4VVVRA9w7RlMOru6hkmRW2PLOEr5zcYZ26TcdmWDVB8q UYMFsvIzsL0js/kK/tniFmIojcsCda4xZ/uZt2gvKLZRshKd17tJa/hbEatRNu98vTjo qKmBjILOE7j0p6ix5I9e3iSfMp2wGQ+3G0x0IQAy3rnStGvl3lpJGPRoRk4wKHSehOFw spsJxySQTJ1TdG6S86jPI5Qo9f3tMz238aUqo4PePhPWsbWAOUWsXWJ9YMPenZnFYa9l TfIw== X-Gm-Message-State: AJIora8XqJKtfqp1AxhRi30rKkxPvb4uzWrv5+0XwAP4TgODoNAhy/sn ejrreH0n31So4Sovz7d6TPWi6n9SDNqsaA== X-Google-Smtp-Source: AGRyM1sK7JtXLDkoMbF7C0EBnsfOqSTLfT/Hz3fUBzvyeiD8bJ+TTXzlwwJKP5VkY0rN4NQcrJVdZw== X-Received: by 2002:a17:902:ef4f:b0:16b:8744:6c5f with SMTP id e15-20020a170902ef4f00b0016b87446c5fmr20376864plx.60.1657561605667; Mon, 11 Jul 2022 10:46:45 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id p10-20020a170902780a00b0016be9fa6807sm3236866pll.284.2022.07.11.10.46.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jul 2022 10:46:45 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Anup Patel , Atish Patra , Guo Ren , linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Will Deacon Subject: [v3 3/5] RISC-V: Fix SBI PMU calls for RV32 Date: Mon, 11 Jul 2022 10:46:30 -0700 Message-Id: <20220711174632.4186047-4-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220711174632.4186047-1-atishp@rivosinc.com> References: <20220711174632.4186047-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Some of the SBI PMU calls does not pass 64bit arguments correctly and not under RV32 compile time flags. Currently, this doesn't create any incorrect results as RV64 ignores any value in the additional register and qemu doesn't support raw events. Fix those SBI calls in order to set correct values for RV32. Fixes: e9991434596f ("RISC-V: Add perf platform driver based on SBI PMU ext= ension") Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_sbi.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 3735337a4cfb..bae614c73b14 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -274,8 +274,13 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *even= t) cflags |=3D SBI_PMU_CFG_FLAG_SET_UINH; =20 /* retrieve the available counter index */ +#if defined(CONFIG_32BIT) + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, cmas= k, + cflags, hwc->event_base, hwc->config, hwc->config >> 32); +#else ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, cmas= k, cflags, hwc->event_base, hwc->config, 0); +#endif if (ret.error) { pr_debug("Not able to find a counter for event %lx config %llx\n", hwc->event_base, hwc->config); @@ -417,8 +422,13 @@ static void pmu_sbi_ctr_start(struct perf_event *event= , u64 ival) struct hw_perf_event *hwc =3D &event->hw; unsigned long flag =3D SBI_PMU_START_FLAG_SET_INIT_VALUE; =20 +#if defined(CONFIG_32BIT) ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, hwc->idx, 1, flag, ival, ival >> 32, 0); +#else + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, hwc->idx, + 1, flag, ival, 0, 0); +#endif if (ret.error && (ret.error !=3D SBI_ERR_ALREADY_STARTED)) pr_err("Starting counter idx %d failed with error %d\n", hwc->idx, sbi_err_map_linux_errno(ret.error)); --=20 2.25.1 From nobody Sat Apr 18 19:11:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE37BC433EF for ; Mon, 11 Jul 2022 17:47:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231248AbiGKRrF (ORCPT ); Mon, 11 Jul 2022 13:47:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46722 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229978AbiGKRqs (ORCPT ); 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Mon, 11 Jul 2022 10:46:46 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Anup Patel , Atish Patra , Guo Ren , linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Will Deacon Subject: [v3 4/5] RISC-V: Move counter info definition to sbi header file Date: Mon, 11 Jul 2022 10:46:31 -0700 Message-Id: <20220711174632.4186047-5-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220711174632.4186047-1-atishp@rivosinc.com> References: <20220711174632.4186047-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Counter info encoding format is defined by the SBI specificaiton. KVM implementation of SBI PMU extension will also leverage this definition. Move the definition to common sbi header file from the sbi pmu driver. Signed-off-by: Atish Patra --- arch/riscv/include/asm/sbi.h | 14 ++++++++++++++ drivers/perf/riscv_pmu_sbi.c | 14 -------------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 9e3c2cf1edaf..d633ac0f5a32 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -122,6 +122,20 @@ enum sbi_ext_pmu_fid { SBI_EXT_PMU_COUNTER_FW_READ, }; =20 +union sbi_pmu_ctr_info { + unsigned long value; + struct { + unsigned long csr:12; + unsigned long width:6; +#if __riscv_xlen =3D=3D 32 + unsigned long reserved:13; +#else + unsigned long reserved:45; +#endif + unsigned long type:1; + }; +}; + #define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(55, 0) #define RISCV_PMU_RAW_EVENT_IDX 0x20000 =20 diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index bae614c73b14..24124546844c 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -21,20 +21,6 @@ #include #include =20 -union sbi_pmu_ctr_info { - unsigned long value; - struct { - unsigned long csr:12; - unsigned long width:6; -#if __riscv_xlen =3D=3D 32 - unsigned long reserved:13; -#else - unsigned long reserved:45; -#endif - unsigned long type:1; - }; -}; - /* * RISC-V doesn't have hetergenous harts yet. This need to be part of * per_cpu in case of harts with different pmu counters --=20 2.25.1 From nobody Sat Apr 18 19:11:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFB40C43334 for ; Mon, 11 Jul 2022 17:47:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231453AbiGKRrI (ORCPT ); Mon, 11 Jul 2022 13:47:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229645AbiGKRqt (ORCPT ); Mon, 11 Jul 2022 13:46:49 -0400 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2CA642B637 for ; Mon, 11 Jul 2022 10:46:48 -0700 (PDT) Received: by mail-pl1-x632.google.com with SMTP id v21so2543531plo.0 for ; Mon, 11 Jul 2022 10:46:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qEKWlCC7AAQFkN2lQOBvhkrAmVJAiIHFQ4je7dwmiQk=; b=2A9Jrfj4QVotrraU60+KHLujeQqELkBCK2o0SIBWPzhzCkkHCw+z8s0bbAF0KbeYxc zbVZelo4wIQOgJAdaUr7IR7bsty4mvle+P+vWkHvPPztirQRuk+aX4pul4bXl4AjBdic imIEgWcf+p+9JjAsfKIerhclb/r9lB6t59zkrgNAswZSUXRyzf3CqJ1L/iRrmkpiI7NM 3Zc8AIUmQjWzoyBrJi2LhUzBgWt3Fs/NwejCUXcnMSDSf5RqEm75DexU1hoeN3T4sUge 7cHa2vTeM6N7sIxrWDQF/2YbULcMwE8DfBJi8CMeC6jtd1x6y0LIQCbfqKw77qdv+2ku V+NQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qEKWlCC7AAQFkN2lQOBvhkrAmVJAiIHFQ4je7dwmiQk=; b=Q4YWjelzNPJtP8aA3JYF6RCtfkrth8IHm+LgvsHEVz6kyWbxsoKCw7WYK8yPwLvxSX wdQPqSIQeBtLIyggdEJpqeG8H73LQV5vwc28kYtQ+GRkS5bV/JpsCK7IY4yZVhfk1yZx fEpqJI1ohZoOxZ6tM3KtBHxfowFzRrJSu+t56fUC9Zol0HNDRf1yTQVxksERSPW02/yX CR43xN5t7sKl6ARwJmACjGn2mkWRzWO3kjfwYdNtyUBIAgClYf2Se2Rnc7v5Tc0YN5Uw y6lQv381nluEDi73Ab9Z6BbY5sqf/lqqXh4GQAfbdOrvWSTNCIdlOHA+0Qkc15PLBbQ8 PcVg== X-Gm-Message-State: AJIora+6ciD35MmTZN2gWBVoZia1n+d/wMCmZDOz5xGbJRVgy8ja76NT osOKUGiqvcFnXpVWsf+OTdLvxRdqWa+Dng== X-Google-Smtp-Source: AGRyM1vDlkAyeYhMVtonPQR3SHvSE41Bb3Dw5m4IwtJFN0pmrxdwI062w3PGSAnkB/fmansJQkKpng== X-Received: by 2002:a17:902:d651:b0:16b:f55e:c626 with SMTP id y17-20020a170902d65100b0016bf55ec626mr20295734plh.78.1657561607597; Mon, 11 Jul 2022 10:46:47 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id p10-20020a170902780a00b0016be9fa6807sm3236866pll.284.2022.07.11.10.46.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jul 2022 10:46:47 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Anup Patel , Atish Patra , Guo Ren , linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Will Deacon Subject: [v3 5/5] RISC-V: Improve SBI definitions Date: Mon, 11 Jul 2022 10:46:32 -0700 Message-Id: <20220711174632.4186047-6-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220711174632.4186047-1-atishp@rivosinc.com> References: <20220711174632.4186047-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Fixed few typos and bit fields not aligned with the spec. Define other related macros that will be useful in the future. Signed-off-by: Atish Patra --- arch/riscv/include/asm/sbi.h | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index d633ac0f5a32..2a0ef738695e 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -136,7 +136,7 @@ union sbi_pmu_ctr_info { }; }; =20 -#define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(55, 0) +#define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0) #define RISCV_PMU_RAW_EVENT_IDX 0x20000 =20 /** General pmu event codes specified in SBI PMU extension */ @@ -203,12 +203,26 @@ enum sbi_pmu_ctr_type { SBI_PMU_CTR_TYPE_FW, }; =20 +/* Helper macros to decode event idx */ +#define SBI_PMU_EVENT_IDX_OFFSET 20 +#define SBI_PMU_EVENT_IDX_MASK 0xFFFFF +#define SBI_PMU_EVENT_IDX_CODE_MASK 0xFFFF +#define SBI_PMU_EVENT_IDX_TYPE_MASK 0xF0000 +#define SBI_PMU_EVENT_RAW_IDX 0x20000 +#define SBI_PMU_FIXED_CTR_MASK 0x07 + +#define SBI_PMU_EVENT_CACHE_ID_CODE_MASK 0xFFF8 +#define SBI_PMU_EVENT_CACHE_OP_ID_CODE_MASK 0x06 +#define SBI_PMU_EVENT_CACHE_RESULT_ID_CODE_MASK 0x01 + +#define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF + /* Flags defined for config matching function */ #define SBI_PMU_CFG_FLAG_SKIP_MATCH (1 << 0) #define SBI_PMU_CFG_FLAG_CLEAR_VALUE (1 << 1) #define SBI_PMU_CFG_FLAG_AUTO_START (1 << 2) #define SBI_PMU_CFG_FLAG_SET_VUINH (1 << 3) -#define SBI_PMU_CFG_FLAG_SET_VSNH (1 << 4) +#define SBI_PMU_CFG_FLAG_SET_VSINH (1 << 4) #define SBI_PMU_CFG_FLAG_SET_UINH (1 << 5) #define SBI_PMU_CFG_FLAG_SET_SINH (1 << 6) #define SBI_PMU_CFG_FLAG_SET_MINH (1 << 7) --=20 2.25.1