From nobody Sun Sep 22 00:28:29 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1FF8C433EF for ; Mon, 11 Jul 2022 12:25:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231540AbiGKMZR (ORCPT ); Mon, 11 Jul 2022 08:25:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49404 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230425AbiGKMZL (ORCPT ); Mon, 11 Jul 2022 08:25:11 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7777E45F5D; Mon, 11 Jul 2022 05:25:10 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id ADF4366019FE; Mon, 11 Jul 2022 13:25:08 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1657542309; bh=WNj+Fngrs3bQ3s4zywv4THTLiM1Sc7weFg7rQrZYyA4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ceyCqKo7TRKXqpMJLLjVVVxkeX7NFgcmBVwiHVgHiBdWcrBW4wXbasuam2Zv3o1Gq Etiy5WNb/pI0J2BHtC9mAvQo/cSHGBdpmV3t6zR4UELoDyyo5Bn4GKVzCHcAD2u+V0 6w2dBWmD8VEM6WdDolQBqFiGgmxPIgUNiNPoTA6VkkCdI6TZbi5JviazImVZ7JCX7G IeOY9F692AZPeAhqbSGzEuzgeP185qP1hdaDmgaegDAN8MZ5M8j5MiwA/++YH6jDVy UxEj155zUjI9vKvxhe4Hw37V5WBTOUIr/ZzPvNsNkibx5JYwHb3EjpzZnIgW7HOkXU e5Fgt1Cg8qqQg== From: AngeloGioacchino Del Regno To: robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, chun-jie.chen@mediatek.com, weiyi.lu@mediatek.com, mbrugger@suse.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, nfraprado@collabora.com Subject: [PATCH 2/3] dt-bindings: power: mediatek: Update example to use phandle to syscon Date: Mon, 11 Jul 2022 14:25:02 +0200 Message-Id: <20220711122503.286743-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220711122503.286743-1-angelogioacchino.delregno@collabora.com> References: <20220711122503.286743-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The preferred way of declaring this node is by using a phandle to syscon: update the example to reflect that. Signed-off-by: AngeloGioacchino Del Regno --- .../power/mediatek,power-controller.yaml | 125 +++++++++--------- 1 file changed, 63 insertions(+), 62 deletions(-) diff --git a/Documentation/devicetree/bindings/power/mediatek,power-control= ler.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controlle= r.yaml index 848fdff7c9d8..bed059e4401d 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -237,76 +237,77 @@ examples: scpsys: syscon@10006000 { compatible =3D "syscon", "simple-mfd"; reg =3D <0 0x10006000 0 0x1000>; + }; + }; =20 - spm: power-controller { - compatible =3D "mediatek,mt8173-power-controller"; + spm: power-controller { + compatible =3D "mediatek,mt8173-power-controller"; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + syscon =3D <&scpsys>; + + /* power domains of the SoC */ + power-domain@MT8173_POWER_DOMAIN_VDEC { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_MM_SEL>; + clock-names =3D "mm"; + #power-domain-cells =3D <0>; + }; + power-domain@MT8173_POWER_DOMAIN_VENC { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_MM_SEL>, + <&topckgen CLK_TOP_VENC_SEL>; + clock-names =3D "mm", "venc"; + #power-domain-cells =3D <0>; + }; + power-domain@MT8173_POWER_DOMAIN_ISP { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_MM_SEL>; + clock-names =3D "mm"; + #power-domain-cells =3D <0>; + }; + power-domain@MT8173_POWER_DOMAIN_MM { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_MM_SEL>; + clock-names =3D "mm"; + #power-domain-cells =3D <0>; + mediatek,infracfg =3D <&infracfg>; + }; + power-domain@MT8173_POWER_DOMAIN_VENC_LT { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_MM_SEL>, + <&topckgen CLK_TOP_VENC_LT_SEL>; + clock-names =3D "mm", "venclt"; + #power-domain-cells =3D <0>; + }; + power-domain@MT8173_POWER_DOMAIN_AUDIO { + reg =3D ; + #power-domain-cells =3D <0>; + }; + power-domain@MT8173_POWER_DOMAIN_USB { + reg =3D ; + #power-domain-cells =3D <0>; + }; + power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC { + reg =3D ; + clocks =3D <&clk26m>; + clock-names =3D "mfg"; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8173_POWER_DOMAIN_MFG_2D { + reg =3D ; #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; =20 - /* power domains of the SoC */ - power-domain@MT8173_POWER_DOMAIN_VDEC { - reg =3D ; - clocks =3D <&topckgen CLK_TOP_MM_SEL>; - clock-names =3D "mm"; - #power-domain-cells =3D <0>; - }; - power-domain@MT8173_POWER_DOMAIN_VENC { - reg =3D ; - clocks =3D <&topckgen CLK_TOP_MM_SEL>, - <&topckgen CLK_TOP_VENC_SEL>; - clock-names =3D "mm", "venc"; - #power-domain-cells =3D <0>; - }; - power-domain@MT8173_POWER_DOMAIN_ISP { - reg =3D ; - clocks =3D <&topckgen CLK_TOP_MM_SEL>; - clock-names =3D "mm"; - #power-domain-cells =3D <0>; - }; - power-domain@MT8173_POWER_DOMAIN_MM { - reg =3D ; - clocks =3D <&topckgen CLK_TOP_MM_SEL>; - clock-names =3D "mm"; + power-domain@MT8173_POWER_DOMAIN_MFG { + reg =3D ; #power-domain-cells =3D <0>; mediatek,infracfg =3D <&infracfg>; }; - power-domain@MT8173_POWER_DOMAIN_VENC_LT { - reg =3D ; - clocks =3D <&topckgen CLK_TOP_MM_SEL>, - <&topckgen CLK_TOP_VENC_LT_SEL>; - clock-names =3D "mm", "venclt"; - #power-domain-cells =3D <0>; - }; - power-domain@MT8173_POWER_DOMAIN_AUDIO { - reg =3D ; - #power-domain-cells =3D <0>; - }; - power-domain@MT8173_POWER_DOMAIN_USB { - reg =3D ; - #power-domain-cells =3D <0>; - }; - power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC { - reg =3D ; - clocks =3D <&clk26m>; - clock-names =3D "mfg"; - #address-cells =3D <1>; - #size-cells =3D <0>; - #power-domain-cells =3D <1>; - - power-domain@MT8173_POWER_DOMAIN_MFG_2D { - reg =3D ; - #address-cells =3D <1>; - #size-cells =3D <0>; - #power-domain-cells =3D <1>; - - power-domain@MT8173_POWER_DOMAIN_MFG { - reg =3D ; - #power-domain-cells =3D <0>; - mediatek,infracfg =3D <&infracfg>; - }; - }; - }; }; }; }; --=20 2.35.1