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[88.92.171.55]) by smtp.gmail.com with ESMTPSA id u2-20020a05651206c200b00488ab8914b5sm1401504lff.213.2022.07.11.01.29.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jul 2022 01:29:47 -0700 (PDT) From: Krzysztof Kozlowski To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Bhupesh Sharma , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: Douglas Anderson , Krzysztof Kozlowski Subject: [PATCH v2 1/5] dt-bindings: mmc: sdhci-msm: fix reg-names entries Date: Mon, 11 Jul 2022 10:29:36 +0200 Message-Id: <20220711082940.39539-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220711082940.39539-1-krzysztof.kozlowski@linaro.org> References: <20220711082940.39539-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Bindings before conversion to DT schema expected reg-names without "_mem" suffix. This was used by older DTS files and by the MSM SDHCI driver. Reported-by: Douglas Anderson Fixes: edfbf8c307ff ("dt-bindings: mmc: sdhci-msm: Fix issues in yaml bindi= ngs") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Douglas Anderson --- .../devicetree/bindings/mmc/sdhci-msm.yaml | 24 +++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documen= tation/devicetree/bindings/mmc/sdhci-msm.yaml index 0853d0c32dc7..fc6e5221985a 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -60,22 +60,22 @@ properties: maxItems: 4 oneOf: - items: - - const: hc_mem + - const: hc - items: - - const: hc_mem - - const: core_mem + - const: hc + - const: core - items: - - const: hc_mem - - const: cqe_mem + - const: hc + - const: cqhci - items: - - const: hc_mem - - const: cqe_mem - - const: ice_mem + - const: hc + - const: cqhci + - const: ice - items: - - const: hc_mem - - const: core_mem - - const: cqe_mem - - const: ice_mem + - const: hc + - const: core + - const: cqhci + - const: ice =20 clocks: minItems: 3 --=20 2.34.1 From nobody Sat Apr 18 21:02:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80462C433EF for ; Mon, 11 Jul 2022 08:30:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230070AbiGKI37 (ORCPT ); Mon, 11 Jul 2022 04:29:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36222 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230023AbiGKI3x (ORCPT ); Mon, 11 Jul 2022 04:29:53 -0400 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2CFE9BC8F for ; Mon, 11 Jul 2022 01:29:52 -0700 (PDT) Received: by mail-lj1-x235.google.com with SMTP id a10so3505387ljj.5 for ; Mon, 11 Jul 2022 01:29:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ECmDrApCWmsy6bTxbWAJtF1tb5Jnxl9Hmbc7aLUQ7zs=; b=oc6SX5BfT6fMqrx+BbEtw0q8Ed8qK5l+j90ZAz+9xdJ25Woju5BEhRm4dCPVua7FVY zWs6IgK8XBHs8im6KsI5Vyqx19oKQT09IBwEsEl6PRSIr55fVrCeCLxynNoAoeYozPcI Jx5tCjylNt8VH3Aau7SZX48ZhaZuaAkh/4m/7mDSi8ECJTdDtV6ZyEYBWNOJ58zLl9it TB/IkamP0veGlXRApjAHP7walbdH6sIXa7P+SMwLqal3+PG28PbmFnEgWcfT9wQ/yMfx dNVudd7OMTXTHnZIl8Kqhhz+uFHC6UjFLUkaa401EjeDp7ptx1LD4YAFdhIdDfIJ6yxC lkSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ECmDrApCWmsy6bTxbWAJtF1tb5Jnxl9Hmbc7aLUQ7zs=; b=dzW6T4nj6Mhbn5bUqMxyyq6ueEho83eu4HXR+hlZrJDUFsP9AbTiuhnaBIqdwWxtAV qP3BEx7Gavpiv0t41ooZWE2yneSSsgl7vF2+gMsjrQi1TVoCn83lJTDcyXgRR1/XGkQ8 FmZ8SVvZKygQZmbe9jLXaVt3JQTJTWRalOZQG8sUi6i8UZ7muSbBT4o9zvgM8PRV8knr SnSp+bzLeF7w7UDe4IBU6SC+88vS26t/gWsZmvQ9qrMEfsR5kmXnqsIHQsrP+WAKcWmj M+ywSk4nhnWd5SsYr6d4HoSa87LBsvBonnS+HKXiXRTb2V7h5w17w6h+mhwVHkObvTdB HLag== X-Gm-Message-State: AJIora/uj5kH1prYggo9uqyC5nfOguSZ8zvMCQEFiEZ6VIcodOBrvmq+ 0xT59GDdqNSNM1XlAwrH8YDlRg== X-Google-Smtp-Source: AGRyM1uQLnnh/Pu9iJAGaTHhyYJeXAp8YyKuN7dPfR9tj5ox+SHwzeeUfcNoeW4io7jwBOYyPmtzVQ== X-Received: by 2002:a05:651c:50f:b0:25d:64a7:d358 with SMTP id o15-20020a05651c050f00b0025d64a7d358mr4895586ljp.523.1657528190568; Mon, 11 Jul 2022 01:29:50 -0700 (PDT) Received: from krzk-bin.. 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[88.92.171.55]) by smtp.gmail.com with ESMTPSA id u2-20020a05651206c200b00488ab8914b5sm1401504lff.213.2022.07.11.01.29.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jul 2022 01:29:50 -0700 (PDT) From: Krzysztof Kozlowski To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Bhupesh Sharma , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: Douglas Anderson , Krzysztof Kozlowski Subject: [PATCH v2 2/5] dt-bindings: mmc: sdhci-msm: constrain reg-names perp variants Date: Mon, 11 Jul 2022 10:29:37 +0200 Message-Id: <20220711082940.39539-3-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220711082940.39539-1-krzysztof.kozlowski@linaro.org> References: <20220711082940.39539-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The entries in arrays must have fixed order, so the bindings and Linux driver expecting various combinations of 'reg' addresses was never actually conforming to guidelines. The 'core' reg entry is valid only for SDCC v4 and lower, so disallow it in SDCC v5. SDCC v4 supports CQE and ICE, so allow them, even though the qcom,sdhci-msm-v4 compatible is used also for earlier SoCs with SDCC v2 or v3, so it is not entirely accurate. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Douglas Anderson --- Changes since v1: 1. Rework the patch based on Doug's feedback. --- .../devicetree/bindings/mmc/sdhci-msm.yaml | 61 ++++++++++++------- 1 file changed, 38 insertions(+), 23 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documen= tation/devicetree/bindings/mmc/sdhci-msm.yaml index fc6e5221985a..2f0fdd65e908 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -49,33 +49,11 @@ properties: =20 reg: minItems: 1 - items: - - description: Host controller register map - - description: SD Core register map - - description: CQE register map - - description: Inline Crypto Engine register map + maxItems: 4 =20 reg-names: minItems: 1 maxItems: 4 - oneOf: - - items: - - const: hc - - items: - - const: hc - - const: core - - items: - - const: hc - - const: cqhci - - items: - - const: hc - - const: cqhci - - const: ice - - items: - - const: hc - - const: core - - const: cqhci - - const: ice =20 clocks: minItems: 3 @@ -177,6 +155,43 @@ required: allOf: - $ref: mmc-controller.yaml# =20 + - if: + properties: + compatible: + contains: + enum: + - qcom,sdhci-msm-v4 + then: + properties: + reg: + minItems: 2 + items: + - description: Host controller register map + - description: SD Core register map + - description: CQE register map + - description: Inline Crypto Engine register map + reg-names: + minItems: 2 + items: + - const: hc + - const: core + - const: cqhci + - const: ice + else: + properties: + reg: + minItems: 1 + items: + - description: Host controller register map + - description: CQE register map + - description: Inline Crypto Engine register map + reg-names: + minItems: 1 + items: + - const: hc + - const: cqhci + - const: ice + unevaluatedProperties: false =20 examples: --=20 2.34.1 From nobody Sat Apr 18 21:02:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4272C433EF for ; Mon, 11 Jul 2022 08:30:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230076AbiGKIaD (ORCPT ); Mon, 11 Jul 2022 04:30:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36174 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230047AbiGKI3z (ORCPT ); Mon, 11 Jul 2022 04:29:55 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E548F1EEF4 for ; Mon, 11 Jul 2022 01:29:53 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id e28so3898072lfj.4 for ; Mon, 11 Jul 2022 01:29:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2gVW47IgmRx1vKZS2dex1FR+qcYbiSpveO6smMK6miE=; b=dmLmpu7odEiBNxCs/eu1tV0kV1400WpTN73alyX9IVIpe/umqwXuNUa8pyeaC0Eb4L dKPfNMwG43WSUEc5xMMLbVTopEJ8Bz1FS3OWu5vpUL76lucr/DN5BfZ/Jo1d5XCTBcTc sziQYL8JqSY7OS0/qvELTeMCqQGPmmViCRkDLtwjiKKYWlk8WdFiPJzjtaukaeJy5Wc1 gOk0Onjlt3AQb5nl4Vci3JOxmhkcAgw7FrAGszH0ofJF+bWiVCZsQg4wJpA/FT8Xd6Dh BMxql0GRLAhr5Uhh2aBLhx4gNQ9+XLXig6kWZ+ElRIN1b7qQc06Lc2FSbNePKrZs7mJe WlmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2gVW47IgmRx1vKZS2dex1FR+qcYbiSpveO6smMK6miE=; b=DzKcdtNjvgvXUJgC9xDDrEGE+S+w2lNiM5dHhl7cR96NmvmdxlwhVYz30277kkZqNq cIx13gXMfGWFqyG6FKdEvMbAXvO9jj2KTxjTSwBhm69FjzE25htMM1+WAy3S4RfXO+jp zMKi9F2uKiRTt9HynrzMBDsMXqAzdwjnp36/casnTADxHCI0kRDZ2dHKvP8W1KlElrjV llGl2Lg+XxbXqX1wlT5Mh6FwLtamo8WWf5UEJdQoHI0oynvM99eKr6JPiLRgcBLKkUky MZr+CBU47xVHmwpiIAGrPlHRoPBIXvlNhVE/9R/KOAaGXz+pxV4KiSWTNKPlSp/FlJpa WbnQ== X-Gm-Message-State: AJIora8iu8K+HLGjvPqrxqdyktKUnCk9Kc6JCaGVpnCVI6G8A9+GZe8p Y37w/AmMNFeScTVmTM8zs+f1yQ== X-Google-Smtp-Source: AGRyM1ta6IBf43di382hxKPOQozp33nV8V5Y1+5U/Kvadh+V2iDRAxsP/Alc58GcbZNsQnbpmVl4Ow== X-Received: by 2002:a05:6512:e88:b0:489:d187:9b3c with SMTP id bi8-20020a0565120e8800b00489d1879b3cmr5147465lfb.669.1657528193463; Mon, 11 Jul 2022 01:29:53 -0700 (PDT) Received: from krzk-bin.. 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[88.92.171.55]) by smtp.gmail.com with ESMTPSA id u2-20020a05651206c200b00488ab8914b5sm1401504lff.213.2022.07.11.01.29.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jul 2022 01:29:52 -0700 (PDT) From: Krzysztof Kozlowski To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Bhupesh Sharma , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: Douglas Anderson , Krzysztof Kozlowski Subject: [PATCH v2 3/5] arm64: dts: qcom: align SDHCI reg-names with DT schema Date: Mon, 11 Jul 2022 10:29:38 +0200 Message-Id: <20220711082940.39539-4-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220711082940.39539-1-krzysztof.kozlowski@linaro.org> References: <20220711082940.39539-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" DT schema requires SDHCI reg names to be hc/core without "_mem" suffix, just like TXT bindings were expecting before the conversion. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Douglas Anderson Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8916.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8953.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8994.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +- 6 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qc= om/ipq8074.dtsi index a6cb0dafcc17..2b9374f61d5b 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -379,7 +379,7 @@ spmi_bus: spmi@200f000 { sdhc_1: mmc@7824900 { compatible =3D "qcom,sdhci-msm-v4"; reg =3D <0x7824900 0x500>, <0x7824000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; =20 interrupts =3D , ; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qc= om/msm8916.dtsi index 48bc2e09128d..0bdf4d39f778 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1469,7 +1469,7 @@ lpass_codec: audio-codec@771c000 { sdhc_1: mmc@7824000 { compatible =3D "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0x07824900 0x11c>, <0x07824000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; =20 interrupts =3D , ; @@ -1487,7 +1487,7 @@ sdhc_1: mmc@7824000 { sdhc_2: mmc@7864000 { compatible =3D "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0x07864900 0x11c>, <0x07864000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; =20 interrupts =3D , ; diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qc= om/msm8953.dtsi index 1bc0ef476cdb..97dde1a429d9 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -799,7 +799,7 @@ sdhc_1: mmc@7824900 { compatible =3D "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; =20 reg =3D <0x7824900 0x500>, <0x7824000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; =20 interrupts =3D , ; @@ -859,7 +859,7 @@ sdhc_2: mmc@7864900 { compatible =3D "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; =20 reg =3D <0x7864900 0x500>, <0x7864000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; =20 interrupts =3D , ; diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qc= om/msm8994.dtsi index 8bc6c070e306..35c1ca080684 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -464,7 +464,7 @@ usb@f9200000 { sdhc1: mmc@f9824900 { compatible =3D "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0xf9824900 0x1a0>, <0xf9824000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; =20 interrupts =3D , ; @@ -487,7 +487,7 @@ sdhc1: mmc@f9824900 { sdhc2: mmc@f98a4900 { compatible =3D "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; =20 interrupts =3D , ; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qc= om/msm8996.dtsi index 25d6b26fab60..9745df5dc007 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2896,7 +2896,7 @@ hsusb_phy2: phy@7412000 { sdhc1: mmc@7464900 { compatible =3D "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0x07464900 0x11c>, <0x07464000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; =20 interrupts =3D , ; @@ -2920,7 +2920,7 @@ sdhc1: mmc@7464900 { sdhc2: mmc@74a4900 { compatible =3D "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0x074a4900 0x314>, <0x074a4000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; =20 interrupts =3D , ; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qc= om/msm8998.dtsi index e263a59d84b0..c98f36f95f3c 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -2078,7 +2078,7 @@ qusb2phy: phy@c012000 { sdhc2: mmc@c0a4900 { compatible =3D "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0x0c0a4900 0x314>, <0x0c0a4000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; =20 interrupts =3D , ; --=20 2.34.1 From nobody Sat Apr 18 21:02:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F180EC433EF for ; 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[88.92.171.55]) by smtp.gmail.com with ESMTPSA id u2-20020a05651206c200b00488ab8914b5sm1401504lff.213.2022.07.11.01.29.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jul 2022 01:29:55 -0700 (PDT) From: Krzysztof Kozlowski To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Bhupesh Sharma , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: Douglas Anderson , Krzysztof Kozlowski Subject: [PATCH v2 4/5] ARM: dts: qcom: align SDHCI reg-names with DT schema Date: Mon, 11 Jul 2022 10:29:39 +0200 Message-Id: <20220711082940.39539-5-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220711082940.39539-1-krzysztof.kozlowski@linaro.org> References: <20220711082940.39539-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" DT schema requires SDHCI reg names to be hc/core without "_mem" suffix, just like TXT bindings were expecting before the conversion. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Douglas Anderson Reviewed-by: Konrad Dybcio --- arch/arm/boot/dts/qcom-apq8084.dtsi | 4 ++-- arch/arm/boot/dts/qcom-ipq4019.dtsi | 1 + arch/arm/boot/dts/qcom-msm8226.dtsi | 6 +++--- arch/arm/boot/dts/qcom-msm8974.dtsi | 6 +++--- arch/arm/boot/dts/qcom-sdx65.dtsi | 2 +- 5 files changed, 10 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-a= pq8084.dtsi index 3e8bded2b5c8..45f3cbcf6238 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -422,7 +422,7 @@ blsp2_uart2: serial@f995e000 { mmc@f9824900 { compatible =3D "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0xf9824900 0x11c>, <0xf9824000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; clocks =3D <&gcc GCC_SDCC1_APPS_CLK>, @@ -435,7 +435,7 @@ mmc@f9824900 { mmc@f98a4900 { compatible =3D "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; clocks =3D <&gcc GCC_SDCC2_APPS_CLK>, diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-i= pq4019.dtsi index a2632349cec4..1b98764bab7a 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -224,6 +224,7 @@ vqmmc: regulator@1948000 { sdhci: mmc@7824900 { compatible =3D "qcom,sdhci-msm-v4"; reg =3D <0x7824900 0x11c>, <0x7824000 0x800>; + reg-names =3D "hc", "core"; interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; bus-width =3D <8>; diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-m= sm8226.dtsi index 0b5effdb269a..f711463d22dc 100644 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -137,7 +137,7 @@ apcs: syscon@f9011000 { sdhc_1: mmc@f9824900 { compatible =3D "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0xf9824900 0x11c>, <0xf9824000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; @@ -153,7 +153,7 @@ sdhc_1: mmc@f9824900 { sdhc_2: mmc@f98a4900 { compatible =3D "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; @@ -169,7 +169,7 @@ sdhc_2: mmc@f98a4900 { sdhc_3: mmc@f9864900 { compatible =3D "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0xf9864900 0x11c>, <0xf9864000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-m= sm8974.dtsi index 11b4206036e6..971eceaef3d1 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -439,7 +439,7 @@ acc3: clock-controller@f90b8000 { sdhc_1: mmc@f9824900 { compatible =3D "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0xf9824900 0x11c>, <0xf9824000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; @@ -456,7 +456,7 @@ sdhc_1: mmc@f9824900 { sdhc_3: mmc@f9864900 { compatible =3D "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0xf9864900 0x11c>, <0xf9864000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; @@ -475,7 +475,7 @@ sdhc_3: mmc@f9864900 { sdhc_2: mmc@f98a4900 { compatible =3D "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names =3D "hc_mem", "core_mem"; + reg-names =3D "hc", "core"; interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx= 65.dtsi index 7a193678b4f5..4f3389cb6300 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -334,7 +334,7 @@ glink-edge { sdhc_1: mmc@8804000 { compatible =3D "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; 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[88.92.171.55]) by smtp.gmail.com with ESMTPSA id u2-20020a05651206c200b00488ab8914b5sm1401504lff.213.2022.07.11.01.29.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jul 2022 01:29:57 -0700 (PDT) From: Krzysztof Kozlowski To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Bhupesh Sharma , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: Douglas Anderson , Krzysztof Kozlowski Subject: [PATCH v2 5/5] ARM: dts: qcom: align SDHCI clocks with DT schema Date: Mon, 11 Jul 2022 10:29:40 +0200 Message-Id: <20220711082940.39539-6-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220711082940.39539-1-krzysztof.kozlowski@linaro.org> References: <20220711082940.39539-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The DT schema expects clocks iface-core order. No functional change. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Douglas Anderson Reviewed-by: Konrad Dybcio --- arch/arm/boot/dts/qcom-apq8084.dtsi | 12 ++++++------ arch/arm/boot/dts/qcom-ipq4019.dtsi | 4 ++-- arch/arm/boot/dts/qcom-msm8226.dtsi | 18 +++++++++--------- arch/arm/boot/dts/qcom-msm8974.dtsi | 18 +++++++++--------- arch/arm/boot/dts/qcom-msm8974pro.dtsi | 6 +++--- 5 files changed, 29 insertions(+), 29 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-a= pq8084.dtsi index 45f3cbcf6238..c887ac5cdd7d 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -425,10 +425,10 @@ mmc@f9824900 { reg-names =3D "hc", "core"; interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; - clocks =3D <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; status =3D "disabled"; }; =20 @@ -438,10 +438,10 @@ mmc@f98a4900 { reg-names =3D "hc", "core"; interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; - clocks =3D <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; status =3D "disabled"; }; =20 diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-i= pq4019.dtsi index 1b98764bab7a..a8a32a5e7e5d 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -228,9 +228,9 @@ sdhci: mmc@7824900 { interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; bus-width =3D <8>; - clocks =3D <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_DCD_XO_CLK>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; status =3D "disabled"; }; =20 diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-m= sm8226.dtsi index f711463d22dc..9d4223bf8fc1 100644 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -141,10 +141,10 @@ sdhc_1: mmc@f9824900 { interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; - clocks =3D <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; pinctrl-names =3D "default"; pinctrl-0 =3D <&sdhc1_default_state>; status =3D "disabled"; @@ -157,10 +157,10 @@ sdhc_2: mmc@f98a4900 { interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; - clocks =3D <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; pinctrl-names =3D "default"; pinctrl-0 =3D <&sdhc2_default_state>; status =3D "disabled"; @@ -173,10 +173,10 @@ sdhc_3: mmc@f9864900 { interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; - clocks =3D <&gcc GCC_SDCC3_APPS_CLK>, - <&gcc GCC_SDCC3_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC3_AHB_CLK>, + <&gcc GCC_SDCC3_APPS_CLK>, <&xo_board>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; pinctrl-names =3D "default"; pinctrl-0 =3D <&sdhc3_default_state>; status =3D "disabled"; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-m= sm8974.dtsi index 971eceaef3d1..1f4baa6ac64d 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -443,10 +443,10 @@ sdhc_1: mmc@f9824900 { interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; - clocks =3D <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; bus-width =3D <8>; non-removable; =20 @@ -460,10 +460,10 @@ sdhc_3: mmc@f9864900 { interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; - clocks =3D <&gcc GCC_SDCC3_APPS_CLK>, - <&gcc GCC_SDCC3_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC3_AHB_CLK>, + <&gcc GCC_SDCC3_APPS_CLK>, <&xo_board>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; bus-width =3D <4>; =20 #address-cells =3D <1>; @@ -479,10 +479,10 @@ sdhc_2: mmc@f98a4900 { interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; - clocks =3D <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; bus-width =3D <4>; =20 #address-cells =3D <1>; diff --git a/arch/arm/boot/dts/qcom-msm8974pro.dtsi b/arch/arm/boot/dts/qco= m-msm8974pro.dtsi index 1e882e16a221..58df6e75ab6d 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974pro.dtsi @@ -10,10 +10,10 @@ &gpu { }; =20 &sdhc_1 { - clocks =3D <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>, <&gcc GCC_SDCC1_CDCCAL_FF_CLK>, <&gcc GCC_SDCC1_CDCCAL_SLEEP_CLK>; - clock-names =3D "core", "iface", "xo", "cal", "sleep"; + clock-names =3D "iface", "core", "xo", "cal", "sleep"; }; --=20 2.34.1