From nobody Sat Apr 18 21:01:38 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9EABCCA483 for ; Sun, 10 Jul 2022 23:06:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229560AbiGJXGQ (ORCPT ); Sun, 10 Jul 2022 19:06:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60788 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229543AbiGJXGI (ORCPT ); Sun, 10 Jul 2022 19:06:08 -0400 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 490E610FC0 for ; Sun, 10 Jul 2022 16:06:07 -0700 (PDT) Received: by mail-wm1-x32d.google.com with SMTP id d13-20020a05600c34cd00b003a2dc1cf0b4so2089658wmq.4 for ; Sun, 10 Jul 2022 16:06:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=t3ZTmvONYAL3UmGbG2MULEJQEOXDk4bgL9Jsh2UKHR0=; b=shjCmOtmTJr3WRbag5oJo/fGtuTm1xqY1Edpx4CJaaiZU343eW60a+82utSz3xgQ6p aWRh/+ep3FFT5CK/PAucz0i721CP1Tv8cjbvbTE+AhRlyVXwHm1otNklh+FMTNdiFjGu 55b4myBFjVznKA/z4iJAZwDdSIxXuSi6gp/LWCCvEsbgcxfUZ4MfqtLHHpblqvIri1yB 4RSYvjtpzs5XMxP29a/xlpF8IaGDvpGJYFFUEVEiNzzzu5RYpUG3VKKrJ5x5b4C4v8W/ VUvCmv7rG2tPfBge19Ypz0vXdpnvffjH4V94S0rjZ2GonwrfU21td/QHNbZRnyGdBDo1 n0nQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=t3ZTmvONYAL3UmGbG2MULEJQEOXDk4bgL9Jsh2UKHR0=; b=gFa1HFli23KGN2oioC6vuDNyVxIkrfyw5tKfv57ZLBdjJojat1n1sLzIFii8tW+998 TuzRqFnpUEVvyX8Lvswx2BKLj7t4T5zFkwx4X+jCG05oZRSH/M94r2CKRtR3Bf7zbV91 we9/lGKCENFCCCR5vh2W2vk5RjMqk/YNAz9jGmMIF4V85p1QqV2kYzp8O4Qu9/BQ8B3B pmWVQLsOMCz4dwekbm+HbZNj9KzVHM8FY39EcQL+y/Eaz12bLv1Ad7SvOQ7H6iag34dm l8ERNaVhmZyvrY9MqUaUq0FgBlynNCJXHtuWTL56QYpJlj0sJtAVLe3FuCtsj6CSaMx3 V+xA== X-Gm-Message-State: AJIora8f4Mj6B0/exR5wBsxDiLo5lnaQ4eh+ZVYUdmeg/2uXw3YXeSKC W2NT+C9S983kApvVGMRhIXbhCw== X-Google-Smtp-Source: AGRyM1u43KlHkERt90c0V0mKxMDOvNBrf0leawFGzCy7FxHSo4Rkj7KffUTXFcFXeKS8Uks57TmrnA== X-Received: by 2002:a05:600c:6024:b0:3a0:4ea4:cfa4 with SMTP id az36-20020a05600c602400b003a04ea4cfa4mr12564968wmb.119.1657494365850; Sun, 10 Jul 2022 16:06:05 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id n4-20020a5d6604000000b0021d650e4df4sm4436047wru.87.2022.07.10.16.06.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Jul 2022 16:06:05 -0700 (PDT) From: Sam Protsenko To: Marek Szyprowski , Krzysztof Kozlowski Cc: Joerg Roedel , Will Deacon , Robin Murphy , Janghyuck Kim , Cho KyongHo , Daniel Mentz , David Virag , Sumit Semwal , iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/7] iommu/exynos: Reuse SysMMU constants for page size and order Date: Mon, 11 Jul 2022 02:05:57 +0300 Message-Id: <20220710230603.13526-2-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220710230603.13526-1-semen.protsenko@linaro.org> References: <20220710230603.13526-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Using SZ_4K in context of SysMMU driver is better than using PAGE_SIZE, as PAGE_SIZE might have different value on different platforms. Though it would be even better to use more specific constants, already existing in SysMMU driver. Make the code more strict by using SPAGE_ORDER and SPAGE_SIZE constants. It also makes sense, as __sysmmu_tlb_invalidate_entry() also uses SPAGE_* constants for further calculations with num_inv param, so it's logical that num_inv should be previously calculated using also SPAGE_* values. Signed-off-by: Sam Protsenko Acked-by: Marek Szyprowski Reviewed-by: Krzysztof Kozlowski --- Changes in v2: - (none) This patch is new and added in v2 drivers/iommu/exynos-iommu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index 79729892eb48..8f80aaa35092 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -340,7 +340,7 @@ static void __sysmmu_set_ptbase(struct sysmmu_drvdata *= data, phys_addr_t pgd) if (MMU_MAJ_VER(data->version) < 5) writel(pgd, data->sfrbase + REG_PT_BASE_ADDR); else - writel(pgd / SZ_4K, data->sfrbase + REG_V5_PT_BASE_PFN); + writel(pgd >> SPAGE_ORDER, data->sfrbase + REG_V5_PT_BASE_PFN); =20 __sysmmu_tlb_invalidate(data); } @@ -550,7 +550,7 @@ static void sysmmu_tlb_invalidate_entry(struct sysmmu_d= rvdata *data, * 64KB page can be one of 16 consecutive sets. */ if (MMU_MAJ_VER(data->version) =3D=3D 2) - num_inv =3D min_t(unsigned int, size / SZ_4K, 64); + num_inv =3D min_t(unsigned int, size / SPAGE_SIZE, 64); =20 if (sysmmu_block(data)) { __sysmmu_tlb_invalidate_entry(data, iova, num_inv); --=20 2.30.2 From nobody Sat Apr 18 21:01:38 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2A0EC433EF for ; Sun, 10 Jul 2022 23:06:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229543AbiGJXGS (ORCPT ); Sun, 10 Jul 2022 19:06:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229645AbiGJXGK (ORCPT ); Sun, 10 Jul 2022 19:06:10 -0400 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8CB031261B for ; Sun, 10 Jul 2022 16:06:08 -0700 (PDT) Received: by mail-wm1-x332.google.com with SMTP id bi22-20020a05600c3d9600b003a04de22ab6so2100436wmb.1 for ; Sun, 10 Jul 2022 16:06:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eG4cDXpCwPd5e9f6H24dRQy0mExW1bAeq7MJJ7YjfTc=; b=vKgGjeledgKSvbyvudX5W+WP80Jb5rPkTbE5n4lbDLPTYE1R3td4O1Fh2SIRlWsChs zNTctxShh7Q0kUWdIvbCbYZY/ghIjcQDxK5qWLSBgHWPm4Rq7lhHUI8Qn/0LmLfmZtvf PLWzfMbYIvCzuqIyGECbXxu9A7kzHlJTlhGr3okDBUAdxWjXo0WaZ9Ga94A/cNp837TS GRkfALXaNHLXDqdxKO9Ky+8WwKvxCSBjLlJuixhEZ8lqjNdhiBSoBY5thpYIwv9vhKCT mNXwinWjmp7CAMs7NcESNaD3xu8w/PJ/YkhF3BY7wmXcz9FHZhKivcjVnQQS7lHbSDT6 pFEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eG4cDXpCwPd5e9f6H24dRQy0mExW1bAeq7MJJ7YjfTc=; b=yTyPbWl0vpfYwz7VhkHPVXbbhN7/9N2T+tEGRILiiOup/2fHyf1jqeIL2O1xHSXCad F6+xRTrlAp9JVa+X58yWNFIb+7AfSdM+nPm/WC/kd9VAVFFQgNjGmgBvPtDxekgIqviS 69TVaXbuHf0TQvjM70aS20n9AUeBiCXimBu79Mzs/DQrbCKmr1sgQuVHYeB2I02AXd3R qNd6wuOFQcvq0hx0PeO8ku5HRxSjhVGnEl3SLyhOeBPfRZRLhSCP1XDJIIVg7H3IkFqj 9tpKoehAYFt2e7L0AvZMOG2PAmJ7eGpB1DujL5bP3a/ce/h7HbUWfjzzXLspU0z37Y64 Visg== X-Gm-Message-State: AJIora++CWy/svtD1/lEiAyXuV8wr3jHgTxsEyWx+HBfsO4u53HnDH3k nJ+4lzG61+joPPWEIwVCkOS8CA== X-Google-Smtp-Source: AGRyM1tn3eeoTDSPR6nUcb7hLnN1jy33xtCICi4w0wZfKNEp3alCe02khff0VldwrNkL1Z8Yh+gQOQ== X-Received: by 2002:a7b:cb03:0:b0:39e:e826:ce6d with SMTP id u3-20020a7bcb03000000b0039ee826ce6dmr12559153wmj.102.1657494367129; Sun, 10 Jul 2022 16:06:07 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id m22-20020a7bcb96000000b003a2cf5eb900sm2687143wmi.40.2022.07.10.16.06.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Jul 2022 16:06:06 -0700 (PDT) From: Sam Protsenko To: Marek Szyprowski , Krzysztof Kozlowski Cc: Joerg Roedel , Will Deacon , Robin Murphy , Janghyuck Kim , Cho KyongHo , Daniel Mentz , David Virag , Sumit Semwal , iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/7] iommu/exynos: Handle failed IOMMU device registration properly Date: Mon, 11 Jul 2022 02:05:58 +0300 Message-Id: <20220710230603.13526-3-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220710230603.13526-1-semen.protsenko@linaro.org> References: <20220710230603.13526-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If iommu_device_register() fails in exynos_sysmmu_probe(), the previous calls have to be cleaned up. In this case, the iommu_device_sysfs_add() should be cleaned up, by calling its remove counterpart call. Signed-off-by: Sam Protsenko Acked-by: Marek Szyprowski Reviewed-by: Krzysztof Kozlowski --- Changes in v2: - (none) This patch is new and added in v2 drivers/iommu/exynos-iommu.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index 8f80aaa35092..c85db9dab851 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -629,7 +629,7 @@ static int exynos_sysmmu_probe(struct platform_device *= pdev) =20 ret =3D iommu_device_register(&data->iommu, &exynos_iommu_ops, dev); if (ret) - return ret; + goto err_iommu_register; =20 platform_set_drvdata(pdev, data); =20 @@ -656,6 +656,10 @@ static int exynos_sysmmu_probe(struct platform_device = *pdev) pm_runtime_enable(dev); =20 return 0; + +err_iommu_register: + iommu_device_sysfs_remove(&data->iommu); + return ret; } =20 static int __maybe_unused exynos_sysmmu_suspend(struct device *dev) --=20 2.30.2 From nobody Sat Apr 18 21:01:38 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B2E3C433EF for ; Sun, 10 Jul 2022 23:06:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229491AbiGJXGX (ORCPT ); Sun, 10 Jul 2022 19:06:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60836 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229544AbiGJXGL (ORCPT ); Sun, 10 Jul 2022 19:06:11 -0400 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9291F597 for ; Sun, 10 Jul 2022 16:06:09 -0700 (PDT) Received: by mail-wr1-x42d.google.com with SMTP id d16so4905390wrv.10 for ; Sun, 10 Jul 2022 16:06:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=R103erxeCCHS3ZUMewsB5C1yy+zcGyX5sa9sukmtQlA=; b=fLuyUwyFBhuSKQzea4YKfooN5u8vLxajhzZfJiUNNmT6fjM23kiTCm6Z5yIImksVh5 lKbtLFd24T7ayF/oB0abItkwp0lNCG0ghAJzPh4G3postibpTtFBBvM4Fntt1BEaOWvP zEyhX4ho27fL4YtKz90nx849VrALn9l90CFJEKmyU41u4qcCLTP9evbyTEfAuyaBC3gN oKvStT4nSnB10aKgpJ29VmiNuHp8pccko5rT27B8qfz9szXra3l/v4EVewqKj/SdJbRR JtuV3zuxQesh8+7sU7ZHpouewD8sn/EUwkU8oDubw4Og8ir0KQ+5xlNDJ61h99y991xI 72cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=R103erxeCCHS3ZUMewsB5C1yy+zcGyX5sa9sukmtQlA=; b=kvP4GSNtRm1S6LqF3AI0lAk7APP3iFAwpgUWlKc0CGzH66lbf/s1vwoARDIRX+Ty45 LEUiYb2wnWPHQgLoQKe1d+8gvFzM2wpZcxEfwufJGqM1CkUmETLPJH0ORWnASKzcW4Cp Z+HCGGCz5CL0EvjTrHRPSVPyF3fF8C6db8DWySjptqVc7yPPzLGr0zN/YCaYB9VJHRAm 9L+Qrre65CjqKrRKAuZ05MO+AMl0rxCzHw9qc1PHucKIeFqS6lpxFzGn9d5nvwcyclO8 Q1K2FirFfTxu7r5820tT4vN6IZBfeqpYy8wzuxmuuQibT/TcjYESEzmehLMLF76VCjDK 0Vzg== X-Gm-Message-State: AJIora+swDFz8sEsS+XGpdQhal1zY7JfjMWF3bEN6HoRw5leC2DNoP/X 3aPe2TUmqqtw/3AkVpHB5MHoPg== X-Google-Smtp-Source: AGRyM1vww+/EwQUG5ItTSVzcGPkgSaNRCtATWrYEb+Z/Gu6CFwsngTsI375t0lfeO503K1T635bVCg== X-Received: by 2002:a5d:4402:0:b0:21d:8093:138c with SMTP id z2-20020a5d4402000000b0021d8093138cmr13985720wrq.535.1657494368329; Sun, 10 Jul 2022 16:06:08 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id m4-20020a5d6244000000b0021d6e917442sm5383041wrv.72.2022.07.10.16.06.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Jul 2022 16:06:07 -0700 (PDT) From: Sam Protsenko To: Marek Szyprowski , Krzysztof Kozlowski Cc: Joerg Roedel , Will Deacon , Robin Murphy , Janghyuck Kim , Cho KyongHo , Daniel Mentz , David Virag , Sumit Semwal , iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/7] iommu/exynos: Set correct dma mask for SysMMU v5+ Date: Mon, 11 Jul 2022 02:05:59 +0300 Message-Id: <20220710230603.13526-4-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220710230603.13526-1-semen.protsenko@linaro.org> References: <20220710230603.13526-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SysMMU v5+ supports 36 bit physical address space. Set corresponding DMA mask to avoid falling back to SWTLBIO usage in dma_map_single() because of failed dma_capable() check. The original code for this fix was suggested by Marek. Signed-off-by: Sam Protsenko Co-developed-by: Marek Szyprowski Signed-off-by: Marek Szyprowski Acked-by: Krzysztof Kozlowski --- Changes in v2: - Handled failed dma_set_mask() call - Replaced "Originally-by" tag by "Co-developed-by" + SoB tags drivers/iommu/exynos-iommu.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index c85db9dab851..494f7d7aa9c5 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -646,6 +646,14 @@ static int exynos_sysmmu_probe(struct platform_device = *pdev) } } =20 + if (MMU_MAJ_VER(data->version) >=3D 5) { + ret =3D dma_set_mask(dev, DMA_BIT_MASK(36)); + if (ret) { + dev_err(dev, "Unable to set DMA mask: %d\n", ret); + goto err_dma_set_mask; + } + } + /* * use the first registered sysmmu device for performing * dma mapping operations on iommu page tables (cpu cache flush) @@ -657,6 +665,8 @@ static int exynos_sysmmu_probe(struct platform_device *= pdev) =20 return 0; =20 +err_dma_set_mask: + iommu_device_unregister(&data->iommu); err_iommu_register: iommu_device_sysfs_remove(&data->iommu); return ret; --=20 2.30.2 From nobody Sat Apr 18 21:01:38 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B363C43334 for ; Sun, 10 Jul 2022 23:06:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229682AbiGJXGZ (ORCPT ); Sun, 10 Jul 2022 19:06:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229510AbiGJXGM (ORCPT ); Sun, 10 Jul 2022 19:06:12 -0400 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2080010FC1 for ; Sun, 10 Jul 2022 16:06:11 -0700 (PDT) Received: by mail-wm1-x334.google.com with SMTP id ay25so2135545wmb.1 for ; Sun, 10 Jul 2022 16:06:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OWpujlI5omHz17Fb+MoaFJbCPt7aAheJ5MhgDzPMgM0=; b=cSG664Q9gF3etdWSbwOEagSbmm/jbAvPlTd0GQyTFqGN0Nmz90AyqP2Ln6A7NZIWX4 BDzgUmWae5Ic+hS20Ca3borTfTTIyVGUL4NwlG9GD1tm/LJ3lGvUNN6RNZlzQiHfH2SE L3QfFmHDRmPjlqrvK85oV8iMPDm/uBBAvs1B0PFQQv8Ll+f9x3mx/pgN97tTGbgNQ7w5 01xhL8TppXdWi6mbTBI9UtIOWPN0GL4H3TkuRZt6t5tBzr18wo6WcVYHWTenWvV3SuNN s9/Ow2ISk4FRzZts//4BO8jKBWa1MPLypBT2YoXFP21TdTdDr0ORkZky7Ha9JMGiwEcN YTcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OWpujlI5omHz17Fb+MoaFJbCPt7aAheJ5MhgDzPMgM0=; b=4ggBlzXwh0k7XN0ltdLsDwgyvt5vc9XnBN3CjeQN+aRLctD0Y2Gzt2O1l7K/0Gf9O/ C5l0bJ1b5F8upbf3qfXEqC7l9mHbmHnIlTFomTdveTXfRx6MnS/JNbEm6qYxpcfMQKl9 UzOSyICoZxY1vnL/61WD5Me3AydA0KA0OPlp51c475L8Fs2SJtNfmQ6j2BE+vRmJcpem qBZ5fO+L/AqBsMWDXBtMYuMoZN/0903LjVKY3IEp7w5RloKmDJONoHKp0c0lKQY6jrJt SNsbR4shCao4S40Yw6SvIYMxtueagR/kpHHXr2t99VLgMmjd3tzRCKMPuOImv97eEae2 w2Bw== X-Gm-Message-State: AJIora97ZOIJhkhpn56WEz0igGCaEyHTV/fs8yM7dctiJnwi4hoRf7/t Le/ptWNRXUR5Z8qjVQfHkSM4Pw== X-Google-Smtp-Source: AGRyM1t2lcHq7wxqO/juKZwr2K4NYwiyQlyw/MxC3xMXkZH43/eHky8In7BlEl8djCE4qAYCjJutfA== X-Received: by 2002:a05:600c:5129:b0:3a1:92e6:563e with SMTP id o41-20020a05600c512900b003a192e6563emr12469243wms.81.1657494369557; Sun, 10 Jul 2022 16:06:09 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id l3-20020a1c7903000000b003a04962ad3esm8775052wme.31.2022.07.10.16.06.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Jul 2022 16:06:09 -0700 (PDT) From: Sam Protsenko To: Marek Szyprowski , Krzysztof Kozlowski Cc: Joerg Roedel , Will Deacon , Robin Murphy , Janghyuck Kim , Cho KyongHo , Daniel Mentz , David Virag , Sumit Semwal , iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/7] iommu/exynos: Use lookup based approach to access registers Date: Mon, 11 Jul 2022 02:06:00 +0300 Message-Id: <20220710230603.13526-5-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220710230603.13526-1-semen.protsenko@linaro.org> References: <20220710230603.13526-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" At the moment the driver supports SysMMU v1..v5 versions. SysMMU v5 has different register layout than SysMMU v1..v3. Instead of checking the version each time before reading/writing the registers, let's create corresponding register table for each SysMMU version and set the needed table on init, checking the SysMMU version one single time. This way is faster and more elegant. No functional change here, just a refactoring patch. Signed-off-by: Sam Protsenko Acked-by: Marek Szyprowski --- Changes in v2: - Reworked existing code (SysMMU v1..v5) to use this approach - Extracted v7 registers to the separate patches - Replaced MMU_REG() with corresponding SysMMU read/write functions - Improved the comment for 0x1 offsets triggering an unaligned access exception - Removed support for VMID number, as only VMID=3D0 (default) is used for now - Renamed register index names to reflect the old SysMMU version register names drivers/iommu/exynos-iommu.c | 141 ++++++++++++++++++++++------------- 1 file changed, 90 insertions(+), 51 deletions(-) diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index 494f7d7aa9c5..0cb1ce10db51 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -136,9 +136,6 @@ static u32 lv2ent_offset(sysmmu_iova_t iova) #define CFG_FLPDCACHE (1 << 20) /* System MMU 3.2+ only */ =20 /* common registers */ -#define REG_MMU_CTRL 0x000 -#define REG_MMU_CFG 0x004 -#define REG_MMU_STATUS 0x008 #define REG_MMU_VERSION 0x034 =20 #define MMU_MAJ_VER(val) ((val) >> 7) @@ -148,31 +145,57 @@ static u32 lv2ent_offset(sysmmu_iova_t iova) #define MAKE_MMU_VER(maj, min) ((((maj) & 0xF) << 7) | ((min) & 0x7F)) =20 /* v1.x - v3.x registers */ -#define REG_MMU_FLUSH 0x00C -#define REG_MMU_FLUSH_ENTRY 0x010 -#define REG_PT_BASE_ADDR 0x014 -#define REG_INT_STATUS 0x018 -#define REG_INT_CLEAR 0x01C - #define REG_PAGE_FAULT_ADDR 0x024 #define REG_AW_FAULT_ADDR 0x028 #define REG_AR_FAULT_ADDR 0x02C #define REG_DEFAULT_SLAVE_ADDR 0x030 =20 /* v5.x registers */ -#define REG_V5_PT_BASE_PFN 0x00C -#define REG_V5_MMU_FLUSH_ALL 0x010 -#define REG_V5_MMU_FLUSH_ENTRY 0x014 -#define REG_V5_MMU_FLUSH_RANGE 0x018 -#define REG_V5_MMU_FLUSH_START 0x020 -#define REG_V5_MMU_FLUSH_END 0x024 -#define REG_V5_INT_STATUS 0x060 -#define REG_V5_INT_CLEAR 0x064 #define REG_V5_FAULT_AR_VA 0x070 #define REG_V5_FAULT_AW_VA 0x080 =20 #define has_sysmmu(dev) (dev_iommu_priv_get(dev) !=3D NULL) =20 +enum { + REG_SET_V1, + REG_SET_V5, + MAX_REG_SET +}; + +enum { + IDX_CTRL, + IDX_CFG, + IDX_STATUS, + IDX_PT_BASE, + IDX_FLUSH_ALL, + IDX_FLUSH_ENTRY, + IDX_FLUSH_RANGE, + IDX_FLUSH_START, + IDX_FLUSH_END, + IDX_INT_STATUS, + IDX_INT_CLEAR, + MAX_REG_IDX +}; + +/* + * Some SysMMU versions might not implement some registers from this set, = thus + * those registers shouldn't be accessed. Set the offsets for those regist= ers to + * 0x1 to trigger an unaligned access exception, which can help one to deb= ug + * related issues. + */ +static const unsigned int sysmmu_regs[MAX_REG_SET][MAX_REG_IDX] =3D { + /* SysMMU v1..v3 */ + { + 0x00, 0x04, 0x08, 0x14, 0x0c, 0x10, 0x1, 0x1, 0x1, + 0x18, 0x1c, + }, + /* SysMMU v5 */ + { + 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x20, 0x24, + 0x60, 0x64, + }, +}; + static struct device *dma_dev; static struct kmem_cache *lv2table_kmem_cache; static sysmmu_pte_t *zero_lv2_table; @@ -274,6 +297,7 @@ struct sysmmu_drvdata { unsigned int version; /* our version */ =20 struct iommu_device iommu; /* IOMMU core handle */ + const unsigned int *regs; /* register set */ }; =20 static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *d= om) @@ -281,20 +305,30 @@ static struct exynos_iommu_domain *to_exynos_domain(s= truct iommu_domain *dom) return container_of(dom, struct exynos_iommu_domain, domain); } =20 +static void sysmmu_write(struct sysmmu_drvdata *data, size_t idx, u32 val) +{ + writel(val, data->sfrbase + data->regs[idx]); +} + +static u32 sysmmu_read(struct sysmmu_drvdata *data, size_t idx) +{ + return readl(data->sfrbase + data->regs[idx]); +} + static void sysmmu_unblock(struct sysmmu_drvdata *data) { - writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL); + sysmmu_write(data, IDX_CTRL, CTRL_ENABLE); } =20 static bool sysmmu_block(struct sysmmu_drvdata *data) { int i =3D 120; =20 - writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL); - while ((i > 0) && !(readl(data->sfrbase + REG_MMU_STATUS) & 1)) + sysmmu_write(data, IDX_CTRL, CTRL_BLOCK); + while (i > 0 && !(sysmmu_read(data, IDX_STATUS) & 0x1)) --i; =20 - if (!(readl(data->sfrbase + REG_MMU_STATUS) & 1)) { + if (!(sysmmu_read(data, IDX_STATUS) & 0x1)) { sysmmu_unblock(data); return false; } @@ -304,10 +338,7 @@ static bool sysmmu_block(struct sysmmu_drvdata *data) =20 static void __sysmmu_tlb_invalidate(struct sysmmu_drvdata *data) { - if (MMU_MAJ_VER(data->version) < 5) - writel(0x1, data->sfrbase + REG_MMU_FLUSH); - else - writel(0x1, data->sfrbase + REG_V5_MMU_FLUSH_ALL); + sysmmu_write(data, IDX_FLUSH_ALL, 0x1); } =20 static void __sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data, @@ -317,31 +348,33 @@ static void __sysmmu_tlb_invalidate_entry(struct sysm= mu_drvdata *data, =20 if (MMU_MAJ_VER(data->version) < 5) { for (i =3D 0; i < num_inv; i++) { - writel((iova & SPAGE_MASK) | 1, - data->sfrbase + REG_MMU_FLUSH_ENTRY); + sysmmu_write(data, IDX_FLUSH_ENTRY, + (iova & SPAGE_MASK) | 0x1); iova +=3D SPAGE_SIZE; } } else { if (num_inv =3D=3D 1) { - writel((iova & SPAGE_MASK) | 1, - data->sfrbase + REG_V5_MMU_FLUSH_ENTRY); + sysmmu_write(data, IDX_FLUSH_ENTRY, + (iova & SPAGE_MASK) | 0x1); } else { - writel((iova & SPAGE_MASK), - data->sfrbase + REG_V5_MMU_FLUSH_START); - writel((iova & SPAGE_MASK) + (num_inv - 1) * SPAGE_SIZE, - data->sfrbase + REG_V5_MMU_FLUSH_END); - writel(1, data->sfrbase + REG_V5_MMU_FLUSH_RANGE); + sysmmu_write(data, IDX_FLUSH_START, iova & SPAGE_MASK); + sysmmu_write(data, IDX_FLUSH_END, (iova & SPAGE_MASK) + + (num_inv - 1) * SPAGE_SIZE); + sysmmu_write(data, IDX_FLUSH_RANGE, 0x1); } } } =20 static void __sysmmu_set_ptbase(struct sysmmu_drvdata *data, phys_addr_t p= gd) { + u32 pt_base; + if (MMU_MAJ_VER(data->version) < 5) - writel(pgd, data->sfrbase + REG_PT_BASE_ADDR); + pt_base =3D pgd; else - writel(pgd >> SPAGE_ORDER, data->sfrbase + REG_V5_PT_BASE_PFN); + pt_base =3D pgd >> SPAGE_ORDER; =20 + sysmmu_write(data, IDX_PT_BASE, pt_base); __sysmmu_tlb_invalidate(data); } =20 @@ -365,8 +398,7 @@ static void __sysmmu_get_version(struct sysmmu_drvdata = *data) { u32 ver; =20 - __sysmmu_enable_clocks(data); - + /* Don't use sysmmu_read() here, as data->regs is not set yet */ ver =3D readl(data->sfrbase + REG_MMU_VERSION); =20 /* controllers on some SoCs don't report proper version */ @@ -377,6 +409,17 @@ static void __sysmmu_get_version(struct sysmmu_drvdata= *data) =20 dev_dbg(data->sysmmu, "hardware version: %d.%d\n", MMU_MAJ_VER(data->version), MMU_MIN_VER(data->version)); +} + +static void sysmmu_get_hw_info(struct sysmmu_drvdata *data) +{ + __sysmmu_enable_clocks(data); + + __sysmmu_get_version(data); + if (MMU_MAJ_VER(data->version) < 5) + data->regs =3D sysmmu_regs[REG_SET_V1]; + else + data->regs =3D sysmmu_regs[REG_SET_V5]; =20 __sysmmu_disable_clocks(data); } @@ -405,19 +448,14 @@ static irqreturn_t exynos_sysmmu_irq(int irq, void *d= ev_id) const struct sysmmu_fault_info *finfo; unsigned int i, n, itype; sysmmu_iova_t fault_addr; - unsigned short reg_status, reg_clear; int ret =3D -ENOSYS; =20 WARN_ON(!data->active); =20 if (MMU_MAJ_VER(data->version) < 5) { - reg_status =3D REG_INT_STATUS; - reg_clear =3D REG_INT_CLEAR; finfo =3D sysmmu_faults; n =3D ARRAY_SIZE(sysmmu_faults); } else { - reg_status =3D REG_V5_INT_STATUS; - reg_clear =3D REG_V5_INT_CLEAR; finfo =3D sysmmu_v5_faults; n =3D ARRAY_SIZE(sysmmu_v5_faults); } @@ -426,7 +464,7 @@ static irqreturn_t exynos_sysmmu_irq(int irq, void *dev= _id) =20 clk_enable(data->clk_master); =20 - itype =3D __ffs(readl(data->sfrbase + reg_status)); + itype =3D __ffs(sysmmu_read(data, IDX_INT_STATUS)); for (i =3D 0; i < n; i++, finfo++) if (finfo->bit =3D=3D itype) break; @@ -443,7 +481,7 @@ static irqreturn_t exynos_sysmmu_irq(int irq, void *dev= _id) /* fault is not recovered by fault handler */ BUG_ON(ret !=3D 0); =20 - writel(1 << itype, data->sfrbase + reg_clear); + sysmmu_write(data, IDX_INT_CLEAR, 1 << itype); =20 sysmmu_unblock(data); =20 @@ -461,8 +499,8 @@ static void __sysmmu_disable(struct sysmmu_drvdata *dat= a) clk_enable(data->clk_master); =20 spin_lock_irqsave(&data->lock, flags); - writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL); - writel(0, data->sfrbase + REG_MMU_CFG); + sysmmu_write(data, IDX_CTRL, CTRL_DISABLE); + sysmmu_write(data, IDX_CFG, 0x0); data->active =3D false; spin_unlock_irqrestore(&data->lock, flags); =20 @@ -482,7 +520,7 @@ static void __sysmmu_init_config(struct sysmmu_drvdata = *data) =20 cfg |=3D CFG_EAP; /* enable access protection bits check */ =20 - writel(cfg, data->sfrbase + REG_MMU_CFG); + sysmmu_write(data, IDX_CFG, cfg); } =20 static void __sysmmu_enable(struct sysmmu_drvdata *data) @@ -492,10 +530,10 @@ static void __sysmmu_enable(struct sysmmu_drvdata *da= ta) __sysmmu_enable_clocks(data); =20 spin_lock_irqsave(&data->lock, flags); - writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL); + sysmmu_write(data, IDX_CTRL, CTRL_BLOCK); __sysmmu_init_config(data); __sysmmu_set_ptbase(data, data->pgtable); - writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL); + sysmmu_write(data, IDX_CTRL, CTRL_ENABLE); data->active =3D true; spin_unlock_irqrestore(&data->lock, flags); =20 @@ -622,6 +660,8 @@ static int exynos_sysmmu_probe(struct platform_device *= pdev) data->sysmmu =3D dev; spin_lock_init(&data->lock); =20 + sysmmu_get_hw_info(data); + ret =3D iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL, dev_name(data->sysmmu)); if (ret) @@ -633,7 +673,6 @@ static int exynos_sysmmu_probe(struct platform_device *= pdev) =20 platform_set_drvdata(pdev, data); =20 - __sysmmu_get_version(data); if (PG_ENT_SHIFT < 0) { if (MMU_MAJ_VER(data->version) < 5) { PG_ENT_SHIFT =3D SYSMMU_PG_ENT_SHIFT; --=20 2.30.2 From nobody Sat Apr 18 21:01:38 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8B09C43334 for ; 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Sun, 10 Jul 2022 16:06:10 -0700 (PDT) From: Sam Protsenko To: Marek Szyprowski , Krzysztof Kozlowski Cc: Joerg Roedel , Will Deacon , Robin Murphy , Janghyuck Kim , Cho KyongHo , Daniel Mentz , David Virag , Sumit Semwal , iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/7] iommu/exynos: Check if SysMMU v7 has VM registers Date: Mon, 11 Jul 2022 02:06:01 +0300 Message-Id: <20220710230603.13526-6-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220710230603.13526-1-semen.protsenko@linaro.org> References: <20220710230603.13526-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SysMMU v7 can have Virtual Machine registers, which implement multiple translation domains. The driver should know if it's true or not, as VM registers shouldn't be accessed if not present. Read corresponding capabilities register to obtain that info, and store it in driver data. Signed-off-by: Sam Protsenko --- Changes in v2: - Removed the 'const' qualifier for local non-pointer variables drivers/iommu/exynos-iommu.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index 0cb1ce10db51..48681189ccf8 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -135,6 +135,9 @@ static u32 lv2ent_offset(sysmmu_iova_t iova) #define CFG_SYSSEL (1 << 22) /* System MMU 3.2 only */ #define CFG_FLPDCACHE (1 << 20) /* System MMU 3.2+ only */ =20 +#define CAPA0_CAPA1_EXIST BIT(11) +#define CAPA1_VCR_ENABLED BIT(14) + /* common registers */ #define REG_MMU_VERSION 0x034 =20 @@ -154,6 +157,10 @@ static u32 lv2ent_offset(sysmmu_iova_t iova) #define REG_V5_FAULT_AR_VA 0x070 #define REG_V5_FAULT_AW_VA 0x080 =20 +/* v7.x registers */ +#define REG_V7_CAPA0 0x870 +#define REG_V7_CAPA1 0x874 + #define has_sysmmu(dev) (dev_iommu_priv_get(dev) !=3D NULL) =20 enum { @@ -298,6 +305,9 @@ struct sysmmu_drvdata { =20 struct iommu_device iommu; /* IOMMU core handle */ const unsigned int *regs; /* register set */ + + /* v7 fields */ + bool has_vcr; /* virtual machine control register */ }; =20 static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *d= om) @@ -411,11 +421,27 @@ static void __sysmmu_get_version(struct sysmmu_drvdat= a *data) MMU_MAJ_VER(data->version), MMU_MIN_VER(data->version)); } =20 +static bool __sysmmu_has_capa1(struct sysmmu_drvdata *data) +{ + u32 capa0 =3D readl(data->sfrbase + REG_V7_CAPA0); + + return capa0 & CAPA0_CAPA1_EXIST; +} + +static void __sysmmu_get_vcr(struct sysmmu_drvdata *data) +{ + u32 capa1 =3D readl(data->sfrbase + REG_V7_CAPA1); + + data->has_vcr =3D capa1 & CAPA1_VCR_ENABLED; +} + static void sysmmu_get_hw_info(struct sysmmu_drvdata *data) { __sysmmu_enable_clocks(data); =20 __sysmmu_get_version(data); + if (MMU_MAJ_VER(data->version) >=3D 7 && __sysmmu_has_capa1(data)) + __sysmmu_get_vcr(data); if (MMU_MAJ_VER(data->version) < 5) data->regs =3D sysmmu_regs[REG_SET_V1]; else --=20 2.30.2 From nobody Sat Apr 18 21:01:38 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6001C433EF for ; Sun, 10 Jul 2022 23:06:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229688AbiGJXGd (ORCPT ); Sun, 10 Jul 2022 19:06:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229660AbiGJXGO (ORCPT ); Sun, 10 Jul 2022 19:06:14 -0400 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D39613FB6 for ; Sun, 10 Jul 2022 16:06:13 -0700 (PDT) Received: by mail-wr1-x42a.google.com with SMTP id h17so4977490wrx.0 for ; Sun, 10 Jul 2022 16:06:13 -0700 (PDT) DKIM-Signature: v=1; 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Sun, 10 Jul 2022 16:06:11 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id z11-20020a05600c0a0b00b0039c747a1e8fsm9713112wmp.7.2022.07.10.16.06.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Jul 2022 16:06:11 -0700 (PDT) From: Sam Protsenko To: Marek Szyprowski , Krzysztof Kozlowski Cc: Joerg Roedel , Will Deacon , Robin Murphy , Janghyuck Kim , Cho KyongHo , Daniel Mentz , David Virag , Sumit Semwal , iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 6/7] iommu/exynos: Add SysMMU v7 register sets Date: Mon, 11 Jul 2022 02:06:02 +0300 Message-Id: <20220710230603.13526-7-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220710230603.13526-1-semen.protsenko@linaro.org> References: <20220710230603.13526-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SysMMU v7 might have different register layouts (VM capable or non-VM capable). Check which layout is implemented in current SysMMU module and prepare the corresponding register table for futher usage. Signed-off-by: Sam Protsenko --- Changes in v2: - (none) This patch is new and added in v2 drivers/iommu/exynos-iommu.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index 48681189ccf8..64bf3331064f 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -166,6 +166,8 @@ static u32 lv2ent_offset(sysmmu_iova_t iova) enum { REG_SET_V1, REG_SET_V5, + REG_SET_V7_NON_VM, + REG_SET_V7_VM, MAX_REG_SET }; =20 @@ -201,6 +203,16 @@ static const unsigned int sysmmu_regs[MAX_REG_SET][MAX= _REG_IDX] =3D { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x20, 0x24, 0x60, 0x64, }, + /* SysMMU v7: Default register set (non-VM) */ + { + 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x20, 0x24, + 0x60, 0x64, + }, + /* SysMMU v7: VM capable register set */ + { + 0x00, 0x04, 0x08, 0x800c, 0x8010, 0x8014, 0x8018, 0x8020, + 0x8024, 0x60, 0x64, + }, }; =20 static struct device *dma_dev; @@ -440,12 +452,18 @@ static void sysmmu_get_hw_info(struct sysmmu_drvdata = *data) __sysmmu_enable_clocks(data); =20 __sysmmu_get_version(data); - if (MMU_MAJ_VER(data->version) >=3D 7 && __sysmmu_has_capa1(data)) - __sysmmu_get_vcr(data); - if (MMU_MAJ_VER(data->version) < 5) + if (MMU_MAJ_VER(data->version) < 5) { data->regs =3D sysmmu_regs[REG_SET_V1]; - else + } else if (MMU_MAJ_VER(data->version) < 7) { data->regs =3D sysmmu_regs[REG_SET_V5]; + } else { + if (__sysmmu_has_capa1(data)) + __sysmmu_get_vcr(data); + if (data->has_vcr) + data->regs =3D sysmmu_regs[REG_SET_V7_VM]; + else + data->regs =3D sysmmu_regs[REG_SET_V7_NON_VM]; + } =20 __sysmmu_disable_clocks(data); } --=20 2.30.2 From nobody Sat Apr 18 21:01:38 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08FC8C433EF for ; Sun, 10 Jul 2022 23:06:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229691AbiGJXGg (ORCPT ); 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Sun, 10 Jul 2022 16:06:12 -0700 (PDT) From: Sam Protsenko To: Marek Szyprowski , Krzysztof Kozlowski Cc: Joerg Roedel , Will Deacon , Robin Murphy , Janghyuck Kim , Cho KyongHo , Daniel Mentz , David Virag , Sumit Semwal , iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 7/7] iommu/exynos: Enable default VM instance on SysMMU v7 Date: Mon, 11 Jul 2022 02:06:03 +0300 Message-Id: <20220710230603.13526-8-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220710230603.13526-1-semen.protsenko@linaro.org> References: <20220710230603.13526-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In order to enable SysMMU v7 with VM register layout, at least the default VM instance (n=3D0) must be enabled, in addition to enabling the SysMMU itself. To do so, add corresponding write to MMU_CTRL_VM[0] register, before writing to MMU_CTRL register. Signed-off-by: Sam Protsenko Acked-by: Marek Szyprowski --- Changes in v2: - Extracted VM enabling code to the separate function - Used new SysMMU read/write functions to access the registers drivers/iommu/exynos-iommu.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index 64bf3331064f..2b333e137f57 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -135,6 +135,8 @@ static u32 lv2ent_offset(sysmmu_iova_t iova) #define CFG_SYSSEL (1 << 22) /* System MMU 3.2 only */ #define CFG_FLPDCACHE (1 << 20) /* System MMU 3.2+ only */ =20 +#define CTRL_VM_ENABLE BIT(0) +#define CTRL_VM_FAULT_MODE_STALL BIT(3) #define CAPA0_CAPA1_EXIST BIT(11) #define CAPA1_VCR_ENABLED BIT(14) =20 @@ -183,6 +185,7 @@ enum { IDX_FLUSH_END, IDX_INT_STATUS, IDX_INT_CLEAR, + IDX_CTRL_VM, MAX_REG_IDX }; =20 @@ -196,22 +199,22 @@ static const unsigned int sysmmu_regs[MAX_REG_SET][MA= X_REG_IDX] =3D { /* SysMMU v1..v3 */ { 0x00, 0x04, 0x08, 0x14, 0x0c, 0x10, 0x1, 0x1, 0x1, - 0x18, 0x1c, + 0x18, 0x1c, 0x1, }, /* SysMMU v5 */ { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x20, 0x24, - 0x60, 0x64, + 0x60, 0x64, 0x1, }, /* SysMMU v7: Default register set (non-VM) */ { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x20, 0x24, - 0x60, 0x64, + 0x60, 0x64, 0x1, }, /* SysMMU v7: VM capable register set */ { 0x00, 0x04, 0x08, 0x800c, 0x8010, 0x8014, 0x8018, 0x8020, - 0x8024, 0x60, 0x64, + 0x8024, 0x60, 0x64, 0x8000, }, }; =20 @@ -567,6 +570,18 @@ static void __sysmmu_init_config(struct sysmmu_drvdata= *data) sysmmu_write(data, IDX_CFG, cfg); } =20 +static void __sysmmu_enable_vid(struct sysmmu_drvdata *data) +{ + u32 ctrl; + + if (MMU_MAJ_VER(data->version) < 7 || !data->has_vcr) + return; + + ctrl =3D sysmmu_read(data, IDX_CTRL_VM); + ctrl |=3D CTRL_VM_ENABLE | CTRL_VM_FAULT_MODE_STALL; + sysmmu_write(data, IDX_CTRL_VM, ctrl); +} + static void __sysmmu_enable(struct sysmmu_drvdata *data) { unsigned long flags; @@ -577,6 +592,7 @@ static void __sysmmu_enable(struct sysmmu_drvdata *data) sysmmu_write(data, IDX_CTRL, CTRL_BLOCK); __sysmmu_init_config(data); __sysmmu_set_ptbase(data, data->pgtable); + __sysmmu_enable_vid(data); sysmmu_write(data, IDX_CTRL, CTRL_ENABLE); data->active =3D true; spin_unlock_irqrestore(&data->lock, flags); --=20 2.30.2