From nobody Sun Apr 19 00:44:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96375C43334 for ; Fri, 8 Jul 2022 14:30:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238127AbiGHOaO (ORCPT ); Fri, 8 Jul 2022 10:30:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51164 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234271AbiGHOaH (ORCPT ); Fri, 8 Jul 2022 10:30:07 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E17B01BE8F; Fri, 8 Jul 2022 07:30:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1657290606; x=1688826606; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zf+7kH8bgglyGlJ9EsT7S7ho3SnvVd1w2aOxWrS9FR4=; b=J70APxQYsP5Pw4tTZZinQ77A9ypj4y5XboJRuI0J23EVVIkVVEaYjVjL fIDhSLNvvMaKAmik+kw39TzmHpEqtEJXfpF7b33GDazdC3Srd2BfDD5st A+udSeiQ0AnS7q+Kk5YeAqQtUUHPgBz0M2IraG1EE3h5PUL/c2D/oXR2k m9CNBn6J59C6M/xR5/73NXawB8KYPnouGrj/GYHQvGNnW8NFMn4ODd7lY e10N30NUxJ9amPgdnmBQjM/ywI5M8dhbu/AclBdL/DWFpsNggirJnw82w ZxN4t4W7XRiPGxZ63QZQEwpEPXZ3tJA1qPbyGMNxml3L17k9sB/nhYBZC Q==; X-IronPort-AV: E=Sophos;i="5.92,255,1650956400"; d="scan'208";a="103658933" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Jul 2022 07:30:06 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 8 Jul 2022 07:30:05 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 8 Jul 2022 07:30:03 -0700 From: Conor Dooley To: Thierry Reding , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , "Lee Jones" , Rob Herring , "Krzysztof Kozlowski" CC: Daire McNamara , , , , , Conor Dooley Subject: [PATCH v4 1/4] dt-bindings: pwm: fix microchip corePWM's pwm-cells Date: Fri, 8 Jul 2022 15:29:35 +0100 Message-ID: <20220708142937.1120121-2-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220708142937.1120121-1-conor.dooley@microchip.com> References: <20220708142937.1120121-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" corePWM is capable of inverted operation but the binding requires \#pwm-cells of 2. Expand the binding to support setting the polarity. Fixes: df77f7735786 ("dt-bindings: pwm: add microchip corepwm binding") Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml b= /Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml index a7fae1772a81..cd8e9a8907f8 100644 --- a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml +++ b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml @@ -30,7 +30,9 @@ properties: maxItems: 1 =20 "#pwm-cells": - const: 2 + enum: [2, 3] + description: + The only flag supported by the controller is PWM_POLARITY_INVERTED. =20 microchip,sync-update-mask: description: | --=20 2.36.1 From nobody Sun Apr 19 00:44:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 480D3C43334 for ; Fri, 8 Jul 2022 14:30:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238150AbiGHOaR (ORCPT ); Fri, 8 Jul 2022 10:30:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51182 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238088AbiGHOaK (ORCPT ); Fri, 8 Jul 2022 10:30:10 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20886B7DC; Fri, 8 Jul 2022 07:30:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1657290609; x=1688826609; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yF1NojDTOGwCGkFGTDOFrruBHppEMQq5PgQMjxraLpE=; b=ha5JYFACH956PPxidTUoFxQV33IEtKmqbHPiDYqjB9MT+gGJo1tUmvOg WU4st+tMecMdEj0TQchzNIYpQX76tHECoVRxb6QGdFqGwhiNN10L5esDN H4Pdjnium4wF5i66DLaj7BSgM8rF+hTmFMoQFF/9jI5z3Ikepw2seqdBI B6On/jNmzij+G0+wUurmTN1gBnUSnk1XDHVbIiXR5DVmosg/Xgj8TBl8w /xntC+Dtys8ibsprsEPGxHPcXr6dZIaYqNJ4cUJKrQU15F0CdTWHXPVtm Bn7/4q2uwOpgsD7d+SszI+0YIBsSNGEe4KYlxuu9Nii5k3KTJ7r2HtmtS A==; X-IronPort-AV: E=Sophos;i="5.92,255,1650956400"; d="scan'208";a="103658958" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Jul 2022 07:30:08 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 8 Jul 2022 07:30:08 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 8 Jul 2022 07:30:06 -0700 From: Conor Dooley To: Thierry Reding , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , "Lee Jones" , Rob Herring , "Krzysztof Kozlowski" CC: Daire McNamara , , , , , Conor Dooley Subject: [PATCH v4 2/4] riscv: dts: fix the icicle's #pwm-cells Date: Fri, 8 Jul 2022 15:29:36 +0100 Message-ID: <20220708142937.1120121-3-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220708142937.1120121-1-conor.dooley@microchip.com> References: <20220708142937.1120121-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" \#pwm-cells for the Icicle kit's fabric PWM was incorrectly set to 2 & blindly overridden by the (out of tree) driver anyway. The core can support inverted operation, so update the entry to correctly report its capabilities. Fixes: 72560c6559b8 ("riscv: dts: microchip: add fpga fabric section to ici= cle kit") Signed-off-by: Conor Dooley --- .../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 2 +- .../dts/microchip/mpfs-tysom-m-fabric.dtsi | 18 ++ .../riscv/boot/dts/microchip/mpfs-tysom-m.dts | 185 ++++++++++++++++++ 3 files changed, 204 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index 0d28858b83f2..e09a13aef268 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -8,7 +8,7 @@ core_pwm0: pwm@41000000 { compatible =3D "microchip,corepwm-rtl-v4"; reg =3D <0x0 0x41000000 0x0 0xF0>; microchip,sync-update-mask =3D /bits/ 32 <0>; - #pwm-cells =3D <2>; + #pwm-cells =3D <3>; clocks =3D <&fabric_clk3>; status =3D "disabled"; }; diff --git a/arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi b/arch/= riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi new file mode 100644 index 000000000000..98f642e83ad4 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2022 Microchip Technology Inc */ + +// #include "dt-bindings/mailbox/miv-ihc.h" + +/ { + fabric_clk3: fabric-clk3 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <62500000>; + }; + + fabric_clk1: fabric-clk1 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <125000000>; + }; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts b/arch/riscv/bo= ot/dts/microchip/mpfs-tysom-m.dts new file mode 100644 index 000000000000..0b664c591255 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Original all-in-one devicetree: + * Copyright (C) 2020-2022 - Aldec + * Rewritten to use includes: + * Copyright (C) 2022 - Conor Dooley + */ + +/dts-v1/; + +#include "mpfs.dtsi" +#include "mpfs-tysom-m-fabric.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define MTIMER_FREQ 1000000 + +/ { + model =3D "Aldec TySOM-M-MPFS250T"; + compatible =3D "aldec,tysom-m-mpfs250t", "microchip,mpfs"; + + aliases { + ethernet0 =3D &mac0; + ethernet1 =3D &mac1; + serial0 =3D &mmuart0; + serial1 =3D &mmuart1; + serial2 =3D &mmuart2; + serial3 =3D &mmuart3; + serial4 =3D &mmuart4; + gpio0 =3D &gpio0; + gpio1 =3D &gpio2; + }; + + chosen { + stdout-path =3D "serial1:115200n8"; + }; + + cpus { + timebase-frequency =3D ; + }; + + ddrc_cache_lo: memory@80000000 { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x0 0x2e000000>; + status =3D "okay"; + }; + + ddrc_cache_hi: memory@1000000000 { + device_type =3D "memory"; + reg =3D <0x10 0x00000000 0x0 0x40000000>; + status =3D "okay"; + }; + + soc { + }; + + leds { + compatible =3D "gpio-leds"; + status =3D "okay"; + + led0 { + gpios =3D <&gpio1 23 1>; + default-state =3D "on"; + linux,default-trigger =3D "heartbeat"; + }; + }; +}; + +&i2c0 { + status =3D "okay"; +}; + +&i2c1 { + status =3D "okay"; + ina219: ina219@45 { + status =3D "okay"; + compatible =3D "ti,ina219"; + reg =3D <0x45>; + shunt-resistor =3D <0x7d0>; + }; +}; + +&gpio1 { + interrupts =3D <27 28 29 30 31 32 33 47 35 36 37 38 39 40 41 42 43 44 45 = 46 34 48 49 50>; + status =3D "okay"; +}; + +&mac0 { + status =3D "okay"; + phy-mode =3D "gmii"; + phy-handle =3D <&phy0>; + +}; + +&mac1 { + status =3D "okay"; + phy-mode =3D "gmii"; + phy-handle =3D <&phy1>; + phy1: ethernet-phy@1 { + reg =3D <1>; + ti,fifo-depth =3D <0x01>; + }; + phy0: ethernet-phy@0 { + reg =3D <0>; + ti,fifo-depth =3D <0x01>; + }; +}; + +&mbox { + status =3D "okay"; +}; + +&mmc { + max-frequency =3D <200000000>; + cap-mmc-highspeed; + cap-sd-highspeed; + no-1-8-v; + disable-wp; + status =3D "okay"; +}; + +&mmuart1 { + status =3D "okay"; +}; + +&mmuart2 { + status =3D "okay"; +}; + +&mmuart3 { + status =3D "okay"; +}; + +&mmuart4 { + status =3D "okay"; +}; + +&refclk { + clock-frequency =3D <125000000>; +}; + +&rtc { + status =3D "okay"; +}; + +&spi0 { + status =3D "okay"; +}; + +&spi1 { + status =3D "okay"; + pseFlash@0 { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "n25q128a11", "jedec,spi-nor"; + status =3D "okay"; + reg =3D <0x0>; + spi-max-frequency =3D <10000000>; + + partition@test-0 { /* test purposes */ + label =3D "qspi-test-0"; + reg =3D <0x00000000 0x00800000>; + }; + partition@test-1 { /* test purposes */ + label =3D "qspi-test-1"; + reg =3D <0x00800000 0x00800000>; + }; + partition@test-2 { /* test purposes */ + label =3D "qspi-test-2"; + reg =3D <0x01000000 0x00800000>; + }; + partition@test-3 { /* test purposes */ + label =3D "qspi-test-3"; + reg =3D <0x01800000 0x00800000>; + }; + }; +}; + +&syscontroller { + status =3D "okay"; +}; + +&usb { + status =3D "okay"; + dr_mode =3D "host"; +}; --=20 2.36.1 From nobody Sun Apr 19 00:44:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95AD6C43334 for ; Fri, 8 Jul 2022 14:30:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238176AbiGHOaV (ORCPT ); Fri, 8 Jul 2022 10:30:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238122AbiGHOaO (ORCPT ); Fri, 8 Jul 2022 10:30:14 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 651B31BE8F; Fri, 8 Jul 2022 07:30:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1657290613; x=1688826613; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lSx0OPdPdvVin79U9nT5HdNOn78XDODzEPHjKHD1c0E=; b=lJwF6Hbvzmml5VP/2TNvOobhp6DtPVmCnylVf8PdlUZUV8vNCAUM60Cn hODXWFcb4Lcu3qs6mBvELeli/ZHRijqeUVIEaIwuY2nj8jeaCT9m4+XJo RO1cDTvJe//qQ7dbqVBjkqjznSy05FYypitJoysJ00cmBXQ3KPBmjh0mC tqOOCngjQDnQwVzTaHZYH99GwG9o0EKfHieXqGe3gdhwAIAwwhp9Qj06B Y0r6EaxoPQyysbT1fq6yZPCXQPj4RpwPUFPdB0MWSp6a061eOwcrbW0lO oZc1d0SOjmpy9zHqAtc1NHG3mD+DbbYymusvj9B00+bKAoABKAlOfx6OA w==; X-IronPort-AV: E=Sophos;i="5.92,255,1650956400"; d="scan'208";a="171340840" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Jul 2022 07:30:12 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 8 Jul 2022 07:30:11 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 8 Jul 2022 07:30:08 -0700 From: Conor Dooley To: Thierry Reding , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , "Lee Jones" , Rob Herring , "Krzysztof Kozlowski" CC: Daire McNamara , , , , , Conor Dooley Subject: [PATCH v4 3/4] pwm: add microchip soft ip corePWM driver Date: Fri, 8 Jul 2022 15:29:37 +0100 Message-ID: <20220708142937.1120121-4-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220708142937.1120121-1-conor.dooley@microchip.com> References: <20220708142937.1120121-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a driver that supports the Microchip FPGA "soft" PWM IP core. Signed-off-by: Conor Dooley --- drivers/pwm/Kconfig | 10 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-microchip-core.c | 355 +++++++++++++++++++++++++++++++ 3 files changed, 366 insertions(+) create mode 100644 drivers/pwm/pwm-microchip-core.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 904de8d61828..007ea5750e73 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -383,6 +383,16 @@ config PWM_MEDIATEK To compile this driver as a module, choose M here: the module will be called pwm-mediatek. =20 +config PWM_MICROCHIP_CORE + tristate "Microchip corePWM PWM support" + depends on SOC_MICROCHIP_POLARFIRE || COMPILE_TEST + depends on HAS_IOMEM && OF + help + PWM driver for Microchip FPGA soft IP core. + + To compile this driver as a module, choose M here: the module + will be called pwm-microchip-core. + config PWM_MXS tristate "Freescale MXS PWM support" depends on ARCH_MXS || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 5c08bdb817b4..43feb7cfc66a 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_PWM_LPSS_PCI) +=3D pwm-lpss-pci.o obj-$(CONFIG_PWM_LPSS_PLATFORM) +=3D pwm-lpss-platform.o obj-$(CONFIG_PWM_MESON) +=3D pwm-meson.o obj-$(CONFIG_PWM_MEDIATEK) +=3D pwm-mediatek.o +obj-$(CONFIG_PWM_MICROCHIP_CORE) +=3D pwm-microchip-core.o obj-$(CONFIG_PWM_MTK_DISP) +=3D pwm-mtk-disp.o obj-$(CONFIG_PWM_MXS) +=3D pwm-mxs.o obj-$(CONFIG_PWM_NTXEC) +=3D pwm-ntxec.o diff --git a/drivers/pwm/pwm-microchip-core.c b/drivers/pwm/pwm-microchip-c= ore.c new file mode 100644 index 000000000000..3471eb2c8645 --- /dev/null +++ b/drivers/pwm/pwm-microchip-core.c @@ -0,0 +1,355 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * corePWM driver for Microchip "soft" FPGA IP cores. + * + * Copyright (c) 2021-2022 Microchip Corporation. All rights reserved. + * Author: Conor Dooley + * Documentation: + * https://www.microsemi.com/document-portal/doc_download/1245275-corepwm-= hb + * + * Limitations: + * - If the IP block is configured without "shadow registers", all register + * writes will take effect immediately, causing glitches on the output. + * If shadow registers *are* enabled, a write to the "SYNC_UPDATE" regis= ter + * notifies the core that it needs to update the registers defining the + * waveform from the contents of the "shadow registers". + * - The IP block has no concept of a duty cycle, only rising/falling edge= s of + * the waveform. Unfortunately, if the rising & falling edges registers = have + * the same value written to them the IP block will do whichever of a ri= sing + * or a falling edge is possible. I.E. a 50% waveform at twice the reque= sted + * period. Therefore to get a 0% waveform, the output is set the max hig= h/low + * time depending on polarity. + * - The PWM period is set for the whole IP block not per channel. The dri= ver + * will only change the period if no other PWM output is enabled. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PREG_TO_VAL(PREG) ((PREG) + 1) + +#define MCHPCOREPWM_PRESCALE_MAX 0x100 +#define MCHPCOREPWM_PERIOD_STEPS_MAX 0xff +#define MCHPCOREPWM_PERIOD_MAX 0xff00 + +#define MCHPCOREPWM_PRESCALE 0x00 +#define MCHPCOREPWM_PERIOD 0x04 +#define MCHPCOREPWM_EN(i) (0x08 + 0x04 * (i)) /* 0x08, 0x0c */ +#define MCHPCOREPWM_POSEDGE(i) (0x10 + 0x08 * (i)) /* 0x10, 0x18, ..., 0x8= 8 */ +#define MCHPCOREPWM_NEGEDGE(i) (0x14 + 0x08 * (i)) /* 0x14, 0x1c, ..., 0x8= c */ +#define MCHPCOREPWM_SYNC_UPD 0xe4 + +struct mchp_core_pwm_chip { + struct pwm_chip chip; + struct clk *clk; + spinlock_t lock; /* protect the shared period */ + void __iomem *base; + u32 sync_update_mask; +}; + +static inline struct mchp_core_pwm_chip *to_mchp_core_pwm(struct pwm_chip = *chip) +{ + return container_of(chip, struct mchp_core_pwm_chip, chip); +} + +static void mchp_core_pwm_enable(struct pwm_chip *chip, struct pwm_device = *pwm, bool enable) +{ + struct mchp_core_pwm_chip *mchp_core_pwm =3D to_mchp_core_pwm(chip); + u8 channel_enable, reg_offset, shift; + + /* + * There are two adjacent 8 bit control regs, the lower reg controls + * 0-7 and the upper reg 8-15. Check if the pwm is in the upper reg + * and if so, offset by the bus width. + */ + reg_offset =3D MCHPCOREPWM_EN(pwm->hwpwm >> 3); + shift =3D pwm->hwpwm > 7 ? pwm->hwpwm - 8 : pwm->hwpwm; + + spin_lock(&mchp_core_pwm->lock); + + channel_enable =3D readb_relaxed(mchp_core_pwm->base + reg_offset); + channel_enable &=3D ~(1 << shift); + channel_enable |=3D (enable << shift); + + writel_relaxed(channel_enable, mchp_core_pwm->base + reg_offset); + + /* + * Write to the sync update registers so that channels with shadow + * registers will also get their enable update. This operation is a NOP + * for channels without shadow registers. + */ + writel_relaxed(1U, mchp_core_pwm->base + MCHPCOREPWM_SYNC_UPD); + + spin_unlock(&mchp_core_pwm->lock); +} + +static void mchp_core_pwm_apply_duty(struct pwm_chip *chip, struct pwm_dev= ice *pwm, + const struct pwm_state *state, u8 prescale, u8 period_steps) +{ + struct mchp_core_pwm_chip *mchp_core_pwm =3D to_mchp_core_pwm(chip); + u64 duty_steps, period, tmp; + u8 posedge, negedge; + u16 prescale_val =3D PREG_TO_VAL(prescale); + u8 period_steps_val =3D PREG_TO_VAL(period_steps); + + period =3D period_steps_val * prescale_val * NSEC_PER_SEC; + period =3D DIV64_U64_ROUND_UP(period, clk_get_rate(mchp_core_pwm->clk)); + + /* + * Calculate the duty cycle in multiples of the prescaled period: + * duty_steps =3D duty_in_ns / step_in_ns + * step_in_ns =3D (prescale * NSEC_PER_SEC) / clk_rate + * The code below is rearranged slightly to only divide once. + * + * Because the period is per channel, it is possible that the requested + * duty cycle is longer than the period, in which case cap it to the + * period. + */ + if (state->duty_cycle > period) { + duty_steps =3D period_steps_val; + } else { + duty_steps =3D state->duty_cycle * clk_get_rate(mchp_core_pwm->clk); + tmp =3D prescale_val * NSEC_PER_SEC; + duty_steps =3D div64_u64(duty_steps, tmp); + } + + /* + * Turn the output on unless posedge =3D=3D negedge, in which case the + * duty is intended to be 0, but limitations of the IP block don't + * allow a zero length duty cycle - so just set the max high/low time + * respectively. + */ + if (state->polarity =3D=3D PWM_POLARITY_INVERSED) { + negedge =3D !duty_steps ? period_steps_val : 0u; + posedge =3D duty_steps; + } else { + posedge =3D !duty_steps ? period_steps_val : 0u; + negedge =3D duty_steps; + } + + writel_relaxed(posedge, mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hw= pwm)); + writel_relaxed(negedge, mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hw= pwm)); +} + +static int mchp_core_pwm_apply_period(struct pwm_chip *chip, const struct = pwm_state *state, + u8 *prescale, u8 *period_steps) +{ + struct mchp_core_pwm_chip *mchp_core_pwm =3D to_mchp_core_pwm(chip); + u64 tmp, clk_rate; + u16 prescale_val, period_steps_val; + + /* + * Calculate the period cycles and prescale values. + * The registers are each 8 bits wide & multiplied to compute the period + * using the formula: + * (clock_period) * (prescale + 1) * (period_steps + 1) + * so the maximum period that can be generated is 0x10000 times the + * period of the input clock. + * However, due to the design of the "hardware", it is not possible to + * attain a 100% duty cycle if the full range of period_steps is used. + * Therefore period_steps is restricted to 0xFE and the maximum multiple + * of the clock period attainable is 0xFF00. + */ + clk_rate =3D clk_get_rate(mchp_core_pwm->clk); + if (clk_rate >=3D NSEC_PER_SEC) + return -EINVAL; + + tmp =3D mul_u64_u64_div_u64(state->period, clk_rate, NSEC_PER_SEC); + + if (tmp >=3D MCHPCOREPWM_PERIOD_MAX) { + *prescale =3D MCHPCOREPWM_PRESCALE_MAX - 1; + *period_steps =3D MCHPCOREPWM_PERIOD_STEPS_MAX - 1; + goto write_registers; + } + + for (prescale_val =3D 1; prescale_val <=3D MCHPCOREPWM_PRESCALE_MAX; pres= cale_val++) { + period_steps_val =3D div_u64(tmp, prescale_val); + if (period_steps_val > MCHPCOREPWM_PERIOD_STEPS_MAX) + continue; + *period_steps =3D period_steps_val - 1; + *prescale =3D prescale_val - 1; + break; + } + +write_registers: + writel_relaxed(*prescale, mchp_core_pwm->base + MCHPCOREPWM_PRESCALE); + writel_relaxed(*period_steps, mchp_core_pwm->base + MCHPCOREPWM_PERIOD); + + return 0; +} + +static int mchp_core_pwm_apply(struct pwm_chip *chip, struct pwm_device *p= wm, + const struct pwm_state *state) +{ + struct mchp_core_pwm_chip *mchp_core_pwm =3D to_mchp_core_pwm(chip); + struct pwm_state current_state =3D pwm->state; + bool period_locked; + u64 period; + u16 channel_enabled; + u8 prescale, period_steps; + int ret; + + if (!state->enabled) { + mchp_core_pwm_enable(chip, pwm, false); + return 0; + } + + /* + * If the only thing that has changed is the duty cycle or the polarity, + * we can shortcut the calculations and just compute/apply the new duty + * cycle pos & neg edges + * As all the channels share the same period, do not allow it to be + * changed if any other channels are enabled. + */ + spin_lock(&mchp_core_pwm->lock); + + channel_enabled =3D (((u16)readb_relaxed(mchp_core_pwm->base + MCHPCOREPW= M_EN(1)) << 8) | + readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_EN(0))); + period_locked =3D channel_enabled & ~(1 << pwm->hwpwm); + + if ((!current_state.enabled || current_state.period !=3D state->period) &= & !period_locked) { + ret =3D mchp_core_pwm_apply_period(chip, state, &prescale, &period_steps= ); + if (ret) { + spin_unlock(&mchp_core_pwm->lock); + return ret; + } + } else { + prescale =3D readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE); + period_steps =3D readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD); + } + + /* + * If the period is locked, it may not be possible to use a period less + * than that requested. + */ + period =3D PREG_TO_VAL(period_steps) * PREG_TO_VAL(prescale) * NSEC_PER_= SEC; + do_div(period, clk_get_rate(mchp_core_pwm->clk)); + if (period > state->period) { + spin_unlock(&mchp_core_pwm->lock); + return -EINVAL; + } + + mchp_core_pwm_apply_duty(chip, pwm, state, prescale, period_steps); + + /* + * Notify the block to update the waveform from the shadow registers. + * The updated values will not appear on the bus until they have been + * applied to the waveform at the beginning of the next period. We must + * write these registers and wait for them to be applied before calling + * enable(). + */ + if (mchp_core_pwm->sync_update_mask & (1 << pwm->hwpwm)) { + writel_relaxed(1U, mchp_core_pwm->base + MCHPCOREPWM_SYNC_UPD); + usleep_range(state->period, state->period * 2); + } + + spin_unlock(&mchp_core_pwm->lock); + + mchp_core_pwm_enable(chip, pwm, true); + + return 0; +} + +static void mchp_core_pwm_get_state(struct pwm_chip *chip, struct pwm_devi= ce *pwm, + struct pwm_state *state) +{ + struct mchp_core_pwm_chip *mchp_core_pwm =3D to_mchp_core_pwm(chip); + u8 prescale, period_steps, duty_steps; + u8 posedge, negedge; + u16 channel_enabled; + + channel_enabled =3D (((u16)readb_relaxed(mchp_core_pwm->base + MCHPCOREPW= M_EN(1)) << 8) | + readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_EN(0))); + + if (channel_enabled & 1 << pwm->hwpwm) + state->enabled =3D true; + else + state->enabled =3D false; + + prescale =3D PREG_TO_VAL(readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_= PRESCALE)); + + posedge =3D readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->= hwpwm)); + negedge =3D readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->= hwpwm)); + + duty_steps =3D abs((s16)posedge - (s16)negedge); + state->duty_cycle =3D duty_steps * prescale * NSEC_PER_SEC; + do_div(state->duty_cycle, clk_get_rate(mchp_core_pwm->clk)); + + state->polarity =3D negedge < posedge ? PWM_POLARITY_INVERSED : PWM_POLAR= ITY_NORMAL; + + period_steps =3D PREG_TO_VAL(readb_relaxed(mchp_core_pwm->base + MCHPCORE= PWM_PERIOD)); + state->period =3D period_steps * prescale * NSEC_PER_SEC; + do_div(state->period, clk_get_rate(mchp_core_pwm->clk)); +} + +static const struct pwm_ops mchp_core_pwm_ops =3D { + .apply =3D mchp_core_pwm_apply, + .get_state =3D mchp_core_pwm_get_state, + .owner =3D THIS_MODULE, +}; + +static const struct of_device_id mchp_core_of_match[] =3D { + { + .compatible =3D "microchip,corepwm-rtl-v4", + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, mchp_core_of_match); + +static int mchp_core_pwm_probe(struct platform_device *pdev) +{ + struct mchp_core_pwm_chip *mchp_pwm; + struct resource *regs; + int ret; + + mchp_pwm =3D devm_kzalloc(&pdev->dev, sizeof(*mchp_pwm), GFP_KERNEL); + if (!mchp_pwm) + return -ENOMEM; + + mchp_pwm->base =3D devm_platform_get_and_ioremap_resource(pdev, 0, ®s); + if (IS_ERR(mchp_pwm->base)) + return PTR_ERR(mchp_pwm->base); + + mchp_pwm->clk =3D devm_clk_get_enabled(&pdev->dev, NULL); + if (IS_ERR(mchp_pwm->clk)) + return PTR_ERR(mchp_pwm->clk); + + if (of_property_read_u32(pdev->dev.of_node, "microchip,sync-update-mask", + &mchp_pwm->sync_update_mask)) + mchp_pwm->sync_update_mask =3D 0u; + + spin_lock_init(&mchp_pwm->lock); + + mchp_pwm->chip.dev =3D &pdev->dev; + mchp_pwm->chip.ops =3D &mchp_core_pwm_ops; + mchp_pwm->chip.npwm =3D 16; + + ret =3D devm_pwmchip_add(&pdev->dev, &mchp_pwm->chip); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n"); + + platform_set_drvdata(pdev, mchp_pwm); + + return 0; +} + +static struct platform_driver mchp_core_pwm_driver =3D { + .driver =3D { + .name =3D "mchp-core-pwm", + .of_match_table =3D mchp_core_of_match, + }, + .probe =3D mchp_core_pwm_probe, +}; +module_platform_driver(mchp_core_pwm_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Conor Dooley "); +MODULE_DESCRIPTION("corePWM driver for Microchip FPGAs"); --=20 2.36.1 From nobody Sun Apr 19 00:44:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03F15C433EF for ; Fri, 8 Jul 2022 14:30:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238187AbiGHOaZ (ORCPT ); Fri, 8 Jul 2022 10:30:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51258 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238148AbiGHOaR (ORCPT ); Fri, 8 Jul 2022 10:30:17 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F2F2326E6; Fri, 8 Jul 2022 07:30:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1657290616; x=1688826616; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fnl5CGvXmbwoIcy91psfgiwxnD3o6LZLHepJqwb/OE0=; b=ZKxTDAwRjdI7OnXWJtlxXl5RWPXvZ0c3gjf668vGlO8gZwLwIgtnoy67 MzubyA3vWZH4rXD/UmDG5ZlmOWjAV6bZXE4ytTFSiI/j1KqLw78AHm+wa 32ffLnjXo9viwfMAQvHxkaXGN9BBYZs/nwNK0pjhXipSWzcKgMAg7avRp loSQj+gJT6HoVYGMbIpGnn45aS6GvvltjeJ5kIv5KKS/CxpYZFbMi+rzC fKSqF39dLnoJ6YnNs+2l1HJ35ie6Qwj/yxb3yi7oIlDUeH3diWcUf4edn Fz0cIdQyYCZp+Afw90WpOSI0yfAAfWltwKpBOeoiHFd+c2wDo3cdiKqsJ A==; X-IronPort-AV: E=Sophos;i="5.92,255,1650956400"; d="scan'208";a="171340873" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Jul 2022 07:30:16 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 8 Jul 2022 07:30:13 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 8 Jul 2022 07:30:11 -0700 From: Conor Dooley To: Thierry Reding , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , "Lee Jones" , Rob Herring , "Krzysztof Kozlowski" CC: Daire McNamara , , , , , Conor Dooley Subject: [PATCH v4 4/4] MAINTAINERS: add pwm to PolarFire SoC entry Date: Fri, 8 Jul 2022 15:29:38 +0100 Message-ID: <20220708142937.1120121-5-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220708142937.1120121-1-conor.dooley@microchip.com> References: <20220708142937.1120121-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the newly introduced pwm driver to the existing PolarFire SoC entry. Signed-off-by: Conor Dooley --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index d64d79eb36a2..f023ae8442ab 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17429,6 +17429,7 @@ L: linux-riscv@lists.infradead.org S: Supported F: arch/riscv/boot/dts/microchip/ F: drivers/mailbox/mailbox-mpfs.c +F: drivers/pwm/pwm-microchip-core.c F: drivers/rtc/rtc-mpfs.c F: drivers/soc/microchip/ F: drivers/spi/spi-microchip-core.c --=20 2.36.1