From nobody Sun Apr 19 00:26:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 511EAC433EF for ; Fri, 8 Jul 2022 10:52:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238080AbiGHKws (ORCPT ); Fri, 8 Jul 2022 06:52:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56408 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237850AbiGHKwr (ORCPT ); Fri, 8 Jul 2022 06:52:47 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id A6F2084EF3; Fri, 8 Jul 2022 03:52:46 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C6774106F; Fri, 8 Jul 2022 03:52:46 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.42]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D86203F70D; Fri, 8 Jul 2022 03:52:44 -0700 (PDT) From: Andre Przywara To: Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski Cc: Linus Walleij , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v13 1/7] dt-bindings: arm: sunxi: Add H616 EMAC compatible Date: Fri, 8 Jul 2022 11:52:29 +0100 Message-Id: <20220708105235.3983266-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220708105235.3983266-1-andre.przywara@arm.com> References: <20220708105235.3983266-1-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Allwinner H616 contains an "EMAC" Ethernet MAC compatible to the A64 version. Add it to the list of compatible strings. Signed-off-by: Andre Przywara Acked-by: Rob Herring --- .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-ema= c.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.ya= ml index 6a4831fd3616c..87f1306831cc9 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml @@ -22,6 +22,7 @@ properties: - enum: - allwinner,sun20i-d1-emac - allwinner,sun50i-h6-emac + - allwinner,sun50i-h616-emac - const: allwinner,sun50i-a64-emac =20 reg: --=20 2.25.1 From nobody Sun Apr 19 00:26:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21A10C433EF for ; Fri, 8 Jul 2022 10:52:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238088AbiGHKwv (ORCPT ); Fri, 8 Jul 2022 06:52:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56434 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237850AbiGHKwt (ORCPT ); Fri, 8 Jul 2022 06:52:49 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 65A1B84EFE; Fri, 8 Jul 2022 03:52:48 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8DA7A1655; Fri, 8 Jul 2022 03:52:48 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.42]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A16CD3F70D; Fri, 8 Jul 2022 03:52:46 -0700 (PDT) From: Andre Przywara To: Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski Cc: Linus Walleij , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v13 2/7] dt-bindings: pinctrl: sunxi: Make interrupts optional Date: Fri, 8 Jul 2022 11:52:30 +0100 Message-Id: <20220708105235.3983266-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220708105235.3983266-1-andre.przywara@arm.com> References: <20220708105235.3983266-1-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The R_PIO pinctrl device on the Allwinner H616 SoC does not have an interrupt (it features only two pins). However the binding requires at least naming one upstream interrupt, plus the #interrupt-cells and interrupt-controller properties. Drop the unconditional requirement for the interrupt properties, and make them dependent on being not this particular pinctrl device. Signed-off-by: Andre Przywara Reviewed-by: Rob Herring Acked-by: Samuel Holland --- .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-= pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a1= 0-pinctrl.yaml index bfce850c20351..360dcd757e9da 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl= .yaml +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl= .yaml @@ -133,14 +133,11 @@ patternProperties: =20 required: - "#gpio-cells" - - "#interrupt-cells" - compatible - reg - - interrupts - clocks - clock-names - gpio-controller - - interrupt-controller =20 allOf: # FIXME: We should have the pin bank supplies here, but not a lot of @@ -148,6 +145,19 @@ allOf: # warnings. =20 - $ref: "pinctrl.yaml#" + - if: + not: + properties: + compatible: + enum: + - allwinner,sun50i-h616-r-pinctrl + + then: + required: + - "#interrupt-cells" + - interrupts + - interrupt-controller + - if: properties: compatible: --=20 2.25.1 From nobody Sun Apr 19 00:26:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F7F4C433EF for ; Fri, 8 Jul 2022 10:52:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238098AbiGHKwz (ORCPT ); Fri, 8 Jul 2022 06:52:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56458 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238086AbiGHKwv (ORCPT ); Fri, 8 Jul 2022 06:52:51 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 2FEAB84EFE; Fri, 8 Jul 2022 03:52:50 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5825D1682; Fri, 8 Jul 2022 03:52:50 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.42]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 695613F70D; Fri, 8 Jul 2022 03:52:48 -0700 (PDT) From: Andre Przywara To: Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski Cc: Linus Walleij , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v13 3/7] arm64: dts: allwinner: Add Allwinner H616 .dtsi file Date: Fri, 8 Jul 2022 11:52:31 +0100 Message-Id: <20220708105235.3983266-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220708105235.3983266-1-andre.przywara@arm.com> References: <20220708105235.3983266-1-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This (relatively) new SoC is similar to the H6, but drops the (broken) PCIe support and the USB 3.0 controller. It also gets the management controller removed, which in turn removes *some*, but not all of the devices formerly dedicated to the ARISC (CPUS). And while there is still the extra sunxi interrupt controller, the package lacks the corresponding NMI pin, so no interrupts for the PMIC. The reserved memory node is actually handled by Trusted Firmware now, but U-Boot fails to propagate this to a separately loaded DTB, so we keep it in here for now, until U-Boot learns to do this properly. Signed-off-by: Andre Przywara Reviewed-by: Samuel Holland --- .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 591 ++++++++++++++++++ 1 file changed, 591 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun50i-h616.dtsi new file mode 100644 index 0000000000000..8a81baf7de249 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -0,0 +1,591 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2020 Arm Ltd. +// based on the H6 dtsi, which is: +// Copyright (C) 2017 Icenowy Zheng + +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + compatible =3D "arm,cortex-a53"; + device_type =3D "cpu"; + reg =3D <0>; + enable-method =3D "psci"; + clocks =3D <&ccu CLK_CPUX>; + }; + + cpu1: cpu@1 { + compatible =3D "arm,cortex-a53"; + device_type =3D "cpu"; + reg =3D <1>; + enable-method =3D "psci"; + clocks =3D <&ccu CLK_CPUX>; + }; + + cpu2: cpu@2 { + compatible =3D "arm,cortex-a53"; + device_type =3D "cpu"; + reg =3D <2>; + enable-method =3D "psci"; + clocks =3D <&ccu CLK_CPUX>; + }; + + cpu3: cpu@3 { + compatible =3D "arm,cortex-a53"; + device_type =3D "cpu"; + reg =3D <3>; + enable-method =3D "psci"; + clocks =3D <&ccu CLK_CPUX>; + }; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* + * 256 KiB reserved for Trusted Firmware-A (BL31). + * This is added by BL31 itself, but some bootloaders fail + * to propagate this into the DTB handed to kernels. + */ + secmon@40000000 { + reg =3D <0x0 0x40000000 0x0 0x40000>; + no-map; + }; + }; + + osc24M: osc24M-clk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <24000000>; + clock-output-names =3D "osc24M"; + }; + + pmu { + compatible =3D "arm,cortex-a53-pmu"; + interrupts =3D , + , + , + ; + interrupt-affinity =3D <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible =3D "arm,psci-0.2"; + method =3D "smc"; + }; + + timer { + compatible =3D "arm,armv8-timer"; + arm,no-tick-in-suspend; + interrupts =3D , + , + , + ; + }; + + soc { + compatible =3D "simple-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x0 0x0 0x40000000>; + + syscon: syscon@3000000 { + compatible =3D "allwinner,sun50i-h616-system-control"; + reg =3D <0x03000000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + sram_c: sram@28000 { + compatible =3D "mmio-sram"; + reg =3D <0x00028000 0x30000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0x00028000 0x30000>; + }; + }; + + ccu: clock@3001000 { + compatible =3D "allwinner,sun50i-h616-ccu"; + reg =3D <0x03001000 0x1000>; + clocks =3D <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>; + clock-names =3D "hosc", "losc", "iosc"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + watchdog: watchdog@30090a0 { + compatible =3D "allwinner,sun50i-h616-wdt", + "allwinner,sun6i-a31-wdt"; + reg =3D <0x030090a0 0x20>; + interrupts =3D ; + clocks =3D <&osc24M>; + }; + + pio: pinctrl@300b000 { + compatible =3D "allwinner,sun50i-h616-pinctrl"; + reg =3D <0x0300b000 0x400>; + interrupts =3D , + , + , + , + , + , + , + ; + clocks =3D <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>; + clock-names =3D "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells =3D <3>; + interrupt-controller; + #interrupt-cells =3D <3>; + + ext_rgmii_pins: rgmii-pins { + pins =3D "PI0", "PI1", "PI2", "PI3", "PI4", + "PI5", "PI7", "PI8", "PI9", "PI10", + "PI11", "PI12", "PI13", "PI14", "PI15", + "PI16"; + function =3D "emac0"; + drive-strength =3D <40>; + }; + + i2c0_pins: i2c0-pins { + pins =3D "PI6", "PI7"; + function =3D "i2c0"; + }; + + i2c3_ph_pins: i2c3-ph-pins { + pins =3D "PH4", "PH5"; + function =3D "i2c3"; + }; + + ir_rx_pin: ir-rx-pin { + pins =3D "PH10"; + function =3D "ir_rx"; + }; + + mmc0_pins: mmc0-pins { + pins =3D "PF0", "PF1", "PF2", "PF3", + "PF4", "PF5"; + function =3D "mmc0"; + drive-strength =3D <30>; + bias-pull-up; + }; + + /omit-if-no-ref/ + mmc1_pins: mmc1-pins { + pins =3D "PG0", "PG1", "PG2", "PG3", + "PG4", "PG5"; + function =3D "mmc1"; + drive-strength =3D <30>; + bias-pull-up; + }; + + mmc2_pins: mmc2-pins { + pins =3D "PC0", "PC1", "PC5", "PC6", + "PC8", "PC9", "PC10", "PC11", + "PC13", "PC14", "PC15", "PC16"; + function =3D "mmc2"; + drive-strength =3D <30>; + bias-pull-up; + }; + + /omit-if-no-ref/ + spi0_pins: spi0-pins { + pins =3D "PC0", "PC2", "PC4"; + function =3D "spi0"; + }; + + /omit-if-no-ref/ + spi0_cs0_pin: spi0-cs0-pin { + pins =3D "PC3"; + function =3D "spi0"; + }; + + /omit-if-no-ref/ + spi1_pins: spi1-pins { + pins =3D "PH6", "PH7", "PH8"; + function =3D "spi1"; + }; + + /omit-if-no-ref/ + spi1_cs0_pin: spi1-cs0-pin { + pins =3D "PH5"; + function =3D "spi1"; + }; + + uart0_ph_pins: uart0-ph-pins { + pins =3D "PH0", "PH1"; + function =3D "uart0"; + }; + + /omit-if-no-ref/ + uart1_pins: uart1-pins { + pins =3D "PG6", "PG7"; + function =3D "uart1"; + }; + + /omit-if-no-ref/ + uart1_rts_cts_pins: uart1-rts-cts-pins { + pins =3D "PG8", "PG9"; + function =3D "uart1"; + }; + }; + + gic: interrupt-controller@3021000 { + compatible =3D "arm,gic-400"; + reg =3D <0x03021000 0x1000>, + <0x03022000 0x2000>, + <0x03024000 0x2000>, + <0x03026000 0x2000>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <3>; + }; + + mmc0: mmc@4020000 { + compatible =3D "allwinner,sun50i-h616-mmc", + "allwinner,sun50i-a100-mmc"; + reg =3D <0x04020000 0x1000>; + clocks =3D <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; + clock-names =3D "ahb", "mmc"; + resets =3D <&ccu RST_BUS_MMC0>; + reset-names =3D "ahb"; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mmc0_pins>; + status =3D "disabled"; + max-frequency =3D <150000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-3_3v; + cap-sdio-irq; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mmc1: mmc@4021000 { + compatible =3D "allwinner,sun50i-h616-mmc", + "allwinner,sun50i-a100-mmc"; + reg =3D <0x04021000 0x1000>; + clocks =3D <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; + clock-names =3D "ahb", "mmc"; + resets =3D <&ccu RST_BUS_MMC1>; + reset-names =3D "ahb"; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mmc1_pins>; + status =3D "disabled"; + max-frequency =3D <150000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-3_3v; + cap-sdio-irq; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mmc2: mmc@4022000 { + compatible =3D "allwinner,sun50i-h616-emmc", + "allwinner,sun50i-a100-emmc"; + reg =3D <0x04022000 0x1000>; + clocks =3D <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; + clock-names =3D "ahb", "mmc"; + resets =3D <&ccu RST_BUS_MMC2>; + reset-names =3D "ahb"; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mmc2_pins>; + status =3D "disabled"; + max-frequency =3D <150000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-3_3v; + cap-sdio-irq; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + uart0: serial@5000000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x05000000 0x400>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&ccu CLK_BUS_UART0>; + resets =3D <&ccu RST_BUS_UART0>; + status =3D "disabled"; + }; + + uart1: serial@5000400 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x05000400 0x400>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&ccu CLK_BUS_UART1>; + resets =3D <&ccu RST_BUS_UART1>; + status =3D "disabled"; + }; + + uart2: serial@5000800 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x05000800 0x400>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&ccu CLK_BUS_UART2>; + resets =3D <&ccu RST_BUS_UART2>; + status =3D "disabled"; + }; + + uart3: serial@5000c00 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x05000c00 0x400>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&ccu CLK_BUS_UART3>; + resets =3D <&ccu RST_BUS_UART3>; + status =3D "disabled"; + }; + + uart4: serial@5001000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x05001000 0x400>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&ccu CLK_BUS_UART4>; + resets =3D <&ccu RST_BUS_UART4>; + status =3D "disabled"; + }; + + uart5: serial@5001400 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x05001400 0x400>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&ccu CLK_BUS_UART5>; + resets =3D <&ccu RST_BUS_UART5>; + status =3D "disabled"; + }; + + i2c0: i2c@5002000 { + compatible =3D "allwinner,sun50i-h616-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg =3D <0x05002000 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_I2C0>; + resets =3D <&ccu RST_BUS_I2C0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_pins>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c1: i2c@5002400 { + compatible =3D "allwinner,sun50i-h616-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg =3D <0x05002400 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_I2C1>; + resets =3D <&ccu RST_BUS_I2C1>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c2: i2c@5002800 { + compatible =3D "allwinner,sun50i-h616-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg =3D <0x05002800 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_I2C2>; + resets =3D <&ccu RST_BUS_I2C2>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c3: i2c@5002c00 { + compatible =3D "allwinner,sun50i-h616-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg =3D <0x05002c00 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_I2C3>; + resets =3D <&ccu RST_BUS_I2C3>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c4: i2c@5003000 { + compatible =3D "allwinner,sun50i-h616-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg =3D <0x05003000 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_I2C4>; + resets =3D <&ccu RST_BUS_I2C4>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + spi0: spi@5010000 { + compatible =3D "allwinner,sun50i-h616-spi", + "allwinner,sun8i-h3-spi"; + reg =3D <0x05010000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names =3D "ahb", "mod"; + resets =3D <&ccu RST_BUS_SPI0>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + spi1: spi@5011000 { + compatible =3D "allwinner,sun50i-h616-spi", + "allwinner,sun8i-h3-spi"; + reg =3D <0x05011000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; + clock-names =3D "ahb", "mod"; + resets =3D <&ccu RST_BUS_SPI1>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + emac0: ethernet@5020000 { + compatible =3D "allwinner,sun50i-h616-emac", + "allwinner,sun50i-a64-emac"; + reg =3D <0x05020000 0x10000>; + interrupts =3D ; + interrupt-names =3D "macirq"; + clocks =3D <&ccu CLK_BUS_EMAC0>; + clock-names =3D "stmmaceth"; + resets =3D <&ccu RST_BUS_EMAC0>; + reset-names =3D "stmmaceth"; + syscon =3D <&syscon>; + status =3D "disabled"; + + mdio0: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + rtc: rtc@7000000 { + compatible =3D "allwinner,sun50i-h616-rtc"; + reg =3D <0x07000000 0x400>; + interrupts =3D ; + clocks =3D <&r_ccu CLK_R_APB1_RTC>, <&osc24M>, + <&ccu CLK_PLL_SYSTEM_32K>; + clock-names =3D "bus", "hosc", + "pll-32k"; + #clock-cells =3D <1>; + }; + + r_ccu: clock@7010000 { + compatible =3D "allwinner,sun50i-h616-r-ccu"; + reg =3D <0x07010000 0x210>; + clocks =3D <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, + <&ccu CLK_PLL_PERIPH0>; + clock-names =3D "hosc", "losc", "iosc", "pll-periph"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + r_pio: pinctrl@7022000 { + compatible =3D "allwinner,sun50i-h616-r-pinctrl"; + reg =3D <0x07022000 0x400>; + clocks =3D <&r_ccu CLK_R_APB1>, <&osc24M>, + <&rtc CLK_OSC32K>; + clock-names =3D "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells =3D <3>; + + /omit-if-no-ref/ + r_i2c_pins: r-i2c-pins { + pins =3D "PL0", "PL1"; + function =3D "s_i2c"; + }; + + r_rsb_pins: r-rsb-pins { + pins =3D "PL0", "PL1"; + function =3D "s_rsb"; + }; + }; + + ir: ir@7040000 { + compatible =3D "allwinner,sun50i-h616-ir", + "allwinner,sun6i-a31-ir"; + reg =3D <0x07040000 0x400>; + interrupts =3D ; + clocks =3D <&r_ccu CLK_R_APB1_IR>, + <&r_ccu CLK_IR>; + clock-names =3D "apb", "ir"; + resets =3D <&r_ccu RST_R_APB1_IR>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ir_rx_pin>; + status =3D "disabled"; + }; + + r_i2c: i2c@7081400 { + compatible =3D "allwinner,sun50i-h616-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg =3D <0x07081400 0x400>; + interrupts =3D ; + clocks =3D <&r_ccu CLK_R_APB2_I2C>; + resets =3D <&r_ccu RST_R_APB2_I2C>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + r_rsb: rsb@7083000 { + compatible =3D "allwinner,sun50i-h616-rsb", + "allwinner,sun8i-a23-rsb"; + reg =3D <0x07083000 0x400>; + interrupts =3D ; + clocks =3D <&r_ccu CLK_R_APB2_RSB>; + clock-frequency =3D <3000000>; + resets =3D <&r_ccu RST_R_APB2_RSB>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&r_rsb_pins>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; --=20 2.25.1 From nobody Sun Apr 19 00:26:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9191CCA480 for ; Fri, 8 Jul 2022 10:52:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238101AbiGHKw5 (ORCPT ); Fri, 8 Jul 2022 06:52:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56474 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237850AbiGHKww (ORCPT ); Fri, 8 Jul 2022 06:52:52 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id EF0CA87369; Fri, 8 Jul 2022 03:52:51 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 231191063; Fri, 8 Jul 2022 03:52:52 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.42]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 334623F70D; Fri, 8 Jul 2022 03:52:50 -0700 (PDT) From: Andre Przywara To: Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski Cc: Linus Walleij , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v13 4/7] dt-bindings: pinctrl: sunxi: allow vcc-pi-supply Date: Fri, 8 Jul 2022 11:52:32 +0100 Message-Id: <20220708105235.3983266-5-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220708105235.3983266-1-andre.przywara@arm.com> References: <20220708105235.3983266-1-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Allwinner H616 SoC contains a VCC_PI pin, which supplies the voltage for GPIO port I. Extend the range of supply port names to include vcc-pi-supply to cover that. Signed-off-by: Andre Przywara Acked-by: Rob Herring Acked-by: Samuel Holland --- .../bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-= pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a1= 0-pinctrl.yaml index 360dcd757e9da..0681b9a3965f0 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl= .yaml +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl= .yaml @@ -127,7 +127,7 @@ patternProperties: =20 additionalProperties: false =20 - "^vcc-p[a-hlm]-supply$": + "^vcc-p[a-ilm]-supply$": description: Power supplies for pin banks. =20 --=20 2.25.1 From nobody Sun Apr 19 00:26:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1595C433EF for ; Fri, 8 Jul 2022 10:53:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238113AbiGHKxC (ORCPT ); Fri, 8 Jul 2022 06:53:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56496 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238091AbiGHKwy (ORCPT ); Fri, 8 Jul 2022 06:52:54 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id CDA3687370; Fri, 8 Jul 2022 03:52:53 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F3F18106F; Fri, 8 Jul 2022 03:52:53 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.42]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F276E3F70D; Fri, 8 Jul 2022 03:52:51 -0700 (PDT) From: Andre Przywara To: Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski Cc: Linus Walleij , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v13 5/7] dt-bindings: arm: sunxi: Add two H616 board compatible strings Date: Fri, 8 Jul 2022 11:52:33 +0100 Message-Id: <20220708105235.3983266-6-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220708105235.3983266-1-andre.przywara@arm.com> References: <20220708105235.3983266-1-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds the two board compatible strings of two boards with the Allwinner H616 SoC. One is a development board from OrangePi, the other some TV box from some formerly unused vendor. Add that vendor to the vendor list on the way. Signed-off-by: Andre Przywara Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/sunxi.yaml | 10 ++++++++++ Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 2 files changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentati= on/devicetree/bindings/arm/sunxi.yaml index 95278a6a9a8ec..0c2356778208a 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -863,6 +863,11 @@ properties: - const: yones-toptech,bs1078-v2 - const: allwinner,sun6i-a31s =20 + - description: X96 Mate TV box + items: + - const: hechuang,x96-mate + - const: allwinner,sun50i-h616 + - description: Xunlong OrangePi items: - const: xunlong,orangepi @@ -963,4 +968,9 @@ properties: - const: xunlong,orangepi-zero-plus2-h3 - const: allwinner,sun8i-h3 =20 + - description: Xunlong OrangePi Zero 2 + items: + - const: xunlong,orangepi-zero2 + - const: allwinner,sun50i-h616 + additionalProperties: true diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 6bb20b4554d7e..628ca77949c73 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -507,6 +507,8 @@ patternProperties: description: Haoyu Microelectronic Co. Ltd. "^hardkernel,.*": description: Hardkernel Co., Ltd + "^hechuang,.*": + description: Shenzhen Hechuang Intelligent Co. "^hideep,.*": description: HiDeep Inc. "^himax,.*": --=20 2.25.1 From nobody Sun Apr 19 00:26:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47D36C433EF for ; Fri, 8 Jul 2022 10:53:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238117AbiGHKxF (ORCPT ); Fri, 8 Jul 2022 06:53:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238104AbiGHKw4 (ORCPT ); Fri, 8 Jul 2022 06:52:56 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 9D5E687340; Fri, 8 Jul 2022 03:52:55 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A6F6F1063; Fri, 8 Jul 2022 03:52:55 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.42]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D0CF33F70D; Fri, 8 Jul 2022 03:52:53 -0700 (PDT) From: Andre Przywara To: Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski Cc: Linus Walleij , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v13 6/7] arm64: dts: allwinner: h616: Add OrangePi Zero 2 board support Date: Fri, 8 Jul 2022 11:52:34 +0100 Message-Id: <20220708105235.3983266-7-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220708105235.3983266-1-andre.przywara@arm.com> References: <20220708105235.3983266-1-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The OrangePi Zero 2 is a development board with the new H616 SoC. It comes with the following features: - Four ARM Cortex-A53 cores, Mali-G31 MP2 GPU - 512MiB/1GiB DDR3 DRAM - AXP305 PMIC - Raspberry-Pi-1 compatible GPIO header - extra 13 pin expansion header, exposing pins for 2x USB 2.0 ports - 1 USB 2.0 host port - 1 USB 2.0 type C port (power supply + OTG) - MicroSD slot - on-board 2MiB bootable SPI NOR flash - 1Gbps Ethernet port (via RTL8211F PHY) - micro-HDMI port - (yet) unsupported Allwinner WiFi/BT chip Add the devicetree file describing the currently supported features. Signed-off-by: Andre Przywara Acked-by: Samuel Holland --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../allwinner/sun50i-h616-orangepi-zero2.dts | 213 ++++++++++++++++++ 2 files changed, 214 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero= 2.dts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/a= llwinner/Makefile index 8fa5c060a4fef..df2214e6d946a 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -38,3 +38,4 @@ dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h6-pine-h64.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h6-pine-h64-model-b.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h6-tanix-tx6.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h6-tanix-tx6-mini.dtb +dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h616-orangepi-zero2.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b= /arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts new file mode 100644 index 0000000000000..02893f3ac99d4 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts @@ -0,0 +1,213 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2020 Arm Ltd. + */ + +/dts-v1/; + +#include "sun50i-h616.dtsi" + +#include +#include +#include + +/ { + model =3D "OrangePi Zero2"; + compatible =3D "xunlong,orangepi-zero2", "allwinner,sun50i-h616"; + + aliases { + ethernet0 =3D &emac0; + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + leds { + compatible =3D "gpio-leds"; + + led-0 { + function =3D LED_FUNCTION_POWER; + color =3D ; + gpios =3D <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */ + default-state =3D "on"; + }; + + led-1 { + function =3D LED_FUNCTION_STATUS; + color =3D ; + gpios =3D <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */ + }; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the USB-C socket */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc-5v"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-always-on; + }; +}; + +&emac0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ext_rgmii_pins>; + phy-mode =3D "rgmii"; + phy-handle =3D <&ext_rgmii_phy>; + phy-supply =3D <®_dcdce>; + allwinner,rx-delay-ps =3D <3100>; + allwinner,tx-delay-ps =3D <700>; + status =3D "okay"; +}; + +&mdio0 { + ext_rgmii_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + }; +}; + +&mmc0 { + vmmc-supply =3D <®_dcdce>; + cd-gpios =3D <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + bus-width =3D <4>; + status =3D "okay"; +}; + +&r_rsb { + status =3D "okay"; + + axp305: pmic@745 { + compatible =3D "x-powers,axp305", "x-powers,axp805", + "x-powers,axp806"; + interrupt-controller; + #interrupt-cells =3D <1>; + reg =3D <0x745>; + + x-powers,self-working-mode; + vina-supply =3D <®_vcc5v>; + vinb-supply =3D <®_vcc5v>; + vinc-supply =3D <®_vcc5v>; + vind-supply =3D <®_vcc5v>; + vine-supply =3D <®_vcc5v>; + aldoin-supply =3D <®_vcc5v>; + bldoin-supply =3D <®_vcc5v>; + cldoin-supply =3D <®_vcc5v>; + + regulators { + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-sys"; + }; + + reg_aldo2: aldo2 { /* 3.3V on headers */ + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc3v3-ext"; + }; + + reg_aldo3: aldo3 { /* 3.3V on headers */ + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc3v3-ext2"; + }; + + reg_bldo1: bldo1 { + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc1v8"; + }; + + bldo2 { + /* unused */ + }; + + bldo3 { + /* unused */ + }; + + bldo4 { + /* unused */ + }; + + cldo1 { + /* reserved */ + }; + + cldo2 { + /* unused */ + }; + + cldo3 { + /* unused */ + }; + + reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt =3D <810000>; + regulator-max-microvolt =3D <1100000>; + regulator-name =3D "vdd-cpu"; + }; + + reg_dcdcc: dcdcc { + regulator-always-on; + regulator-min-microvolt =3D <810000>; + regulator-max-microvolt =3D <990000>; + regulator-name =3D "vdd-gpu-sys"; + }; + + reg_dcdcd: dcdcd { + regulator-always-on; + regulator-min-microvolt =3D <1500000>; + regulator-max-microvolt =3D <1500000>; + regulator-name =3D "vdd-dram"; + }; + + reg_dcdce: dcdce { + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-eth-mmc"; + }; + + sw { + /* unused */ + }; + }; + }; +}; + +&pio { + vcc-pc-supply =3D <®_aldo1>; + vcc-pf-supply =3D <®_aldo1>; + vcc-pg-supply =3D <®_bldo1>; + vcc-ph-supply =3D <®_aldo1>; + vcc-pi-supply =3D <®_aldo1>; +}; + +&spi0 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi0_pins>, <&spi0_cs0_pin>; + + flash@0 { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <40000000>; + }; +}; + +&uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_ph_pins>; + status =3D "okay"; +}; --=20 2.25.1 From nobody Sun Apr 19 00:26:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7AE24C43334 for ; Fri, 8 Jul 2022 10:53:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238040AbiGHKxJ (ORCPT ); Fri, 8 Jul 2022 06:53:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56542 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238108AbiGHKw6 (ORCPT ); Fri, 8 Jul 2022 06:52:58 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 3156884EF3; Fri, 8 Jul 2022 03:52:57 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5A5CF106F; Fri, 8 Jul 2022 03:52:57 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.42]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 824413F70D; Fri, 8 Jul 2022 03:52:55 -0700 (PDT) From: Andre Przywara To: Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski Cc: Linus Walleij , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v13 7/7] arm64: dts: allwinner: h616: Add X96 Mate TV box support Date: Fri, 8 Jul 2022 11:52:35 +0100 Message-Id: <20220708105235.3983266-8-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220708105235.3983266-1-andre.przywara@arm.com> References: <20220708105235.3983266-1-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The X96 Mate is an Allwinner H616 based TV box, featuring: - Four ARM Cortex-A53 cores, Mali-G31 MP2 GPU - 2GiB/4GiB RAM (fully usable!) - 16/32/64GiB eMMC - 100Mbps Ethernet (via embedded AC200 EPHY, not yet supported) - Unsupported Allwinner WiFi chip - 2 x USB 2.0 host ports - HDMI port - IR receiver - 5V/2A DC power supply via barrel plug Add a basic devicetree for it, with SD card and eMMC working, as well as serial and the essential peripherals, like the AXP PMIC. This DT is somewhat minimal, and should work on many other similar TV boxes with the Allwinner H616 chip. Signed-off-by: Andre Przywara Reviewed-by: Samuel Holland --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../dts/allwinner/sun50i-h616-x96-mate.dts | 177 ++++++++++++++++++ 2 files changed, 178 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/a= llwinner/Makefile index df2214e6d946a..6a96494a2e0a3 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -39,3 +39,4 @@ dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h6-pine-h64-model-b.= dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h6-tanix-tx6.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h6-tanix-tx6-mini.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h616-orangepi-zero2.dtb +dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h616-x96-mate.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts b/arch/= arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts new file mode 100644 index 0000000000000..6619db34714a4 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2021 Arm Ltd. + */ + +/dts-v1/; + +#include "sun50i-h616.dtsi" + +#include +#include + +/ { + model =3D "X96 Mate"; + compatible =3D "hechuang,x96-mate", "allwinner,sun50i-h616"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the DC input */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc-5v"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-always-on; + }; +}; + +&ir { + status =3D "okay"; +}; + +&mmc0 { + vmmc-supply =3D <®_dcdce>; + cd-gpios =3D <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + bus-width =3D <4>; + status =3D "okay"; +}; + +&mmc2 { + vmmc-supply =3D <®_dcdce>; + vqmmc-supply =3D <®_bldo1>; + bus-width =3D <8>; + non-removable; + cap-mmc-hw-reset; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + status =3D "okay"; +}; + +&r_rsb { + status =3D "okay"; + + axp305: pmic@745 { + compatible =3D "x-powers,axp305", "x-powers,axp805", + "x-powers,axp806"; + interrupt-controller; + #interrupt-cells =3D <1>; + reg =3D <0x745>; + + x-powers,self-working-mode; + vina-supply =3D <®_vcc5v>; + vinb-supply =3D <®_vcc5v>; + vinc-supply =3D <®_vcc5v>; + vind-supply =3D <®_vcc5v>; + vine-supply =3D <®_vcc5v>; + aldoin-supply =3D <®_vcc5v>; + bldoin-supply =3D <®_vcc5v>; + cldoin-supply =3D <®_vcc5v>; + + regulators { + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-sys"; + }; + + /* Enabled by the Android BSP */ + reg_aldo2: aldo2 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc3v3-ext"; + status =3D "disabled"; + }; + + /* Enabled by the Android BSP */ + reg_aldo3: aldo3 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc3v3-ext2"; + status =3D "disabled"; + }; + + reg_bldo1: bldo1 { + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc1v8"; + }; + + /* Enabled by the Android BSP */ + reg_bldo2: bldo2 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc1v8-2"; + status =3D "disabled"; + }; + + bldo3 { + /* unused */ + }; + + bldo4 { + /* unused */ + }; + + cldo1 { + regulator-min-microvolt =3D <2500000>; + regulator-max-microvolt =3D <2500000>; + regulator-name =3D "vcc2v5"; + }; + + cldo2 { + /* unused */ + }; + + cldo3 { + /* unused */ + }; + + reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt =3D <810000>; + regulator-max-microvolt =3D <1100000>; + regulator-name =3D "vdd-cpu"; + }; + + reg_dcdcc: dcdcc { + regulator-always-on; + regulator-min-microvolt =3D <810000>; + regulator-max-microvolt =3D <990000>; + regulator-name =3D "vdd-gpu-sys"; + }; + + reg_dcdcd: dcdcd { + regulator-always-on; + regulator-min-microvolt =3D <1360000>; + regulator-max-microvolt =3D <1360000>; + regulator-name =3D "vdd-dram"; + }; + + reg_dcdce: dcdce { + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-eth-mmc"; + }; + + sw { + /* unused */ + }; + }; + }; +}; + +&uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_ph_pins>; + status =3D "okay"; +}; --=20 2.25.1