From nobody Sun Apr 19 00:28:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5DD1C433EF for ; Fri, 8 Jul 2022 09:50:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237880AbiGHJuZ (ORCPT ); Fri, 8 Jul 2022 05:50:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39770 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237867AbiGHJuV (ORCPT ); Fri, 8 Jul 2022 05:50:21 -0400 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B376E81498 for ; Fri, 8 Jul 2022 02:50:17 -0700 (PDT) Received: by mail-pj1-x1032.google.com with SMTP id g16-20020a17090a7d1000b001ea9f820449so1396846pjl.5 for ; Fri, 08 Jul 2022 02:50:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bytedance-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4jkOqxcIBQLQ5eXTZyOJgkqi8V8OLaYB23LUkp1ByWQ=; b=1BQ/tfXanGFpMFjNAcJaktjsNTJO2Ix+TlfvkM8+DRdCM+TQJgbOKjIpF3MiANq3It c7hfVkGdQsdjKCLbbEjWgodkcKTUPOfsQ6bXqxpiuCSzKmawmYzxWzqxIYAtM+fdJ4uL 2OsyvV/scdUurXA5YlvqJksdhJTMcVKWIWjLknH5i/+aSa8x+VpWW9MImoS3Ci1or+x1 gIPYJorcVidrhYhYcDv5VzHBlb1o7j9vdkigw011F5prGRrWR5v00fjrkajH1kev1V5X Ldr88ehPn9JaZeJXLtdyI6Xa+KiFoYshqug9TIK+3oWpNP0xmI+X1IjMPOJ2nvxpdN6T me+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4jkOqxcIBQLQ5eXTZyOJgkqi8V8OLaYB23LUkp1ByWQ=; b=LtTUg0BxzGw7JjXeAoB/TYrCKu5tvaM3p1EiBcq3Sw3nZBRNe/W+sKL4nAVxPbdiIo fmkUCsOd9KVstUHk+WSYdYAYAhIZ19zF11n2Mk495WaefWCDnLDGqxupo/Gz+bL3AMtq t1G0VneNm01TbZKgPE6sC9PL7u2ZjjYy5giMabPqXikr5M0utSgDbWpYG2SbVxDCAG0U UbDObXbJ5Kr/2pmdlL3giBz0f+QWddYhlDfZV3TIuccPOw9TKRl24OqFwwT2vE3+H3wQ rsC4u8k9i8aD7RSzvyBizq4Nxi4qIbIZsJdaK2tXVLxIXr6Yqk2bB6iSCDerQrYrWYwE gx4w== X-Gm-Message-State: AJIora/CJomajoJNywYnych37anvNNgqOY+H6ZecCOsRy4yukkKfSF5r eRwDoxcHRNJfTZH13IuezOwoHw== X-Google-Smtp-Source: AGRyM1u7AMj7GkfbB3EyA7uxddW7w0Or4OxuSPugOlKsXFvBWgXG7+x3nFx/fqpi5m0+YBUIZ0NXMw== X-Received: by 2002:a17:903:2686:b0:16b:d663:5b4f with SMTP id jf6-20020a170903268600b0016bd6635b4fmr2773886plb.129.1657273817282; Fri, 08 Jul 2022 02:50:17 -0700 (PDT) Received: from C02DW0BEMD6R.bytedance.net ([139.177.225.235]) by smtp.gmail.com with ESMTPSA id c18-20020a621c12000000b0051bbd79fc9csm28551035pfc.57.2022.07.08.02.50.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 02:50:16 -0700 (PDT) From: Qi Zheng To: arnd@arndb.de, catalin.marinas@arm.com, will@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Qi Zheng Subject: [PATCH v1 1/2] arm64: run softirqs on the per-CPU IRQ stack Date: Fri, 8 Jul 2022 17:49:49 +0800 Message-Id: <20220708094950.41944-2-zhengqi.arch@bytedance.com> X-Mailer: git-send-email 2.24.3 (Apple Git-128) In-Reply-To: <20220708094950.41944-1-zhengqi.arch@bytedance.com> References: <20220708094950.41944-1-zhengqi.arch@bytedance.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently arm64 supports per-CPU IRQ stack, but softirqs are still handled in the task context. Since any call to local_bh_enable() at any level in the task's call stack may trigger a softirq processing run, which could potentially cause a task stack overflow if the combined stack footprints exceed the stack's size, let's run these softirqs on the IRQ stack as well. Signed-off-by: Qi Zheng Acked-by: Will Deacon Reviewed-by: Arnd Bergmann --- arch/arm64/Kconfig | 1 + arch/arm64/kernel/irq.c | 13 +++++++++++++ 2 files changed, 14 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 4c1e1d2d2f8b..be0a9f0052ee 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -230,6 +230,7 @@ config ARM64 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD select TRACE_IRQFLAGS_SUPPORT select TRACE_IRQFLAGS_NMI_SUPPORT + select HAVE_SOFTIRQ_ON_OWN_STACK help ARM 64-bit (AArch64) Linux support. =20 diff --git a/arch/arm64/kernel/irq.c b/arch/arm64/kernel/irq.c index bda49430c9ea..c36ad20a52f3 100644 --- a/arch/arm64/kernel/irq.c +++ b/arch/arm64/kernel/irq.c @@ -22,6 +22,7 @@ #include #include #include +#include =20 /* Only access this in an NMI enter/exit */ DEFINE_PER_CPU(struct nmi_ctx, nmi_contexts); @@ -71,6 +72,18 @@ static void init_irq_stacks(void) } #endif =20 +#ifndef CONFIG_PREEMPT_RT +static void ____do_softirq(struct pt_regs *regs) +{ + __do_softirq(); +} + +void do_softirq_own_stack(void) +{ + call_on_irq_stack(NULL, ____do_softirq); +} +#endif + static void default_handle_irq(struct pt_regs *regs) { panic("IRQ taken without a root IRQ handler\n"); --=20 2.20.1 From nobody Sun Apr 19 00:28:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BADF3C43334 for ; Fri, 8 Jul 2022 09:50:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237888AbiGHJu0 (ORCPT ); Fri, 8 Jul 2022 05:50:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39684 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237851AbiGHJuX (ORCPT ); Fri, 8 Jul 2022 05:50:23 -0400 Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 322278149D for ; Fri, 8 Jul 2022 02:50:21 -0700 (PDT) Received: by mail-pl1-x62c.google.com with SMTP id j12so9142101plj.8 for ; Fri, 08 Jul 2022 02:50:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bytedance-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CInbfRCxTX+lwwkZS0ynkKJhKDRk8XEefCQvvOFfbPc=; b=ClhBVlZfVVoQ+wE0Sn6Rnn1/9c8DzQQe6ttcNMbc2xCavg3qotM59YLWu/VmdcfDjC 2DJ0fsVR6N6KQUBChyvfwf78+eeIySZ3Gd+rrBvOc1Zwpxqk0SPqZuJDlaPMbZ8q2uuv UbHbx3qw3QiWfWMGiH3eUEdJuZjQ1icnwBtF7/+KfuV14dv4X3q8TQRtjMyFxWQ2idjz kUttfKOA/lct8cgjojawMCX32ZbjJsFfkyjnQho4+dLR9Bg9QKmSo7/dilbHTPw9XkVN K3KP3eroLTaBUHozYSNI19itv3VkatfEFZ8jLYOpUSjAluVakIZi3REAXmjCe45f0Mot aULg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CInbfRCxTX+lwwkZS0ynkKJhKDRk8XEefCQvvOFfbPc=; b=0whSovoWVbA77A89CjrUO9l8SGwrRAepZ8gnFSykNUpnJ1ka+QLrf+VaOF7WjKaLtP DWu3qIaPERadSW2eHsJ5Ad2z50srvQ0S3cWGlFsZWDHdKP7Nl/hU+afGDfNPhCNfeQe8 Mmgd1e2Kl59kERGEwhVBqw+mTNYyhFk0X0MFrRZXF71zVJzkAKvoGfwWuGvXo+ZJdI0t UHs8+P6rr7AyKWBSK4mItOdCVFfg3k4sK27BUz7cIpVt7SrGgGjEau7F2wmf/7Z3tJMa p6KW2KqFzTJfGOgdoi8UDBq6JPoaUHJYZTob3X980yd57FzkcPVO/tjQfPfEFtLQpqnK yujw== X-Gm-Message-State: AJIora+KrYapYVGgHePc13ZgxHi/ySZl5TCnR2Eu5/mQNRGxkzwjl4kM LebogtxBFKPIIUl3qAtAjC9mJJlyspzv7A== X-Google-Smtp-Source: AGRyM1tG2M7PjSIqi4dbhDxtx2UUOUHT2lI/8aPRs4+wPizXPgf2JHK3Q0g43E1i3OBy9b5r+6gNhA== X-Received: by 2002:a17:902:c992:b0:16b:d8b9:1c5f with SMTP id g18-20020a170902c99200b0016bd8b91c5fmr2786028plc.93.1657273820740; Fri, 08 Jul 2022 02:50:20 -0700 (PDT) Received: from C02DW0BEMD6R.bytedance.net ([139.177.225.235]) by smtp.gmail.com with ESMTPSA id c18-20020a621c12000000b0051bbd79fc9csm28551035pfc.57.2022.07.08.02.50.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 02:50:20 -0700 (PDT) From: Qi Zheng To: arnd@arndb.de, catalin.marinas@arm.com, will@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Qi Zheng Subject: [PATCH v1 2/2] arm64: support HAVE_IRQ_EXIT_ON_IRQ_STACK Date: Fri, 8 Jul 2022 17:49:50 +0800 Message-Id: <20220708094950.41944-3-zhengqi.arch@bytedance.com> X-Mailer: git-send-email 2.24.3 (Apple Git-128) In-Reply-To: <20220708094950.41944-1-zhengqi.arch@bytedance.com> References: <20220708094950.41944-1-zhengqi.arch@bytedance.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since softirqs are handled on the per-CPU IRQ stack, let's support HAVE_IRQ_EXIT_ON_IRQ_STACK which causes the core code to invoke __do_softirq() directly without going through do_softirq_own_stack(). Signed-off-by: Qi Zheng --- arch/arm64/Kconfig | 1 + arch/arm64/include/asm/exception.h | 4 +++- arch/arm64/kernel/entry-common.c | 30 ++++++++++++++++++++---------- arch/arm64/kernel/entry.S | 6 ++++-- arch/arm64/kernel/irq.c | 5 +++-- 5 files changed, 31 insertions(+), 15 deletions(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index be0a9f0052ee..d2cc7daecce3 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -231,6 +231,7 @@ config ARM64 select TRACE_IRQFLAGS_SUPPORT select TRACE_IRQFLAGS_NMI_SUPPORT select HAVE_SOFTIRQ_ON_OWN_STACK + select HAVE_IRQ_EXIT_ON_IRQ_STACK help ARM 64-bit (AArch64) Linux support. =20 diff --git a/arch/arm64/include/asm/exception.h b/arch/arm64/include/asm/ex= ception.h index d94aecff9690..8bff0aa7ab50 100644 --- a/arch/arm64/include/asm/exception.h +++ b/arch/arm64/include/asm/exception.h @@ -54,7 +54,9 @@ asmlinkage void el0t_32_fiq_handler(struct pt_regs *regs); asmlinkage void el0t_32_error_handler(struct pt_regs *regs); =20 asmlinkage void call_on_irq_stack(struct pt_regs *regs, - void (*func)(struct pt_regs *)); + void (*func)(struct pt_regs *), + void (*do_func)(struct pt_regs *, + void (*)(struct pt_regs *))); asmlinkage void asm_exit_to_user_mode(struct pt_regs *regs); =20 void do_mem_abort(unsigned long far, unsigned long esr, struct pt_regs *re= gs); diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-com= mon.c index c75ca36b4a49..935d1ab150b5 100644 --- a/arch/arm64/kernel/entry-common.c +++ b/arch/arm64/kernel/entry-common.c @@ -266,14 +266,16 @@ static void __sched arm64_preempt_schedule_irq(void) } =20 static void do_interrupt_handler(struct pt_regs *regs, - void (*handler)(struct pt_regs *)) + void (*handler)(struct pt_regs *), + void (*do_handler)(struct pt_regs *, + void (*)(struct pt_regs *))) { struct pt_regs *old_regs =3D set_irq_regs(regs); =20 if (on_thread_stack()) - call_on_irq_stack(regs, handler); + call_on_irq_stack(regs, handler, do_handler); else - handler(regs); + do_handler(regs, handler); =20 set_irq_regs(old_regs); } @@ -441,22 +443,32 @@ asmlinkage void noinstr el1h_64_sync_handler(struct p= t_regs *regs) } } =20 +static void nmi_handler(struct pt_regs *regs, void (*handler)(struct pt_re= gs *)) +{ + handler(regs); +} + static __always_inline void __el1_pnmi(struct pt_regs *regs, void (*handler)(struct pt_regs *)) { arm64_enter_nmi(regs); - do_interrupt_handler(regs, handler); + do_interrupt_handler(regs, handler, nmi_handler); arm64_exit_nmi(regs); } =20 +static void irq_handler(struct pt_regs *regs, void (*handler)(struct pt_re= gs *)) +{ + irq_enter_rcu(); + handler(regs); + irq_exit_rcu(); +} + static __always_inline void __el1_irq(struct pt_regs *regs, void (*handler)(struct pt_regs *)) { enter_from_kernel_mode(regs); =20 - irq_enter_rcu(); - do_interrupt_handler(regs, handler); - irq_exit_rcu(); + do_interrupt_handler(regs, handler, irq_handler); =20 arm64_preempt_schedule_irq(); =20 @@ -699,9 +711,7 @@ static void noinstr el0_interrupt(struct pt_regs *regs, if (regs->pc & BIT(55)) arm64_apply_bp_hardening(); =20 - irq_enter_rcu(); - do_interrupt_handler(regs, handler); - irq_exit_rcu(); + do_interrupt_handler(regs, handler, irq_handler); =20 exit_to_user_mode(regs); } diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 254fe31c03a0..1c351391f6bd 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -867,7 +867,9 @@ NOKPROBE(ret_from_fork) =20 /* * void call_on_irq_stack(struct pt_regs *regs, - * void (*func)(struct pt_regs *)); + * void (*func)(struct pt_regs *) + * void (*do_func)(struct pt_regs *, + * void (*)(struct pt_regs *))); * * Calls func(regs) using this CPU's irq stack and shadow irq stack. */ @@ -886,7 +888,7 @@ SYM_FUNC_START(call_on_irq_stack) =20 /* Move to the new stack and call the function there */ mov sp, x16 - blr x1 + blr x2 =20 /* * Restore the SP from the FP, and restore the FP and LR from the frame diff --git a/arch/arm64/kernel/irq.c b/arch/arm64/kernel/irq.c index c36ad20a52f3..003db605bc4f 100644 --- a/arch/arm64/kernel/irq.c +++ b/arch/arm64/kernel/irq.c @@ -73,14 +73,15 @@ static void init_irq_stacks(void) #endif =20 #ifndef CONFIG_PREEMPT_RT -static void ____do_softirq(struct pt_regs *regs) +static void ____do_softirq(struct pt_regs *regs, + void (*handler)(struct pt_regs *)) { __do_softirq(); } =20 void do_softirq_own_stack(void) { - call_on_irq_stack(NULL, ____do_softirq); + call_on_irq_stack(NULL, NULL, ____do_softirq); } #endif =20 --=20 2.20.1