From nobody Sat Sep 21 21:38:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE285C433EF for ; Fri, 8 Jul 2022 02:16:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235943AbiGHCQQ (ORCPT ); Thu, 7 Jul 2022 22:16:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235930AbiGHCQN (ORCPT ); Thu, 7 Jul 2022 22:16:13 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B2769735BE; Thu, 7 Jul 2022 19:16:11 -0700 (PDT) X-UUID: 98be3b3f05624c2dbac412fddffd324b-20220708 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8,REQID:c84d5ba6-739f-45a3-8fc7-3b94666ee26b,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:-5 X-CID-META: VersionHash:0f94e32,CLOUDID:8b6cb963-0b3f-4b2c-b3a6-ed5c044366a0,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: 98be3b3f05624c2dbac412fddffd324b-20220708 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 330383402; Fri, 08 Jul 2022 10:16:04 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 8 Jul 2022 10:16:04 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 8 Jul 2022 10:16:03 +0800 From: Xiangsheng Hou To: , , CC: , , , , , , Xiangsheng Hou Subject: [PATCH V3 1/2] arm64: dts: mt8173: Fix nor_flash node Date: Fri, 8 Jul 2022 10:15:47 +0800 Message-ID: <20220708021548.21453-2-xiangsheng.hou@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220708021548.21453-1-xiangsheng.hou@mediatek.com> References: <20220708021548.21453-1-xiangsheng.hou@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add axi clock since the driver change to DMA mode which need to enable axi clock. And change spi clock to 26MHz as default. Signed-off-by: Xiangsheng Hou Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts= /mediatek/mt8173.dtsi index 40d7b47fc52e..e603170100af 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -790,9 +790,12 @@ thermal: thermal@1100b000 { nor_flash: spi@1100d000 { compatible =3D "mediatek,mt8173-nor"; reg =3D <0 0x1100d000 0 0xe0>; + assigned-clocks =3D <&topckgen CLK_TOP_SPI_SEL>; + assigned-clock-parents =3D <&clk26m>; clocks =3D <&pericfg CLK_PERI_SPI>, - <&topckgen CLK_TOP_SPINFI_IFR_SEL>; - clock-names =3D "spi", "sf"; + <&topckgen CLK_TOP_SPINFI_IFR_SEL>, + <&pericfg CLK_PERI_NFI>; + clock-names =3D "spi", "sf", "axi"; #address-cells =3D <1>; #size-cells =3D <0>; status =3D "disabled"; --=20 2.25.1 From nobody Sat Sep 21 21:38:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DABB7C433EF for ; Fri, 8 Jul 2022 02:16:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237006AbiGHCQS (ORCPT ); Thu, 7 Jul 2022 22:16:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236946AbiGHCQN (ORCPT ); Thu, 7 Jul 2022 22:16:13 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D37ED73920; Thu, 7 Jul 2022 19:16:12 -0700 (PDT) X-UUID: 9f581c1d58584bb59cfb2a4ec83401bc-20220708 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8,REQID:fabd76fc-30d5-4a60-9fdd-d2df5de58071,OB:10,L OB:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,A CTION:release,TS:90 X-CID-INFO: VERSION:1.1.8,REQID:fabd76fc-30d5-4a60-9fdd-d2df5de58071,OB:10,LOB :0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:90 X-CID-META: VersionHash:0f94e32,CLOUDID:e86cb963-0b3f-4b2c-b3a6-ed5c044366a0,C OID:0a08b12eb58e,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: 9f581c1d58584bb59cfb2a4ec83401bc-20220708 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1753973875; Fri, 08 Jul 2022 10:16:07 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 8 Jul 2022 10:16:05 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 8 Jul 2022 10:16:05 +0800 From: Xiangsheng Hou To: , , CC: , , , , , , Xiangsheng Hou Subject: [PATCH V3 2/2] dt-bindings: mediatek: Add axi clock in mt8173 dts example Date: Fri, 8 Jul 2022 10:15:48 +0800 Message-ID: <20220708021548.21453-3-xiangsheng.hou@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220708021548.21453-1-xiangsheng.hou@mediatek.com> References: <20220708021548.21453-1-xiangsheng.hou@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" For mt8173, it is needed to add the axi clock for dma mode. Signed-off-by: Xiangsheng Hou --- .../devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yam= l b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml index 41e60fe4b09f..413b907eecf5 100644 --- a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml @@ -82,8 +82,8 @@ examples: compatible =3D "mediatek,mt8173-nor"; reg =3D <0 0x1100d000 0 0xe0>; interrupts =3D <1>; - clocks =3D <&pericfg CLK_PERI_SPI>, <&topckgen CLK_TOP_SPINFI_IFR_= SEL>; - clock-names =3D "spi", "sf"; + clocks =3D <&pericfg CLK_PERI_SPI>, <&topckgen CLK_TOP_SPINFI_IFR_= SEL>, <&pericfg CLK_PERI_NFI>; + clock-names =3D "spi", "sf", "axi"; #address-cells =3D <1>; #size-cells =3D <0>; =20 --=20 2.25.1