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([51.37.234.167]) by smtp.gmail.com with ESMTPSA id bn24-20020a056000061800b0020fe35aec4bsm38625743wrb.70.2022.07.07.15.04.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jul 2022 15:04:57 -0700 (PDT) From: Conor Dooley To: Paul Walmsley , Palmer Dabbelt , Palmer Dabbelt , Albert Ou , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , "Rafael J . Wysocki" Cc: Daire McNamara , Conor Dooley , Niklas Cassel , Damien Le Moal , Geert Uytterhoeven , Zong Li , Emil Renner Berthing , Jonas Hahnfeld , Guo Ren , Anup Patel , Atish Patra , Changbin Du , Heiko Stuebner , Philipp Tomsich , Rob Herring , Marc Zyngier , Viresh Kumar , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Brice Goglin Subject: [RFC 1/4] riscv: arch-topology: fix default topology reporting Date: Thu, 7 Jul 2022 23:04:34 +0100 Message-Id: <20220707220436.4105443-2-mail@conchuod.ie> X-Mailer: git-send-email 2.37.0 In-Reply-To: <20220707220436.4105443-1-mail@conchuod.ie> References: <20220707220436.4105443-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley RISC-V has no sane defaults to fall back on where there is no cpu-map in the devicetree. Without sane defaults, the package, core and thread IDs are all set to -1. This causes user-visible inaccuracies for tools like hwloc/lstopo which rely on the sysfs cpu topology files to detect a system's topology. Add sane defaults in ~the exact same way as ARM64. CC: stable@vger.kernel.org Fixes: 03f11f03dbfe ("RISC-V: Parse cpu topology during boot.") Reported-by: Brice Goglin Link: https://github.com/open-mpi/hwloc/issues/536 Signed-off-by: Conor Dooley --- Sudeep suggested that this be backported rather than the changes to the devicetrees adding cpu-map since that property is optional. That patchset is still valid in it's own right. Changes since v1: - removed the GENERIC_ARCH_TOPOLOGY dependancy on SMP - removed a duplicate call to update_siblings_masks() --- arch/riscv/Kconfig | 2 +- arch/riscv/include/asm/topology.h | 13 +++++++++++++ arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/smpboot.c | 5 ++++- arch/riscv/kernel/topology.c | 32 +++++++++++++++++++++++++++++++ 5 files changed, 51 insertions(+), 2 deletions(-) create mode 100644 arch/riscv/include/asm/topology.h create mode 100644 arch/riscv/kernel/topology.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 2af0701b7518..4b6c2fdbb57c 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -52,7 +52,7 @@ config RISCV select COMMON_CLK select CPU_PM if CPU_IDLE select EDAC_SUPPORT - select GENERIC_ARCH_TOPOLOGY if SMP + select GENERIC_ARCH_TOPOLOGY select GENERIC_ATOMIC64 if !64BIT select GENERIC_CLOCKEVENTS_BROADCAST if SMP select GENERIC_EARLY_IOREMAP diff --git a/arch/riscv/include/asm/topology.h b/arch/riscv/include/asm/top= ology.h new file mode 100644 index 000000000000..36bc6ecda898 --- /dev/null +++ b/arch/riscv/include/asm/topology.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries + */ + +#ifndef _ASM_RISCV_TOPOLOGY_H +#define _ASM_RISCV_TOPOLOGY_H + +#include + +void store_cpu_topology(unsigned int cpuid); + +#endif /* _ASM_RISCV_TOPOLOGY_H */ diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index c71d6591d539..9518882ba6f9 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -50,6 +50,7 @@ obj-y +=3D riscv_ksyms.o obj-y +=3D stacktrace.o obj-y +=3D cacheinfo.o obj-y +=3D patch.o +obj-y +=3D topology.o obj-y +=3D probes/ obj-$(CONFIG_MMU) +=3D vdso.o vdso/ =20 diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index f1e4948a4b52..a8239b4b61f3 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -32,6 +32,7 @@ #include #include #include +#include =20 #include "head.h" =20 @@ -40,6 +41,8 @@ static DECLARE_COMPLETION(cpu_running); void __init smp_prepare_boot_cpu(void) { init_cpu_topology(); + + store_cpu_topology(smp_processor_id()); } =20 void __init smp_prepare_cpus(unsigned int max_cpus) @@ -161,9 +164,9 @@ asmlinkage __visible void smp_callin(void) mmgrab(mm); current->active_mm =3D mm; =20 + store_cpu_topology(curr_cpuid); notify_cpu_starting(curr_cpuid); numa_add_cpu(curr_cpuid); - update_siblings_masks(curr_cpuid); set_cpu_online(curr_cpuid, 1); =20 /* diff --git a/arch/riscv/kernel/topology.c b/arch/riscv/kernel/topology.c new file mode 100644 index 000000000000..db72862bd5b5 --- /dev/null +++ b/arch/riscv/kernel/topology.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries + * + * Based on the arm64 version, which was in turn based on arm32, which was + * ultimately based on sh's. + * The arm64 version was listed as: + * Copyright (C) 2011,2013,2014 Linaro Limited. + */ + +#include +#include +#include + +void store_cpu_topology(unsigned int cpuid) +{ + struct cpu_topology *cpuid_topo =3D &cpu_topology[cpuid]; + + if (cpuid_topo->package_id !=3D -1) + goto topology_populated; + + cpuid_topo->thread_id =3D -1; + cpuid_topo->core_id =3D cpuid; + cpuid_topo->package_id =3D cpu_to_node(cpuid); + + pr_debug("CPU%u: package %d core %d thread %d\n", + cpuid, cpuid_topo->package_id, cpuid_topo->core_id, + cpuid_topo->thread_id); + +topology_populated: + update_siblings_masks(cpuid); +} --=20 2.37.0 From nobody Sun Apr 19 00:26:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 963BBC43334 for ; Thu, 7 Jul 2022 22:05:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236216AbiGGWFI (ORCPT ); Thu, 7 Jul 2022 18:05:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37416 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236684AbiGGWFC (ORCPT ); Thu, 7 Jul 2022 18:05:02 -0400 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2D7E72B1BA for ; Thu, 7 Jul 2022 15:05:01 -0700 (PDT) Received: by mail-wm1-x336.google.com with SMTP id v67-20020a1cac46000000b003a1888b9d36so120789wme.0 for ; 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([51.37.234.167]) by smtp.gmail.com with ESMTPSA id bn24-20020a056000061800b0020fe35aec4bsm38625743wrb.70.2022.07.07.15.04.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jul 2022 15:04:59 -0700 (PDT) From: Conor Dooley To: Paul Walmsley , Palmer Dabbelt , Palmer Dabbelt , Albert Ou , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , "Rafael J . Wysocki" Cc: Daire McNamara , Conor Dooley , Niklas Cassel , Damien Le Moal , Geert Uytterhoeven , Zong Li , Emil Renner Berthing , Jonas Hahnfeld , Guo Ren , Anup Patel , Atish Patra , Changbin Du , Heiko Stuebner , Philipp Tomsich , Rob Herring , Marc Zyngier , Viresh Kumar , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Brice Goglin Subject: [RFC 2/4] arch-topology: add a default implementation of store_cpu_topology() Date: Thu, 7 Jul 2022 23:04:35 +0100 Message-Id: <20220707220436.4105443-3-mail@conchuod.ie> X-Mailer: git-send-email 2.37.0 In-Reply-To: <20220707220436.4105443-1-mail@conchuod.ie> References: <20220707220436.4105443-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley RISC-V & arm64 both use an almost identical method of filling in default vales for arch topology. Create a weakly defined default implementation with the intent of migrating both archs to use it. Signed-off-by: Conor Dooley --- drivers/base/arch_topology.c | 19 +++++++++++++++++++ include/linux/arch_topology.h | 1 + 2 files changed, 20 insertions(+) diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c index 441e14ac33a4..07e84c6ac5c2 100644 --- a/drivers/base/arch_topology.c +++ b/drivers/base/arch_topology.c @@ -765,6 +765,25 @@ void update_siblings_masks(unsigned int cpuid) } } =20 +void __weak store_cpu_topology(unsigned int cpuid) +{ + struct cpu_topology *cpuid_topo =3D &cpu_topology[cpuid]; + + if (cpuid_topo->package_id !=3D -1) + goto topology_populated; + + cpuid_topo->thread_id =3D -1; + cpuid_topo->core_id =3D cpuid; + cpuid_topo->package_id =3D cpu_to_node(cpuid); + + pr_debug("CPU%u: package %d core %d thread %d\n", + cpuid, cpuid_topo->package_id, cpuid_topo->core_id, + cpuid_topo->thread_id); + +topology_populated: + update_siblings_masks(cpuid); +} + static void clear_cpu_topology(int cpu) { struct cpu_topology *cpu_topo =3D &cpu_topology[cpu]; diff --git a/include/linux/arch_topology.h b/include/linux/arch_topology.h index a07b510e7dc5..fee306b8a541 100644 --- a/include/linux/arch_topology.h +++ b/include/linux/arch_topology.h @@ -92,6 +92,7 @@ void update_siblings_masks(unsigned int cpu); void remove_cpu_topology(unsigned int cpuid); void reset_cpu_topology(void); int parse_acpi_topology(void); + #endif =20 #endif /* _LINUX_ARCH_TOPOLOGY_H_ */ --=20 2.37.0 From nobody Sun Apr 19 00:26:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B276C43334 for ; Thu, 7 Jul 2022 22:05:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236602AbiGGWFQ (ORCPT ); Thu, 7 Jul 2022 18:05:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37504 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236730AbiGGWFG (ORCPT ); Thu, 7 Jul 2022 18:05:06 -0400 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D3312CC8A for ; Thu, 7 Jul 2022 15:05:03 -0700 (PDT) Received: by mail-wr1-x42f.google.com with SMTP id q9so28128975wrd.8 for ; Thu, 07 Jul 2022 15:05:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hjZHB/xWJ3nWli7ZfNwXsxb5s5FyrkVe3kCR2sto3MY=; b=YAksl8QG4Ad+/zsLgP3rFBKEVMf4C2+ycllCQpHkGjWiGmXMrv44Fa5DhcIcWd6OL0 nSTFK6m5aqU3OdaAoJJlvx90zXqFH5x1SntHlfXOfmFM2szSOaT/cE4rNrCxUdQ0k/sb /MXyrA28CE+ypPlAWUYiPH/jh+0UZxSU6DqiijerAqCzqowZEABCeK7WJpCw83jCWrPN HOA9Wt1xlePu2vJNvPB59XhOaCfAaoCWjXki4pgl5sLkfmlFKReDiNi3ADDzQ/feC8+5 CEFG1S2hd5Dk7O/gc4h/Ij2d+6Dp0wuaAqLn9hrf7s2FMU0JpxwUaKqg4II8nREXih3L 4U8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hjZHB/xWJ3nWli7ZfNwXsxb5s5FyrkVe3kCR2sto3MY=; b=phKUZyr6zY4+r6HZCKfzuoL0Oyi/jT7Ju4Gc06xIaDflyswZ1zmOyZgvJNWAQ0i37Z G/S3rnQbdR7OND9rpeGcziEALkILwnscrs5Wgkr3/sS6GBNheO5Zs2iI5x9UcrAUDyWZ D37bdGIv4VE/FfOch2LHp4SlzM8ApA6czOrc21DCWAf4dewvp4jWhprAFT6z+knYBk2U sS1nEd+6nqmXnFAdLhBtcV5uphdZ9A4qZCX7AoNPrDx/hhHRMlQ7bCqQs6+vNXfuu2fP tWn+xmjNoV7CaAZ1fmu/iJnrQ2HIKsL4rSgUPnB/HOPOOQcya42nJ7w+APoIolfrgD1Q JKAw== X-Gm-Message-State: AJIora+bCdxBPd95DncRTKMIGzKdv651et5kbs+1B50lpJR3Y6RgqIri bBXcbIobXRiw/Uky616oh3S0sg== X-Google-Smtp-Source: AGRyM1ucM2HayA4Nu/4tlRlCtdGGmAk0G8SNuvQDYgL/iSBK+mKdFbxIG/Vfscu+gH+wgAlYNt1K1g== X-Received: by 2002:adf:d206:0:b0:21d:6434:a158 with SMTP id j6-20020adfd206000000b0021d6434a158mr66682wrh.37.1657231501756; Thu, 07 Jul 2022 15:05:01 -0700 (PDT) Received: from henark71.. ([51.37.234.167]) by smtp.gmail.com with ESMTPSA id bn24-20020a056000061800b0020fe35aec4bsm38625743wrb.70.2022.07.07.15.04.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jul 2022 15:05:01 -0700 (PDT) From: Conor Dooley To: Paul Walmsley , Palmer Dabbelt , Palmer Dabbelt , Albert Ou , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , "Rafael J . Wysocki" Cc: Daire McNamara , Conor Dooley , Niklas Cassel , Damien Le Moal , Geert Uytterhoeven , Zong Li , Emil Renner Berthing , Jonas Hahnfeld , Guo Ren , Anup Patel , Atish Patra , Changbin Du , Heiko Stuebner , Philipp Tomsich , Rob Herring , Marc Zyngier , Viresh Kumar , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Brice Goglin Subject: [RFC 3/4] riscv: arch-topology: move riscv to the generic store_cpu_topology() Date: Thu, 7 Jul 2022 23:04:36 +0100 Message-Id: <20220707220436.4105443-4-mail@conchuod.ie> X-Mailer: git-send-email 2.37.0 In-Reply-To: <20220707220436.4105443-1-mail@conchuod.ie> References: <20220707220436.4105443-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley The default implementation of store_cpu_topology() is exactly that used by RISC-V so revert the portions of aaaabbbbccccdddd ("riscv: arch-topology: fix default topology reporting") which add the arch specific version. Signed-off-by: Conor Dooley --- arch/riscv/include/asm/topology.h | 13 ------------- arch/riscv/kernel/Makefile | 1 - arch/riscv/kernel/smpboot.c | 1 - arch/riscv/kernel/topology.c | 32 ------------------------------- 4 files changed, 47 deletions(-) delete mode 100644 arch/riscv/include/asm/topology.h delete mode 100644 arch/riscv/kernel/topology.c diff --git a/arch/riscv/include/asm/topology.h b/arch/riscv/include/asm/top= ology.h deleted file mode 100644 index 36bc6ecda898..000000000000 --- a/arch/riscv/include/asm/topology.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries - */ - -#ifndef _ASM_RISCV_TOPOLOGY_H -#define _ASM_RISCV_TOPOLOGY_H - -#include - -void store_cpu_topology(unsigned int cpuid); - -#endif /* _ASM_RISCV_TOPOLOGY_H */ diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 9518882ba6f9..c71d6591d539 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -50,7 +50,6 @@ obj-y +=3D riscv_ksyms.o obj-y +=3D stacktrace.o obj-y +=3D cacheinfo.o obj-y +=3D patch.o -obj-y +=3D topology.o obj-y +=3D probes/ obj-$(CONFIG_MMU) +=3D vdso.o vdso/ =20 diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index a8239b4b61f3..a1c861f84fe2 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -32,7 +32,6 @@ #include #include #include -#include =20 #include "head.h" =20 diff --git a/arch/riscv/kernel/topology.c b/arch/riscv/kernel/topology.c deleted file mode 100644 index db72862bd5b5..000000000000 --- a/arch/riscv/kernel/topology.c +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries - * - * Based on the arm64 version, which was in turn based on arm32, which was - * ultimately based on sh's. - * The arm64 version was listed as: - * Copyright (C) 2011,2013,2014 Linaro Limited. - */ - -#include -#include -#include - -void store_cpu_topology(unsigned int cpuid) -{ - struct cpu_topology *cpuid_topo =3D &cpu_topology[cpuid]; - - if (cpuid_topo->package_id !=3D -1) - goto topology_populated; - - cpuid_topo->thread_id =3D -1; - cpuid_topo->core_id =3D cpuid; - cpuid_topo->package_id =3D cpu_to_node(cpuid); - - pr_debug("CPU%u: package %d core %d thread %d\n", - cpuid, cpuid_topo->package_id, cpuid_topo->core_id, - cpuid_topo->thread_id); - -topology_populated: - update_siblings_masks(cpuid); -} --=20 2.37.0 From nobody Sun Apr 19 00:26:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7EC37C43334 for ; Thu, 7 Jul 2022 22:05:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236791AbiGGWFM (ORCPT ); Thu, 7 Jul 2022 18:05:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37506 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236732AbiGGWFG (ORCPT ); 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([51.37.234.167]) by smtp.gmail.com with ESMTPSA id bn24-20020a056000061800b0020fe35aec4bsm38625743wrb.70.2022.07.07.15.05.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jul 2022 15:05:02 -0700 (PDT) From: Conor Dooley To: Paul Walmsley , Palmer Dabbelt , Palmer Dabbelt , Albert Ou , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , "Rafael J . Wysocki" Cc: Daire McNamara , Conor Dooley , Niklas Cassel , Damien Le Moal , Geert Uytterhoeven , Zong Li , Emil Renner Berthing , Jonas Hahnfeld , Guo Ren , Anup Patel , Atish Patra , Changbin Du , Heiko Stuebner , Philipp Tomsich , Rob Herring , Marc Zyngier , Viresh Kumar , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Brice Goglin Subject: [RFC 4/4] arm64: arch-topology move arm64 to the generic store_cpu_topology() Date: Thu, 7 Jul 2022 23:04:37 +0100 Message-Id: <20220707220436.4105443-5-mail@conchuod.ie> X-Mailer: git-send-email 2.37.0 In-Reply-To: <20220707220436.4105443-1-mail@conchuod.ie> References: <20220707220436.4105443-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley The default implementation of store_cpu_topology() was derived from the arm64 implementation, but with the mpidr bits removed. Extract the mpidr bits from the arch implementation to the callsites & use the generic version. Signed-off-by: Conor Dooley --- arch/arm64/kernel/smp.c | 16 +++++++++++++-- arch/arm64/kernel/topology.c | 40 ------------------------------------ 2 files changed, 14 insertions(+), 42 deletions(-) diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 62ed361a4376..9e8acaa4c2f7 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -234,7 +234,12 @@ asmlinkage notrace void secondary_start_kernel(void) * Log the CPU info before it is marked online and might get read. */ cpuinfo_store_cpu(); - store_cpu_topology(cpu); + + /* + * Uniprocessor systems can rely on default topology values + */ + if (!(mpidr & MPIDR_UP_BITMASK)) + store_cpu_topology(cpu); =20 /* * Enable GIC and timers. @@ -719,6 +724,7 @@ void __init smp_init_cpus(void) void __init smp_prepare_cpus(unsigned int max_cpus) { const struct cpu_operations *ops; + u64 mpidr; int err; unsigned int cpu; unsigned int this_cpu; @@ -726,7 +732,13 @@ void __init smp_prepare_cpus(unsigned int max_cpus) init_cpu_topology(); =20 this_cpu =3D smp_processor_id(); - store_cpu_topology(this_cpu); + mpidr =3D read_cpuid_mpidr(); + + /* + * Uniprocessor systems can rely on default topology values + */ + if (!(mpidr & MPIDR_UP_BITMASK)) + store_cpu_topology(this_cpu); numa_store_cpu_info(this_cpu); numa_add_cpu(this_cpu); =20 diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index 869ffc4d4484..7889a00f5487 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -22,46 +22,6 @@ #include #include =20 -void store_cpu_topology(unsigned int cpuid) -{ - struct cpu_topology *cpuid_topo =3D &cpu_topology[cpuid]; - u64 mpidr; - - if (cpuid_topo->package_id !=3D -1) - goto topology_populated; - - mpidr =3D read_cpuid_mpidr(); - - /* Uniprocessor systems can rely on default topology values */ - if (mpidr & MPIDR_UP_BITMASK) - return; - - /* - * This would be the place to create cpu topology based on MPIDR. - * - * However, it cannot be trusted to depict the actual topology; some - * pieces of the architecture enforce an artificial cap on Aff0 values - * (e.g. GICv3's ICC_SGI1R_EL1 limits it to 15), leading to an - * artificial cycling of Aff1, Aff2 and Aff3 values. IOW, these end up - * having absolutely no relationship to the actual underlying system - * topology, and cannot be reasonably used as core / package ID. - * - * If the MT bit is set, Aff0 *could* be used to define a thread ID, but - * we still wouldn't be able to obtain a sane core ID. This means we - * need to entirely ignore MPIDR for any topology deduction. - */ - cpuid_topo->thread_id =3D -1; - cpuid_topo->core_id =3D cpuid; - cpuid_topo->package_id =3D cpu_to_node(cpuid); - - pr_debug("CPU%u: cluster %d core %d thread %d mpidr %#016llx\n", - cpuid, cpuid_topo->package_id, cpuid_topo->core_id, - cpuid_topo->thread_id, mpidr); - -topology_populated: - update_siblings_masks(cpuid); -} - #ifdef CONFIG_ACPI static bool __init acpi_cpu_is_threaded(int cpu) { --=20 2.37.0