From nobody Sun Apr 19 00:46:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3911CCA479 for ; Thu, 7 Jul 2022 19:50:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236805AbiGGTuF (ORCPT ); Thu, 7 Jul 2022 15:50:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33452 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236367AbiGGTuE (ORCPT ); Thu, 7 Jul 2022 15:50:04 -0400 Received: from mx1.riseup.net (mx1.riseup.net [198.252.153.129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 15EF15A2E7 for ; Thu, 7 Jul 2022 12:50:02 -0700 (PDT) Received: from fews1.riseup.net (fews1-pn.riseup.net [10.0.1.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "mail.riseup.net", Issuer "R3" (not verified)) by mx1.riseup.net (Postfix) with ESMTPS id 4Lf6Sp2Dr6zDr4k; Thu, 7 Jul 2022 19:50:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1657223402; bh=ied7/wQBWyRAGNRM3YJQ9nmwASEEztOFVReHeNDPqs4=; h=From:To:Cc:Subject:Date:From; b=fOz0/Uf6U90A9zYKjLrYyhaK5DOKfrFIvBM0bBMLHLM9VoHoTj9ZNQ0iwIL5u+zEg AXXyOp3vVyjQtpP6Niv30wOp8BgS0agFINCJYPfOw15jlGX0oCHKxGiK25p318rtNi ZVCcN8sHivF7gRafsWqVjJfzsx2zMERBdPOxal4w= X-Riseup-User-ID: 8654BB5CEEAED37E29E93B549D0D383934D30FA2C2F8B642BBBDF6AF5CF020CD Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4Lf6Sk2jRDz5vXK; Thu, 7 Jul 2022 19:49:58 +0000 (UTC) From: =?UTF-8?q?Ma=C3=ADra=20Canal?= To: Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , christian.koenig@amd.com, Xinhui.Pan@amd.com, David Airlie , Daniel Vetter Cc: amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Ma=C3=ADra=20Canal?= Subject: [PATCH] drm/amd/display: Drop dm_sw_gfx7_2d_thin_l_vp and dm_sw_gfx7_2d_thin_gl Date: Thu, 7 Jul 2022 16:49:49 -0300 Message-Id: <20220707194949.103978-1-mairacanal@riseup.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As the enum dm_sw_gfx7_2d_thin_gl and dm_sw_gfx7_2d_thin_l_vp are not used on the codebase, this commit drops those entries from enum dm_swizzle_mode. Signed-off-by: Ma=C3=ADra Canal --- .../dc/dml/dcn20/display_mode_vba_20.c | 26 +++++------------- .../dc/dml/dcn20/display_mode_vba_20v2.c | 26 +++++------------- .../dc/dml/dcn21/display_mode_vba_21.c | 27 +++++-------------- .../amd/display/dc/dml/display_mode_enums.h | 2 -- .../display/dc/dml/dml_wrapper_translation.c | 9 ------- 5 files changed, 19 insertions(+), 71 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c index d3b5b6fedf04..4e4cb0927057 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c @@ -938,7 +938,7 @@ static unsigned int CalculateVMAndRowBytes( *MetaRowByte =3D 0; } =20 - if (SurfaceTiling =3D=3D dm_sw_linear || SurfaceTiling =3D=3D dm_sw_gfx7_= 2d_thin_gl || SurfaceTiling =3D=3D dm_sw_gfx7_2d_thin_l_vp) { + if (SurfaceTiling =3D=3D dm_sw_linear) { MacroTileSizeBytes =3D 256; MacroTileHeight =3D BlockHeight256Bytes; } else if (SurfaceTiling =3D=3D dm_sw_4kb_s || SurfaceTiling =3D=3D dm_sw= _4kb_s_x @@ -3347,26 +3347,12 @@ void dml20_ModeSupportAndSystemConfigurationFull(st= ruct display_mode_lib *mode_l =3D=3D dm_420_8 || mode_lib->vba.SourcePixelFormat[k] =3D=3D dm_420_10)) - || (((mode_lib->vba.SurfaceTiling[k] =3D=3D dm_sw_gfx7_2d_thin_gl - || mode_lib->vba.SurfaceTiling[k] - =3D=3D dm_sw_gfx7_2d_thin_l_vp) - && !((mode_lib->vba.SourcePixelFormat[k] - =3D=3D dm_444_64 + || (mode_lib->vba.DCCEnable[k] =3D=3D true + && (mode_lib->vba.SurfaceTiling[k] =3D=3D dm_sw_linear || mode_lib->vba.SourcePixelFormat[k] - =3D=3D dm_444_32) - && mode_lib->vba.SourceScan[k] - =3D=3D dm_horz - && mode_lib->vba.SupportGFX7CompatibleTilingIn32bppAnd64bpp - =3D=3D true - && mode_lib->vba.DCCEnable[k] - =3D=3D false)) - || (mode_lib->vba.DCCEnable[k] =3D=3D true - && (mode_lib->vba.SurfaceTiling[k] - =3D=3D dm_sw_linear - || mode_lib->vba.SourcePixelFormat[k] - =3D=3D dm_420_8 - || mode_lib->vba.SourcePixelFormat[k] - =3D=3D dm_420_10)))) { + =3D=3D dm_420_8 + || mode_lib->vba.SourcePixelFormat[k] + =3D=3D dm_420_10))) { mode_lib->vba.SourceFormatPixelAndScanSupport =3D false; } } diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2= .c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c index 63bbdf8b8678..eaa0cdb599ba 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c @@ -998,7 +998,7 @@ static unsigned int CalculateVMAndRowBytes( *MetaRowByte =3D 0; } =20 - if (SurfaceTiling =3D=3D dm_sw_linear || SurfaceTiling =3D=3D dm_sw_gfx7_= 2d_thin_gl || SurfaceTiling =3D=3D dm_sw_gfx7_2d_thin_l_vp) { + if (SurfaceTiling =3D=3D dm_sw_linear) { MacroTileSizeBytes =3D 256; MacroTileHeight =3D BlockHeight256Bytes; } else if (SurfaceTiling =3D=3D dm_sw_4kb_s || SurfaceTiling =3D=3D dm_sw= _4kb_s_x @@ -3454,26 +3454,12 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(= struct display_mode_lib *mode =3D=3D dm_420_8 || mode_lib->vba.SourcePixelFormat[k] =3D=3D dm_420_10)) - || (((mode_lib->vba.SurfaceTiling[k] =3D=3D dm_sw_gfx7_2d_thin_gl - || mode_lib->vba.SurfaceTiling[k] - =3D=3D dm_sw_gfx7_2d_thin_l_vp) - && !((mode_lib->vba.SourcePixelFormat[k] - =3D=3D dm_444_64 + || (mode_lib->vba.DCCEnable[k] =3D=3D true + && (mode_lib->vba.SurfaceTiling[k] =3D=3D dm_sw_linear || mode_lib->vba.SourcePixelFormat[k] - =3D=3D dm_444_32) - && mode_lib->vba.SourceScan[k] - =3D=3D dm_horz - && mode_lib->vba.SupportGFX7CompatibleTilingIn32bppAnd64bpp - =3D=3D true - && mode_lib->vba.DCCEnable[k] - =3D=3D false)) - || (mode_lib->vba.DCCEnable[k] =3D=3D true - && (mode_lib->vba.SurfaceTiling[k] - =3D=3D dm_sw_linear - || mode_lib->vba.SourcePixelFormat[k] - =3D=3D dm_420_8 - || mode_lib->vba.SourcePixelFormat[k] - =3D=3D dm_420_10)))) { + =3D=3D dm_420_8 + || mode_lib->vba.SourcePixelFormat[k] + =3D=3D dm_420_10))) { mode_lib->vba.SourceFormatPixelAndScanSupport =3D false; } } diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c index 8a7485e21d53..198d81861ac5 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c @@ -1342,7 +1342,7 @@ static unsigned int CalculateVMAndRowBytes( *MetaRowByte =3D 0; } =20 - if (SurfaceTiling =3D=3D dm_sw_linear || SurfaceTiling =3D=3D dm_sw_gfx7_= 2d_thin_gl || SurfaceTiling =3D=3D dm_sw_gfx7_2d_thin_l_vp) { + if (SurfaceTiling =3D=3D dm_sw_linear) { MacroTileSizeBytes =3D 256; MacroTileHeight =3D BlockHeight256Bytes; } else if (SurfaceTiling =3D=3D dm_sw_4kb_s || SurfaceTiling =3D=3D dm_sw= _4kb_s_x @@ -3579,26 +3579,13 @@ void dml21_ModeSupportAndSystemConfigurationFull(st= ruct display_mode_lib *mode_l =3D=3D dm_420_8 || mode_lib->vba.SourcePixelFormat[k] =3D=3D dm_420_10)) - || (((mode_lib->vba.SurfaceTiling[k] =3D=3D dm_sw_gfx7_2d_thin_gl - || mode_lib->vba.SurfaceTiling[k] - =3D=3D dm_sw_gfx7_2d_thin_l_vp) - && !((mode_lib->vba.SourcePixelFormat[k] - =3D=3D dm_444_64 + || (mode_lib->vba.DCCEnable[k] =3D=3D true + && (mode_lib->vba.SurfaceTiling[k] + =3D=3D dm_sw_linear || mode_lib->vba.SourcePixelFormat[k] - =3D=3D dm_444_32) - && mode_lib->vba.SourceScan[k] - =3D=3D dm_horz - && mode_lib->vba.SupportGFX7CompatibleTilingIn32bppAnd64bpp - =3D=3D true - && mode_lib->vba.DCCEnable[k] - =3D=3D false)) - || (mode_lib->vba.DCCEnable[k] =3D=3D true - && (mode_lib->vba.SurfaceTiling[k] - =3D=3D dm_sw_linear - || mode_lib->vba.SourcePixelFormat[k] - =3D=3D dm_420_8 - || mode_lib->vba.SourcePixelFormat[k] - =3D=3D dm_420_10)))) { + =3D=3D dm_420_8 + || mode_lib->vba.SourcePixelFormat[k] + =3D=3D dm_420_10))) { mode_lib->vba.SourceFormatPixelAndScanSupport =3D false; } } diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h b/driv= ers/gpu/drm/amd/display/dc/dml/display_mode_enums.h index f394b3f3922a..0e06727d40b3 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h @@ -89,8 +89,6 @@ enum dm_swizzle_mode { dm_sw_var_s_x =3D 29, dm_sw_var_d_x =3D 30, dm_sw_var_r_x =3D 31, - dm_sw_gfx7_2d_thin_l_vp, - dm_sw_gfx7_2d_thin_gl, }; enum lb_depth { dm_lb_10 =3D 0, dm_lb_8 =3D 1, dm_lb_6 =3D 2, dm_lb_12 =3D 3, dm_lb_16 = =3D 4, diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper_translation.c b= /drivers/gpu/drm/amd/display/dc/dml/dml_wrapper_translation.c index 4ec5310a2962..9edcb6fc83c1 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper_translation.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper_translation.c @@ -35,15 +35,6 @@ static void gfx10array_mode_to_dml_params( case DC_ARRAY_LINEAR_GENERAL: *sw_mode =3D dm_sw_linear; break; - case DC_ARRAY_2D_TILED_THIN1: -// DC_LEGACY_TILING_ADDR_GEN_ZERO - undefined as per current code hence re= moved -#if 0 - if (compat_level =3D=3D DC_LEGACY_TILING_ADDR_GEN_ZERO) - *sw_mode =3D dm_sw_gfx7_2d_thin_l_vp; - else - *sw_mode =3D dm_sw_gfx7_2d_thin_gl; -#endif - break; default: ASSERT(0); /* Not supported */ break; --=20 2.36.1