From nobody Sat Sep 21 22:52:10 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07D3DC43334 for ; Thu, 7 Jul 2022 05:46:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233584AbiGGFqi (ORCPT ); Thu, 7 Jul 2022 01:46:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33632 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232901AbiGGFqd (ORCPT ); Thu, 7 Jul 2022 01:46:33 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D40B03139F; Wed, 6 Jul 2022 22:46:32 -0700 (PDT) X-UUID: 325c50e0cdf04af1b73fd155d898424b-20220707 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8,REQID:885cf4f0-48e3-4476-a3cd-eacdb9d3dad1,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:-5 X-CID-META: VersionHash:0f94e32,CLOUDID:a384a463-0b3f-4b2c-b3a6-ed5c044366a0,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: 325c50e0cdf04af1b73fd155d898424b-20220707 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 688955489; Thu, 07 Jul 2022 13:46:24 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Thu, 7 Jul 2022 13:46:23 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 7 Jul 2022 13:46:21 +0800 From: Kewei Xu To: CC: , , , , , , , , , , , , , , , , Subject: [PATCH V1 1/2] dt-bindings: i2c: update bindings for MT8188 SoC Date: Thu, 7 Jul 2022 13:46:16 +0800 Message-ID: <20220707054617.13583-2-kewei.xu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220707054617.13583-1-kewei.xu@mediatek.com> References: <20220707054617.13583-1-kewei.xu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a DT binding documentation for the MT8188 soc. Signed-off-by: Kewei Xu Reviewed-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml b/Docume= ntation/devicetree/bindings/i2c/i2c-mt65xx.yaml index 16a1a3118204..4e730fb7be56 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml @@ -27,6 +27,7 @@ properties: - const: mediatek,mt8173-i2c - const: mediatek,mt8183-i2c - const: mediatek,mt8186-i2c + - const: mediatek,mt8188-i2c - const: mediatek,mt8192-i2c - items: - enum: --=20 2.18.0 From nobody Sat Sep 21 22:52:10 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 051EECCA483 for ; Thu, 7 Jul 2022 05:46:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233372AbiGGFqg (ORCPT ); Thu, 7 Jul 2022 01:46:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33624 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229553AbiGGFqd (ORCPT ); Thu, 7 Jul 2022 01:46:33 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D49893138F; Wed, 6 Jul 2022 22:46:31 -0700 (PDT) X-UUID: b8c1fbdbd01a469a9df8b49ac9075df6-20220707 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8,REQID:324c0550-b744-43dc-8772-009357135868,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:100,FILE:0,RULE:Release_Ham,A CTION:release,TS:95 X-CID-INFO: VERSION:1.1.8,REQID:324c0550-b744-43dc-8772-009357135868,OB:0,LOB: 0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:100,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:95 X-CID-META: VersionHash:0f94e32,CLOUDID:a484a463-0b3f-4b2c-b3a6-ed5c044366a0,C OID:c9092bbef628,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: b8c1fbdbd01a469a9df8b49ac9075df6-20220707 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 262505786; Thu, 07 Jul 2022 13:46:25 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Thu, 7 Jul 2022 13:46:24 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 7 Jul 2022 13:46:23 +0800 From: Kewei Xu To: CC: , , , , , , , , , , , , , , , , Subject: [PATCH 2/2] i2c: mediatek: Add i2c compatible for Mediatek MT8188 Date: Thu, 7 Jul 2022 13:46:17 +0800 Message-ID: <20220707054617.13583-3-kewei.xu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220707054617.13583-1-kewei.xu@mediatek.com> References: <20220707054617.13583-1-kewei.xu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add i2c compatible for MT8188. Compare to MT8192 i2c controller, The MT8188 i2c OFFSET_SLAVE_ADDR register changed from 0x04 to 0x94. Signed-off-by: Kewei Xu --- drivers/i2c/busses/i2c-mt65xx.c | 41 +++++++++++++++++++++++++++++++-- 1 file changed, 39 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65x= x.c index 8e6985354fd5..aa2e1cb87420 100644 --- a/drivers/i2c/busses/i2c-mt65xx.c +++ b/drivers/i2c/busses/i2c-mt65xx.c @@ -135,6 +135,7 @@ enum mtk_trans_op { enum I2C_REGS_OFFSET { OFFSET_DATA_PORT, OFFSET_SLAVE_ADDR, + OFFSET_SLAVE_ADDR1, OFFSET_INTR_MASK, OFFSET_INTR_STAT, OFFSET_CONTROL, @@ -203,6 +204,7 @@ static const u16 mt_i2c_regs_v1[] =3D { static const u16 mt_i2c_regs_v2[] =3D { [OFFSET_DATA_PORT] =3D 0x0, [OFFSET_SLAVE_ADDR] =3D 0x4, + [OFFSET_SLAVE_ADDR1] =3D 0x94, [OFFSET_INTR_MASK] =3D 0x8, [OFFSET_INTR_STAT] =3D 0xc, [OFFSET_CONTROL] =3D 0x10, @@ -241,6 +243,7 @@ struct mtk_i2c_compatible { unsigned char ltiming_adjust: 1; unsigned char apdma_sync: 1; unsigned char max_dma_support; + unsigned char slave_addr_ver; }; =20 struct mtk_i2c_ac_timing { @@ -345,6 +348,7 @@ static const struct mtk_i2c_compatible mt2712_compat = =3D { .ltiming_adjust =3D 0, .apdma_sync =3D 0, .max_dma_support =3D 33, + .slave_addr_ver =3D 0, }; =20 static const struct mtk_i2c_compatible mt6577_compat =3D { @@ -359,6 +363,7 @@ static const struct mtk_i2c_compatible mt6577_compat = =3D { .ltiming_adjust =3D 0, .apdma_sync =3D 0, .max_dma_support =3D 32, + .slave_addr_ver =3D 0, }; =20 static const struct mtk_i2c_compatible mt6589_compat =3D { @@ -373,6 +378,7 @@ static const struct mtk_i2c_compatible mt6589_compat = =3D { .ltiming_adjust =3D 0, .apdma_sync =3D 0, .max_dma_support =3D 32, + .slave_addr_ver =3D 0, }; =20 static const struct mtk_i2c_compatible mt7622_compat =3D { @@ -387,6 +393,7 @@ static const struct mtk_i2c_compatible mt7622_compat = =3D { .ltiming_adjust =3D 0, .apdma_sync =3D 0, .max_dma_support =3D 32, + .slave_addr_ver =3D 0, }; =20 static const struct mtk_i2c_compatible mt8168_compat =3D { @@ -400,6 +407,7 @@ static const struct mtk_i2c_compatible mt8168_compat = =3D { .ltiming_adjust =3D 0, .apdma_sync =3D 0, .max_dma_support =3D 33, + .slave_addr_ver =3D 0, }; =20 static const struct mtk_i2c_compatible mt8173_compat =3D { @@ -413,6 +421,7 @@ static const struct mtk_i2c_compatible mt8173_compat = =3D { .ltiming_adjust =3D 0, .apdma_sync =3D 0, .max_dma_support =3D 33, + .slave_addr_ver =3D 0, }; =20 static const struct mtk_i2c_compatible mt8183_compat =3D { @@ -427,6 +436,7 @@ static const struct mtk_i2c_compatible mt8183_compat = =3D { .ltiming_adjust =3D 1, .apdma_sync =3D 0, .max_dma_support =3D 33, + .slave_addr_ver =3D 0, }; =20 static const struct mtk_i2c_compatible mt8186_compat =3D { @@ -440,6 +450,21 @@ static const struct mtk_i2c_compatible mt8186_compat = =3D { .ltiming_adjust =3D 1, .apdma_sync =3D 0, .max_dma_support =3D 36, + .slave_addr_ver =3D 0, +}; + +static const struct mtk_i2c_compatible mt8188_compat =3D { + .regs =3D mt_i2c_regs_v2, + .pmic_i2c =3D 0, + .dcm =3D 0, + .auto_restart =3D 1, + .aux_len_reg =3D 1, + .timing_adjust =3D 1, + .dma_sync =3D 0, + .ltiming_adjust =3D 1, + .apdma_sync =3D 1, + .max_dma_support =3D 36, + .slave_addr_ver =3D 1, }; =20 static const struct mtk_i2c_compatible mt8192_compat =3D { @@ -454,6 +479,7 @@ static const struct mtk_i2c_compatible mt8192_compat = =3D { .ltiming_adjust =3D 1, .apdma_sync =3D 1, .max_dma_support =3D 36, + .slave_addr_ver =3D 0, }; =20 static const struct of_device_id mtk_i2c_of_match[] =3D { @@ -465,6 +491,7 @@ static const struct of_device_id mtk_i2c_of_match[] =3D= { { .compatible =3D "mediatek,mt8173-i2c", .data =3D &mt8173_compat }, { .compatible =3D "mediatek,mt8183-i2c", .data =3D &mt8183_compat }, { .compatible =3D "mediatek,mt8186-i2c", .data =3D &mt8186_compat }, + { .compatible =3D "mediatek,mt8188-i2c", .data =3D &mt8188_compat }, { .compatible =3D "mediatek,mt8192-i2c", .data =3D &mt8192_compat }, {} }; @@ -877,8 +904,15 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsi= gned int parent_clk) =20 static void i2c_dump_register(struct mtk_i2c *i2c) { + enum I2C_REGS_OFFSET sla_addr_offset; + + if (i2c->dev_comp->slave_addr_ver =3D=3D 1) + sla_addr_offset =3D OFFSET_SLAVE_ADDR1; + else + sla_addr_offset =3D OFFSET_SLAVE_ADDR; + dev_dbg(i2c->dev, "SLAVE_ADDR: 0x%x, INTR_MASK: 0x%x\n", - mtk_i2c_readw(i2c, OFFSET_SLAVE_ADDR), + mtk_i2c_readw(i2c, sla_addr_offset), mtk_i2c_readw(i2c, OFFSET_INTR_MASK)); dev_dbg(i2c->dev, "INTR_STAT: 0x%x, CONTROL: 0x%x\n", mtk_i2c_readw(i2c, OFFSET_INTR_STAT), @@ -982,7 +1016,10 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, s= truct i2c_msg *msgs, mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); =20 addr_reg =3D i2c_8bit_addr_from_msg(msgs); - mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR); + if (i2c->dev_comp->slave_addr_ver =3D=3D 1) + mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR1); + else + mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR); =20 /* Clear interrupt status */ mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR | --=20 2.18.0