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([51.37.234.167]) by smtp.gmail.com with ESMTPSA id f7-20020a05600c4e8700b003a17ab4e7c8sm26876310wmq.39.2022.07.06.11.46.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Jul 2022 11:46:33 -0700 (PDT) From: Conor Dooley To: Paul Walmsley , Palmer Dabbelt , Palmer Dabbelt , Albert Ou , Sudeep Holla Cc: Daire McNamara , Conor Dooley , Niklas Cassel , Damien Le Moal , Geert Uytterhoeven , Zong Li , Emil Renner Berthing , Jonas Hahnfeld , Guo Ren , Anup Patel , Atish Patra , Changbin Du , Heiko Stuebner , Philipp Tomsich , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Brice Goglin Subject: [PATCH] riscv: arch-topology: fix default topology reporting Date: Wed, 6 Jul 2022 19:45:59 +0100 Message-Id: <20220706184558.2557301-1-mail@conchuod.ie> X-Mailer: git-send-email 2.37.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley RISC-V has no sane defaults to fall back on where there is no cpu-map in the devicetree. Without sane defaults, the package, core and thread IDs are all set to -1. This causes user-visible inaccuracies for tools like hwloc/lstopo which rely on the sysfs cpu topology files to detect a system's topology. Add sane defaults in ~the exact same way as ARM64. CC: stable@vger.kernel.org Fixes: 03f11f03dbfe ("RISC-V: Parse cpu topology during boot.") Reported-by: Brice Goglin Link: https://github.com/open-mpi/hwloc/issues/536 Signed-off-by: Conor Dooley Reported-by: kernel test robot --- Sudeep suggested that this be backported rather than the changes to the devicetrees adding cpu-map since that property is optional. That patchset is still valid in it's own right. arch/riscv/include/asm/topology.h | 13 +++++++++++++ arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/smpboot.c | 4 ++++ arch/riscv/kernel/topology.c | 32 +++++++++++++++++++++++++++++++ 4 files changed, 50 insertions(+) create mode 100644 arch/riscv/include/asm/topology.h create mode 100644 arch/riscv/kernel/topology.c diff --git a/arch/riscv/include/asm/topology.h b/arch/riscv/include/asm/top= ology.h new file mode 100644 index 000000000000..36bc6ecda898 --- /dev/null +++ b/arch/riscv/include/asm/topology.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries + */ + +#ifndef _ASM_RISCV_TOPOLOGY_H +#define _ASM_RISCV_TOPOLOGY_H + +#include + +void store_cpu_topology(unsigned int cpuid); + +#endif /* _ASM_RISCV_TOPOLOGY_H */ diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index c71d6591d539..9518882ba6f9 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -50,6 +50,7 @@ obj-y +=3D riscv_ksyms.o obj-y +=3D stacktrace.o obj-y +=3D cacheinfo.o obj-y +=3D patch.o +obj-y +=3D topology.o obj-y +=3D probes/ obj-$(CONFIG_MMU) +=3D vdso.o vdso/ =20 diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index f1e4948a4b52..d551c7f452d4 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -32,6 +32,7 @@ #include #include #include +#include =20 #include "head.h" =20 @@ -40,6 +41,8 @@ static DECLARE_COMPLETION(cpu_running); void __init smp_prepare_boot_cpu(void) { init_cpu_topology(); + + store_cpu_topology(smp_processor_id()); } =20 void __init smp_prepare_cpus(unsigned int max_cpus) @@ -161,6 +164,7 @@ asmlinkage __visible void smp_callin(void) mmgrab(mm); current->active_mm =3D mm; =20 + store_cpu_topology(curr_cpuid); notify_cpu_starting(curr_cpuid); numa_add_cpu(curr_cpuid); update_siblings_masks(curr_cpuid); diff --git a/arch/riscv/kernel/topology.c b/arch/riscv/kernel/topology.c new file mode 100644 index 000000000000..db72862bd5b5 --- /dev/null +++ b/arch/riscv/kernel/topology.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries + * + * Based on the arm64 version, which was in turn based on arm32, which was + * ultimately based on sh's. + * The arm64 version was listed as: + * Copyright (C) 2011,2013,2014 Linaro Limited. + */ + +#include +#include +#include + +void store_cpu_topology(unsigned int cpuid) +{ + struct cpu_topology *cpuid_topo =3D &cpu_topology[cpuid]; + + if (cpuid_topo->package_id !=3D -1) + goto topology_populated; + + cpuid_topo->thread_id =3D -1; + cpuid_topo->core_id =3D cpuid; + cpuid_topo->package_id =3D cpu_to_node(cpuid); + + pr_debug("CPU%u: package %d core %d thread %d\n", + cpuid, cpuid_topo->package_id, cpuid_topo->core_id, + cpuid_topo->thread_id); + +topology_populated: + update_siblings_masks(cpuid); +} base-commit: b6f1f2fa2bddd69ff46a190b8120bd440fd50563 --=20 2.37.0