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[86.26.103.58]) by smtp.gmail.com with ESMTPSA id n35-20020a05600c3ba300b003a039054567sm24678143wms.18.2022.07.06.03.07.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Jul 2022 03:07:28 -0700 (PDT) From: Srinivas Kandagatla To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org, Claudiu Beznea , Krzysztof Kozlowski , Srinivas Kandagatla Subject: [PATCH 1/7] dt-bindings: microchip-otpc: document Microchip OTPC Date: Wed, 6 Jul 2022 11:06:21 +0100 Message-Id: <20220706100627.6534-2-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220706100627.6534-1-srinivas.kandagatla@linaro.org> References: <20220706100627.6534-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Document Microchip OTP controller. Signed-off-by: Claudiu Beznea Reviewed-by: Krzysztof Kozlowski Signed-off-by: Srinivas Kandagatla --- .../nvmem/microchip,sama7g5-otpc.yaml | 50 +++++++++++++++++++ .../nvmem/microchip,sama7g5-otpc.h | 12 +++++ 2 files changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/microchip,sama7= g5-otpc.yaml create mode 100644 include/dt-bindings/nvmem/microchip,sama7g5-otpc.h diff --git a/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc= .yaml b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml new file mode 100644 index 000000000000..c3c96fd0baac --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/microchip,sama7g5-otpc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip SAMA7G5 OTP Controller (OTPC) + +maintainers: + - Claudiu Beznea + +description: | + OTP controller drives a NVMEM memory where system specific data + (e.g. calibration data for analog cells, hardware configuration + settings, chip identifiers) or user specific data could be stored. + +allOf: + - $ref: "nvmem.yaml#" + +properties: + compatible: + items: + - const: microchip,sama7g5-otpc + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + otpc: efuse@e8c00000 { + compatible =3D "microchip,sama7g5-otpc", "syscon"; + reg =3D <0xe8c00000 0xec>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + temperature_calib: calib@1 { + reg =3D ; + }; + }; + +... diff --git a/include/dt-bindings/nvmem/microchip,sama7g5-otpc.h b/include/d= t-bindings/nvmem/microchip,sama7g5-otpc.h new file mode 100644 index 000000000000..f570b23165a2 --- /dev/null +++ b/include/dt-bindings/nvmem/microchip,sama7g5-otpc.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ + +#ifndef _DT_BINDINGS_NVMEM_MICROCHIP_OTPC_H +#define _DT_BINDINGS_NVMEM_MICROCHIP_OTPC_H + +/* + * Need to have it as a multiple of 4 as NVMEM memory is registered with + * stride =3D 4. + */ +#define OTP_PKT(id) ((id) * 4) + +#endif --=20 2.25.1 From nobody Sun Apr 19 04:06:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A654C433EF for ; Wed, 6 Jul 2022 10:08:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230151AbiGFKIJ (ORCPT ); Wed, 6 Jul 2022 06:08:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232795AbiGFKHn (ORCPT ); Wed, 6 Jul 2022 06:07:43 -0400 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 227F625589 for ; Wed, 6 Jul 2022 03:07:30 -0700 (PDT) Received: by mail-wr1-x435.google.com with SMTP id s1so21308814wra.9 for ; Wed, 06 Jul 2022 03:07:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HK8OWVwLen3ZuOawEOM+ll24bLLsBaO0ZTOSGq1+ba8=; b=c4S3SjxFCzwvwTucPvU3PZS3nWw+nui64zwUwvR83OU9ofGT6qp9Blv0tJBKIBfuBR nvJUuXYr0Q77LsSfVVt4T4Vixi67THXYZ1yUJlhQwx32CV0OeZBEcx2ZAGTluuk4QkKe vFkTu1PQZ0eUO0F8KGBeMhuBo1iVBGBiRtWEB+EfWc981fyIXvWuwt2nvt1fgejgamqb eajYUcxWnIWQyfWVUpr+VOx0ZFClXWWHALga0Jq0ML/ouOjWS7PTcbzRjEk89JfekKMC U5GzE3J8GegEGSGzSyhAyHuXIhHc46w4To5CDOUgMscBdJ0YUyJvxMjMPde6SFBU0PnF lO+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HK8OWVwLen3ZuOawEOM+ll24bLLsBaO0ZTOSGq1+ba8=; b=7D97Z5pRINTD5/vkbMUFuyMxcVHSeCJEQ+ZGNHreIGhBdxaISsWxkrBnAur0mup1C7 +xvA5gRBPCYj0V1MJDHbRSGM6eKccpaZjWQjNs6RlPdmWWQe4VaP6ZjHwstKubRk+Yfl ZRDq+urEO5Pk5YH2B33HQKkMAkYbXuXcurrX1AF1Op9jtAy5u6qXW+55YzJFHc5zkgBV dZs0YaGTsnxu03142nu24HpBY1zyIA5u6dt16HGV53fBvIv5SDlZvtb3UTEIeR2mkr/b 5Eg0NJ6OI4drmYt38r7qm2TTIqb2IfSeE7ni4zHJihSnKQp3pkUi4cLlo/zKxvl0/ya1 xzXw== X-Gm-Message-State: AJIora9N7cPWjo+AUBg1DvUaZo86xFxe1306giUI4Mp081K9esfcUY+f SVEDuLZQ/XriI9sLqJJmRnVr0A== X-Google-Smtp-Source: AGRyM1uSZhWo6qditsJz0p6v1TG7WUtuWHcovPI+metrI9dzrKWoEfd2v/4JBYWcexo40sn6ZQuk2g== X-Received: by 2002:a05:6000:1449:b0:21b:b171:5eb8 with SMTP id v9-20020a056000144900b0021bb1715eb8mr37239241wrx.634.1657102049603; Wed, 06 Jul 2022 03:07:29 -0700 (PDT) Received: from srini-hackbase.lan (cpc90716-aztw32-2-0-cust825.18-1.cable.virginm.net. [86.26.103.58]) by smtp.gmail.com with ESMTPSA id n35-20020a05600c3ba300b003a039054567sm24678143wms.18.2022.07.06.03.07.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Jul 2022 03:07:29 -0700 (PDT) From: Srinivas Kandagatla To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org, Claudiu Beznea , Srinivas Kandagatla Subject: [PATCH 2/7] nvmem: microchip-otpc: add support Date: Wed, 6 Jul 2022 11:06:22 +0100 Message-Id: <20220706100627.6534-3-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220706100627.6534-1-srinivas.kandagatla@linaro.org> References: <20220706100627.6534-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add support for Microchip OTP controller available on SAMA7G5. The OTPC controls the access to a non-volatile memory. The memory behind OTPC is organized into packets, packets are composed by a fixed length header (4 bytes long) and a variable length payload (payload length is available in the header). When software request the data at an offset in memory the OTPC will return (via header + data registers) the whole packet that has a word at that offset. For the OTP memory layout like below: offset OTP Memory layout . . . ... . . . 0x0E +-----------+ <--- packet X | header X | 0x12 +-----------+ | payload X | 0x16 | | | | 0x1A | | +-----------+ . . . ... . . . if user requests data at address 0x16 the data started at 0x0E will be returned by controller. User will be able to fetch the whole packet starting at 0x0E (or parts of the packet) via proper registers. The same packet will be returned if software request the data at offset 0x0E or 0x12 or 0x1A. The OTP will be populated by Microchip with at least 2 packets first one being boot configuration packet and the 2nd one being temperature calibration packet. The packet order will be preserved b/w different chip revisions but the packet sizes may change. For the above reasons and to keep the same software able to work on all chip variants the read function of the driver is working with a packet id instead of an offset in OTP memory. Signed-off-by: Claudiu Beznea Signed-off-by: Srinivas Kandagatla --- MAINTAINERS | 8 + drivers/nvmem/Kconfig | 7 + drivers/nvmem/Makefile | 2 + drivers/nvmem/microchip-otpc.c | 288 +++++++++++++++++++++++++++++++++ 4 files changed, 305 insertions(+) create mode 100644 drivers/nvmem/microchip-otpc.c diff --git a/MAINTAINERS b/MAINTAINERS index a6d3bd9d2a8d..e51eeb0ee0ed 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13100,6 +13100,14 @@ S: Supported F: Documentation/devicetree/bindings/mtd/atmel-nand.txt F: drivers/mtd/nand/raw/atmel/* =20 +MICROCHIP OTPC DRIVER +M: Claudiu Beznea +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Supported +F: Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml +F: drivers/nvmem/microchip-otpc.c +F: dt-bindings/nvmem/microchip,sama7g5-otpc.h + MICROCHIP PWM DRIVER M: Claudiu Beznea L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index 967d0084800e..d72d879a6d34 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -107,6 +107,13 @@ config MTK_EFUSE This driver can also be built as a module. If so, the module will be called efuse-mtk. =20 +config MICROCHIP_OTPC + tristate "Microchip OTPC support" + depends on ARCH_AT91 || COMPILE_TEST + help + This driver enable the OTP controller available on Microchip SAMA7G5 + SoCs. It controlls the access to the OTP memory connected to it. + config NVMEM_NINTENDO_OTP tristate "Nintendo Wii and Wii U OTP Support" depends on WII || COMPILE_TEST diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index 00e136a0a123..c710b64f9fe4 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -67,3 +67,5 @@ obj-$(CONFIG_NVMEM_SUNPLUS_OCOTP) +=3D nvmem_sunplus_ocot= p.o nvmem_sunplus_ocotp-y :=3D sunplus-ocotp.o obj-$(CONFIG_NVMEM_APPLE_EFUSES) +=3D nvmem-apple-efuses.o nvmem-apple-efuses-y :=3D apple-efuses.o +obj-$(CONFIG_MICROCHIP_OTPC) +=3D nvmem-microchip-otpc.o +nvmem-microchip-otpc-y :=3D microchip-otpc.o diff --git a/drivers/nvmem/microchip-otpc.c b/drivers/nvmem/microchip-otpc.c new file mode 100644 index 000000000000..436e0dc4f337 --- /dev/null +++ b/drivers/nvmem/microchip-otpc.c @@ -0,0 +1,288 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * OTP Memory controller + * + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries + * + * Author: Claudiu Beznea + */ + +#include +#include +#include +#include +#include +#include + +#define MCHP_OTPC_CR (0x0) +#define MCHP_OTPC_CR_READ BIT(6) +#define MCHP_OTPC_MR (0x4) +#define MCHP_OTPC_MR_ADDR GENMASK(31, 16) +#define MCHP_OTPC_AR (0x8) +#define MCHP_OTPC_SR (0xc) +#define MCHP_OTPC_SR_READ BIT(6) +#define MCHP_OTPC_HR (0x20) +#define MCHP_OTPC_HR_SIZE GENMASK(15, 8) +#define MCHP_OTPC_DR (0x24) + +#define MCHP_OTPC_NAME "mchp-otpc" +#define MCHP_OTPC_SIZE (11 * 1024) + +/** + * struct mchp_otpc - OTPC private data structure + * @base: base address + * @dev: struct device pointer + * @packets: list of packets in OTP memory + * @npackets: number of packets in OTP memory + */ +struct mchp_otpc { + void __iomem *base; + struct device *dev; + struct list_head packets; + u32 npackets; +}; + +/** + * struct mchp_otpc_packet - OTPC packet data structure + * @list: list head + * @id: packet ID + * @offset: packet offset (in words) in OTP memory + */ +struct mchp_otpc_packet { + struct list_head list; + u32 id; + u32 offset; +}; + +static struct mchp_otpc_packet *mchp_otpc_id_to_packet(struct mchp_otpc *o= tpc, + u32 id) +{ + struct mchp_otpc_packet *packet; + + if (id >=3D otpc->npackets) + return NULL; + + list_for_each_entry(packet, &otpc->packets, list) { + if (packet->id =3D=3D id) + return packet; + } + + return NULL; +} + +static int mchp_otpc_prepare_read(struct mchp_otpc *otpc, + unsigned int offset) +{ + u32 tmp; + + /* Set address. */ + tmp =3D readl_relaxed(otpc->base + MCHP_OTPC_MR); + tmp &=3D ~MCHP_OTPC_MR_ADDR; + tmp |=3D FIELD_PREP(MCHP_OTPC_MR_ADDR, offset); + writel_relaxed(tmp, otpc->base + MCHP_OTPC_MR); + + /* Set read. */ + tmp =3D readl_relaxed(otpc->base + MCHP_OTPC_CR); + tmp |=3D MCHP_OTPC_CR_READ; + writel_relaxed(tmp, otpc->base + MCHP_OTPC_CR); + + /* Wait for packet to be transferred into temporary buffers. */ + return read_poll_timeout(readl_relaxed, tmp, !(tmp & MCHP_OTPC_SR_READ), + 10000, 2000, false, otpc->base + MCHP_OTPC_SR); +} + +/* + * OTPC memory is organized into packets. Each packets contains a header a= nd + * a payload. Header is 4 bytes long and contains the size of the payload. + * Payload size varies. The memory footprint is something as follows: + * + * Memory offset Memory footprint Packet ID + * ------------- ---------------- --------- + * + * 0x0 +------------+ <-- packet 0 + * | header 0 | + * 0x4 +------------+ + * | payload 0 | + * . . + * . ... . + * . . + * offset1 +------------+ <-- packet 1 + * | header 1 | + * offset1 + 0x4 +------------+ + * | payload 1 | + * . . + * . ... . + * . . + * offset2 +------------+ <-- packet 2 + * . . + * . ... . + * . . + * offsetN +------------+ <-- packet N + * | header N | + * offsetN + 0x4 +------------+ + * | payload N | + * . . + * . ... . + * . . + * +------------+ + * + * where offset1, offset2, offsetN depends on the size of payload 0, paylo= ad 1, + * payload N-1. + * + * The access to memory is done on a per packet basis: the control registe= rs + * need to be updated with an offset address (within a packet range) and t= he + * data registers will be update by controller with information contained = by + * that packet. E.g. if control registers are updated with any address wit= hin + * the range [offset1, offset2) the data registers are updated by controll= er + * with packet 1. Header data is accessible though MCHP_OTPC_HR register. + * Payload data is accessible though MCHP_OTPC_DR and MCHP_OTPC_AR registe= rs. + * There is no direct mapping b/w the offset requested by software and the + * offset returned by hardware. + * + * For this, the read function will return the first requested bytes in the + * packet. The user will have to be aware of the memory footprint before d= oing + * the read request. + */ +static int mchp_otpc_read(void *priv, unsigned int off, void *val, + size_t bytes) +{ + struct mchp_otpc *otpc =3D priv; + struct mchp_otpc_packet *packet; + u32 *buf =3D val; + u32 offset; + size_t len =3D 0; + int ret, payload_size; + + /* + * We reach this point with off being multiple of stride =3D 4 to + * be able to cross the subsystem. Inside the driver we use continuous + * unsigned integer numbers for packet id, thus devide off by 4 + * before passing it to mchp_otpc_id_to_packet(). + */ + packet =3D mchp_otpc_id_to_packet(otpc, off / 4); + if (!packet) + return -EINVAL; + offset =3D packet->offset; + + while (len < bytes) { + ret =3D mchp_otpc_prepare_read(otpc, offset); + if (ret) + return ret; + + /* Read and save header content. */ + *buf++ =3D readl_relaxed(otpc->base + MCHP_OTPC_HR); + len +=3D sizeof(*buf); + offset++; + if (len >=3D bytes) + break; + + /* Read and save payload content. */ + payload_size =3D FIELD_GET(MCHP_OTPC_HR_SIZE, *(buf - 1)); + writel_relaxed(0UL, otpc->base + MCHP_OTPC_AR); + do { + *buf++ =3D readl_relaxed(otpc->base + MCHP_OTPC_DR); + len +=3D sizeof(*buf); + offset++; + payload_size--; + } while (payload_size >=3D 0 && len < bytes); + } + + return 0; +} + +static int mchp_otpc_init_packets_list(struct mchp_otpc *otpc, u32 *size) +{ + struct mchp_otpc_packet *packet; + u32 word, word_pos =3D 0, id =3D 0, npackets =3D 0, payload_size; + int ret; + + INIT_LIST_HEAD(&otpc->packets); + *size =3D 0; + + while (*size < MCHP_OTPC_SIZE) { + ret =3D mchp_otpc_prepare_read(otpc, word_pos); + if (ret) + return ret; + + word =3D readl_relaxed(otpc->base + MCHP_OTPC_HR); + payload_size =3D FIELD_GET(MCHP_OTPC_HR_SIZE, word); + if (!payload_size) + break; + + packet =3D devm_kzalloc(otpc->dev, sizeof(*packet), GFP_KERNEL); + if (!packet) + return -ENOMEM; + + packet->id =3D id++; + packet->offset =3D word_pos; + INIT_LIST_HEAD(&packet->list); + list_add_tail(&packet->list, &otpc->packets); + + /* Count size by adding header and paload sizes. */ + *size +=3D 4 * (payload_size + 1); + /* Next word: this packet (header, payload) position + 1. */ + word_pos +=3D payload_size + 2; + + npackets++; + } + + otpc->npackets =3D npackets; + + return 0; +} + +static struct nvmem_config mchp_nvmem_config =3D { + .name =3D MCHP_OTPC_NAME, + .type =3D NVMEM_TYPE_OTP, + .read_only =3D true, + .word_size =3D 4, + .stride =3D 4, + .reg_read =3D mchp_otpc_read, +}; + +static int mchp_otpc_probe(struct platform_device *pdev) +{ + struct nvmem_device *nvmem; + struct mchp_otpc *otpc; + u32 size; + int ret; + + otpc =3D devm_kzalloc(&pdev->dev, sizeof(*otpc), GFP_KERNEL); + if (!otpc) + return -ENOMEM; + + otpc->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(otpc->base)) + return PTR_ERR(otpc->base); + + otpc->dev =3D &pdev->dev; + ret =3D mchp_otpc_init_packets_list(otpc, &size); + if (ret) + return ret; + + mchp_nvmem_config.dev =3D otpc->dev; + mchp_nvmem_config.size =3D size; + mchp_nvmem_config.priv =3D otpc; + nvmem =3D devm_nvmem_register(&pdev->dev, &mchp_nvmem_config); + + return PTR_ERR_OR_ZERO(nvmem); +} + +static const struct of_device_id __maybe_unused mchp_otpc_ids[] =3D { + { .compatible =3D "microchip,sama7g5-otpc", }, + { }, +}; +MODULE_DEVICE_TABLE(of, mchp_otpc_ids); + +static struct platform_driver mchp_otpc_driver =3D { + .probe =3D mchp_otpc_probe, + .driver =3D { + .name =3D MCHP_OTPC_NAME, + .of_match_table =3D of_match_ptr(mchp_otpc_ids), + }, +}; +module_platform_driver(mchp_otpc_driver); + +MODULE_AUTHOR("Claudiu Beznea "); +MODULE_DESCRIPTION("Microchip SAMA7G5 OTPC driver"); +MODULE_LICENSE("GPL"); --=20 2.25.1 From nobody Sun Apr 19 04:06:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5122EC43334 for ; Wed, 6 Jul 2022 10:08:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232884AbiGFKIO (ORCPT ); Wed, 6 Jul 2022 06:08:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46350 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232797AbiGFKHn (ORCPT ); Wed, 6 Jul 2022 06:07:43 -0400 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3BEC72559A for ; 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[86.26.103.58]) by smtp.gmail.com with ESMTPSA id n35-20020a05600c3ba300b003a039054567sm24678143wms.18.2022.07.06.03.07.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Jul 2022 03:07:30 -0700 (PDT) From: Srinivas Kandagatla To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org, Lukas Bulwahn , Claudiu Beznea , Srinivas Kandagatla Subject: [PATCH 3/7] MAINTAINERS: rectify file pattern in MICROCHIP OTPC DRIVER Date: Wed, 6 Jul 2022 11:06:23 +0100 Message-Id: <20220706100627.6534-4-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220706100627.6534-1-srinivas.kandagatla@linaro.org> References: <20220706100627.6534-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Lukas Bulwahn Commit 6b291610dd57 ("nvmem: microchip-otpc: add support") adds the Microchip otpc driver and a corresponding MAINTAINERS section, but slips in a slightly wrong file pattern. Hence, ./scripts/get_maintainer.pl --self-test=3Dpatterns complains about a broken reference. Rectify this file pattern in MICROCHIP OTPC DRIVER. Signed-off-by: Lukas Bulwahn Acked-by: Claudiu Beznea Signed-off-by: Srinivas Kandagatla --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index e51eeb0ee0ed..62a02b67db25 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13106,7 +13106,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated = for non-subscribers) S: Supported F: Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml F: drivers/nvmem/microchip-otpc.c -F: dt-bindings/nvmem/microchip,sama7g5-otpc.h +F: include/dt-bindings/nvmem/microchip,sama7g5-otpc.h =20 MICROCHIP PWM DRIVER M: Claudiu Beznea --=20 2.25.1 From nobody Sun Apr 19 04:06:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7FC01C433EF for ; Wed, 6 Jul 2022 10:08:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233026AbiGFKIT (ORCPT ); Wed, 6 Jul 2022 06:08:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46356 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232812AbiGFKHo (ORCPT ); Wed, 6 Jul 2022 06:07:44 -0400 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7024D255AE for ; Wed, 6 Jul 2022 03:07:33 -0700 (PDT) Received: by mail-wr1-x42e.google.com with SMTP id r14so15527759wrg.1 for ; Wed, 06 Jul 2022 03:07:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RV7crcrnHKpDR+JNHqiUBuQdjQCZb9VboNC1TvQ0gW8=; b=zJUCSNvP9yZ+p4ALIcEWbwB922qRIYqUJVITA2czxsD6ZIQEUTbLfBNpLINcHzMJeo 4aEo/MxYDJKeUBNvZhinZBh4HD+ncGq/Bdx7rDsjmP4e8x7FoAQ7l1+GNNbmvC9v8b0C WUjZzAADOPJffgFIfN+n1MVs83XedLrQ78MWi1901rjT55Puzw4JpbHNurAwiQC0nZX9 ru7IpD6az0PPFppMQt7ws4bjs2YNUuhk089MizGAbxDULrqRgvoDAaOt1qG0QgQL08UJ DZPn4PnffwtRnLQy7k3NSfo7S05XN8YRFaQ1cKyNZSrR+RNBiyXJIbSyHVzhvowFn+03 3j3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RV7crcrnHKpDR+JNHqiUBuQdjQCZb9VboNC1TvQ0gW8=; b=Nu1KcamkDwVVNrvulh44WCiBOgJnGjvBdKlQndVdYOIHaGYK7PklFrjy1UA9A8rOjX vgaanyL///+DERzv+Wg9y66dG0BeBLBMH8wWm+MaSnn9AwJDCJGGOhQ3gQBYtf4ZLn8n 7fI+sqb41EUkwqmKqHCRW/0TVCsXQfC02MH3C+OSi7Sw05CyskoD6CPcopVAbvJEQXrt fdCaETDswrkOq8EoMHZSSDK4ai++xuQ/MWs75CIGy+6FACEmKUq2QU7e1AwiXd7P7Xwb So32n+7vek8AQ82BzbKlnFF1l85Y/p6bAhEbuWb/UxR3Yy4lwD56/8ni4dwrb7v024Ds iVBg== X-Gm-Message-State: AJIora+v3rIyQeyivcvZUe7ADSYB4USxuPLu1unHXwX3ZGhdJgWF6gRn GmMZ4GU8E+SN2VViLso+ZvuM+A== X-Google-Smtp-Source: AGRyM1vsuEiLpgFjfJ2YRNAqjZ43kbtzJyqEr1FOLrjFzorK5fs+8U5fYUK6WXGBeNENzwT3W+Msdw== X-Received: by 2002:a05:6000:237:b0:21d:4d65:32b3 with SMTP id l23-20020a056000023700b0021d4d6532b3mr24855054wrz.169.1657102051976; Wed, 06 Jul 2022 03:07:31 -0700 (PDT) Received: from srini-hackbase.lan (cpc90716-aztw32-2-0-cust825.18-1.cable.virginm.net. [86.26.103.58]) by smtp.gmail.com with ESMTPSA id n35-20020a05600c3ba300b003a039054567sm24678143wms.18.2022.07.06.03.07.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Jul 2022 03:07:31 -0700 (PDT) From: Srinivas Kandagatla To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org, Chunfeng Yun , Krzysztof Kozlowski , Rob Herring , Srinivas Kandagatla Subject: [PATCH 4/7] dt-bindings: nvmem: convert mtk-efuse.txt to YAML schema Date: Wed, 6 Jul 2022 11:06:24 +0100 Message-Id: <20220706100627.6534-5-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220706100627.6534-1-srinivas.kandagatla@linaro.org> References: <20220706100627.6534-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Chunfeng Yun Convert mtk-efuse.txt to YAML schema mediatek,efuse.yaml Reviewed-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Chunfeng Yun Signed-off-by: Srinivas Kandagatla --- .../bindings/nvmem/mediatek,efuse.yaml | 87 +++++++++++++++++++ .../devicetree/bindings/nvmem/mtk-efuse.txt | 43 --------- 2 files changed, 87 insertions(+), 43 deletions(-) create mode 100644 Documentation/devicetree/bindings/nvmem/mediatek,efuse.= yaml delete mode 100644 Documentation/devicetree/bindings/nvmem/mtk-efuse.txt diff --git a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml b/= Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml new file mode 100644 index 000000000000..f6e01ddb7499 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/mediatek,efuse.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek efuse + +description: | + MediaTek's efuse is used for storing calibration data, it can be accessed + on ARM devices usiong I/O mapped memory. + +maintainers: + - Andrew-CT Chen + - Lala Lin + +allOf: + - $ref: "nvmem.yaml#" + +properties: + $nodename: + pattern: "^efuse@[0-9a-f]+$" + + compatible: + oneOf: + - items: + - enum: + - mediatek,mt7622-efuse + - mediatek,mt7623-efuse + - mediatek,mt8173-efuse + - mediatek,mt8192-efuse + - mediatek,mt8195-efuse + - mediatek,mt8516-efuse + - const: mediatek,efuse + - const: mediatek,mt8173-efuse + deprecated: true + + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + efuse@11c10000 { + compatible =3D "mediatek,mt8195-efuse", "mediatek,efuse"; + reg =3D <0x11c10000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + u3_tx_imp_p0: usb3-tx-imp@184,1 { + reg =3D <0x184 0x1>; + bits =3D <0 5>; + }; + u3_rx_imp_p0: usb3-rx-imp@184,2 { + reg =3D <0x184 0x2>; + bits =3D <5 5>; + }; + u3_intr_p0: usb3-intr@185 { + reg =3D <0x185 0x1>; + bits =3D <2 6>; + }; + comb_tx_imp_p1: usb3-tx-imp@186,1 { + reg =3D <0x186 0x1>; + bits =3D <0 5>; + }; + comb_rx_imp_p1: usb3-rx-imp@186,2 { + reg =3D <0x186 0x2>; + bits =3D <5 5>; + }; + comb_intr_p1: usb3-intr@187 { + reg =3D <0x187 0x1>; + bits =3D <2 6>; + }; + u2_intr_p0: usb2-intr-p0@188,1 { + reg =3D <0x188 0x1>; + bits =3D <0 5>; + }; + u2_intr_p1: usb2-intr-p1@188,2 { + reg =3D <0x188 0x2>; + bits =3D <5 5>; + }; + }; diff --git a/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt b/Docume= ntation/devicetree/bindings/nvmem/mtk-efuse.txt deleted file mode 100644 index 39d529599444..000000000000 --- a/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt +++ /dev/null @@ -1,43 +0,0 @@ -=3D Mediatek MTK-EFUSE device tree bindings =3D - -This binding is intended to represent MTK-EFUSE which is found in most Med= iatek SOCs. - -Required properties: -- compatible: should be - "mediatek,mt7622-efuse", "mediatek,efuse": for MT7622 - "mediatek,mt7623-efuse", "mediatek,efuse": for MT7623 - "mediatek,mt8173-efuse" or "mediatek,efuse": for MT8173 - "mediatek,mt8192-efuse", "mediatek,efuse": for MT8192 - "mediatek,mt8195-efuse", "mediatek,efuse": for MT8195 - "mediatek,mt8516-efuse", "mediatek,efuse": for MT8516 -- reg: Should contain registers location and length -- bits: contain the bits range by offset and size - -=3D Data cells =3D -Are child nodes of MTK-EFUSE, bindings of which as described in -bindings/nvmem/nvmem.txt - -Example: - - efuse: efuse@10206000 { - compatible =3D "mediatek,mt8173-efuse"; - reg =3D <0 0x10206000 0 0x1000>; - #address-cells =3D <1>; - #size-cells =3D <1>; - - /* Data cells */ - thermal_calibration: calib@528 { - reg =3D <0x528 0xc>; - }; - }; - -=3D Data consumers =3D -Are device nodes which consume nvmem data cells. - -For example: - - thermal { - ... - nvmem-cells =3D <&thermal_calibration>; - nvmem-cell-names =3D "calibration"; - }; --=20 2.25.1 From nobody Sun Apr 19 04:06:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82B59C433EF for ; Wed, 6 Jul 2022 10:08:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233040AbiGFKIW (ORCPT ); Wed, 6 Jul 2022 06:08:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46358 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232832AbiGFKHo (ORCPT ); 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[86.26.103.58]) by smtp.gmail.com with ESMTPSA id n35-20020a05600c3ba300b003a039054567sm24678143wms.18.2022.07.06.03.07.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Jul 2022 03:07:32 -0700 (PDT) From: Srinivas Kandagatla To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org, Chunfeng Yun , Rob Herring , Srinivas Kandagatla Subject: [PATCH 5/7] dt-bindings: nvmem: mediatek: efuse: add support mt8183 Date: Wed, 6 Jul 2022 11:06:25 +0100 Message-Id: <20220706100627.6534-6-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220706100627.6534-1-srinivas.kandagatla@linaro.org> References: <20220706100627.6534-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Chunfeng Yun Add "mediatek,mt8183-efuse" to fix dtbs check warning. Acked-by: Rob Herring Signed-off-by: Chunfeng Yun Signed-off-by: Srinivas Kandagatla --- Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml b/= Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml index f6e01ddb7499..7c7233e29ecf 100644 --- a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml +++ b/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml @@ -28,6 +28,7 @@ properties: - mediatek,mt7622-efuse - mediatek,mt7623-efuse - mediatek,mt8173-efuse + - mediatek,mt8183-efuse - mediatek,mt8192-efuse - mediatek,mt8195-efuse - mediatek,mt8516-efuse --=20 2.25.1 From nobody Sun Apr 19 04:06:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3D33C43334 for ; Wed, 6 Jul 2022 10:08:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232761AbiGFKI1 (ORCPT ); Wed, 6 Jul 2022 06:08:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46206 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232842AbiGFKHo (ORCPT ); Wed, 6 Jul 2022 06:07:44 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E7164255BB for ; Wed, 6 Jul 2022 03:07:35 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id b26so21339779wrc.2 for ; Wed, 06 Jul 2022 03:07:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oJaroou6RFRRIcoYQ6MD8TjOea6cFRR/OWy8aALAjLE=; b=W9NhYK4AWqLyIUUY6oJm55UzVT5vblwkS9xHir1qGjEcynj40iM+PLyqch+tvCKsUW VC+8LqHVu4zt7B3dnRPcfwf/yT8LVkbr5PvqGC2MLMuDzLMzzAEVeRE+2Nl/36sdExC0 EOzeLmYUAB4TXq5srHzeL2nvQjNOrbu5cEbO9dE963RSU9IFNnPYV9TQ97k9tTexDxSF qpmRE/HI6rzZHR5Jp4QCL7WJuy2mfGElCTANCpRK6IhX3xGifPIFQwOPBNhkmAXKOV2+ URHH2ooYP6ABX7qRaUffUrjZQC1UgsuPjlRbMIQmZUke2PN+iucW5T26j3JzHHvkpgKz yxog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oJaroou6RFRRIcoYQ6MD8TjOea6cFRR/OWy8aALAjLE=; b=P+LasdiTh6bULaScEgAS2Bc88yHd1DZ4ZvVi02trbgUbTaC5yVMSsj1GIItkSn7vyj evjtOZmWfP6VdUkDEJAFwxNBg9l9IGtXFsPmNspxoUTxtUtyGwvVZBarSnW4YVrxGwoR jNdEBuksRYKseIvcVaCvQUg4U+ohvcvzBo0UzQWsi0A3qNGfnqt5MR8A4pH+cRn7Aqnc Y5x5hgVixrQjLwhWob2/ddzFZiKp1HoPjS94BxOm1I50/kvKBnMPF2NmQPGG9ar9VcDW 2xK8FgTZN1kNlY2pbEDabdQK1REszCDs7VImJTaQYYSilnWoJUuqxKzkYJOPR/ynzIr8 aaBA== X-Gm-Message-State: AJIora+bDQOpU4E0k/J6CSsaazpJYuag5qsNXF8x/WU7x8AtXOU6ULJ1 xJPbwsCtcqTHprl62J52Upc8rw== X-Google-Smtp-Source: AGRyM1u7Bwmcpy1A9qZ3DV/VjB4V3kkZw+jedmFXANJaSDuijXRT2hie3nh2G0M2gMVmAaA5QTOrnQ== X-Received: by 2002:a05:6000:15c3:b0:21b:ac2b:d5f5 with SMTP id y3-20020a05600015c300b0021bac2bd5f5mr35562481wry.607.1657102054434; Wed, 06 Jul 2022 03:07:34 -0700 (PDT) Received: from srini-hackbase.lan (cpc90716-aztw32-2-0-cust825.18-1.cable.virginm.net. [86.26.103.58]) by smtp.gmail.com with ESMTPSA id n35-20020a05600c3ba300b003a039054567sm24678143wms.18.2022.07.06.03.07.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Jul 2022 03:07:33 -0700 (PDT) From: Srinivas Kandagatla To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org, Allen-KH Cheng , Rob Herring , Srinivas Kandagatla Subject: [PATCH 6/7] dt-bindings: nvmem: mediatek: efuse: add support for mt8186 Date: Wed, 6 Jul 2022 11:06:26 +0100 Message-Id: <20220706100627.6534-7-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220706100627.6534-1-srinivas.kandagatla@linaro.org> References: <20220706100627.6534-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Allen-KH Cheng Add compatible for mt8186 SoC. Signed-off-by: Allen-KH Cheng Acked-by: Rob Herring Signed-off-by: Srinivas Kandagatla --- Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml b/= Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml index 7c7233e29ecf..b5a1109f2ee1 100644 --- a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml +++ b/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml @@ -29,6 +29,7 @@ properties: - mediatek,mt7623-efuse - mediatek,mt8173-efuse - mediatek,mt8183-efuse + - mediatek,mt8186-efuse - mediatek,mt8192-efuse - mediatek,mt8195-efuse - mediatek,mt8516-efuse --=20 2.25.1 From nobody Sun Apr 19 04:06:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10BBBC433EF for ; Wed, 6 Jul 2022 10:08:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232603AbiGFKIb (ORCPT ); Wed, 6 Jul 2022 06:08:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46366 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232856AbiGFKHq (ORCPT ); Wed, 6 Jul 2022 06:07:46 -0400 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F1BBF25C48 for ; Wed, 6 Jul 2022 03:07:36 -0700 (PDT) Received: by mail-wm1-x32e.google.com with SMTP id c131-20020a1c3589000000b003a19b2bce36so5703322wma.4 for ; Wed, 06 Jul 2022 03:07:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D8DtgYwJoP/V2130+PGEO/pkL1xXDKz8qmvliOW/LJI=; b=MAbBA1ZvhfFw4fDm6wOAOKOuxS/qKDxsuvcH1T72Dugsw9aoGSmRktizFEXOJn/XZo VzGmTecvl7q22iDePjsT21Y+RpDifbceiBq4CyuIxr5uz7lnkMy25yZYiuMgA9p5tWMm JU7caoTydExMRtKdVO/svDNqO2CG5mtnOENdjFLoDWWUJtH5OouT0+meYHPcNxEx+vLU k7Er1mT0v30LUtgolRto1kXf6ilOqpuOOu8yvS0e/JN/5puHNHMcf6caIvaRNiwQ5FbB gC9dRkZ/+veunifxFt07o3AwkXlvYOC+6AiiKZb008NbXoMKU4JWAnTeyRn4x+JxH3I5 umgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D8DtgYwJoP/V2130+PGEO/pkL1xXDKz8qmvliOW/LJI=; b=UWQxetYWRAM33TyxN2Zt/KRMqBo+QqRz1jYcc7TtjIBubjG451bLDlTMFzfTMC4oQ5 OTy6J3XcpBmW7IABG/d03sBJ0GPP/XtjYRDXiD0WviIuK45GYkyGbZJCLIaNGi7C8k2t bcv77GOnJ3/rH/J19wERMzUrIGgHphQQX3WSkqSxXiudaZWL1Z6UN7XfMNH1tP2Riqmc +qhlCZy5AhICZlLhs3n/M3Tv/jzX8MZY9exujaP/XO1CzG35eijTdPCqlFTEzLbeFgev piklu9Gev38M/hOHOrfDX9kSRhlkNfeeMN4U/YVbzhz8NS3p9gW6LjnZaiAnxjdeNDJR V+3Q== X-Gm-Message-State: AJIora+4DOpQr8uTlZrdr4zSceqUm8qr2iz1RTjCh8QgkBbKw6/TQQje XvcR8B/SsPWVPnSUxC0m/WHZ4w== X-Google-Smtp-Source: AGRyM1sTiuaoxWI3ZvWwLGuTZmjpKap/Ril3DCU2PyAV7HdhhcPy4GNOJ1qVBRpsmcrHbFW2K3KwPQ== X-Received: by 2002:a7b:cb98:0:b0:3a2:afc8:72cd with SMTP id m24-20020a7bcb98000000b003a2afc872cdmr13222310wmi.98.1657102055591; Wed, 06 Jul 2022 03:07:35 -0700 (PDT) Received: from srini-hackbase.lan (cpc90716-aztw32-2-0-cust825.18-1.cable.virginm.net. [86.26.103.58]) by smtp.gmail.com with ESMTPSA id n35-20020a05600c3ba300b003a039054567sm24678143wms.18.2022.07.06.03.07.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Jul 2022 03:07:35 -0700 (PDT) From: Srinivas Kandagatla To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno , Srinivas Kandagatla Subject: [PATCH 7/7] nvmem: mtk-efuse: Simplify with devm_platform_get_and_ioremap_resource() Date: Wed, 6 Jul 2022 11:06:27 +0100 Message-Id: <20220706100627.6534-8-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220706100627.6534-1-srinivas.kandagatla@linaro.org> References: <20220706100627.6534-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: AngeloGioacchino Del Regno Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. No functional changes. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Srinivas Kandagatla --- drivers/nvmem/mtk-efuse.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/nvmem/mtk-efuse.c b/drivers/nvmem/mtk-efuse.c index e9a375dd84af..a08e0aedd21c 100644 --- a/drivers/nvmem/mtk-efuse.c +++ b/drivers/nvmem/mtk-efuse.c @@ -41,8 +41,7 @@ static int mtk_efuse_probe(struct platform_device *pdev) if (!priv) return -ENOMEM; =20 - res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); - priv->base =3D devm_ioremap_resource(dev, res); + priv->base =3D devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(priv->base)) return PTR_ERR(priv->base); =20 --=20 2.25.1