From nobody Sat Sep 21 23:40:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98EAACCA47C for ; Wed, 6 Jul 2022 07:55:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231508AbiGFHzG (ORCPT ); Wed, 6 Jul 2022 03:55:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231331AbiGFHzF (ORCPT ); Wed, 6 Jul 2022 03:55:05 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 93635BC9E; Wed, 6 Jul 2022 00:55:02 -0700 (PDT) X-UUID: c0645bd417bd4659af0d22d61d936c7b-20220706 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8,REQID:0c423ea9-0f13-4539-9aac-25625100d6aa,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:0f94e32,CLOUDID:07ea8c63-0b3f-4b2c-b3a6-ed5c044366a0,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: c0645bd417bd4659af0d22d61d936c7b-20220706 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 950240033; Wed, 06 Jul 2022 15:54:57 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Wed, 6 Jul 2022 15:54:55 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 6 Jul 2022 15:54:55 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , "Krzysztof Kozlowski" , Hans Verkuil CC: Chun-Kuang Hu , Rob Landley , Laurent Pinchart , , , , , , Alexandre Courbot , , , , , Benjamin Gaignard , AngeloGioacchino Del Regno , daoyuan huang , Ping-Hsun Wu , , , , , , , , , Subject: [PATCH v21 3/4] arm64: dts: mt8183: add Mediatek MDP3 nodes Date: Wed, 6 Jul 2022 15:54:53 +0800 Message-ID: <20220706075454.15569-4-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220706075454.15569-1-moudy.ho@mediatek.com> References: <20220706075454.15569-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device nodes for Media Data Path 3 (MDP3) modules. Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 63 ++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts= /mediatek/mt8183.dtsi index 9485c1efc87c..daad94a60fb8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1691,6 +1691,60 @@ mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0 0x1000>; }; =20 + mdp3-rdma0@14001000 { + compatible =3D "mediatek,mt8183-mdp3-rdma"; + reg =3D <0 0x14001000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x1000 0x1000>; + mediatek,gce-events =3D , + ; + power-domains =3D <&spm MT8183_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_MDP_RDMA0>, + <&mmsys CLK_MM_MDP_RSZ1>; + iommus =3D <&iommu M4U_PORT_MDP_RDMA0>; + mboxes =3D <&gce 20 CMDQ_THR_PRIO_LOWEST 0>, + <&gce 21 CMDQ_THR_PRIO_LOWEST 0>; + }; + + mdp3-rsz0@14003000 { + compatible =3D "mediatek,mt8183-mdp3-rsz"; + reg =3D <0 0x14003000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x3000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&mmsys CLK_MM_MDP_RSZ0>; + }; + + mdp3-rsz1@14004000 { + compatible =3D "mediatek,mt8183-mdp3-rsz"; + reg =3D <0 0x14004000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x4000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&mmsys CLK_MM_MDP_RSZ1>; + }; + + mdp3-wrot0@14005000 { + compatible =3D "mediatek,mt8183-mdp3-wrot"; + reg =3D <0 0x14005000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x5000 0x1000>; + mediatek,gce-events =3D , + ; + power-domains =3D <&spm MT8183_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_MDP_WROT0>; + iommus =3D <&iommu M4U_PORT_MDP_WROT0>; + }; + + mdp3-wdma@14006000 { + compatible =3D "mediatek,mt8183-mdp3-wdma"; + reg =3D <0 0x14006000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x6000 0x1000>; + mediatek,gce-events =3D , + ; + power-domains =3D <&spm MT8183_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_MDP_WDMA0>; + iommus =3D <&iommu M4U_PORT_MDP_WDMA0>; + }; + ovl0: ovl@14008000 { compatible =3D "mediatek,mt8183-disp-ovl"; reg =3D <0 0x14008000 0 0x1000>; @@ -1834,6 +1888,15 @@ power-domains =3D <&spm MT8183_POWER_DOMAIN_DISP>; }; =20 + mdp3-ccorr@1401c000 { + compatible =3D "mediatek,mt8183-mdp3-ccorr"; + reg =3D <0 0x1401c000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0xc000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&mmsys CLK_MM_MDP_CCORR>; + }; + imgsys: syscon@15020000 { compatible =3D "mediatek,mt8183-imgsys", "syscon"; reg =3D <0 0x15020000 0 0x1000>; --=20 2.18.0