From nobody Sat Sep 21 22:40:25 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C288C433EF for ; Tue, 5 Jul 2022 10:25:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229954AbiGEKZx (ORCPT ); Tue, 5 Jul 2022 06:25:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231308AbiGEKZp (ORCPT ); Tue, 5 Jul 2022 06:25:45 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1E74AE6C; Tue, 5 Jul 2022 03:25:39 -0700 (PDT) X-UUID: 7188962c75d04bd6af6038151b670d1a-20220705 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8,REQID:50bc81cf-2c11-48c2-8199-6e93489a7070,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:-5 X-CID-META: VersionHash:0f94e32,CLOUDID:bd3d9886-57f0-47ca-ba27-fe8c57fbf305,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: 7188962c75d04bd6af6038151b670d1a-20220705 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1962218896; Tue, 05 Jul 2022 18:25:34 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Tue, 5 Jul 2022 18:25:32 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Tue, 5 Jul 2022 18:25:32 +0800 From: Bo-Chen Chen To: , , , , , , CC: , , , , , , , , , , , , , , Bo-Chen Chen Subject: [PATCH v16 1/5] drm/mediatek: dpi: Add YUV422 output support Date: Tue, 5 Jul 2022 18:25:26 +0800 Message-ID: <20220705102530.1344-2-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220705102530.1344-1-rex-bc.chen@mediatek.com> References: <20220705102530.1344-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dp_intf supports YUV422 as output format. In MT8195 Chrome project, YUV422 output format is used for 4K resolution. To support this, it is also needed to support color format transfer. Color format transfer is a new feature for both dpi and dpintf of MT8195. The input format could be RGB888 and output format for dp_intf should be YUV422. Therefore, we add a mtk_dpi_matrix_sel() helper to update the DPI_MATRIX_SET register depending on the color format. Signed-off-by: Guillaume Ranquet Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_dpi.c | 34 +++++++++++++++++++------ drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 6 +++++ 2 files changed, 32 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index ea8d866e67bc..79060f272e4a 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -54,7 +54,8 @@ enum mtk_dpi_out_channel_swap { }; =20 enum mtk_dpi_out_color_format { - MTK_DPI_COLOR_FORMAT_RGB + MTK_DPI_COLOR_FORMAT_RGB, + MTK_DPI_COLOR_FORMAT_YCBCR_422 }; =20 struct mtk_dpi { @@ -409,12 +410,26 @@ static void mtk_dpi_config_disable_edge(struct mtk_dp= i *dpi) static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, enum mtk_dpi_out_color_format format) { - /* only support RGB888 */ - mtk_dpi_config_yuv422_enable(dpi, false); - mtk_dpi_config_csc_enable(dpi, false); - if (dpi->conf->swap_input_support) - mtk_dpi_config_swap_input(dpi, false); - mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); + if (format =3D=3D MTK_DPI_COLOR_FORMAT_YCBCR_422) { + mtk_dpi_config_yuv422_enable(dpi, true); + mtk_dpi_config_csc_enable(dpi, true); + + /* + * If height is smaller than 720, we need to use RGB_TO_BT601 + * to transfer to yuv422. Otherwise, we use RGB_TO_JPEG. + */ + mtk_dpi_mask(dpi, DPI_MATRIX_SET, dpi->mode.hdisplay <=3D 720 ? + MATRIX_SEL_RGB_TO_BT601 : MATRIX_SEL_RGB_TO_JPEG, + INT_MATRIX_SEL_MASK); + + mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); + } else { + mtk_dpi_config_yuv422_enable(dpi, false); + mtk_dpi_config_csc_enable(dpi, false); + if (dpi->conf->swap_input_support) + mtk_dpi_config_swap_input(dpi, false); + mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); + } } =20 static void mtk_dpi_dual_edge(struct mtk_dpi *dpi) @@ -648,7 +663,10 @@ static int mtk_dpi_bridge_atomic_check(struct drm_brid= ge *bridge, dpi->bit_num =3D MTK_DPI_OUT_BIT_NUM_8BITS; dpi->channel_swap =3D MTK_DPI_OUT_CHANNEL_SWAP_RGB; dpi->yc_map =3D MTK_DPI_OUT_YC_MAP_RGB; - dpi->color_format =3D MTK_DPI_COLOR_FORMAT_RGB; + if (out_bus_format =3D=3D MEDIA_BUS_FMT_YUYV8_1X16) + dpi->color_format =3D MTK_DPI_COLOR_FORMAT_YCBCR_422; + else + dpi->color_format =3D MTK_DPI_COLOR_FORMAT_RGB; =20 return 0; } diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/medi= atek/mtk_dpi_regs.h index 3a02fabe1662..9ce300313f3e 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h @@ -217,4 +217,10 @@ =20 #define EDGE_SEL_EN BIT(5) #define H_FRE_2N BIT(25) + +#define DPI_MATRIX_SET 0xB4 +#define INT_MATRIX_SEL_MASK GENMASK(4, 0) +#define MATRIX_SEL_RGB_TO_JPEG 0 +#define MATRIX_SEL_RGB_TO_BT601 2 + #endif /* __MTK_DPI_REGS_H */ --=20 2.18.0 From nobody Sat Sep 21 22:40:25 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BC3FC433EF for ; Tue, 5 Jul 2022 10:26:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231809AbiGEK0D (ORCPT ); Tue, 5 Jul 2022 06:26:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49098 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231305AbiGEKZp (ORCPT ); Tue, 5 Jul 2022 06:25:45 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1FE3ADA9; Tue, 5 Jul 2022 03:25:38 -0700 (PDT) X-UUID: 8c24fe79ded24773b19b27d97bb6c30b-20220705 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8,REQID:876d2e1e-016d-408d-8dd4-52a68c40fee2,OB:0,LO B:0,IP:0,URL:5,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:5 X-CID-META: VersionHash:0f94e32,CLOUDID:9fa47563-0b3f-4b2c-b3a6-ed5c044366a0,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:1,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: 8c24fe79ded24773b19b27d97bb6c30b-20220705 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 555438540; Tue, 05 Jul 2022 18:25:34 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Tue, 5 Jul 2022 18:25:32 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Tue, 5 Jul 2022 18:25:32 +0800 From: Bo-Chen Chen To: , , , , , , CC: , , , , , , , , , , , , , , Bo-Chen Chen Subject: [PATCH v16 2/5] drm/mediatek: dpi: add config to support direct connection to dpi panels Date: Tue, 5 Jul 2022 18:25:27 +0800 Message-ID: <20220705102530.1344-3-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220705102530.1344-1-rex-bc.chen@mediatek.com> References: <20220705102530.1344-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MediaTek dpi supports direct connection to dpi panels while dp_intf does not support. Therefore, add a config "support_direct_pin" to control this. Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_dpi.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 79060f272e4a..da7b2c72881b 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -123,6 +123,7 @@ struct mtk_dpi_yc_limit { * @num_output_fmts: Quantity of supported output formats. * @is_ck_de_pol: Support CK/DE polarity. * @swap_input_support: Support input swap function. + * @support_direct_pin: IP supports direct connection to dpi panels. * @dimension_mask: Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PO= RCH * (no shift). * @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift). @@ -139,6 +140,7 @@ struct mtk_dpi_conf { u32 num_output_fmts; bool is_ck_de_pol; bool swap_input_support; + bool support_direct_pin; u32 dimension_mask; u32 hvsize_mask; u32 channel_swap_shift; @@ -580,11 +582,13 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *d= pi, mtk_dpi_config_channel_limit(dpi); mtk_dpi_config_bit_num(dpi, dpi->bit_num); mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); - mtk_dpi_config_yc_map(dpi, dpi->yc_map); mtk_dpi_config_color_format(dpi, dpi->color_format); - mtk_dpi_config_2n_h_fre(dpi); - mtk_dpi_dual_edge(dpi); - mtk_dpi_config_disable_edge(dpi); + if (dpi->conf->support_direct_pin) { + mtk_dpi_config_yc_map(dpi, dpi->yc_map); + mtk_dpi_config_2n_h_fre(dpi); + mtk_dpi_dual_edge(dpi); + mtk_dpi_config_disable_edge(dpi); + } mtk_dpi_sw_reset(dpi, false); =20 return 0; @@ -843,6 +847,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol =3D true, .swap_input_support =3D true, + .support_direct_pin =3D true, .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, @@ -859,6 +864,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol =3D true, .swap_input_support =3D true, + .support_direct_pin =3D true, .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, @@ -874,6 +880,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts), .is_ck_de_pol =3D true, .swap_input_support =3D true, + .support_direct_pin =3D true, .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, @@ -889,6 +896,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts), .is_ck_de_pol =3D true, .swap_input_support =3D true, + .support_direct_pin =3D true, .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, --=20 2.18.0 From nobody Sat Sep 21 22:40:25 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CEAF3C43334 for ; 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Tue, 05 Jul 2022 18:25:34 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Tue, 5 Jul 2022 18:25:33 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Tue, 5 Jul 2022 18:25:33 +0800 From: Bo-Chen Chen To: , , , , , , CC: , , , , , , , , , , , , , , Bo-Chen Chen Subject: [PATCH v16 3/5] drm/mediatek: dpi: Add input_2pixel config support Date: Tue, 5 Jul 2022 18:25:28 +0800 Message-ID: <20220705102530.1344-4-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220705102530.1344-1-rex-bc.chen@mediatek.com> References: <20220705102530.1344-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The input pixel per iteration could be different, so we add a new config "input_2pixel" to control this. Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_dpi.c | 7 +++++++ drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 1 + 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index da7b2c72881b..a1dcb3089c3a 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -124,6 +124,8 @@ struct mtk_dpi_yc_limit { * @is_ck_de_pol: Support CK/DE polarity. * @swap_input_support: Support input swap function. * @support_direct_pin: IP supports direct connection to dpi panels. + * @input_2pixel: Input pixel of dp_intf is 2 pixel per round, so enable t= his + * config to enable this feature. * @dimension_mask: Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PO= RCH * (no shift). * @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift). @@ -141,6 +143,7 @@ struct mtk_dpi_conf { bool is_ck_de_pol; bool swap_input_support; bool support_direct_pin; + bool input_2pixel; u32 dimension_mask; u32 hvsize_mask; u32 channel_swap_shift; @@ -589,6 +592,10 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dp= i, mtk_dpi_dual_edge(dpi); mtk_dpi_config_disable_edge(dpi); } + if (dpi->conf->input_2pixel) { + mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN, + DPINTF_INPUT_2P_EN); + } mtk_dpi_sw_reset(dpi, false); =20 return 0; diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/medi= atek/mtk_dpi_regs.h index 9ce300313f3e..305066577d41 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h @@ -40,6 +40,7 @@ #define FAKE_DE_LEVEN BIT(21) #define FAKE_DE_RODD BIT(22) #define FAKE_DE_REVEN BIT(23) +#define DPINTF_INPUT_2P_EN BIT(29) =20 #define DPI_OUTPUT_SETTING 0x14 #define CH_SWAP 0 --=20 2.18.0 From nobody Sat Sep 21 22:40:25 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DC38C433EF for ; Tue, 5 Jul 2022 10:25:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230004AbiGEKZ4 (ORCPT ); Tue, 5 Jul 2022 06:25:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49102 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231231AbiGEKZp (ORCPT ); Tue, 5 Jul 2022 06:25:45 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2ADA82189; Tue, 5 Jul 2022 03:25:40 -0700 (PDT) X-UUID: d15fdab4606244ff822c8f542a7472f6-20220705 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8,REQID:7f422703-0c95-4a9c-ba81-549e013d5603,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:-5 X-CID-META: VersionHash:0f94e32,CLOUDID:a0a47563-0b3f-4b2c-b3a6-ed5c044366a0,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: d15fdab4606244ff822c8f542a7472f6-20220705 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1818336431; Tue, 05 Jul 2022 18:25:34 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Tue, 5 Jul 2022 18:25:33 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Tue, 5 Jul 2022 18:25:33 +0800 From: Bo-Chen Chen To: , , , , , , CC: , , , , , , , , , , , , , , Bo-Chen Chen Subject: [PATCH v16 4/5] drm/mediatek: dpi: Add pixels_per_iter config support Date: Tue, 5 Jul 2022 18:25:29 +0800 Message-ID: <20220705102530.1344-5-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220705102530.1344-1-rex-bc.chen@mediatek.com> References: <20220705102530.1344-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The quantity of output for one iteration could be different for dpi and dp_intf. For dp_intf, it's 4 pixels for one iteration it's 1 pixel for one iteration for dpi. Therefore, we add a new config "pixels_per_iter" to control quantity of transferred pixels per iteration. Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_dpi.c | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index a1dcb3089c3a..5f71a68c6a0b 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -132,6 +132,7 @@ struct mtk_dpi_yc_limit { * @channel_swap_shift: Shift value of channel swap. * @yuv422_en_bit: Enable bit of yuv422. * @csc_enable_bit: Enable bit of CSC. + * @pixels_per_iter: Quantity of transferred pixels per iteration. */ struct mtk_dpi_conf { unsigned int (*cal_factor)(int clock); @@ -149,6 +150,7 @@ struct mtk_dpi_conf { u32 channel_swap_shift; u32 yuv422_en_bit; u32 csc_enable_bit; + u32 pixels_per_iter; }; =20 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mas= k) @@ -522,7 +524,14 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dp= i, clk_set_rate(dpi->tvd_clk, pll_rate); pll_rate =3D clk_get_rate(dpi->tvd_clk); =20 + /* + * Depending on the IP version, we may output a different amount of + * pixels for each iteration: divide the clock by this number and + * adjust the display porches accordingly. + */ vm.pixelclock =3D pll_rate / factor; + vm.pixelclock /=3D dpi->conf->pixels_per_iter; + if ((dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_LE) || (dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_BE)) clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2); @@ -541,9 +550,16 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dp= i, MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; dpi_pol.vsync_pol =3D vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ? MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; - hsync.sync_width =3D vm.hsync_len; - hsync.back_porch =3D vm.hback_porch; - hsync.front_porch =3D vm.hfront_porch; + + /* + * Depending on the IP version, we may output a different amount of + * pixels for each iteration: divide the clock by this number and + * adjust the display porches accordingly. + */ + hsync.sync_width =3D vm.hsync_len / dpi->conf->pixels_per_iter; + hsync.back_porch =3D vm.hback_porch / dpi->conf->pixels_per_iter; + hsync.front_porch =3D vm.hfront_porch / dpi->conf->pixels_per_iter; + hsync.shift_half_line =3D false; vsync_lodd.sync_width =3D vm.vsync_len; vsync_lodd.back_porch =3D vm.vback_porch; @@ -852,6 +868,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .max_clock_khz =3D 300000, .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), + .pixels_per_iter =3D 1, .is_ck_de_pol =3D true, .swap_input_support =3D true, .support_direct_pin =3D true, @@ -869,6 +886,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .max_clock_khz =3D 150000, .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), + .pixels_per_iter =3D 1, .is_ck_de_pol =3D true, .swap_input_support =3D true, .support_direct_pin =3D true, @@ -885,6 +903,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .max_clock_khz =3D 100000, .output_fmts =3D mt8183_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts), + .pixels_per_iter =3D 1, .is_ck_de_pol =3D true, .swap_input_support =3D true, .support_direct_pin =3D true, @@ -901,6 +920,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .max_clock_khz =3D 150000, .output_fmts =3D mt8183_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts), + .pixels_per_iter =3D 1, .is_ck_de_pol =3D true, .swap_input_support =3D true, .support_direct_pin =3D true, --=20 2.18.0 From nobody Sat Sep 21 22:40:25 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E470C433EF for ; Tue, 5 Jul 2022 10:26:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231817AbiGEK0I (ORCPT ); Tue, 5 Jul 2022 06:26:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49112 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231372AbiGEKZq (ORCPT ); Tue, 5 Jul 2022 06:25:46 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 202DA2AC3; Tue, 5 Jul 2022 03:25:41 -0700 (PDT) X-UUID: 443a77fc714a46e48ff617db64538ef4-20220705 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8,REQID:72fa5360-ef72-4550-8bff-0c7b1ea22e5d,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:-5 X-CID-META: VersionHash:0f94e32,CLOUDID:36eea7d6-5d6d-4eaf-a635-828a3ee48b7c,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: 443a77fc714a46e48ff617db64538ef4-20220705 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1788566286; Tue, 05 Jul 2022 18:25:34 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Tue, 5 Jul 2022 18:25:33 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Tue, 5 Jul 2022 18:25:33 +0800 From: Bo-Chen Chen To: , , , , , , CC: , , , , , , , , , , , , , , Bo-Chen Chen Subject: [PATCH v16 5/5] drm/mediatek: dpi: Add dp_intf support Date: Tue, 5 Jul 2022 18:25:30 +0800 Message-ID: <20220705102530.1344-6-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220705102530.1344-1-rex-bc.chen@mediatek.com> References: <20220705102530.1344-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Guillaume Ranquet Dpintf is the displayport interface hardware unit. This unit is similar to dpi and can reuse most of the code. This patch adds support for mt8195-dpintf to this dpi driver. Main differences are: - 4 pixels for one iteration for dp_intf while dpi is 1 pixel for one iteration. Therefore, we add a new config "pixels_per_iter" to control quantity of transferred pixels per iteration. - Input of dp_intf is two pixels per iteration, so we add a new config "input_2pixel" to control this. - Some register contents differ slightly between the two components. To work around this I added register bits/masks with a DPINTF_ prefix and use them where different. Based on a separate driver for dpintf created by Jitao shi . Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Guillaume Ranquet Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_dpi.c | 32 +++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 11 +++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 4 +++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 ++ 5 files changed, 51 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 5f71a68c6a0b..c176d2041eca 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -853,6 +853,16 @@ static unsigned int mt8183_calculate_factor(int clock) return 2; } =20 +static unsigned int mt8195_dpintf_calculate_factor(int clock) +{ + if (clock < 70000) + return 4; + else if (clock < 200000) + return 2; + else + return 1; +} + static const u32 mt8173_output_fmts[] =3D { MEDIA_BUS_FMT_RGB888_1X24, }; @@ -862,6 +872,11 @@ static const u32 mt8183_output_fmts[] =3D { MEDIA_BUS_FMT_RGB888_2X12_BE, }; =20 +static const u32 mt8195_output_fmts[] =3D { + MEDIA_BUS_FMT_RGB888_1X24, + MEDIA_BUS_FMT_YUYV8_1X16, +}; + static const struct mtk_dpi_conf mt8173_conf =3D { .cal_factor =3D mt8173_calculate_factor, .reg_h_fre_con =3D 0xe0, @@ -931,6 +946,20 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .csc_enable_bit =3D CSC_ENABLE, }; =20 +static const struct mtk_dpi_conf mt8195_dpintf_conf =3D { + .cal_factor =3D mt8195_dpintf_calculate_factor, + .max_clock_khz =3D 600000, + .output_fmts =3D mt8195_output_fmts, + .num_output_fmts =3D ARRAY_SIZE(mt8195_output_fmts), + .pixels_per_iter =3D 4, + .input_2pixel =3D true, + .dimension_mask =3D DPINTF_HPW_MASK, + .hvsize_mask =3D DPINTF_HSIZE_MASK, + .channel_swap_shift =3D DPINTF_CH_SWAP, + .yuv422_en_bit =3D DPINTF_YUV422_EN, + .csc_enable_bit =3D DPINTF_CSC_ENABLE, +}; + static int mtk_dpi_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -1053,6 +1082,9 @@ static const struct of_device_id mtk_dpi_of_ids[] =3D= { { .compatible =3D "mediatek,mt8192-dpi", .data =3D &mt8192_conf, }, + { .compatible =3D "mediatek,mt8195-dp-intf", + .data =3D &mt8195_dpintf_conf, + }, { }, }; MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids); diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/medi= atek/mtk_dpi_regs.h index 305066577d41..62bd4931b344 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h @@ -40,10 +40,13 @@ #define FAKE_DE_LEVEN BIT(21) #define FAKE_DE_RODD BIT(22) #define FAKE_DE_REVEN BIT(23) +#define DPINTF_YUV422_EN BIT(24) +#define DPINTF_CSC_ENABLE BIT(26) #define DPINTF_INPUT_2P_EN BIT(29) =20 #define DPI_OUTPUT_SETTING 0x14 #define CH_SWAP 0 +#define DPINTF_CH_SWAP 1 #define CH_SWAP_MASK (0x7 << 0) #define SWAP_RGB 0x00 #define SWAP_GBR 0x01 @@ -81,8 +84,10 @@ #define DPI_SIZE 0x18 #define HSIZE 0 #define HSIZE_MASK (0x1FFF << 0) +#define DPINTF_HSIZE_MASK (0xFFFF << 0) #define VSIZE 16 #define VSIZE_MASK (0x1FFF << 16) +#define DPINTF_VSIZE_MASK (0xFFFF << 16) =20 #define DPI_DDR_SETTING 0x1C #define DDR_EN BIT(0) @@ -94,24 +99,30 @@ #define DPI_TGEN_HWIDTH 0x20 #define HPW 0 #define HPW_MASK (0xFFF << 0) +#define DPINTF_HPW_MASK (0xFFFF << 0) =20 #define DPI_TGEN_HPORCH 0x24 #define HBP 0 #define HBP_MASK (0xFFF << 0) +#define DPINTF_HBP_MASK (0xFFFF << 0) #define HFP 16 #define HFP_MASK (0xFFF << 16) +#define DPINTF_HFP_MASK (0xFFFF << 16) =20 #define DPI_TGEN_VWIDTH 0x28 #define DPI_TGEN_VPORCH 0x2C =20 #define VSYNC_WIDTH_SHIFT 0 #define VSYNC_WIDTH_MASK (0xFFF << 0) +#define DPINTF_VSYNC_WIDTH_MASK (0xFFFF << 0) #define VSYNC_HALF_LINE_SHIFT 16 #define VSYNC_HALF_LINE_MASK BIT(16) #define VSYNC_BACK_PORCH_SHIFT 0 #define VSYNC_BACK_PORCH_MASK (0xFFF << 0) +#define DPINTF_VSYNC_BACK_PORCH_MASK (0xFFFF << 0) #define VSYNC_FRONT_PORCH_SHIFT 16 #define VSYNC_FRONT_PORCH_MASK (0xFFF << 16) +#define DPINTF_VSYNC_FRONT_PORCH_MASK (0xFFFF << 16) =20 #define DPI_BG_HCNTL 0x30 #define BG_RIGHT (0x1FFF << 0) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/= mediatek/mtk_drm_ddp_comp.c index 2aab1e1eda36..5bef085714a1 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -427,6 +427,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COM= P_TYPE_MAX] =3D { [MTK_DISP_RDMA] =3D "rdma", [MTK_DISP_UFOE] =3D "ufoe", [MTK_DISP_WDMA] =3D "wdma", + [MTK_DP_INTF] =3D "dp-intf", [MTK_DPI] =3D "dpi", [MTK_DSI] =3D "dsi", }; @@ -450,6 +451,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[= DDP_COMPONENT_DRM_ID_MAX] [DDP_COMPONENT_DRM_OVL_ADAPTOR] =3D { MTK_DISP_OVL_ADAPTOR, 0, &ddp_ovl_a= daptor }, [DDP_COMPONENT_DSC0] =3D { MTK_DISP_DSC, 0, &ddp_dsc }, [DDP_COMPONENT_DSC1] =3D { MTK_DISP_DSC, 1, &ddp_dsc }, + [DDP_COMPONENT_DP_INTF0] =3D { MTK_DP_INTF, 0, &ddp_dpi }, + [DDP_COMPONENT_DP_INTF1] =3D { MTK_DP_INTF, 1, &ddp_dpi }, [DDP_COMPONENT_DSI0] =3D { MTK_DSI, 0, &ddp_dsi }, [DDP_COMPONENT_DSI1] =3D { MTK_DSI, 1, &ddp_dsi }, [DDP_COMPONENT_DSI2] =3D { MTK_DSI, 2, &ddp_dsi }, @@ -575,6 +578,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct = mtk_ddp_comp *comp, type =3D=3D MTK_DISP_PWM || type =3D=3D MTK_DISP_RDMA || type =3D=3D MTK_DPI || + type =3D=3D MTK_DP_INTF || type =3D=3D MTK_DSI) return 0; =20 diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/= mediatek/mtk_drm_ddp_comp.h index af9a6671f9c4..3084cc4e2830 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -38,6 +38,7 @@ enum mtk_ddp_comp_type { MTK_DISP_UFOE, MTK_DISP_WDMA, MTK_DPI, + MTK_DP_INTF, MTK_DSI, MTK_DDP_COMP_TYPE_MAX, }; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index 78e79c8449c8..a7a0dbbca823 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -788,6 +788,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = =3D { .data =3D (void *)MTK_DPI }, { .compatible =3D "mediatek,mt8192-dpi", .data =3D (void *)MTK_DPI }, + { .compatible =3D "mediatek,mt8195-dp-intf", + .data =3D (void *)MTK_DP_INTF }, { .compatible =3D "mediatek,mt2701-dsi", .data =3D (void *)MTK_DSI }, { .compatible =3D "mediatek,mt8173-dsi", @@ -931,6 +933,7 @@ static int mtk_drm_probe(struct platform_device *pdev) comp_type =3D=3D MTK_DISP_OVL_2L || comp_type =3D=3D MTK_DISP_OVL_ADAPTOR || comp_type =3D=3D MTK_DISP_RDMA || + comp_type =3D=3D MTK_DP_INTF || comp_type =3D=3D MTK_DPI || comp_type =3D=3D MTK_DSI) { dev_info(dev, "Adding component match for %pOF\n", --=20 2.18.0