From nobody Sun Apr 19 09:08:23 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F0A0C43334 for ; Mon, 4 Jul 2022 12:16:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231475AbiGDMQ1 (ORCPT ); Mon, 4 Jul 2022 08:16:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53326 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234020AbiGDMQX (ORCPT ); Mon, 4 Jul 2022 08:16:23 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B345DC7; Mon, 4 Jul 2022 05:16:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1656936983; x=1688472983; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1zpvFutj9ylvTYybbRgrTiqXegJkTTl/MiyrxahTwa8=; b=z1wQH2g+qA0WogVQBbFolbyw9HasDQTaCVJqh5CmgEZaKOmFRfmip1mt Aixzf5h1RWBrY108wPP5V3G9ZPzcLENS+bTyxxjvRzMsYqusYGwXwIKo7 WtxSgZiAAWgIfPaO9fOsWexMFx0iSASHBeXdLlIviA28/aOlitjYMjPZW WFDSaF7Acp3495HKKOLjF1FpcDlPUb8vs1e3FnIIbNtOe5QeuV47TASF2 AVDMNMpqVGCE7faQTmIwAVTRfLj0vfC5gBs39LyGPRC1H/FqCBdFlkA6z jOgReLgNrs0OgdJnoyXkuKbuovLo3JwQ+DHWjqGHYY6/w5DmxouRcwo5K Q==; X-IronPort-AV: E=Sophos;i="5.92,243,1650956400"; d="scan'208";a="180647849" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 04 Jul 2022 05:16:22 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 4 Jul 2022 05:16:22 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 4 Jul 2022 05:16:19 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Philipp Zabel , Daire McNamara CC: Paul Walmsley , Albert Ou , , , , , Rob Herring Subject: [PATCH v2 01/12] dt-bindings: clk: microchip: mpfs: add reset controller support Date: Mon, 4 Jul 2022 13:15:48 +0100 Message-ID: <20220704121558.2088698-2-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220704121558.2088698-1-conor.dooley@microchip.com> References: <20220704121558.2088698-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The "peripheral" devices on PolarFire SoC can be put into reset, so update the device tree binding to reflect the presence of a reset controller. Reviewed-by: Rob Herring Signed-off-by: Conor Dooley Reviewed-by: Daire McNamara --- .../bindings/clock/microchip,mpfs.yaml | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml b/= Documentation/devicetree/bindings/clock/microchip,mpfs.yaml index 016a4f378b9b..1d0b6a4fda42 100644 --- a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml @@ -40,8 +40,21 @@ properties: const: 1 description: | The clock consumer should specify the desired clock by having the cl= ock - ID in its "clocks" phandle cell. See include/dt-bindings/clock/micro= chip,mpfs-clock.h - for the full list of PolarFire clock IDs. + ID in its "clocks" phandle cell. + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full li= st of + PolarFire clock IDs. + + resets: + maxItems: 1 + + '#reset-cells': + description: + The AHB/AXI peripherals on the PolarFire SoC have reset support, so = from + CLK_ENVM to CLK_CFM. The reset consumer should specify the desired + peripheral via the clock ID in its "resets" phandle cell. + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full li= st of + PolarFire clock IDs. + const: 1 =20 required: - compatible --=20 2.36.1 From nobody Sun Apr 19 09:08:23 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AC9ACCA47C for ; Mon, 4 Jul 2022 12:16:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233903AbiGDMQf (ORCPT ); Mon, 4 Jul 2022 08:16:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53420 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234177AbiGDMQ1 (ORCPT ); Mon, 4 Jul 2022 08:16:27 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 99D3B5FD1; Mon, 4 Jul 2022 05:16:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1656936986; x=1688472986; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OXB45vMtUs1nfpYjQaPxWOb/6F6yUpAgZPrlzrfPAk4=; b=pJtHMdf6ZniIEw0IAS6In39v7+tcxx3RqVMwnZnNZpT36f8OKit/YPlc bOkFv/2+kVeoPaYJav8An2vzkMCEEzXkpCr7C8ohcbEiSF8LQY0JxRk/E rHARRg0E1QJ0pjvQsOBHPGauqQ2+Xf/e0DCt7pbhqkbUgIIYch1Ni/sxR quMkbwCJjc7tL0EEXOkU/3fZCFlsbCn0gV8NtfXa3nFlikYWBcrYLVqTv M6aw3pN2tBC36QDKvlkruN1KHy7IH8E0XsS3yhfO4Jp+crVzPlfB8alTj VY6Wt4Xn0ckNvfs86Aq1YO4zKWY5ZgkxGoutMqfKw3sap1q02d3Tb9XAR g==; X-IronPort-AV: E=Sophos;i="5.92,243,1650956400"; d="scan'208";a="180647863" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 04 Jul 2022 05:16:25 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 4 Jul 2022 05:16:25 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 4 Jul 2022 05:16:22 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Philipp Zabel , Daire McNamara CC: Paul Walmsley , Albert Ou , , , , Subject: [PATCH v2 02/12] clk: microchip: mpfs: add reset controller Date: Mon, 4 Jul 2022 13:15:49 +0100 Message-ID: <20220704121558.2088698-3-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220704121558.2088698-1-conor.dooley@microchip.com> References: <20220704121558.2088698-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a reset controller to PolarFire SoC's clock driver. This reset controller is registered as an aux device and read/write functions exported to the drivers namespace so that the reset controller can access the peripheral device reset register. Signed-off-by: Conor Dooley Reviewed-by: Daire McNamara --- drivers/clk/microchip/Kconfig | 1 + drivers/clk/microchip/clk-mpfs.c | 116 ++++++++++++++++++++++++++++--- include/soc/microchip/mpfs.h | 8 +++ 3 files changed, 114 insertions(+), 11 deletions(-) diff --git a/drivers/clk/microchip/Kconfig b/drivers/clk/microchip/Kconfig index a5a99873c4f5..b46e864b3bd8 100644 --- a/drivers/clk/microchip/Kconfig +++ b/drivers/clk/microchip/Kconfig @@ -6,5 +6,6 @@ config COMMON_CLK_PIC32 config MCHP_CLK_MPFS bool "Clk driver for PolarFire SoC" depends on (RISCV && SOC_MICROCHIP_POLARFIRE) || COMPILE_TEST + select AUXILIARY_BUS help Supports Clock Configuration for PolarFire SoC diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-m= pfs.c index 070c3b896559..a93f78619dc3 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -3,12 +3,14 @@ * Daire McNamara, * Copyright (C) 2020 Microchip Technology Inc. All rights reserved. */ +#include #include #include #include #include #include #include +#include =20 /* address offset of control registers */ #define REG_MSSPLL_REF_CR 0x08u @@ -28,6 +30,7 @@ #define MSSPLL_FIXED_DIV 4u =20 struct mpfs_clock_data { + struct device *dev; void __iomem *base; void __iomem *msspll_base; struct clk_hw_onecell_data hw_data; @@ -302,10 +305,6 @@ static int mpfs_periph_clk_enable(struct clk_hw *hw) =20 spin_lock_irqsave(&mpfs_clk_lock, flags); =20 - reg =3D readl_relaxed(base_addr + REG_SUBBLK_RESET_CR); - val =3D reg & ~(1u << periph->shift); - writel_relaxed(val, base_addr + REG_SUBBLK_RESET_CR); - reg =3D readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); val =3D reg | (1u << periph->shift); writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR); @@ -339,12 +338,9 @@ static int mpfs_periph_clk_is_enabled(struct clk_hw *h= w) void __iomem *base_addr =3D periph_hw->sys_base; u32 reg; =20 - reg =3D readl_relaxed(base_addr + REG_SUBBLK_RESET_CR); - if ((reg & (1u << periph->shift)) =3D=3D 0u) { - reg =3D readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); - if (reg & (1u << periph->shift)) - return 1; - } + reg =3D readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); + if (reg & (1u << periph->shift)) + return 1; =20 return 0; } @@ -438,6 +434,98 @@ static int mpfs_clk_register_periphs(struct device *de= v, struct mpfs_periph_hw_c return 0; } =20 +/* + * Peripheral clock resets + */ + +#if IS_ENABLED(CONFIG_RESET_CONTROLLER) + +u32 mpfs_reset_read(struct device *dev) +{ + struct mpfs_clock_data *clock_data =3D dev_get_drvdata(dev->parent); + + return readl_relaxed(clock_data->base + REG_SUBBLK_RESET_CR); +} +EXPORT_SYMBOL_NS_GPL(mpfs_reset_read, MCHP_CLK_MPFS); + +void mpfs_reset_write(struct device *dev, u32 val) +{ + struct mpfs_clock_data *clock_data =3D dev_get_drvdata(dev->parent); + + writel_relaxed(val, clock_data->base + REG_SUBBLK_RESET_CR); +} +EXPORT_SYMBOL_NS_GPL(mpfs_reset_write, MCHP_CLK_MPFS); + +static void mpfs_reset_unregister_adev(void *_adev) +{ + struct auxiliary_device *adev =3D _adev; + + auxiliary_device_delete(adev); +} + +static void mpfs_reset_adev_release(struct device *dev) +{ + struct auxiliary_device *adev =3D to_auxiliary_dev(dev); + + auxiliary_device_uninit(adev); + + kfree(adev); +} + +static struct auxiliary_device *mpfs_reset_adev_alloc(struct mpfs_clock_da= ta *clk_data) +{ + struct auxiliary_device *adev; + int ret; + + adev =3D kzalloc(sizeof(*adev), GFP_KERNEL); + if (!adev) + return ERR_PTR(-ENOMEM); + + adev->name =3D "reset-mpfs"; + adev->dev.parent =3D clk_data->dev; + adev->dev.release =3D mpfs_reset_adev_release; + adev->id =3D 666u; + + ret =3D auxiliary_device_init(adev); + if (ret) { + kfree(adev); + return ERR_PTR(ret); + } + + return adev; +} + +static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data) +{ + struct auxiliary_device *adev; + int ret; + + adev =3D mpfs_reset_adev_alloc(clk_data); + if (IS_ERR(adev)) + return PTR_ERR(adev); + + ret =3D auxiliary_device_add(adev); + if (ret) { + auxiliary_device_uninit(adev); + return ret; + } + + ret =3D devm_add_action_or_reset(clk_data->dev, mpfs_reset_unregister_ade= v, adev); + if (ret) + return ret; + + return 0; +} + +#else /* !CONFIG_RESET_CONTROLLER */ + +static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data) +{ + return 0; +} + +#endif /* !CONFIG_RESET_CONTROLLER */ + static int mpfs_clk_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -462,6 +550,8 @@ static int mpfs_clk_probe(struct platform_device *pdev) return PTR_ERR(clk_data->msspll_base); =20 clk_data->hw_data.num =3D num_clks; + clk_data->dev =3D dev; + dev_set_drvdata(dev, clk_data); =20 ret =3D mpfs_clk_register_mssplls(dev, mpfs_msspll_clks, ARRAY_SIZE(mpfs_= msspll_clks), clk_data); @@ -481,6 +571,10 @@ static int mpfs_clk_probe(struct platform_device *pdev) if (ret) return ret; =20 + ret =3D mpfs_reset_controller_register(clk_data); + if (ret) + return ret; + return ret; } =20 @@ -488,7 +582,7 @@ static const struct of_device_id mpfs_clk_of_match_tabl= e[] =3D { { .compatible =3D "microchip,mpfs-clkcfg", }, {} }; -MODULE_DEVICE_TABLE(of, mpfs_clk_match_table); +MODULE_DEVICE_TABLE(of, mpfs_clk_of_match_table); =20 static struct platform_driver mpfs_clk_driver =3D { .probe =3D mpfs_clk_probe, diff --git a/include/soc/microchip/mpfs.h b/include/soc/microchip/mpfs.h index 6466515262bd..f916dcde457f 100644 --- a/include/soc/microchip/mpfs.h +++ b/include/soc/microchip/mpfs.h @@ -40,4 +40,12 @@ struct mpfs_sys_controller *mpfs_sys_controller_get(stru= ct device *dev); =20 #endif /* if IS_ENABLED(CONFIG_POLARFIRE_SOC_SYS_CTRL) */ =20 +#if IS_ENABLED(CONFIG_MCHP_CLK_MPFS) + +u32 mpfs_reset_read(struct device *dev); + +void mpfs_reset_write(struct device *dev, u32 val); + +#endif /* if IS_ENABLED(CONFIG_MCHP_CLK_MPFS) */ + #endif /* __SOC_MPFS_H__ */ --=20 2.36.1 From nobody Sun Apr 19 09:08:23 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CDDDECCA482 for ; Mon, 4 Jul 2022 12:16:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234358AbiGDMQi (ORCPT ); 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X-IronPort-AV: E=Sophos;i="5.92,243,1650956400"; d="scan'208";a="102909240" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 04 Jul 2022 05:16:28 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 4 Jul 2022 05:16:28 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 4 Jul 2022 05:16:26 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Philipp Zabel , Daire McNamara CC: Paul Walmsley , Albert Ou , , , , Subject: [PATCH v2 03/12] reset: add polarfire soc reset support Date: Mon, 4 Jul 2022 13:15:50 +0100 Message-ID: <20220704121558.2088698-4-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220704121558.2088698-1-conor.dooley@microchip.com> References: <20220704121558.2088698-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for the resets on Microchip's PolarFire SoC (MPFS). Reset control is a single register, wedged in between registers for clock control. To fit with existed DT etc, the reset controller is created using the aux device framework & set up in the clock driver. Signed-off-by: Conor Dooley Acked-by: Philipp Zabel Reviewed-by: Daire McNamara Reviewed-by: Philipp Zabel --- drivers/reset/Kconfig | 7 ++ drivers/reset/Makefile | 2 +- drivers/reset/reset-mpfs.c | 157 +++++++++++++++++++++++++++++++++++++ 3 files changed, 165 insertions(+), 1 deletion(-) create mode 100644 drivers/reset/reset-mpfs.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 93c8d07ee328..edfdc7b2bc5f 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -122,6 +122,13 @@ config RESET_MCHP_SPARX5 help This driver supports switch core reset for the Microchip Sparx5 SoC. =20 +config RESET_POLARFIRE_SOC + bool "Microchip PolarFire SoC (MPFS) Reset Driver" + depends on AUXILIARY_BUS && MCHP_CLK_MPFS + default MCHP_CLK_MPFS + help + This driver supports peripheral reset for the Microchip PolarFire SoC + config RESET_MESON tristate "Meson Reset Driver" depends on ARCH_MESON || COMPILE_TEST diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index a80a9c4008a7..5fac3a753858 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_RESET_K210) +=3D reset-k210.o obj-$(CONFIG_RESET_LANTIQ) +=3D reset-lantiq.o obj-$(CONFIG_RESET_LPC18XX) +=3D reset-lpc18xx.o obj-$(CONFIG_RESET_MCHP_SPARX5) +=3D reset-microchip-sparx5.o +obj-$(CONFIG_RESET_POLARFIRE_SOC) +=3D reset-mpfs.o obj-$(CONFIG_RESET_MESON) +=3D reset-meson.o obj-$(CONFIG_RESET_MESON_AUDIO_ARB) +=3D reset-meson-audio-arb.o obj-$(CONFIG_RESET_NPCM) +=3D reset-npcm.o @@ -38,4 +39,3 @@ obj-$(CONFIG_RESET_UNIPHIER) +=3D reset-uniphier.o obj-$(CONFIG_RESET_UNIPHIER_GLUE) +=3D reset-uniphier-glue.o obj-$(CONFIG_RESET_ZYNQ) +=3D reset-zynq.o obj-$(CONFIG_ARCH_ZYNQMP) +=3D reset-zynqmp.o - diff --git a/drivers/reset/reset-mpfs.c b/drivers/reset/reset-mpfs.c new file mode 100644 index 000000000000..1580d1b68d61 --- /dev/null +++ b/drivers/reset/reset-mpfs.c @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * PolarFire SoC (MPFS) Peripheral Clock Reset Controller + * + * Author: Conor Dooley + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. + * + */ +#include +#include +#include +#include +#include +#include +#include + +/* + * The ENVM reset is the lowest bit in the register & I am using the CLK_F= OO + * defines in the dt to make things easier to configure - so this is accou= nting + * for the offset of 3 there. + */ +#define MPFS_PERIPH_OFFSET CLK_ENVM +#define MPFS_NUM_RESETS 30u +#define MPFS_SLEEP_MIN_US 100 +#define MPFS_SLEEP_MAX_US 200 + +/* block concurrent access to the soft reset register */ +static DEFINE_SPINLOCK(mpfs_reset_lock); + +/* + * Peripheral clock resets + */ + +static int mpfs_assert(struct reset_controller_dev *rcdev, unsigned long i= d) +{ + unsigned long flags; + u32 reg; + + spin_lock_irqsave(&mpfs_reset_lock, flags); + + reg =3D mpfs_reset_read(rcdev->dev); + reg |=3D BIT(id); + mpfs_reset_write(rcdev->dev, reg); + + spin_unlock_irqrestore(&mpfs_reset_lock, flags); + + return 0; +} + +static int mpfs_deassert(struct reset_controller_dev *rcdev, unsigned long= id) +{ + unsigned long flags; + u32 reg, val; + + spin_lock_irqsave(&mpfs_reset_lock, flags); + + reg =3D mpfs_reset_read(rcdev->dev); + val =3D reg & ~BIT(id); + mpfs_reset_write(rcdev->dev, val); + + spin_unlock_irqrestore(&mpfs_reset_lock, flags); + + return 0; +} + +static int mpfs_status(struct reset_controller_dev *rcdev, unsigned long i= d) +{ + u32 reg =3D mpfs_reset_read(rcdev->dev); + + /* + * It is safe to return here as MPFS_NUM_RESETS makes sure the sign bit + * is never hit. + */ + return (reg & BIT(id)); +} + +static int mpfs_reset(struct reset_controller_dev *rcdev, unsigned long id) +{ + mpfs_assert(rcdev, id); + + usleep_range(MPFS_SLEEP_MIN_US, MPFS_SLEEP_MAX_US); + + mpfs_deassert(rcdev, id); + + return 0; +} + +static const struct reset_control_ops mpfs_reset_ops =3D { + .reset =3D mpfs_reset, + .assert =3D mpfs_assert, + .deassert =3D mpfs_deassert, + .status =3D mpfs_status, +}; + +static int mpfs_reset_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + unsigned int index =3D reset_spec->args[0]; + + /* + * CLK_RESERVED does not map to a clock, but it does map to a reset, + * so it has to be accounted for here. It is the reset for the fabric, + * so if this reset gets called - do not reset it. + */ + if (index =3D=3D CLK_RESERVED) { + dev_err(rcdev->dev, "Resetting the fabric is not supported\n"); + return -EINVAL; + } + + if (index < MPFS_PERIPH_OFFSET || index >=3D (MPFS_PERIPH_OFFSET + rcdev-= >nr_resets)) { + dev_err(rcdev->dev, "Invalid reset index %u\n", index); + return -EINVAL; + } + + return index - MPFS_PERIPH_OFFSET; +} + +static int mpfs_reset_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct device *dev =3D &adev->dev; + struct reset_controller_dev *rcdev; + + rcdev =3D devm_kzalloc(dev, sizeof(*rcdev), GFP_KERNEL); + if (!rcdev) + return -ENOMEM; + + rcdev->dev =3D dev; + rcdev->dev->parent =3D dev->parent; + rcdev->ops =3D &mpfs_reset_ops; + rcdev->of_node =3D dev->parent->of_node; + rcdev->of_reset_n_cells =3D 1; + rcdev->of_xlate =3D mpfs_reset_xlate; + rcdev->nr_resets =3D MPFS_NUM_RESETS; + + return devm_reset_controller_register(dev, rcdev); +} + +static const struct auxiliary_device_id mpfs_reset_ids[] =3D { + { + .name =3D "clk_mpfs.reset-mpfs", + }, + { } +}; +MODULE_DEVICE_TABLE(auxiliary, mpfs_reset_ids); + +static struct auxiliary_driver mpfs_reset_driver =3D { + .probe =3D mpfs_reset_probe, + .id_table =3D mpfs_reset_ids, +}; + +module_auxiliary_driver(mpfs_reset_driver); + +MODULE_DESCRIPTION("Microchip PolarFire SoC Reset Driver"); +MODULE_AUTHOR("Conor Dooley "); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS(MCHP_CLK_MPFS); --=20 2.36.1 From nobody Sun Apr 19 09:08:23 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D4B2CCA479 for ; Mon, 4 Jul 2022 12:16:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234218AbiGDMQl (ORCPT ); Mon, 4 Jul 2022 08:16:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53660 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234152AbiGDMQe (ORCPT ); Mon, 4 Jul 2022 08:16:34 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 01F221147C; Mon, 4 Jul 2022 05:16:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1656936992; x=1688472992; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ko9vKOsJ7sZrLYlGKuINmPgddn22iKvDujCMEuBPRPQ=; b=Gzt40sQO23Y6B18/elxlsFMJw585IDjv0FrOYLWJrzC2SnmWieo9gjwV qAiKl2v3Jh7CdaF406V0w4Bh0IoFWZTAWFPOYFjA4nB06g+gGXMhTaRSk 4JBLYfMk+zm0u8B5H6OBIQIw10XHULbhLiHDdHQXjNm44UAGmL5wZ7IFb KjzS/SfLFwsMVpFDwBwiQjsKiXzTWIloIKb5yBE+KjT/nzejefACOn7W1 KDVg/WprUmL7OqsYFiLliJVOTV1FOPmz4A9L+w2P6EaOg0+L54MZ5YPak ZXkDReZCuGKp118yGH+4x+j9UVmx2VkgINm3zQOsMz8kmqX5nXxflwFXj Q==; X-IronPort-AV: E=Sophos;i="5.92,243,1650956400"; d="scan'208";a="170953274" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 04 Jul 2022 05:16:32 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 4 Jul 2022 05:16:32 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 4 Jul 2022 05:16:29 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Philipp Zabel , Daire McNamara CC: Paul Walmsley , Albert Ou , , , , Subject: [PATCH v2 04/12] MAINTAINERS: add polarfire soc reset controller Date: Mon, 4 Jul 2022 13:15:51 +0100 Message-ID: <20220704121558.2088698-5-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220704121558.2088698-1-conor.dooley@microchip.com> References: <20220704121558.2088698-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the newly added reset controller for the PolarFire SoC (MPFS) to the existing MAINTAINERS entry. Signed-off-by: Conor Dooley Reviewed-by: Daire McNamara --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 1fc9ead83d2a..7b82ffce6c22 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17159,6 +17159,7 @@ L: linux-riscv@lists.infradead.org S: Supported F: arch/riscv/boot/dts/microchip/ F: drivers/mailbox/mailbox-mpfs.c +F: drivers/reset/reset-mpfs.c F: drivers/soc/microchip/ F: include/soc/microchip/mpfs.h =20 --=20 2.36.1 From nobody Sun Apr 19 09:08:23 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB3F5CCA479 for ; Mon, 4 Jul 2022 12:16:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234453AbiGDMQx (ORCPT ); Mon, 4 Jul 2022 08:16:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53474 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233544AbiGDMQk (ORCPT ); Mon, 4 Jul 2022 08:16:40 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DAE98FD0C; Mon, 4 Jul 2022 05:16:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1656936996; x=1688472996; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vbBZBVb8B22VRpxKb/0dz1k5O/GgdpM5EBwjjdArU6w=; b=zMxJ2mURmdR/hW/41s1n61m8cGbq6HA4IsrRGLVG43qDcK6YLghy+r6s E2ox+/UIqP16hYxg6vCx/z1WnO/rlGuCkcwJX2R5QNgnS20sBW33ale9V V4pKsv+As4znt9GNOGS0ubKK22TAIvWR9OANZKEnPX7+ghAfaF/Wvs5Kb yEQ5c3LFUFQfmbtgE8Wv2By16cHZhB09D1z6cxwK2KGUS38F0P7ALyfOZ eeAZGtZI1knKMXkCkmd6VxTw7oMK1pDkUDgfajluRkAENXZilo3t0VrEI cMi670CdJjMjmq0LNmqbMRVFbcORytXv6HEzAvoj9pT9jOP5ooqqHkic7 A==; X-IronPort-AV: E=Sophos;i="5.92,243,1650956400"; d="scan'208";a="166262012" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 04 Jul 2022 05:16:36 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 4 Jul 2022 05:16:35 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 4 Jul 2022 05:16:32 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Philipp Zabel , Daire McNamara CC: Paul Walmsley , Albert Ou , , , , Subject: [PATCH v2 05/12] riscv: dts: microchip: add mpfs specific macb reset support Date: Mon, 4 Jul 2022 13:15:52 +0100 Message-ID: <20220704121558.2088698-6-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220704121558.2088698-1-conor.dooley@microchip.com> References: <20220704121558.2088698-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The macb on PolarFire SoC has reset support which the generic compatible does not use. Add the newly introduced MPFS specific compatible as the primary compatible to avail of this support & wire up the reset to the clock controllers devicetree entry. Signed-off-by: Conor Dooley Reviewed-by: Daire McNamara --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/= microchip/mpfs.dtsi index 8c3259134194..5a33cbf9467a 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -197,6 +197,7 @@ clkcfg: clkcfg@20002000 { reg =3D <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; clocks =3D <&refclk>; #clock-cells =3D <1>; + #reset-cells =3D <1>; }; =20 mmuart0: serial@20000000 { @@ -331,7 +332,7 @@ i2c1: i2c@2010b000 { }; =20 mac0: ethernet@20110000 { - compatible =3D "cdns,macb"; + compatible =3D "microchip,mpfs-macb", "cdns,macb"; reg =3D <0x0 0x20110000 0x0 0x2000>; #address-cells =3D <1>; #size-cells =3D <0>; @@ -340,11 +341,12 @@ mac0: ethernet@20110000 { local-mac-address =3D [00 00 00 00 00 00]; clocks =3D <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; clock-names =3D "pclk", "hclk"; + resets =3D <&clkcfg CLK_MAC0>; status =3D "disabled"; }; =20 mac1: ethernet@20112000 { - compatible =3D "cdns,macb"; + compatible =3D "microchip,mpfs-macb", "cdns,macb"; reg =3D <0x0 0x20112000 0x0 0x2000>; #address-cells =3D <1>; #size-cells =3D <0>; @@ -353,6 +355,7 @@ mac1: ethernet@20112000 { local-mac-address =3D [00 00 00 00 00 00]; clocks =3D <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; clock-names =3D "pclk", "hclk"; + resets =3D <&clkcfg CLK_MAC1>; status =3D "disabled"; }; =20 --=20 2.36.1 From nobody Sun Apr 19 09:08:23 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C759C433EF for ; Mon, 4 Jul 2022 12:16:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234472AbiGDMQ4 (ORCPT ); Mon, 4 Jul 2022 08:16:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53498 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234404AbiGDMQo (ORCPT ); Mon, 4 Jul 2022 08:16:44 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BCDC1DF28; Mon, 4 Jul 2022 05:16:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1656937002; x=1688473002; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eJyjWXL9c84MeJXb2RPk2+RjYUjKmqKhd+L3kczClrw=; b=cq0c38OC7I8aAcSoF+umOT0lucx45Z924q0FzNSg6tB13y2+wDcKBsff 4hNaufAYecylmnoK6r+700zro3foj4ihLLWJUOuISdSckMmERmv8i44Kl qcPk9+TyVlotAtlAU/9irLC2ZZm8ixYkCyKswyXrp6BN+RA07BjPQSyth kgN8lOSWx2RAMlHcN6QP1XkcaSVAyaEPvEl0MZVsvAdLP21kw56c828eD JwZp2dTC6JFpmjeInZcjydoRr/jRTbCaIiq1ylzp6WaA7E1OS6GaLV79c wWp+tWJjSsavhJ/jpJ7X/8hYOUfM2CuvpPIYnUmslTCo43cnEoLDVfFD8 w==; X-IronPort-AV: E=Sophos;i="5.92,243,1650956400"; d="scan'208";a="163197485" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 04 Jul 2022 05:16:41 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 4 Jul 2022 05:16:38 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 4 Jul 2022 05:16:35 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Philipp Zabel , Daire McNamara CC: Paul Walmsley , Albert Ou , , , , Subject: [PATCH v2 06/12] clk: microchip: mpfs: add module_authors entries Date: Mon, 4 Jul 2022 13:15:53 +0100 Message-ID: <20220704121558.2088698-7-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220704121558.2088698-1-conor.dooley@microchip.com> References: <20220704121558.2088698-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add myself and Daire as authors since we were mainly responsible for the drivers development. Signed-off-by: Conor Dooley Reviewed-by: Daire McNamara --- drivers/clk/microchip/clk-mpfs.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-m= pfs.c index a93f78619dc3..c7cafd61b7f7 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -1,7 +1,9 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Daire McNamara, - * Copyright (C) 2020 Microchip Technology Inc. All rights reserved. + * Author: Daire McNamara + * Author: Conor Dooley + * + * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved. */ #include #include @@ -605,4 +607,6 @@ static void __exit clk_mpfs_exit(void) module_exit(clk_mpfs_exit); =20 MODULE_DESCRIPTION("Microchip PolarFire SoC Clock Driver"); +MODULE_AUTHOR("Daire McNamara "); +MODULE_AUTHOR("Conor Dooley "); MODULE_LICENSE("GPL v2"); --=20 2.36.1 From nobody Sun Apr 19 09:08:23 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D204FC433EF for ; Mon, 4 Jul 2022 12:17:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234404AbiGDMQ6 (ORCPT ); Mon, 4 Jul 2022 08:16:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54098 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234177AbiGDMQp (ORCPT ); Mon, 4 Jul 2022 08:16:45 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 76EE612080; Mon, 4 Jul 2022 05:16:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1656937003; x=1688473003; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Mzg8ZCgvIj+8F4A33eNTKpQ/g0iJ645P4B1jsOTxDBA=; b=E2W027HUCCd8/3PE5scyyEAhyC3lHCf4YeXD2EtczNZcqdNkFZo/GkrX EsmTN4Jt/RmCneJh1YZI0XwGrNnZi4V/2aN2Dmpg6UwR88hSyBabwsqMZ WMyzJg6Fq4jjhwiX4UEkMbbcI1yqZgqWPtpwSySyq7QG7U4MKVYcnPG33 7Buudt1GfMGitYSvOR44gZ9gQWBGvu36eCsO6s7tlcCH5Du9XMXa75A7K +l3WRBidN1oZWorbXIYpp3TlWSxvro1J6Cwft7jHanwmxio5aAv4q++IH wuD9Yff4LOby7WbFvaGUTHb+RPs2pqfJzQn494/cx3lWZd3BCPRHjHahx w==; X-IronPort-AV: E=Sophos;i="5.92,243,1650956400"; d="scan'208";a="163197495" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 04 Jul 2022 05:16:42 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 4 Jul 2022 05:16:41 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 4 Jul 2022 05:16:38 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Philipp Zabel , Daire McNamara CC: Paul Walmsley , Albert Ou , , , , Subject: [PATCH v2 07/12] clk: microchip: mpfs: add MSS pll's set & round rate Date: Mon, 4 Jul 2022 13:15:54 +0100 Message-ID: <20220704121558.2088698-8-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220704121558.2088698-1-conor.dooley@microchip.com> References: <20220704121558.2088698-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The MSS pll is not a fixed frequency clock, so add set() & round_rate() support. Control is limited to a 7 bit output divider as other devices on the FPGA occupy the other three outputs of the PLL & prevent changing the multiplier. Signed-off-by: Conor Dooley Reviewed-by: Daire McNamara --- drivers/clk/microchip/clk-mpfs.c | 54 ++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-m= pfs.c index c7cafd61b7f7..a23f63bcd074 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -131,8 +131,62 @@ static unsigned long mpfs_clk_msspll_recalc_rate(struc= t clk_hw *hw, unsigned lon return prate * mult / (ref_div * MSSPLL_FIXED_DIV * postdiv); } =20 +static long mpfs_clk_msspll_round_rate(struct clk_hw *hw, unsigned long ra= te, unsigned long *prate) +{ + struct mpfs_msspll_hw_clock *msspll_hw =3D to_mpfs_msspll_clk(hw); + void __iomem *mult_addr =3D msspll_hw->base + msspll_hw->reg_offset; + void __iomem *ref_div_addr =3D msspll_hw->base + REG_MSSPLL_REF_CR; + u32 mult, ref_div; + unsigned long rate_before_ctrl; + + mult =3D readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; + mult &=3D clk_div_mask(MSSPLL_FBDIV_WIDTH); + ref_div =3D readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; + ref_div &=3D clk_div_mask(MSSPLL_REFDIV_WIDTH); + + rate_before_ctrl =3D rate * (ref_div * MSSPLL_FIXED_DIV) / mult; + + return divider_round_rate(hw, rate_before_ctrl, prate, NULL, MSSPLL_POSTD= IV_WIDTH, + msspll_hw->flags); +} + +static int mpfs_clk_msspll_set_rate(struct clk_hw *hw, unsigned long rate,= unsigned long prate) +{ + struct mpfs_msspll_hw_clock *msspll_hw =3D to_mpfs_msspll_clk(hw); + void __iomem *mult_addr =3D msspll_hw->base + msspll_hw->reg_offset; + void __iomem *ref_div_addr =3D msspll_hw->base + REG_MSSPLL_REF_CR; + void __iomem *postdiv_addr =3D msspll_hw->base + REG_MSSPLL_POSTDIV_CR; + u32 mult, ref_div, postdiv; + int divider_setting; + unsigned long rate_before_ctrl, flags; + + mult =3D readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; + mult &=3D clk_div_mask(MSSPLL_FBDIV_WIDTH); + ref_div =3D readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; + ref_div &=3D clk_div_mask(MSSPLL_REFDIV_WIDTH); + + rate_before_ctrl =3D rate * (ref_div * MSSPLL_FIXED_DIV) / mult; + divider_setting =3D divider_get_val(rate_before_ctrl, prate, NULL, MSSPLL= _POSTDIV_WIDTH, + msspll_hw->flags); + + if (divider_setting < 0) + return divider_setting; + + spin_lock_irqsave(&mpfs_clk_lock, flags); + + postdiv =3D readl_relaxed(postdiv_addr); + postdiv &=3D ~(clk_div_mask(MSSPLL_POSTDIV_WIDTH) << MSSPLL_POSTDIV_SHIFT= ); + writel_relaxed(postdiv, postdiv_addr); + + spin_unlock_irqrestore(&mpfs_clk_lock, flags); + + return 0; +} + static const struct clk_ops mpfs_clk_msspll_ops =3D { .recalc_rate =3D mpfs_clk_msspll_recalc_rate, + .round_rate =3D mpfs_clk_msspll_round_rate, + .set_rate =3D mpfs_clk_msspll_set_rate, }; =20 #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \ --=20 2.36.1 From nobody Sun Apr 19 09:08:23 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87FD8CCA479 for ; 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X-IronPort-AV: E=Sophos;i="5.92,243,1650956400"; d="scan'208";a="166262039" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 04 Jul 2022 05:16:47 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 4 Jul 2022 05:16:44 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 4 Jul 2022 05:16:41 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Philipp Zabel , Daire McNamara CC: Paul Walmsley , Albert Ou , , , , Subject: [PATCH v2 08/12] clk: microchip: mpfs: move id & offset out of clock structs Date: Mon, 4 Jul 2022 13:15:55 +0100 Message-ID: <20220704121558.2088698-9-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220704121558.2088698-1-conor.dooley@microchip.com> References: <20220704121558.2088698-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The id and offset are the only thing differentiating the clock structs from "regular" clock structures. On the pretext of converting to more normal structures, move the id and offset out of the clock structs and into the hw structs instead. Signed-off-by: Conor Dooley Reviewed-by: Daire McNamara --- drivers/clk/microchip/clk-mpfs.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-m= pfs.c index a23f63bcd074..750f28481498 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -53,8 +53,6 @@ struct mpfs_msspll_hw_clock { =20 struct mpfs_cfg_clock { const struct clk_div_table *table; - unsigned int id; - u32 reg_offset; u8 shift; u8 width; u8 flags; @@ -65,12 +63,13 @@ struct mpfs_cfg_hw_clock { void __iomem *sys_base; struct clk_hw hw; struct clk_init_data init; + unsigned int id; + u32 reg_offset; }; =20 #define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, h= w) =20 struct mpfs_periph_clock { - unsigned int id; u8 shift; }; =20 @@ -78,6 +77,7 @@ struct mpfs_periph_hw_clock { struct mpfs_periph_clock periph; void __iomem *sys_base; struct clk_hw hw; + unsigned int id; }; =20 #define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_cl= ock, hw) @@ -243,7 +243,7 @@ static unsigned long mpfs_cfg_clk_recalc_rate(struct cl= k_hw *hw, unsigned long p void __iomem *base_addr =3D cfg_hw->sys_base; u32 val; =20 - val =3D readl_relaxed(base_addr + cfg->reg_offset) >> cfg->shift; + val =3D readl_relaxed(base_addr + cfg_hw->reg_offset) >> cfg->shift; val &=3D clk_div_mask(cfg->width); =20 return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->w= idth); @@ -272,10 +272,10 @@ static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, u= nsigned long rate, unsigned return divider_setting; =20 spin_lock_irqsave(&mpfs_clk_lock, flags); - val =3D readl_relaxed(base_addr + cfg->reg_offset); + val =3D readl_relaxed(base_addr + cfg_hw->reg_offset); val &=3D ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift); val |=3D divider_setting << cfg->shift; - writel_relaxed(val, base_addr + cfg->reg_offset); + writel_relaxed(val, base_addr + cfg_hw->reg_offset); =20 spin_unlock_irqrestore(&mpfs_clk_lock, flags); =20 @@ -289,11 +289,11 @@ static const struct clk_ops mpfs_clk_cfg_ops =3D { }; =20 #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offs= et) { \ - .cfg.id =3D _id, \ + .id =3D _id, \ .cfg.shift =3D _shift, \ .cfg.width =3D _width, \ .cfg.table =3D _table, \ - .cfg.reg_offset =3D _offset, \ + .reg_offset =3D _offset, \ .cfg.flags =3D _flags, \ .hw.init =3D CLK_HW_INIT(_name, _parent, &mpfs_clk_cfg_ops, 0), \ } @@ -306,11 +306,11 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] =3D { CLK_CFG(CLK_AHB, "clk_ahb", "clk_msspll", 4, 2, mpfs_div_ahb_table, 0, REG_CLOCK_CONFIG_CR), { - .cfg.id =3D CLK_RTCREF, + .id =3D CLK_RTCREF, .cfg.shift =3D 0, .cfg.width =3D 12, .cfg.table =3D mpfs_div_rtcref_table, - .cfg.reg_offset =3D REG_RTC_CLOCK_CR, + .reg_offset =3D REG_RTC_CLOCK_CR, .cfg.flags =3D CLK_DIVIDER_ONE_BASED, .hw.init =3D CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &mpfs_clk_cfg_ops,= 0), @@ -338,9 +338,9 @@ static int mpfs_clk_register_cfgs(struct device *dev, s= truct mpfs_cfg_hw_clock * ret =3D mpfs_clk_register_cfg(dev, cfg_hw, sys_base); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", - cfg_hw->cfg.id); + cfg_hw->id); =20 - id =3D cfg_hw->cfg.id; + id =3D cfg_hw->id; data->hw_data.hws[id] =3D &cfg_hw->hw; } =20 @@ -408,7 +408,7 @@ static const struct clk_ops mpfs_periph_clk_ops =3D { }; =20 #define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \ - .periph.id =3D _id, \ + .id =3D _id, \ .periph.shift =3D _shift, \ .hw.init =3D CLK_HW_INIT_HW(_name, _parent, &mpfs_periph_clk_ops, \ _flags), \ @@ -481,9 +481,9 @@ static int mpfs_clk_register_periphs(struct device *dev= , struct mpfs_periph_hw_c ret =3D mpfs_clk_register_periph(dev, periph_hw, sys_base); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", - periph_hw->periph.id); + periph_hw->id); =20 - id =3D periph_hws[i].periph.id; + id =3D periph_hws[i].id; data->hw_data.hws[id] =3D &periph_hw->hw; } =20 --=20 2.36.1 From nobody Sun Apr 19 09:08:23 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36E16C43334 for ; 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X-IronPort-AV: E=Sophos;i="5.92,243,1650956400"; d="scan'208";a="170953303" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 04 Jul 2022 05:16:48 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 4 Jul 2022 05:16:47 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 4 Jul 2022 05:16:44 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Philipp Zabel , Daire McNamara CC: Paul Walmsley , Albert Ou , , , , Subject: [PATCH v2 09/12] clk: microchip: mpfs: simplify control reg access Date: Mon, 4 Jul 2022 13:15:56 +0100 Message-ID: <20220704121558.2088698-10-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220704121558.2088698-1-conor.dooley@microchip.com> References: <20220704121558.2088698-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The control reg addresses are known when the clocks are registered, so we can, instead of assigning a base pointer to the structs, assign the control reg addresses directly. Accordingly, remove the interim variables used during reads/writes to those registers. Signed-off-by: Conor Dooley Reviewed-by: Daire McNamara --- drivers/clk/microchip/clk-mpfs.c | 42 +++++++++++++------------------- 1 file changed, 17 insertions(+), 25 deletions(-) diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-m= pfs.c index 750f28481498..0330c2839a24 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -52,6 +52,7 @@ struct mpfs_msspll_hw_clock { #define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_cl= ock, hw) =20 struct mpfs_cfg_clock { + void __iomem *reg; const struct clk_div_table *table; u8 shift; u8 width; @@ -60,7 +61,6 @@ struct mpfs_cfg_clock { =20 struct mpfs_cfg_hw_clock { struct mpfs_cfg_clock cfg; - void __iomem *sys_base; struct clk_hw hw; struct clk_init_data init; unsigned int id; @@ -70,12 +70,12 @@ struct mpfs_cfg_hw_clock { #define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, h= w) =20 struct mpfs_periph_clock { + void __iomem *reg; u8 shift; }; =20 struct mpfs_periph_hw_clock { struct mpfs_periph_clock periph; - void __iomem *sys_base; struct clk_hw hw; unsigned int id; }; @@ -214,14 +214,13 @@ static int mpfs_clk_register_msspll(struct device *de= v, struct mpfs_msspll_hw_cl static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspl= l_hw_clock *msspll_hws, unsigned int num_clks, struct mpfs_clock_data *data) { - void __iomem *base =3D data->msspll_base; unsigned int i; int ret; =20 for (i =3D 0; i < num_clks; i++) { struct mpfs_msspll_hw_clock *msspll_hw =3D &msspll_hws[i]; =20 - ret =3D mpfs_clk_register_msspll(dev, msspll_hw, base); + ret =3D mpfs_clk_register_msspll(dev, msspll_hw, data->msspll_base); if (ret) return dev_err_probe(dev, ret, "failed to register msspll id: %d\n", CLK_MSSPLL); @@ -240,10 +239,9 @@ static unsigned long mpfs_cfg_clk_recalc_rate(struct c= lk_hw *hw, unsigned long p { struct mpfs_cfg_hw_clock *cfg_hw =3D to_mpfs_cfg_clk(hw); struct mpfs_cfg_clock *cfg =3D &cfg_hw->cfg; - void __iomem *base_addr =3D cfg_hw->sys_base; u32 val; =20 - val =3D readl_relaxed(base_addr + cfg_hw->reg_offset) >> cfg->shift; + val =3D readl_relaxed(cfg->reg) >> cfg->shift; val &=3D clk_div_mask(cfg->width); =20 return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->w= idth); @@ -261,7 +259,6 @@ static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, uns= igned long rate, unsigned { struct mpfs_cfg_hw_clock *cfg_hw =3D to_mpfs_cfg_clk(hw); struct mpfs_cfg_clock *cfg =3D &cfg_hw->cfg; - void __iomem *base_addr =3D cfg_hw->sys_base; unsigned long flags; u32 val; int divider_setting; @@ -272,10 +269,10 @@ static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, u= nsigned long rate, unsigned return divider_setting; =20 spin_lock_irqsave(&mpfs_clk_lock, flags); - val =3D readl_relaxed(base_addr + cfg_hw->reg_offset); + val =3D readl_relaxed(cfg->reg); val &=3D ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift); val |=3D divider_setting << cfg->shift; - writel_relaxed(val, base_addr + cfg_hw->reg_offset); + writel_relaxed(val, cfg->reg); =20 spin_unlock_irqrestore(&mpfs_clk_lock, flags); =20 @@ -318,9 +315,9 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] =3D { }; =20 static int mpfs_clk_register_cfg(struct device *dev, struct mpfs_cfg_hw_cl= ock *cfg_hw, - void __iomem *sys_base) + void __iomem *base) { - cfg_hw->sys_base =3D sys_base; + cfg_hw->cfg.reg =3D base + cfg_hw->reg_offset; =20 return devm_clk_hw_register(dev, &cfg_hw->hw); } @@ -328,14 +325,13 @@ static int mpfs_clk_register_cfg(struct device *dev, = struct mpfs_cfg_hw_clock *c static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_c= lock *cfg_hws, unsigned int num_clks, struct mpfs_clock_data *data) { - void __iomem *sys_base =3D data->base; unsigned int i, id; int ret; =20 for (i =3D 0; i < num_clks; i++) { struct mpfs_cfg_hw_clock *cfg_hw =3D &cfg_hws[i]; =20 - ret =3D mpfs_clk_register_cfg(dev, cfg_hw, sys_base); + ret =3D mpfs_clk_register_cfg(dev, cfg_hw, data->base); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", cfg_hw->id); @@ -355,15 +351,14 @@ static int mpfs_periph_clk_enable(struct clk_hw *hw) { struct mpfs_periph_hw_clock *periph_hw =3D to_mpfs_periph_clk(hw); struct mpfs_periph_clock *periph =3D &periph_hw->periph; - void __iomem *base_addr =3D periph_hw->sys_base; u32 reg, val; unsigned long flags; =20 spin_lock_irqsave(&mpfs_clk_lock, flags); =20 - reg =3D readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); + reg =3D readl_relaxed(periph->reg); val =3D reg | (1u << periph->shift); - writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR); + writel_relaxed(val, periph->reg); =20 spin_unlock_irqrestore(&mpfs_clk_lock, flags); =20 @@ -374,15 +369,14 @@ static void mpfs_periph_clk_disable(struct clk_hw *hw) { struct mpfs_periph_hw_clock *periph_hw =3D to_mpfs_periph_clk(hw); struct mpfs_periph_clock *periph =3D &periph_hw->periph; - void __iomem *base_addr =3D periph_hw->sys_base; u32 reg, val; unsigned long flags; =20 spin_lock_irqsave(&mpfs_clk_lock, flags); =20 - reg =3D readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); + reg =3D readl_relaxed(periph->reg); val =3D reg & ~(1u << periph->shift); - writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR); + writel_relaxed(val, periph->reg); =20 spin_unlock_irqrestore(&mpfs_clk_lock, flags); } @@ -391,10 +385,9 @@ static int mpfs_periph_clk_is_enabled(struct clk_hw *h= w) { struct mpfs_periph_hw_clock *periph_hw =3D to_mpfs_periph_clk(hw); struct mpfs_periph_clock *periph =3D &periph_hw->periph; - void __iomem *base_addr =3D periph_hw->sys_base; u32 reg; =20 - reg =3D readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); + reg =3D readl_relaxed(periph->reg); if (reg & (1u << periph->shift)) return 1; =20 @@ -461,9 +454,9 @@ static struct mpfs_periph_hw_clock mpfs_periph_clks[] = =3D { }; =20 static int mpfs_clk_register_periph(struct device *dev, struct mpfs_periph= _hw_clock *periph_hw, - void __iomem *sys_base) + void __iomem *base) { - periph_hw->sys_base =3D sys_base; + periph_hw->periph.reg =3D base + REG_SUBBLK_CLOCK_CR; =20 return devm_clk_hw_register(dev, &periph_hw->hw); } @@ -471,14 +464,13 @@ static int mpfs_clk_register_periph(struct device *de= v, struct mpfs_periph_hw_cl static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_perip= h_hw_clock *periph_hws, int num_clks, struct mpfs_clock_data *data) { - void __iomem *sys_base =3D data->base; unsigned int i, id; int ret; =20 for (i =3D 0; i < num_clks; i++) { struct mpfs_periph_hw_clock *periph_hw =3D &periph_hws[i]; =20 - ret =3D mpfs_clk_register_periph(dev, periph_hw, sys_base); + ret =3D mpfs_clk_register_periph(dev, periph_hw, data->base); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", periph_hw->id); --=20 2.36.1 From nobody Sun Apr 19 09:08:23 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35C08CCA481 for ; Mon, 4 Jul 2022 12:18:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233980AbiGDMSB (ORCPT ); Mon, 4 Jul 2022 08:18:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54062 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234400AbiGDMQy (ORCPT ); Mon, 4 Jul 2022 08:16:54 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B7C7BE0B3; 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Mon, 4 Jul 2022 05:16:50 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 4 Jul 2022 05:16:48 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Philipp Zabel , Daire McNamara CC: Paul Walmsley , Albert Ou , , , , Subject: [PATCH v2 10/12] clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo() Date: Mon, 4 Jul 2022 13:15:57 +0100 Message-ID: <20220704121558.2088698-11-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220704121558.2088698-1-conor.dooley@microchip.com> References: <20220704121558.2088698-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The register functions are now comprised of only a single operation each and no longer add anything to the driver. Delete them. Signed-off-by: Conor Dooley Reviewed-by: Daire McNamara --- drivers/clk/microchip/clk-mpfs.c | 33 ++++++-------------------------- 1 file changed, 6 insertions(+), 27 deletions(-) diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-m= pfs.c index 0330c2839a24..e58d0bc4669a 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -203,14 +203,6 @@ static struct mpfs_msspll_hw_clock mpfs_msspll_clks[] = =3D { MSSPLL_FBDIV_WIDTH, 0, REG_MSSPLL_SSCG_2_CR), }; =20 -static int mpfs_clk_register_msspll(struct device *dev, struct mpfs_msspll= _hw_clock *msspll_hw, - void __iomem *base) -{ - msspll_hw->base =3D base; - - return devm_clk_hw_register(dev, &msspll_hw->hw); -} - static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspl= l_hw_clock *msspll_hws, unsigned int num_clks, struct mpfs_clock_data *data) { @@ -220,7 +212,8 @@ static int mpfs_clk_register_mssplls(struct device *dev= , struct mpfs_msspll_hw_c for (i =3D 0; i < num_clks; i++) { struct mpfs_msspll_hw_clock *msspll_hw =3D &msspll_hws[i]; =20 - ret =3D mpfs_clk_register_msspll(dev, msspll_hw, data->msspll_base); + msspll_hw->base =3D data->msspll_base; + ret =3D devm_clk_hw_register(dev, &msspll_hw->hw); if (ret) return dev_err_probe(dev, ret, "failed to register msspll id: %d\n", CLK_MSSPLL); @@ -314,14 +307,6 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] =3D { } }; =20 -static int mpfs_clk_register_cfg(struct device *dev, struct mpfs_cfg_hw_cl= ock *cfg_hw, - void __iomem *base) -{ - cfg_hw->cfg.reg =3D base + cfg_hw->reg_offset; - - return devm_clk_hw_register(dev, &cfg_hw->hw); -} - static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_c= lock *cfg_hws, unsigned int num_clks, struct mpfs_clock_data *data) { @@ -331,7 +316,8 @@ static int mpfs_clk_register_cfgs(struct device *dev, s= truct mpfs_cfg_hw_clock * for (i =3D 0; i < num_clks; i++) { struct mpfs_cfg_hw_clock *cfg_hw =3D &cfg_hws[i]; =20 - ret =3D mpfs_clk_register_cfg(dev, cfg_hw, data->base); + cfg_hw->cfg.reg =3D data->base + cfg_hw->reg_offset; + ret =3D devm_clk_hw_register(dev, &cfg_hw->hw); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", cfg_hw->id); @@ -453,14 +439,6 @@ static struct mpfs_periph_hw_clock mpfs_periph_clks[] = =3D { CLK_PERIPH(CLK_CFM, "clk_periph_cfm", PARENT_CLK(AHB), 29, 0), }; =20 -static int mpfs_clk_register_periph(struct device *dev, struct mpfs_periph= _hw_clock *periph_hw, - void __iomem *base) -{ - periph_hw->periph.reg =3D base + REG_SUBBLK_CLOCK_CR; - - return devm_clk_hw_register(dev, &periph_hw->hw); -} - static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_perip= h_hw_clock *periph_hws, int num_clks, struct mpfs_clock_data *data) { @@ -470,7 +448,8 @@ static int mpfs_clk_register_periphs(struct device *dev= , struct mpfs_periph_hw_c for (i =3D 0; i < num_clks; i++) { struct mpfs_periph_hw_clock *periph_hw =3D &periph_hws[i]; =20 - ret =3D mpfs_clk_register_periph(dev, periph_hw, data->base); + periph_hw->periph.reg =3D data->base + REG_SUBBLK_CLOCK_CR; + ret =3D devm_clk_hw_register(dev, &periph_hw->hw); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", periph_hw->id); --=20 2.36.1 From nobody Sun Apr 19 09:08:23 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA48FC43334 for ; Mon, 4 Jul 2022 12:18:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234352AbiGDMSJ (ORCPT ); Mon, 4 Jul 2022 08:18:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53922 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231339AbiGDMRR (ORCPT ); Mon, 4 Jul 2022 08:17:17 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9D8261263F; Mon, 4 Jul 2022 05:17:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1656937021; x=1688473021; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cyGVS60gG5sog/TGKIss/AIPg2gKY2XrIx5CQ4aywGs=; b=gwezSYrjWskZteo+bCuFYllggWB7YGHOcp74CjCLUlukQUyPeH3j31EB xcDGMdMFRvLBpQUM98qFdH+JOmMRo3q5CnA+1TPfOOV+LMnt2dq1rzzg5 1T0txSp3m1ybh5FfA2te96wsLHFKskxCp1G5C5An6pX2JfSzA/hDgaelt 6EOHkIp7xa6WaldTaoqp+H7O8eGRIH0fY+V2dWrhesD4CDfRM5dUjh+KR xs/6N1lqR6xZDOEOIjG+dJimHtaSTzBgxSOkK3O3m1Iy7RJ2VdR5fdiUv WUgXdtKlzFVJeULSLaFvb2uRdZhna2sfxkGf4a+6gToo8TS4EkC3x00Lq g==; X-IronPort-AV: E=Sophos;i="5.92,243,1650956400"; d="scan'208";a="102909278" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 04 Jul 2022 05:16:59 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 4 Jul 2022 05:16:53 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 4 Jul 2022 05:16:51 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Philipp Zabel , Daire McNamara CC: Paul Walmsley , Albert Ou , , , , Subject: [PATCH v2 11/12] clk: microchip: mpfs: convert cfg_clk to clk_divider Date: Mon, 4 Jul 2022 13:15:58 +0100 Message-ID: <20220704121558.2088698-12-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220704121558.2088698-1-conor.dooley@microchip.com> References: <20220704121558.2088698-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The cfg_clk struct is now just a redefinition of the clk_divider struct with custom implentations of the ops, that implement an extra level of redirection. Remove the custom struct and replace it with clk_divider. Signed-off-by: Conor Dooley Reviewed-by: Daire McNamara --- drivers/clk/microchip/clk-mpfs.c | 76 ++++---------------------------- 1 file changed, 8 insertions(+), 68 deletions(-) diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-m= pfs.c index e58d0bc4669a..1d9e8c1e56b6 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -51,24 +51,13 @@ struct mpfs_msspll_hw_clock { =20 #define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_cl= ock, hw) =20 -struct mpfs_cfg_clock { - void __iomem *reg; - const struct clk_div_table *table; - u8 shift; - u8 width; - u8 flags; -}; - struct mpfs_cfg_hw_clock { - struct mpfs_cfg_clock cfg; - struct clk_hw hw; + struct clk_divider cfg; struct clk_init_data init; unsigned int id; u32 reg_offset; }; =20 -#define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, h= w) - struct mpfs_periph_clock { void __iomem *reg; u8 shift; @@ -228,56 +217,6 @@ static int mpfs_clk_register_mssplls(struct device *de= v, struct mpfs_msspll_hw_c * "CFG" clocks */ =20 -static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned = long prate) -{ - struct mpfs_cfg_hw_clock *cfg_hw =3D to_mpfs_cfg_clk(hw); - struct mpfs_cfg_clock *cfg =3D &cfg_hw->cfg; - u32 val; - - val =3D readl_relaxed(cfg->reg) >> cfg->shift; - val &=3D clk_div_mask(cfg->width); - - return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->w= idth); -} - -static long mpfs_cfg_clk_round_rate(struct clk_hw *hw, unsigned long rate,= unsigned long *prate) -{ - struct mpfs_cfg_hw_clock *cfg_hw =3D to_mpfs_cfg_clk(hw); - struct mpfs_cfg_clock *cfg =3D &cfg_hw->cfg; - - return divider_round_rate(hw, rate, prate, cfg->table, cfg->width, 0); -} - -static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, un= signed long prate) -{ - struct mpfs_cfg_hw_clock *cfg_hw =3D to_mpfs_cfg_clk(hw); - struct mpfs_cfg_clock *cfg =3D &cfg_hw->cfg; - unsigned long flags; - u32 val; - int divider_setting; - - divider_setting =3D divider_get_val(rate, prate, cfg->table, cfg->width, = 0); - - if (divider_setting < 0) - return divider_setting; - - spin_lock_irqsave(&mpfs_clk_lock, flags); - val =3D readl_relaxed(cfg->reg); - val &=3D ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift); - val |=3D divider_setting << cfg->shift; - writel_relaxed(val, cfg->reg); - - spin_unlock_irqrestore(&mpfs_clk_lock, flags); - - return 0; -} - -static const struct clk_ops mpfs_clk_cfg_ops =3D { - .recalc_rate =3D mpfs_cfg_clk_recalc_rate, - .round_rate =3D mpfs_cfg_clk_round_rate, - .set_rate =3D mpfs_cfg_clk_set_rate, -}; - #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offs= et) { \ .id =3D _id, \ .cfg.shift =3D _shift, \ @@ -285,7 +224,8 @@ static const struct clk_ops mpfs_clk_cfg_ops =3D { .cfg.table =3D _table, \ .reg_offset =3D _offset, \ .cfg.flags =3D _flags, \ - .hw.init =3D CLK_HW_INIT(_name, _parent, &mpfs_clk_cfg_ops, 0), \ + .cfg.hw.init =3D CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0), \ + .cfg.lock =3D &mpfs_clk_lock, \ } =20 static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] =3D { @@ -302,8 +242,8 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] =3D { .cfg.table =3D mpfs_div_rtcref_table, .reg_offset =3D REG_RTC_CLOCK_CR, .cfg.flags =3D CLK_DIVIDER_ONE_BASED, - .hw.init =3D - CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &mpfs_clk_cfg_ops,= 0), + .cfg.hw.init =3D + CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &clk_divider_ops, = 0), } }; =20 @@ -317,13 +257,13 @@ static int mpfs_clk_register_cfgs(struct device *dev,= struct mpfs_cfg_hw_clock * struct mpfs_cfg_hw_clock *cfg_hw =3D &cfg_hws[i]; =20 cfg_hw->cfg.reg =3D data->base + cfg_hw->reg_offset; - ret =3D devm_clk_hw_register(dev, &cfg_hw->hw); + ret =3D devm_clk_hw_register(dev, &cfg_hw->cfg.hw); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", cfg_hw->id); =20 id =3D cfg_hw->id; - data->hw_data.hws[id] =3D &cfg_hw->hw; + data->hw_data.hws[id] =3D &cfg_hw->cfg.hw; } =20 return 0; @@ -393,7 +333,7 @@ static const struct clk_ops mpfs_periph_clk_ops =3D { _flags), \ } =20 -#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT].hw) +#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT].cfg.hw) =20 /* * Critical clocks: --=20 2.36.1 From nobody Sun Apr 19 09:08:23 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86716C433EF for ; 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X-IronPort-AV: E=Sophos;i="5.92,243,1650956400"; d="scan'208";a="170686875" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 04 Jul 2022 05:16:58 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 4 Jul 2022 05:16:56 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 4 Jul 2022 05:16:54 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Philipp Zabel , Daire McNamara CC: Paul Walmsley , Albert Ou , , , , Subject: [PATCH v2 12/12] clk: microchip: mpfs: convert periph_clk to clk_gate Date: Mon, 4 Jul 2022 13:15:59 +0100 Message-ID: <20220704121558.2088698-13-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220704121558.2088698-1-conor.dooley@microchip.com> References: <20220704121558.2088698-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" With the reset code moved to the recently added reset controller, there is no need for custom ops any longer. Remove the custom ops and the custom struct by converting to a clk_gate. Signed-off-by: Conor Dooley Reviewed-by: Daire McNamara --- drivers/clk/microchip/clk-mpfs.c | 74 +++----------------------------- 1 file changed, 7 insertions(+), 67 deletions(-) diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-m= pfs.c index 1d9e8c1e56b6..2d5585c6ef21 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -58,19 +58,11 @@ struct mpfs_cfg_hw_clock { u32 reg_offset; }; =20 -struct mpfs_periph_clock { - void __iomem *reg; - u8 shift; -}; - struct mpfs_periph_hw_clock { - struct mpfs_periph_clock periph; - struct clk_hw hw; + struct clk_gate periph; unsigned int id; }; =20 -#define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_cl= ock, hw) - /* * mpfs_clk_lock prevents anything else from writing to the * mpfs clk block while a software locked register is being written. @@ -273,64 +265,12 @@ static int mpfs_clk_register_cfgs(struct device *dev,= struct mpfs_cfg_hw_clock * * peripheral clocks - devices connected to axi or ahb buses. */ =20 -static int mpfs_periph_clk_enable(struct clk_hw *hw) -{ - struct mpfs_periph_hw_clock *periph_hw =3D to_mpfs_periph_clk(hw); - struct mpfs_periph_clock *periph =3D &periph_hw->periph; - u32 reg, val; - unsigned long flags; - - spin_lock_irqsave(&mpfs_clk_lock, flags); - - reg =3D readl_relaxed(periph->reg); - val =3D reg | (1u << periph->shift); - writel_relaxed(val, periph->reg); - - spin_unlock_irqrestore(&mpfs_clk_lock, flags); - - return 0; -} - -static void mpfs_periph_clk_disable(struct clk_hw *hw) -{ - struct mpfs_periph_hw_clock *periph_hw =3D to_mpfs_periph_clk(hw); - struct mpfs_periph_clock *periph =3D &periph_hw->periph; - u32 reg, val; - unsigned long flags; - - spin_lock_irqsave(&mpfs_clk_lock, flags); - - reg =3D readl_relaxed(periph->reg); - val =3D reg & ~(1u << periph->shift); - writel_relaxed(val, periph->reg); - - spin_unlock_irqrestore(&mpfs_clk_lock, flags); -} - -static int mpfs_periph_clk_is_enabled(struct clk_hw *hw) -{ - struct mpfs_periph_hw_clock *periph_hw =3D to_mpfs_periph_clk(hw); - struct mpfs_periph_clock *periph =3D &periph_hw->periph; - u32 reg; - - reg =3D readl_relaxed(periph->reg); - if (reg & (1u << periph->shift)) - return 1; - - return 0; -} - -static const struct clk_ops mpfs_periph_clk_ops =3D { - .enable =3D mpfs_periph_clk_enable, - .disable =3D mpfs_periph_clk_disable, - .is_enabled =3D mpfs_periph_clk_is_enabled, -}; - #define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \ - .id =3D _id, \ - .periph.shift =3D _shift, \ - .hw.init =3D CLK_HW_INIT_HW(_name, _parent, &mpfs_periph_clk_ops, \ + .id =3D _id, \ + .periph.bit_idx =3D _shift, \ + .periph.hw.init =3D CLK_HW_INIT_HW(_name, _parent, &clk_gate_ops, \ _flags), \ + .periph.lock =3D &mpfs_clk_lock, \ } =20 #define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT].cfg.hw) @@ -389,13 +329,13 @@ static int mpfs_clk_register_periphs(struct device *d= ev, struct mpfs_periph_hw_c struct mpfs_periph_hw_clock *periph_hw =3D &periph_hws[i]; =20 periph_hw->periph.reg =3D data->base + REG_SUBBLK_CLOCK_CR; - ret =3D devm_clk_hw_register(dev, &periph_hw->hw); + ret =3D devm_clk_hw_register(dev, &periph_hw->periph.hw); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", periph_hw->id); =20 id =3D periph_hws[i].id; - data->hw_data.hws[id] =3D &periph_hw->hw; + data->hw_data.hws[id] =3D &periph_hw->periph.hw; } =20 return 0; --=20 2.36.1