From nobody Sat Sep 21 23:34:39 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BAA99C433EF for ; Mon, 4 Jul 2022 10:01:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234101AbiGDKBK (ORCPT ); Mon, 4 Jul 2022 06:01:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52036 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234029AbiGDKAm (ORCPT ); Mon, 4 Jul 2022 06:00:42 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BA5A9DE99; Mon, 4 Jul 2022 03:00:40 -0700 (PDT) X-UUID: 23f7023660df4b0c9587f1b802ebd709-20220704 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.7,REQID:55a2ac7a-6bec-4b15-aa0f-4384b2abef32,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:87442a2,CLOUDID:c7d68dd6-5d6d-4eaf-a635-828a3ee48b7c,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: 23f7023660df4b0c9587f1b802ebd709-20220704 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1630907575; Mon, 04 Jul 2022 18:00:30 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Mon, 4 Jul 2022 18:00:30 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Mon, 4 Jul 2022 18:00:30 +0800 From: Tinghan Shen To: Yong Wu , Joerg Roedel , Will Deacon , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Chun-Jie Chen , AngeloGioacchino Del Regno , Enric Balletbo i Serra , Tinghan Shen , Weiyi Lu CC: , , , , , , YT Lee Subject: [PATCH v1 06/16] arm64: dts: mt8195: Add cpufreq node Date: Mon, 4 Jul 2022 18:00:18 +0800 Message-ID: <20220704100028.19932-7-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220704100028.19932-1-tinghan.shen@mediatek.com> References: <20220704100028.19932-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: YT Lee Add cpufreq node for mt8195. Signed-off-by: YT Lee Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 8032b839dfe8..900aaa16f862 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -26,6 +26,7 @@ compatible =3D "arm,cortex-a55"; reg =3D <0x000>; enable-method =3D "psci"; + performance-domains =3D <&performance 0>; clock-frequency =3D <1701000000>; capacity-dmips-mhz =3D <578>; cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; @@ -38,6 +39,7 @@ compatible =3D "arm,cortex-a55"; reg =3D <0x100>; enable-method =3D "psci"; + performance-domains =3D <&performance 0>; clock-frequency =3D <1701000000>; capacity-dmips-mhz =3D <578>; cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; @@ -50,6 +52,7 @@ compatible =3D "arm,cortex-a55"; reg =3D <0x200>; enable-method =3D "psci"; + performance-domains =3D <&performance 0>; clock-frequency =3D <1701000000>; capacity-dmips-mhz =3D <578>; cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; @@ -62,6 +65,7 @@ compatible =3D "arm,cortex-a55"; reg =3D <0x300>; enable-method =3D "psci"; + performance-domains =3D <&performance 0>; clock-frequency =3D <1701000000>; capacity-dmips-mhz =3D <578>; cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; @@ -74,6 +78,7 @@ compatible =3D "arm,cortex-a78"; reg =3D <0x400>; enable-method =3D "psci"; + performance-domains =3D <&performance 1>; clock-frequency =3D <2171000000>; capacity-dmips-mhz =3D <1024>; cpu-idle-states =3D <&cpu_off_b &cluster_off_b>; @@ -86,6 +91,7 @@ compatible =3D "arm,cortex-a78"; reg =3D <0x500>; enable-method =3D "psci"; + performance-domains =3D <&performance 1>; clock-frequency =3D <2171000000>; capacity-dmips-mhz =3D <1024>; cpu-idle-states =3D <&cpu_off_b &cluster_off_b>; @@ -98,6 +104,7 @@ compatible =3D "arm,cortex-a78"; reg =3D <0x600>; enable-method =3D "psci"; + performance-domains =3D <&performance 1>; clock-frequency =3D <2171000000>; capacity-dmips-mhz =3D <1024>; cpu-idle-states =3D <&cpu_off_b &cluster_off_b>; @@ -110,6 +117,7 @@ compatible =3D "arm,cortex-a78"; reg =3D <0x700>; enable-method =3D "psci"; + performance-domains =3D <&performance 1>; clock-frequency =3D <2171000000>; capacity-dmips-mhz =3D <1024>; cpu-idle-states =3D <&cpu_off_b &cluster_off_b>; @@ -231,6 +239,12 @@ clock-output-names =3D "clk32k"; }; =20 + performance: performance-controller@11bc10 { + compatible =3D "mediatek,cpufreq-hw"; + reg =3D <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; + #performance-domain-cells =3D <1>; + }; + pmu-a55 { compatible =3D "arm,cortex-a55-pmu"; interrupt-parent =3D <&gic>; --=20 2.18.0