From nobody Sat Sep 21 23:32:04 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 179F5CCA479 for ; Mon, 4 Jul 2022 10:00:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234058AbiGDKAo (ORCPT ); Mon, 4 Jul 2022 06:00:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51934 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234016AbiGDKAj (ORCPT ); Mon, 4 Jul 2022 06:00:39 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DC05F959A; Mon, 4 Jul 2022 03:00:37 -0700 (PDT) X-UUID: 7dfffcc6278b42e5998d049148fc0bef-20220704 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.7,REQID:6b4bf71d-9afd-4878-8315-c9b07596cc5a,OB:0,LO B:20,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,AC TION:release,TS:95 X-CID-INFO: VERSION:1.1.7,REQID:6b4bf71d-9afd-4878-8315-c9b07596cc5a,OB:0,LOB: 20,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,AC TION:quarantine,TS:95 X-CID-META: VersionHash:87442a2,CLOUDID:a8915b63-0b3f-4b2c-b3a6-ed5c044366a0,C OID:40f5900786c6,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: 7dfffcc6278b42e5998d049148fc0bef-20220704 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1828719792; Mon, 04 Jul 2022 18:00:30 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Mon, 4 Jul 2022 18:00:29 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Mon, 4 Jul 2022 18:00:29 +0800 From: Tinghan Shen To: Yong Wu , Joerg Roedel , "Will Deacon" , Rob Herring , "Krzysztof Kozlowski" , Matthias Brugger , Chun-Jie Chen , AngeloGioacchino Del Regno , "Enric Balletbo i Serra" , Tinghan Shen , Weiyi Lu CC: , , , , , Subject: [PATCH v1 03/16] dt-bindings: power: mediatek: Refine multiple level power domain nodes Date: Mon, 4 Jul 2022 18:00:15 +0800 Message-ID: <20220704100028.19932-4-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220704100028.19932-1-tinghan.shen@mediatek.com> References: <20220704100028.19932-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extract duplicated properties and support more levels of power domain nodes. This change fix following error when do dtbs_check, arch/arm64/boot/dts/mediatek/mt8195-evb.dtb: power-controller: power-do= main@15:power-domain@16:power-domain@18: 'power-domain@19', 'power-domain@2= 0', 'power-domain@21' do not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/power/mediatek,power-contr= oller.yaml Signed-off-by: Tinghan Shen --- .../power/mediatek,power-controller.yaml | 132 ++---------------- 1 file changed, 12 insertions(+), 120 deletions(-) diff --git a/Documentation/devicetree/bindings/power/mediatek,power-control= ler.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controlle= r.yaml index 135c6f722091..09a537a802b8 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -39,8 +39,17 @@ properties: '#size-cells': const: 0 =20 +required: + - compatible + +additionalProperties: false + patternProperties: "^power-domain@[0-9a-f]+$": + $ref: "#/$defs/power-domain-node" + +$defs: + power-domain-node: type: object description: | Represents the power domains within the power controller node as doc= umented @@ -98,127 +107,10 @@ patternProperties: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the device containing the SMI register ran= ge. =20 - patternProperties: - "^power-domain@[0-9a-f]+$": - type: object - description: | - Represents a power domain child within a power domain parent nod= e. - - properties: - - '#power-domain-cells': - description: - Must be 0 for nodes representing a single PM domain and 1 fo= r nodes - providing multiple PM domains. - - '#address-cells': - const: 1 - - '#size-cells': - const: 0 - - reg: - maxItems: 1 - - clocks: - description: | - A number of phandles to clocks that need to be enabled durin= g domain - power-up sequencing. - - clock-names: - description: | - List of names of clocks, in order to match the power-up sequ= encing - for each power domain we need to group the clocks by name. B= ASIC - clocks need to be enabled before enabling the corresponding = power - domain, and should not have a '-' in their name (i.e mm, mfg= , venc). - SUSBYS clocks need to be enabled before releasing the bus pr= otection, - and should contain a '-' in their name (i.e mm-0, isp-0, cam= -0). - - In order to follow properly the power-up sequencing, the clo= cks must - be specified by order, adding first the BASIC clocks followe= d by the - SUSBSYS clocks. - - domain-supply: - description: domain regulator supply. - - mediatek,infracfg: - $ref: /schemas/types.yaml#/definitions/phandle - description: phandle to the device containing the INFRACFG reg= ister range. - - mediatek,smi: - $ref: /schemas/types.yaml#/definitions/phandle - description: phandle to the device containing the SMI register= range. - - patternProperties: - "^power-domain@[0-9a-f]+$": - type: object - description: | - Represents a power domain child within a power domain parent= node. - - properties: + required: + - reg =20 - '#power-domain-cells': - description: - Must be 0 for nodes representing a single PM domain and = 1 for nodes - providing multiple PM domains. - - '#address-cells': - const: 1 - - '#size-cells': - const: 0 - - reg: - maxItems: 1 - - clocks: - description: | - A number of phandles to clocks that need to be enabled d= uring domain - power-up sequencing. - - clock-names: - description: | - List of names of clocks, in order to match the power-up = sequencing - for each power domain we need to group the clocks by nam= e. BASIC - clocks need to be enabled before enabling the correspond= ing power - domain, and should not have a '-' in their name (i.e mm,= mfg, venc). - SUSBYS clocks need to be enabled before releasing the bu= s protection, - and should contain a '-' in their name (i.e mm-0, isp-0,= cam-0). - - In order to follow properly the power-up sequencing, the= clocks must - be specified by order, adding first the BASIC clocks fol= lowed by the - SUSBSYS clocks. - - domain-supply: - description: domain regulator supply. - - mediatek,infracfg: - $ref: /schemas/types.yaml#/definitions/phandle - description: phandle to the device containing the INFRACFG= register range. - - mediatek,smi: - $ref: /schemas/types.yaml#/definitions/phandle - description: phandle to the device containing the SMI regi= ster range. - - required: - - reg - - additionalProperties: false - - required: - - reg - - additionalProperties: false - - required: - - reg - - additionalProperties: false - -required: - - compatible - -additionalProperties: false + additionalProperties: false =20 examples: - | --=20 2.18.0