From nobody Sun Apr 19 10:40:13 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C78A8C433EF for ; Sat, 2 Jul 2022 02:00:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231320AbiGBCAn (ORCPT ); Fri, 1 Jul 2022 22:00:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229458AbiGBCAj (ORCPT ); Fri, 1 Jul 2022 22:00:39 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED6983F30C for ; Fri, 1 Jul 2022 19:00:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1656727238; x=1688263238; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HXVKMoFdhQcvlC95LGmOfs8ndIYoqrdegsd+kEhGg1A=; b=c/4enOKynP7tIESdnRLEMiMkPPiPs9DVMfTlxC7Q/t9n6q1h4KZVUi4b Nulddmj+Ev9WFdxOxrLZ3oCz69Xjm+6tJxizLoNB/7bBWWRAc3fr+kAGA yLTQ1LJm2dnchf0QVZXbyJm53lDxU8f4Wz6RQLikE207yQ5md/0fI5MX0 qqhVEo/4RRQ36GecQ6hfktOJd2HA+VVUO+Wpsoi4UcvNjHmn5wD8B3QMx kPy9G0iCbHlCTEg1lmoTHt6lSc04SeRaCZrqDZNOihSABFBlC46eN5QsU X7oPXbq4N87lV/KFb97GrM6yFNsSWF7RokxVAiaDma78zSbPn00aeBD1j A==; X-IronPort-AV: E=McAfee;i="6400,9594,10395"; a="262573729" X-IronPort-AV: E=Sophos;i="5.92,238,1650956400"; d="scan'208";a="262573729" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jul 2022 19:00:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,238,1650956400"; d="scan'208";a="589518283" Received: from allen-box.sh.intel.com ([10.239.159.48]) by orsmga007.jf.intel.com with ESMTP; 01 Jul 2022 19:00:35 -0700 From: Lu Baolu To: Joerg Roedel , Steve Wahl , Kevin Tian Cc: David Woodhouse , Jerry Snitselaar , Mike Travis , Dimitri Sivanich , Russ Anderson , iommu@lists.linux.dev, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v2 1/6] iommu/vt-d: Remove unused domain_get_iommu() Date: Sat, 2 Jul 2022 09:56:05 +0800 Message-Id: <20220702015610.2849494-2-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220702015610.2849494-1-baolu.lu@linux.intel.com> References: <20220702015610.2849494-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" It is not used anywhere. Remove it to avoid dead code. Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian --- drivers/iommu/intel/iommu.h | 1 - drivers/iommu/intel/iommu.c | 18 ------------------ 2 files changed, 19 deletions(-) diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index df64d3d9c49a..56e0d8cd2102 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -725,7 +725,6 @@ extern int dmar_ir_support(void); =20 void *alloc_pgtable_page(int node); void free_pgtable_page(void *vaddr); -struct intel_iommu *domain_get_iommu(struct dmar_domain *domain); void iommu_flush_write_buffer(struct intel_iommu *iommu); int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct device *dev= ); struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn= ); diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index da6cfea0f0d6..781e060352e6 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -445,24 +445,6 @@ int iommu_calculate_agaw(struct intel_iommu *iommu) return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH); } =20 -/* This functionin only returns single iommu in a domain */ -struct intel_iommu *domain_get_iommu(struct dmar_domain *domain) -{ - int iommu_id; - - /* si_domain and vm domain should not get here. */ - if (WARN_ON(!iommu_is_dma_domain(&domain->domain))) - return NULL; - - for_each_domain_iommu(iommu_id, domain) - break; - - if (iommu_id < 0 || iommu_id >=3D g_num_of_iommus) - return NULL; - - return g_iommus[iommu_id]; -} - static inline bool iommu_paging_structure_coherency(struct intel_iommu *io= mmu) { return sm_supported(iommu) ? --=20 2.25.1 From nobody Sun Apr 19 10:40:13 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7564FC43334 for ; Sat, 2 Jul 2022 02:00:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231514AbiGBCAp (ORCPT ); Fri, 1 Jul 2022 22:00:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35044 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231293AbiGBCAm (ORCPT ); Fri, 1 Jul 2022 22:00:42 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 395A5403DA for ; Fri, 1 Jul 2022 19:00:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1656727242; x=1688263242; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DFPmBvFWYw27ZARg+5iSaqlrtN1/1OkiNoJ7ea+BTfU=; b=fgic+F8qDXJDaGY93VGtEL3+R6WCo/YDY0zdLHylehKbWGYsmQ5xwwUE BvsMicTB6zwmevqOub1tIOb2los4hUzYNF40qi62HbZdYSYET3C4AiUip oN4wN1uBNoXa0vQZZVE6TPqwVqa1TtYRjd/QHA59CfAZeSiN/ZzJ5d6Bx U2C4YZOQzw33nJX22t5pcmbsER4gR+95z8y1BXcisNBx0X+CUfROMDcPA 8ScDW1wPaCZcURzngtuIeZlI+efdYxqUXWAj2hS8yR5vlS+07KvrcCst9 XJiL2fr7ec7YmI4Td0/SUEWfQv+ApQOwRbWnKcwi66bMxX/JowH8DypHC Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10395"; a="262573735" X-IronPort-AV: E=Sophos;i="5.92,238,1650956400"; d="scan'208";a="262573735" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jul 2022 19:00:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,238,1650956400"; d="scan'208";a="589518295" Received: from allen-box.sh.intel.com ([10.239.159.48]) by orsmga007.jf.intel.com with ESMTP; 01 Jul 2022 19:00:39 -0700 From: Lu Baolu To: Joerg Roedel , Steve Wahl , Kevin Tian Cc: David Woodhouse , Jerry Snitselaar , Mike Travis , Dimitri Sivanich , Russ Anderson , iommu@lists.linux.dev, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v2 2/6] iommu/vt-d: Use IDA interface to manage iommu sequence id Date: Sat, 2 Jul 2022 09:56:06 +0800 Message-Id: <20220702015610.2849494-3-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220702015610.2849494-1-baolu.lu@linux.intel.com> References: <20220702015610.2849494-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Switch dmar unit sequence id allocation and release from bitmap to IDA interface. Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian --- drivers/iommu/intel/dmar.c | 35 ++++++++--------------------------- 1 file changed, 8 insertions(+), 27 deletions(-) diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c index 2a5e0f91e647..6327b34f5aa7 100644 --- a/drivers/iommu/intel/dmar.c +++ b/drivers/iommu/intel/dmar.c @@ -60,7 +60,7 @@ LIST_HEAD(dmar_drhd_units); =20 struct acpi_table_header * __initdata dmar_tbl; static int dmar_dev_scope_status =3D 1; -static unsigned long dmar_seq_ids[BITS_TO_LONGS(DMAR_UNITS_SUPPORTED)]; +static DEFINE_IDA(dmar_seq_ids); =20 static int alloc_iommu(struct dmar_drhd_unit *drhd); static void free_iommu(struct intel_iommu *iommu); @@ -1023,28 +1023,6 @@ static int map_iommu(struct intel_iommu *iommu, u64 = phys_addr) return err; } =20 -static int dmar_alloc_seq_id(struct intel_iommu *iommu) -{ - iommu->seq_id =3D find_first_zero_bit(dmar_seq_ids, - DMAR_UNITS_SUPPORTED); - if (iommu->seq_id >=3D DMAR_UNITS_SUPPORTED) { - iommu->seq_id =3D -1; - } else { - set_bit(iommu->seq_id, dmar_seq_ids); - sprintf(iommu->name, "dmar%d", iommu->seq_id); - } - - return iommu->seq_id; -} - -static void dmar_free_seq_id(struct intel_iommu *iommu) -{ - if (iommu->seq_id >=3D 0) { - clear_bit(iommu->seq_id, dmar_seq_ids); - iommu->seq_id =3D -1; - } -} - static int alloc_iommu(struct dmar_drhd_unit *drhd) { struct intel_iommu *iommu; @@ -1062,11 +1040,14 @@ static int alloc_iommu(struct dmar_drhd_unit *drhd) if (!iommu) return -ENOMEM; =20 - if (dmar_alloc_seq_id(iommu) < 0) { + iommu->seq_id =3D ida_alloc_range(&dmar_seq_ids, 0, + DMAR_UNITS_SUPPORTED - 1, GFP_KERNEL); + if (iommu->seq_id < 0) { pr_err("Failed to allocate seq_id\n"); - err =3D -ENOSPC; + err =3D iommu->seq_id; goto error; } + sprintf(iommu->name, "dmar%d", iommu->seq_id); =20 err =3D map_iommu(iommu, drhd->reg_base_addr); if (err) { @@ -1150,7 +1131,7 @@ static int alloc_iommu(struct dmar_drhd_unit *drhd) err_unmap: unmap_iommu(iommu); error_free_seq_id: - dmar_free_seq_id(iommu); + ida_free(&dmar_seq_ids, iommu->seq_id); error: kfree(iommu); return err; @@ -1183,7 +1164,7 @@ static void free_iommu(struct intel_iommu *iommu) if (iommu->reg) unmap_iommu(iommu); =20 - dmar_free_seq_id(iommu); + ida_free(&dmar_seq_ids, iommu->seq_id); kfree(iommu); } =20 --=20 2.25.1 From nobody Sun Apr 19 10:40:13 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8BEADC43334 for ; Sat, 2 Jul 2022 02:00:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231545AbiGBCAw (ORCPT ); Fri, 1 Jul 2022 22:00:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35146 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231547AbiGBCAr (ORCPT ); Fri, 1 Jul 2022 22:00:47 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 86B2873596 for ; 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d="scan'208";a="589518312" Received: from allen-box.sh.intel.com ([10.239.159.48]) by orsmga007.jf.intel.com with ESMTP; 01 Jul 2022 19:00:42 -0700 From: Lu Baolu To: Joerg Roedel , Steve Wahl , Kevin Tian Cc: David Woodhouse , Jerry Snitselaar , Mike Travis , Dimitri Sivanich , Russ Anderson , iommu@lists.linux.dev, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v2 3/6] iommu/vt-d: Refactor iommu information of each domain Date: Sat, 2 Jul 2022 09:56:07 +0800 Message-Id: <20220702015610.2849494-4-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220702015610.2849494-1-baolu.lu@linux.intel.com> References: <20220702015610.2849494-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" When a DMA domain is attached to a device, it needs to allocate a domain ID from its IOMMU. Currently, the domain ID information is stored in two static arrays embedded in the domain structure. This can lead to memory waste when the driver is running on a small platform. This optimizes these static arrays by replacing them with an xarray and consuming memory on demand. Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian --- drivers/iommu/intel/iommu.h | 29 ++++++--- drivers/iommu/intel/iommu.c | 124 +++++++++++++++++++++--------------- drivers/iommu/intel/pasid.c | 2 +- drivers/iommu/intel/svm.c | 2 +- 4 files changed, 94 insertions(+), 63 deletions(-) diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index 56e0d8cd2102..fae45bbb0c7f 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -21,6 +21,7 @@ #include #include #include +#include =20 #include #include @@ -524,17 +525,17 @@ struct context_entry { */ #define DOMAIN_FLAG_USE_FIRST_LEVEL BIT(1) =20 -struct dmar_domain { - int nid; /* node id */ - - unsigned int iommu_refcnt[DMAR_UNITS_SUPPORTED]; - /* Refcount of devices per iommu */ - - - u16 iommu_did[DMAR_UNITS_SUPPORTED]; - /* Domain ids per IOMMU. Use u16 since +struct iommu_domain_info { + struct intel_iommu *iommu; + unsigned int refcnt; /* Refcount of devices per iommu */ + u16 did; /* Domain ids per IOMMU. Use u16 since * domain ids are 16 bit wide according * to VT-d spec, section 9.3 */ +}; + +struct dmar_domain { + int nid; /* node id */ + struct xarray iommu_array; /* Attached IOMMU array */ =20 u8 has_iotlb_device: 1; u8 iommu_coherency: 1; /* indicate coherency of iommu access */ @@ -640,6 +641,16 @@ static inline struct dmar_domain *to_dmar_domain(struc= t iommu_domain *dom) return container_of(dom, struct dmar_domain, domain); } =20 +/* Retrieve the domain ID which has allocated to the domain */ +static inline u16 +domain_id_iommu(struct dmar_domain *domain, struct intel_iommu *iommu) +{ + struct iommu_domain_info *info =3D + xa_load(&domain->iommu_array, iommu->seq_id); + + return info->did; +} + /* * 0: readable * 1: writable diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 781e060352e6..70408c234f5b 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -254,10 +254,6 @@ static inline void context_clear_entry(struct context_= entry *context) static struct dmar_domain *si_domain; static int hw_pass_through =3D 1; =20 -#define for_each_domain_iommu(idx, domain) \ - for (idx =3D 0; idx < g_num_of_iommus; idx++) \ - if (domain->iommu_refcnt[idx]) - struct dmar_rmrr_unit { struct list_head list; /* list of rmrr units */ struct acpi_dmar_header *hdr; /* ACPI header */ @@ -453,16 +449,16 @@ static inline bool iommu_paging_structure_coherency(s= truct intel_iommu *iommu) =20 static void domain_update_iommu_coherency(struct dmar_domain *domain) { + struct iommu_domain_info *info; struct dmar_drhd_unit *drhd; struct intel_iommu *iommu; bool found =3D false; - int i; + unsigned long i; =20 domain->iommu_coherency =3D true; - - for_each_domain_iommu(i, domain) { + xa_for_each(&domain->iommu_array, i, info) { found =3D true; - if (!iommu_paging_structure_coherency(g_iommus[i])) { + if (!iommu_paging_structure_coherency(info->iommu)) { domain->iommu_coherency =3D false; break; } @@ -1495,7 +1491,7 @@ static void iommu_flush_iotlb_psi(struct intel_iommu = *iommu, unsigned int aligned_pages =3D __roundup_pow_of_two(pages); unsigned int mask =3D ilog2(aligned_pages); uint64_t addr =3D (uint64_t)pfn << VTD_PAGE_SHIFT; - u16 did =3D domain->iommu_did[iommu->seq_id]; + u16 did =3D domain_id_iommu(domain, iommu); =20 BUG_ON(pages =3D=3D 0); =20 @@ -1565,11 +1561,12 @@ static inline void __mapping_notify_one(struct inte= l_iommu *iommu, static void intel_flush_iotlb_all(struct iommu_domain *domain) { struct dmar_domain *dmar_domain =3D to_dmar_domain(domain); - int idx; + struct iommu_domain_info *info; + unsigned long idx; =20 - for_each_domain_iommu(idx, dmar_domain) { - struct intel_iommu *iommu =3D g_iommus[idx]; - u16 did =3D dmar_domain->iommu_did[iommu->seq_id]; + xa_for_each(&dmar_domain->iommu_array, idx, info) { + struct intel_iommu *iommu =3D info->iommu; + u16 did =3D domain_id_iommu(dmar_domain, iommu); =20 if (domain_use_first_level(dmar_domain)) qi_flush_piotlb(iommu, did, PASID_RID2PASID, 0, -1, 0); @@ -1745,6 +1742,7 @@ static struct dmar_domain *alloc_domain(unsigned int = type) domain->has_iotlb_device =3D false; INIT_LIST_HEAD(&domain->devices); spin_lock_init(&domain->lock); + xa_init(&domain->iommu_array); =20 return domain; } @@ -1752,45 +1750,67 @@ static struct dmar_domain *alloc_domain(unsigned in= t type) static int domain_attach_iommu(struct dmar_domain *domain, struct intel_iommu *iommu) { + struct iommu_domain_info *info, *curr; unsigned long ndomains; - int num, ret =3D 0; + int num, ret =3D -ENOSPC; + + info =3D kzalloc(sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; =20 spin_lock(&iommu->lock); - domain->iommu_refcnt[iommu->seq_id] +=3D 1; - if (domain->iommu_refcnt[iommu->seq_id] =3D=3D 1) { - ndomains =3D cap_ndoms(iommu->cap); - num =3D find_first_zero_bit(iommu->domain_ids, ndomains); - - if (num >=3D ndomains) { - pr_err("%s: No free domain ids\n", iommu->name); - domain->iommu_refcnt[iommu->seq_id] -=3D 1; - ret =3D -ENOSPC; - goto out_unlock; - } + curr =3D xa_load(&domain->iommu_array, iommu->seq_id); + if (curr) { + curr->refcnt++; + spin_unlock(&iommu->lock); + kfree(info); + return 0; + } =20 - set_bit(num, iommu->domain_ids); - domain->iommu_did[iommu->seq_id] =3D num; - domain->nid =3D iommu->node; - domain_update_iommu_cap(domain); + ndomains =3D cap_ndoms(iommu->cap); + num =3D find_first_zero_bit(iommu->domain_ids, ndomains); + if (num >=3D ndomains) { + pr_err("%s: No free domain ids\n", iommu->name); + goto err_unlock; } =20 -out_unlock: + set_bit(num, iommu->domain_ids); + info->refcnt =3D 1; + info->did =3D num; + info->iommu =3D iommu; + domain->nid =3D iommu->node; + curr =3D xa_cmpxchg(&domain->iommu_array, iommu->seq_id, + NULL, info, GFP_ATOMIC); + if (curr) { + ret =3D xa_err(curr) ? : -EBUSY; + goto err_clear; + } + domain_update_iommu_cap(domain); + spin_unlock(&iommu->lock); + return 0; + +err_clear: + clear_bit(info->did, iommu->domain_ids); +err_unlock: + spin_unlock(&iommu->lock); + kfree(info); return ret; } =20 static void domain_detach_iommu(struct dmar_domain *domain, struct intel_iommu *iommu) { - int num; + struct iommu_domain_info *info; =20 spin_lock(&iommu->lock); - domain->iommu_refcnt[iommu->seq_id] -=3D 1; - if (domain->iommu_refcnt[iommu->seq_id] =3D=3D 0) { - num =3D domain->iommu_did[iommu->seq_id]; - clear_bit(num, iommu->domain_ids); + info =3D xa_load(&domain->iommu_array, iommu->seq_id); + if (--info->refcnt =3D=3D 0) { + clear_bit(info->did, iommu->domain_ids); + xa_erase(&domain->iommu_array, iommu->seq_id); + domain->nid =3D NUMA_NO_NODE; domain_update_iommu_cap(domain); - domain->iommu_did[iommu->seq_id] =3D 0; + kfree(info); } spin_unlock(&iommu->lock); } @@ -1880,7 +1900,7 @@ static int domain_context_mapping_one(struct dmar_dom= ain *domain, { struct device_domain_info *info =3D iommu_support_dev_iotlb(domain, iommu, bus, devfn); - u16 did =3D domain->iommu_did[iommu->seq_id]; + u16 did =3D domain_id_iommu(domain, iommu); int translation =3D CONTEXT_TT_MULTI_LEVEL; struct context_entry *context; int ret; @@ -2130,8 +2150,9 @@ static void switch_to_super_page(struct dmar_domain *= domain, unsigned long end_pfn, int level) { unsigned long lvl_pages =3D lvl_to_nr_pages(level); + struct iommu_domain_info *info; struct dma_pte *pte =3D NULL; - int i; + unsigned long i; =20 while (start_pfn <=3D end_pfn) { if (!pte) @@ -2142,8 +2163,8 @@ static void switch_to_super_page(struct dmar_domain *= domain, start_pfn + lvl_pages - 1, level + 1); =20 - for_each_domain_iommu(i, domain) - iommu_flush_iotlb_psi(g_iommus[i], domain, + xa_for_each(&domain->iommu_array, i, info) + iommu_flush_iotlb_psi(info->iommu, domain, start_pfn, lvl_pages, 0, 0); } @@ -2273,7 +2294,7 @@ static void domain_context_clear_one(struct device_do= main_info *info, u8 bus, u8 if (hw_pass_through && domain_type_is_si(info->domain)) did_old =3D FLPT_DEFAULT_DID; else - did_old =3D info->domain->iommu_did[iommu->seq_id]; + did_old =3D domain_id_iommu(info->domain, iommu); } else { did_old =3D context_domain_id(context); } @@ -2331,7 +2352,7 @@ static int domain_setup_first_level(struct intel_iomm= u *iommu, flags |=3D PASID_FLAG_PAGE_SNOOP; =20 return intel_pasid_setup_first_level(iommu, dev, (pgd_t *)pgd, pasid, - domain->iommu_did[iommu->seq_id], + domain_id_iommu(domain, iommu), flags); } =20 @@ -4369,15 +4390,16 @@ static void intel_iommu_tlb_sync(struct iommu_domai= n *domain, struct dmar_domain *dmar_domain =3D to_dmar_domain(domain); unsigned long iova_pfn =3D IOVA_PFN(gather->start); size_t size =3D gather->end - gather->start; + struct iommu_domain_info *info; unsigned long start_pfn; unsigned long nrpages; - int iommu_id; + unsigned long i; =20 nrpages =3D aligned_nrpages(gather->start, size); start_pfn =3D mm_to_dma_pfn(iova_pfn); =20 - for_each_domain_iommu(iommu_id, dmar_domain) - iommu_flush_iotlb_psi(g_iommus[iommu_id], dmar_domain, + xa_for_each(&dmar_domain->iommu_array, i, info) + iommu_flush_iotlb_psi(info->iommu, dmar_domain, start_pfn, nrpages, list_empty(&gather->freelist), 0); =20 @@ -4622,7 +4644,7 @@ int intel_iommu_enable_pasid(struct intel_iommu *iomm= u, struct device *dev) context[0].lo =3D ctx_lo; wmb(); iommu->flush.flush_context(iommu, - domain->iommu_did[iommu->seq_id], + domain_id_iommu(domain, iommu), PCI_DEVID(info->bus, info->devfn), DMA_CCMD_MASK_NOBIT, DMA_CCMD_DEVICE_INVL); @@ -4759,13 +4781,11 @@ static void intel_iommu_iotlb_sync_map(struct iommu= _domain *domain, struct dmar_domain *dmar_domain =3D to_dmar_domain(domain); unsigned long pages =3D aligned_nrpages(iova, size); unsigned long pfn =3D iova >> VTD_PAGE_SHIFT; - struct intel_iommu *iommu; - int iommu_id; + struct iommu_domain_info *info; + unsigned long i; =20 - for_each_domain_iommu(iommu_id, dmar_domain) { - iommu =3D g_iommus[iommu_id]; - __mapping_notify_one(iommu, dmar_domain, pfn, pages); - } + xa_for_each(&dmar_domain->iommu_array, i, info) + __mapping_notify_one(info->iommu, dmar_domain, pfn, pages); } =20 const struct iommu_ops intel_iommu_ops =3D { diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c index c30de2339de5..006026dc18d4 100644 --- a/drivers/iommu/intel/pasid.c +++ b/drivers/iommu/intel/pasid.c @@ -626,7 +626,7 @@ int intel_pasid_setup_second_level(struct intel_iommu *= iommu, } =20 pgd_val =3D virt_to_phys(pgd); - did =3D domain->iommu_did[iommu->seq_id]; + did =3D domain_id_iommu(domain, iommu); =20 spin_lock(&iommu->lock); pte =3D intel_pasid_get_entry(dev, pasid); diff --git a/drivers/iommu/intel/svm.c b/drivers/iommu/intel/svm.c index 64072e628bbd..8bcfb93dda56 100644 --- a/drivers/iommu/intel/svm.c +++ b/drivers/iommu/intel/svm.c @@ -541,7 +541,7 @@ static void intel_svm_drain_prq(struct device *dev, u32= pasid) domain =3D info->domain; pdev =3D to_pci_dev(dev); sid =3D PCI_DEVID(info->bus, info->devfn); - did =3D domain->iommu_did[iommu->seq_id]; + did =3D domain_id_iommu(domain, iommu); qdep =3D pci_ats_queue_depth(pdev); =20 /* --=20 2.25.1 From nobody Sun Apr 19 10:40:13 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75B2DC433EF for ; Sat, 2 Jul 2022 02:00:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231686AbiGBCAz (ORCPT ); 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X-IronPort-AV: E=McAfee;i="6400,9594,10395"; a="262573748" X-IronPort-AV: E=Sophos;i="5.92,238,1650956400"; d="scan'208";a="262573748" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jul 2022 19:00:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,238,1650956400"; d="scan'208";a="589518325" Received: from allen-box.sh.intel.com ([10.239.159.48]) by orsmga007.jf.intel.com with ESMTP; 01 Jul 2022 19:00:45 -0700 From: Lu Baolu To: Joerg Roedel , Steve Wahl , Kevin Tian Cc: David Woodhouse , Jerry Snitselaar , Mike Travis , Dimitri Sivanich , Russ Anderson , iommu@lists.linux.dev, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v2 4/6] iommu/vt-d: Remove unnecessary check in intel_iommu_add() Date: Sat, 2 Jul 2022 09:56:08 +0800 Message-Id: <20220702015610.2849494-5-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220702015610.2849494-1-baolu.lu@linux.intel.com> References: <20220702015610.2849494-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Intel IOMMU hot-add process starts from dmar_device_hotplug(). It uses the global dmar_global_lock to synchronize all the hot-add and hot-remove paths. In the hot-add path, the new IOMMU data structures are allocated firstly by dmar_parse_one_drhd() and then initialized by dmar_hp_add_drhd(). All the IOMMU units are allocated and initialized in the same synchronized path. There is no case where any IOMMU unit is created and then initialized for multiple times. This removes the unnecessary check in intel_iommu_add() which is the last reference place of the global IOMMU array. Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian --- drivers/iommu/intel/iommu.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 70408c234f5b..d79c48c5fc8c 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -3463,9 +3463,6 @@ static int intel_iommu_add(struct dmar_drhd_unit *dma= ru) int sp, ret; struct intel_iommu *iommu =3D dmaru->iommu; =20 - if (g_iommus[iommu->seq_id]) - return 0; - ret =3D intel_cap_audit(CAP_AUDIT_HOTPLUG_DMAR, iommu); if (ret) goto out; --=20 2.25.1 From nobody Sun Apr 19 10:40:13 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D81CC433EF for ; Sat, 2 Jul 2022 02:00:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231794AbiGBCA4 (ORCPT ); Fri, 1 Jul 2022 22:00:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35286 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231547AbiGBCAw (ORCPT ); Fri, 1 Jul 2022 22:00:52 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D106057248 for ; Fri, 1 Jul 2022 19:00:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1656727251; x=1688263251; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CTgci0gtk4B8onuxHazyj9YA3lG/u654uE8PqymAGq8=; b=i7+0tn/0yndprTvOnpbsxJurSRsMETDZ2RElHGacwfxB2F7Xi/2ThB1y BV60Ho6gGwnbtq28NYS+FyAdDUYi82XK/gAEji0L42QPQA6qndMAscaQz oatKNq6057Vdtl9kA9IkirofDAFI4UosDR2qH3Qu/Ko24E101vcehgNmS 3qn/6u/pHSvL14D3HsnEOF+ey3iOC3flxv4hA7TejSr2sW6rZ57tmCsHy O+Q8HLk2sxQHDXAagrn9kb1YtdJGrI45ZgAB+qK5KUKXcT65nFxB1SkPB ReD4FbV6OIIfmVozYGv7KnmB/iMs5bYgaJM7rDwMEgIwsBOG2R0t9pNH/ w==; X-IronPort-AV: E=McAfee;i="6400,9594,10395"; a="262573756" X-IronPort-AV: E=Sophos;i="5.92,238,1650956400"; d="scan'208";a="262573756" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jul 2022 19:00:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,238,1650956400"; d="scan'208";a="589518336" Received: from allen-box.sh.intel.com ([10.239.159.48]) by orsmga007.jf.intel.com with ESMTP; 01 Jul 2022 19:00:48 -0700 From: Lu Baolu To: Joerg Roedel , Steve Wahl , Kevin Tian Cc: David Woodhouse , Jerry Snitselaar , Mike Travis , Dimitri Sivanich , Russ Anderson , iommu@lists.linux.dev, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v2 5/6] iommu/vt-d: Remove global g_iommus array Date: Sat, 2 Jul 2022 09:56:09 +0800 Message-Id: <20220702015610.2849494-6-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220702015610.2849494-1-baolu.lu@linux.intel.com> References: <20220702015610.2849494-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The g_iommus and g_num_of_iommus is not used anywhere. Remove them to avoid dead code. Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian --- drivers/iommu/intel/iommu.c | 44 ------------------------------------- 1 file changed, 44 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index d79c48c5fc8c..73a48e2d4fbe 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -126,9 +126,6 @@ static inline unsigned long virt_to_dma_pfn(void *p) return page_to_dma_pfn(virt_to_page(p)); } =20 -/* global iommu list, set NULL for ignored DMAR units */ -static struct intel_iommu **g_iommus; - static void __init check_tylersburg_isoch(void); static int rwbf_quirk; =20 @@ -287,9 +284,6 @@ static LIST_HEAD(dmar_satc_units); #define for_each_rmrr_units(rmrr) \ list_for_each_entry(rmrr, &dmar_rmrr_units, list) =20 -/* bitmap for indexing intel_iommus */ -static int g_num_of_iommus; - static void dmar_remove_one_dev_info(struct device *dev); =20 int dmar_disabled =3D !IS_ENABLED(CONFIG_INTEL_IOMMU_DEFAULT_ON); @@ -1694,8 +1688,6 @@ static void free_dmar_iommu(struct intel_iommu *iommu) iommu->domain_ids =3D NULL; } =20 - g_iommus[iommu->seq_id] =3D NULL; - /* free context mapping */ free_context_table(iommu); =20 @@ -2901,36 +2893,6 @@ static int __init init_dmars(void) struct intel_iommu *iommu; int ret; =20 - /* - * for each drhd - * allocate root - * initialize and program root entry to not present - * endfor - */ - for_each_drhd_unit(drhd) { - /* - * lock not needed as this is only incremented in the single - * threaded kernel __init code path all other access are read - * only - */ - if (g_num_of_iommus < DMAR_UNITS_SUPPORTED) { - g_num_of_iommus++; - continue; - } - pr_err_once("Exceeded %d IOMMUs\n", DMAR_UNITS_SUPPORTED); - } - - /* Preallocate enough resources for IOMMU hot-addition */ - if (g_num_of_iommus < DMAR_UNITS_SUPPORTED) - g_num_of_iommus =3D DMAR_UNITS_SUPPORTED; - - g_iommus =3D kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *), - GFP_KERNEL); - if (!g_iommus) { - ret =3D -ENOMEM; - goto error; - } - ret =3D intel_cap_audit(CAP_AUDIT_STATIC_DMAR, NULL); if (ret) goto free_iommu; @@ -2953,8 +2915,6 @@ static int __init init_dmars(void) intel_pasid_max_id); } =20 - g_iommus[iommu->seq_id] =3D iommu; - intel_iommu_init_qi(iommu); =20 ret =3D iommu_init_domains(iommu); @@ -3080,9 +3040,6 @@ static int __init init_dmars(void) free_dmar_iommu(iommu); } =20 - kfree(g_iommus); - -error: return ret; } =20 @@ -3486,7 +3443,6 @@ static int intel_iommu_add(struct dmar_drhd_unit *dma= ru) if (iommu->gcmd & DMA_GCMD_TE) iommu_disable_translation(iommu); =20 - g_iommus[iommu->seq_id] =3D iommu; ret =3D iommu_init_domains(iommu); if (ret =3D=3D 0) ret =3D iommu_alloc_root_entry(iommu); --=20 2.25.1 From nobody Sun Apr 19 10:40:13 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 771EAC43334 for ; Sat, 2 Jul 2022 02:01:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232048AbiGBCBD (ORCPT ); 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X-IronPort-AV: E=McAfee;i="6400,9594,10395"; a="262573761" X-IronPort-AV: E=Sophos;i="5.92,238,1650956400"; d="scan'208";a="262573761" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jul 2022 19:00:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,238,1650956400"; d="scan'208";a="589518343" Received: from allen-box.sh.intel.com ([10.239.159.48]) by orsmga007.jf.intel.com with ESMTP; 01 Jul 2022 19:00:51 -0700 From: Lu Baolu To: Joerg Roedel , Steve Wahl , Kevin Tian Cc: David Woodhouse , Jerry Snitselaar , Mike Travis , Dimitri Sivanich , Russ Anderson , iommu@lists.linux.dev, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v2 6/6] iommu/vt-d: Make DMAR_UNITS_SUPPORTED default 1024 Date: Sat, 2 Jul 2022 09:56:10 +0800 Message-Id: <20220702015610.2849494-7-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220702015610.2849494-1-baolu.lu@linux.intel.com> References: <20220702015610.2849494-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If the available hardware exceeds DMAR_UNITS_SUPPORTED (previously set to MAX_IO_APICS, or 128), it causes these messages: "DMAR: Failed to allocate seq_id", "DMAR: Parse DMAR table failure.", and "x2apic: IRQ remapping doesn't support X2APIC mode x2apic disabled"; and the system fails to boot properly. To support up to 64 sockets with 10 DMAR units each (640), make the value of DMAR_UNITS_SUPPORTED default 1024. Signed-off-by: Steve Wahl Link: https://lore.kernel.org/linux-iommu/20220615183650.32075-1-steve.wahl= @hpe.com/ Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian --- include/linux/dmar.h | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/include/linux/dmar.h b/include/linux/dmar.h index cbd714a198a0..d81a51978d01 100644 --- a/include/linux/dmar.h +++ b/include/linux/dmar.h @@ -18,11 +18,7 @@ =20 struct acpi_dmar_header; =20 -#ifdef CONFIG_X86 -# define DMAR_UNITS_SUPPORTED MAX_IO_APICS -#else -# define DMAR_UNITS_SUPPORTED 64 -#endif +#define DMAR_UNITS_SUPPORTED 1024 =20 /* DMAR Flags */ #define DMAR_INTR_REMAP 0x1 --=20 2.25.1