From nobody Sun Apr 19 10:41:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B7E4C43334 for ; Fri, 1 Jul 2022 14:48:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233662AbiGAOsS (ORCPT ); Fri, 1 Jul 2022 10:48:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43160 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233472AbiGAOsK (ORCPT ); Fri, 1 Jul 2022 10:48:10 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C895D2E693; Fri, 1 Jul 2022 07:47:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1656686879; x=1688222879; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Rf7fW/FCxNnSxG/1HF5J6f4FI/REm839eNlYY1nJDw8=; b=C3d/Q6GkA4NhD02YfR+XNWPTB9upU+noTsfEmWKvATpU2/UUGQ3/vZo4 FyNAD94X1a5NxYnzBLRnYVDEPi510VrH4CsniPPVteeHB5ur9K1JxQIJ+ YNk8raFbpdiHazQGlPM9acDM/sEjrAVOKQzBJSTqZmjAb7UD8086hPMXx E23RY8gYwwLczQfaP0JSIKz9SuwKxqo6ewZFku9oxmlrkkVCyy3EWEnEI e7Lj74IFNVs0biBtFufguvreAXlvaUgj8bNH4OHCXhDca/XXUybfPYq6R eiB0ES0PMphXRxbswlDgYyfYUyHmvaGItErM5x9iiSL/Gsifzn5l4gC6A A==; X-IronPort-AV: E=Sophos;i="5.92,237,1650956400"; d="scan'208";a="102666208" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Jul 2022 07:47:47 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 1 Jul 2022 07:47:46 -0700 Received: from CHE-LT-I17769U.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 1 Jul 2022 07:47:25 -0700 From: Arun Ramadoss To: , , , CC: Woojung Huh , , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , "Rob Herring" , Krzysztof Kozlowski , Russell King , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , "Song Liu" , Yonghong Song , John Fastabend , KP Singh Subject: [Patch net-next v15 01/13] dt-bindings: net: make internal-delay-ps based on phy-mode Date: Fri, 1 Jul 2022 20:16:40 +0530 Message-ID: <20220701144652.10526-2-arun.ramadoss@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220701144652.10526-1-arun.ramadoss@microchip.com> References: <20220701144652.10526-1-arun.ramadoss@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Prasanna Vengateshan *-internal-delay-ps properties would be applicable only for RGMII interface modes. It is changed as per the request. Ran dt_binding_check to confirm nothing is broken. link: https://lore.kernel.org/netdev/d8e5f6a8-a7e1-dabd-f4b4-ea8ea21d0a1d@g= mail.com/ Signed-off-by: Prasanna Vengateshan Signed-off-by: Arun Ramadoss Reviewed-by: Andrew Lunn Reviewed-by: Rob Herring Reviewed-by: Florian Fainelli --- .../bindings/net/ethernet-controller.yaml | 35 ++++++++++++------- 1 file changed, 23 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml= b/Documentation/devicetree/bindings/net/ethernet-controller.yaml index 4f15463611f8..56d9aca8c954 100644 --- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml @@ -133,12 +133,6 @@ properties: and is useful for determining certain configuration settings such as flow control thresholds. =20 - rx-internal-delay-ps: - description: | - RGMII Receive Clock Delay defined in pico seconds. - This is used for controllers that have configurable RX internal dela= ys. - If this property is present then the MAC applies the RX delay. - sfp: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -150,12 +144,6 @@ properties: The size of the controller\'s transmit fifo in bytes. This is used for components that can have configurable fifo sizes. =20 - tx-internal-delay-ps: - description: | - RGMII Transmit Clock Delay defined in pico seconds. - This is used for controllers that have configurable TX internal dela= ys. - If this property is present then the MAC applies the TX delay. - managed: description: Specifies the PHY management type. If auto is set and fixed-link @@ -232,6 +220,29 @@ properties: required: - speed =20 +allOf: + - if: + properties: + phy-mode: + contains: + enum: + - rgmii + - rgmii-rxid + - rgmii-txid + - rgmii-id + then: + properties: + rx-internal-delay-ps: + description: + RGMII Receive Clock Delay defined in pico seconds.This is used= for + controllers that have configurable RX internal delays. If this + property is present then the MAC applies the RX delay. + tx-internal-delay-ps: + description: + RGMII Transmit Clock Delay defined in pico seconds.This is use= d for + controllers that have configurable TX internal delays. If this + property is present then the MAC applies the TX delay. + additionalProperties: true =20 ... --=20 2.36.1 From nobody Sun Apr 19 10:41:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80E3ACCA47B for ; Fri, 1 Jul 2022 14:57:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233978AbiGAO5t (ORCPT ); Fri, 1 Jul 2022 10:57:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52924 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233933AbiGAO5k (ORCPT ); Fri, 1 Jul 2022 10:57:40 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0A39635AAB; Fri, 1 Jul 2022 07:57:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1656687458; x=1688223458; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WJDGz9/OvbfrZuiibHXSknluM0ipvvuQF6SC2KRZewk=; b=XpdDK/vk8HZahl9dubTFpMVGyUeh56ynki+XUP5UdytcQSWBFhfBBVHk SiJ0GQZIidsYm7a1Rpv63FS1A05vbdQVZL6Ba94k/yinkeRYuvpOwLv7h X8dHFzKPLm6OugWpCp1GYoqTNZIR+YliZUEaLt/fdXUPOpgjtNKbwwjTd 6jfAwoHTLft6gV3a2FsFtDLXdUIaO7BW2zp6j0IyZrBGapfgb7NKYAyep 8xXHaHpNHI0b3+oIopgFxrAh0irCFuA7J4sJj4IAOwYucne8JfY0fJlBf iSLviZ8JiAqw4F+5Pc4h6Ns0/mFeGxSPqIrrXtAqzneIxCyvQMC3/D2xL A==; X-IronPort-AV: E=Sophos;i="5.92,237,1650956400"; d="scan'208";a="166021967" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Jul 2022 07:57:37 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 1 Jul 2022 07:57:37 -0700 Received: from CHE-LT-I17769U.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 1 Jul 2022 07:57:17 -0700 From: Arun Ramadoss To: , , , CC: Woojung Huh , , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , "Rob Herring" , Krzysztof Kozlowski , Russell King , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , "Song Liu" , Yonghong Song , John Fastabend , KP Singh Subject: [Patch net-next v15 02/13] dt-bindings: net: dsa: dt bindings for microchip lan937x Date: Fri, 1 Jul 2022 20:27:03 +0530 Message-ID: <20220701145703.22165-1-arun.ramadoss@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220701144652.10526-1-arun.ramadoss@microchip.com> References: <20220701144652.10526-1-arun.ramadoss@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Prasanna Vengateshan Documentation in .yaml format and updates to the MAINTAINERS Also 'make dt_binding_check' is passed. RGMII internal delay values for the mac is retrieved from rx-internal-delay-ps & tx-internal-delay-ps as per the feedback from v3 patch series. https://lore.kernel.org/netdev/20210802121550.gqgbipqdvp5x76ii@skbuf/ It supports only the delay value of 0ns and 2ns. Signed-off-by: Prasanna Vengateshan Signed-off-by: Arun Ramadoss Reviewed-by: Rob Herring Reviewed-by: Florian Fainelli --- .../bindings/net/dsa/microchip,lan937x.yaml | 192 ++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 193 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/dsa/microchip,lan= 937x.yaml diff --git a/Documentation/devicetree/bindings/net/dsa/microchip,lan937x.ya= ml b/Documentation/devicetree/bindings/net/dsa/microchip,lan937x.yaml new file mode 100644 index 000000000000..630bf0f8294b --- /dev/null +++ b/Documentation/devicetree/bindings/net/dsa/microchip,lan937x.yaml @@ -0,0 +1,192 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/dsa/microchip,lan937x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LAN937x Ethernet Switch Series Tree Bindings + +maintainers: + - UNGLinuxDriver@microchip.com + +allOf: + - $ref: dsa.yaml# + +properties: + compatible: + enum: + - microchip,lan9370 + - microchip,lan9371 + - microchip,lan9372 + - microchip,lan9373 + - microchip,lan9374 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 50000000 + + reset-gpios: + description: Optional gpio specifier for a reset line + maxItems: 1 + + mdio: + $ref: /schemas/net/mdio.yaml# + unevaluatedProperties: false + +patternProperties: + "^(ethernet-)?ports$": + patternProperties: + "^(ethernet-)?port@[0-9]+$": + allOf: + - if: + properties: + phy-mode: + contains: + enum: + - rgmii + - rgmii-id + - rgmii-txid + - rgmii-rxid + then: + properties: + rx-internal-delay-ps: + enum: [0, 2000] + default: 0 + tx-internal-delay-ps: + enum: [0, 2000] + default: 0 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + macb0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + fixed-link { + speed =3D <1000>; + full-duplex; + }; + }; + + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + lan9374: switch@0 { + compatible =3D "microchip,lan9374"; + reg =3D <0>; + spi-max-frequency =3D <44000000>; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + label =3D "lan1"; + phy-mode =3D "internal"; + phy-handle =3D <&t1phy0>; + }; + + port@1 { + reg =3D <1>; + label =3D "lan2"; + phy-mode =3D "internal"; + phy-handle =3D <&t1phy1>; + }; + + port@2 { + reg =3D <2>; + label =3D "lan4"; + phy-mode =3D "internal"; + phy-handle =3D <&t1phy2>; + }; + + port@3 { + reg =3D <3>; + label =3D "lan6"; + phy-mode =3D "internal"; + phy-handle =3D <&t1phy3>; + }; + + port@4 { + reg =3D <4>; + phy-mode =3D "rgmii"; + tx-internal-delay-ps =3D <2000>; + rx-internal-delay-ps =3D <2000>; + ethernet =3D <&macb0>; + + fixed-link { + speed =3D <1000>; + full-duplex; + }; + }; + + port@5 { + reg =3D <5>; + label =3D "lan7"; + phy-mode =3D "rgmii"; + tx-internal-delay-ps =3D <2000>; + rx-internal-delay-ps =3D <2000>; + + fixed-link { + speed =3D <1000>; + full-duplex; + }; + }; + + port@6 { + reg =3D <6>; + label =3D "lan5"; + phy-mode =3D "internal"; + phy-handle =3D <&t1phy6>; + }; + + port@7 { + reg =3D <7>; + label =3D "lan3"; + phy-mode =3D "internal"; + phy-handle =3D <&t1phy7>; + }; + }; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + t1phy0: ethernet-phy@0{ + reg =3D <0x0>; + }; + + t1phy1: ethernet-phy@1{ + reg =3D <0x1>; + }; + + t1phy2: ethernet-phy@2{ + reg =3D <0x2>; + }; + + t1phy3: ethernet-phy@3{ + reg =3D <0x3>; + }; + + t1phy6: ethernet-phy@6{ + reg =3D <0x6>; + }; + + t1phy7: ethernet-phy@7{ + reg =3D <0x7>; + }; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index d99fedb48ab5..99f8a65fd79b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13104,6 +13104,7 @@ M: UNGLinuxDriver@microchip.com L: netdev@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml +F: Documentation/devicetree/bindings/net/dsa/microchip,lan937x.yaml F: drivers/net/dsa/microchip/* F: include/linux/platform_data/microchip-ksz.h F: net/dsa/tag_ksz.c --=20 2.36.1 From nobody Sun Apr 19 10:41:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2BE6AC43334 for ; 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X-IronPort-AV: E=Sophos;i="5.92,237,1650956400"; d="scan'208";a="102667616" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Jul 2022 08:00:46 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 1 Jul 2022 08:00:46 -0700 Received: from CHE-LT-I17769U.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 1 Jul 2022 08:00:26 -0700 From: Arun Ramadoss To: , , , CC: Woojung Huh , , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , "Rob Herring" , Krzysztof Kozlowski , Russell King , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , "Song Liu" , Yonghong Song , John Fastabend , KP Singh Subject: [Patch net-next v15 03/13] net: dsa: tag_ksz: add tag handling for Microchip LAN937x Date: Fri, 1 Jul 2022 20:30:20 +0530 Message-ID: <20220701150020.23735-1-arun.ramadoss@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220701144652.10526-1-arun.ramadoss@microchip.com> References: <20220701144652.10526-1-arun.ramadoss@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Prasanna Vengateshan The Microchip LAN937X switches have a tagging protocol which is very similar to KSZ tagging. So that the implementation is added to tag_ksz.c and reused common APIs Signed-off-by: Prasanna Vengateshan Signed-off-by: Arun Ramadoss Reviewed-by: Vladimir Oltean Reviewed-by: Florian Fainelli --- include/net/dsa.h | 2 ++ net/dsa/Kconfig | 4 ++-- net/dsa/tag_ksz.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 63 insertions(+), 2 deletions(-) diff --git a/include/net/dsa.h b/include/net/dsa.h index ea7bf007f34f..b902b31bebce 100644 --- a/include/net/dsa.h +++ b/include/net/dsa.h @@ -54,6 +54,7 @@ struct phylink_link_state; #define DSA_TAG_PROTO_RTL8_4_VALUE 24 #define DSA_TAG_PROTO_RTL8_4T_VALUE 25 #define DSA_TAG_PROTO_RZN1_A5PSW_VALUE 26 +#define DSA_TAG_PROTO_LAN937X_VALUE 27 =20 enum dsa_tag_protocol { DSA_TAG_PROTO_NONE =3D DSA_TAG_PROTO_NONE_VALUE, @@ -83,6 +84,7 @@ enum dsa_tag_protocol { DSA_TAG_PROTO_RTL8_4 =3D DSA_TAG_PROTO_RTL8_4_VALUE, DSA_TAG_PROTO_RTL8_4T =3D DSA_TAG_PROTO_RTL8_4T_VALUE, DSA_TAG_PROTO_RZN1_A5PSW =3D DSA_TAG_PROTO_RZN1_A5PSW_VALUE, + DSA_TAG_PROTO_LAN937X =3D DSA_TAG_PROTO_LAN937X_VALUE, }; =20 struct dsa_switch; diff --git a/net/dsa/Kconfig b/net/dsa/Kconfig index 63853fff4e2f..3eef72ce99a4 100644 --- a/net/dsa/Kconfig +++ b/net/dsa/Kconfig @@ -87,10 +87,10 @@ config NET_DSA_TAG_MTK Mediatek switches. =20 config NET_DSA_TAG_KSZ - tristate "Tag driver for Microchip 8795/9477/9893 families of switches" + tristate "Tag driver for Microchip 8795/937x/9477/9893 families of switch= es" help Say Y if you want to enable support for tagging frames for the - Microchip 8795/9477/9893 families of switches. + Microchip 8795/937x/9477/9893 families of switches. =20 config NET_DSA_TAG_OCELOT tristate "Tag driver for Ocelot family of switches, using NPI port" diff --git a/net/dsa/tag_ksz.c b/net/dsa/tag_ksz.c index 3509fc967ca9..38fa19c1e2d5 100644 --- a/net/dsa/tag_ksz.c +++ b/net/dsa/tag_ksz.c @@ -193,10 +193,69 @@ static const struct dsa_device_ops ksz9893_netdev_ops= =3D { DSA_TAG_DRIVER(ksz9893_netdev_ops); MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_KSZ9893); =20 +/* For xmit, 2 bytes are added before FCS. + * -----------------------------------------------------------------------= ---- + * DA(6bytes)|SA(6bytes)|....|Data(nbytes)|tag0(1byte)|tag1(1byte)|FCS(4by= tes) + * -----------------------------------------------------------------------= ---- + * tag0 : represents tag override, lookup and valid + * tag1 : each bit represents port (eg, 0x01=3Dport1, 0x02=3Dport2, 0x80= =3Dport8) + * + * For rcv, 1 byte is added before FCS. + * -----------------------------------------------------------------------= ---- + * DA(6bytes)|SA(6bytes)|....|Data(nbytes)|tag0(1byte)|FCS(4bytes) + * -----------------------------------------------------------------------= ---- + * tag0 : zero-based value represents port + * (eg, 0x00=3Dport1, 0x02=3Dport3, 0x07=3Dport8) + */ +#define LAN937X_EGRESS_TAG_LEN 2 + +#define LAN937X_TAIL_TAG_BLOCKING_OVERRIDE BIT(11) +#define LAN937X_TAIL_TAG_LOOKUP BIT(12) +#define LAN937X_TAIL_TAG_VALID BIT(13) +#define LAN937X_TAIL_TAG_PORT_MASK 7 + +static struct sk_buff *lan937x_xmit(struct sk_buff *skb, + struct net_device *dev) +{ + struct dsa_port *dp =3D dsa_slave_to_port(dev); + const struct ethhdr *hdr =3D eth_hdr(skb); + __be16 *tag; + u16 val; + + if (skb->ip_summed =3D=3D CHECKSUM_PARTIAL && skb_checksum_help(skb)) + return NULL; + + tag =3D skb_put(skb, LAN937X_EGRESS_TAG_LEN); + + val =3D BIT(dp->index); + + if (is_link_local_ether_addr(hdr->h_dest)) + val |=3D LAN937X_TAIL_TAG_BLOCKING_OVERRIDE; + + /* Tail tag valid bit - This bit should always be set by the CPU */ + val |=3D LAN937X_TAIL_TAG_VALID; + + put_unaligned_be16(val, tag); + + return skb; +} + +static const struct dsa_device_ops lan937x_netdev_ops =3D { + .name =3D "lan937x", + .proto =3D DSA_TAG_PROTO_LAN937X, + .xmit =3D lan937x_xmit, + .rcv =3D ksz9477_rcv, + .needed_tailroom =3D LAN937X_EGRESS_TAG_LEN, +}; + +DSA_TAG_DRIVER(lan937x_netdev_ops); +MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_LAN937X); + static struct dsa_tag_driver *dsa_tag_driver_array[] =3D { &DSA_TAG_DRIVER_NAME(ksz8795_netdev_ops), &DSA_TAG_DRIVER_NAME(ksz9477_netdev_ops), &DSA_TAG_DRIVER_NAME(ksz9893_netdev_ops), + &DSA_TAG_DRIVER_NAME(lan937x_netdev_ops), }; =20 module_dsa_tag_drivers(dsa_tag_driver_array); --=20 2.36.1 From nobody Sun Apr 19 10:41:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43DFBC43334 for ; Fri, 1 Jul 2022 15:01:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231772AbiGAPBj (ORCPT ); Fri, 1 Jul 2022 11:01:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57930 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231715AbiGAPBd (ORCPT ); Fri, 1 Jul 2022 11:01:33 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9553F24F28; Fri, 1 Jul 2022 08:01:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; 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Fri, 1 Jul 2022 08:01:08 -0700 From: Arun Ramadoss To: , , , CC: Woojung Huh , , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , "Rob Herring" , Krzysztof Kozlowski , Russell King , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , "Song Liu" , Yonghong Song , John Fastabend , KP Singh Subject: [Patch net-next v15 04/13] net: dsa: microchip: generic access to ksz9477 static and reserved table Date: Fri, 1 Jul 2022 20:31:01 +0530 Message-ID: <20220701150101.23787-1-arun.ramadoss@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220701144652.10526-1-arun.ramadoss@microchip.com> References: <20220701144652.10526-1-arun.ramadoss@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The ksz9477 and lan937x has few difference in the static and reserved table register 0x041C. For the ksz9477 if the bit 0 is 1 - read operation and 0 - write operation. But for lan937x bit 1:0 used for selecting the read/write operation, 01 - write and 10 - read. To use ksz9477 mdb add/del and enable_stp_addr for the lan937x, masks & shifts are introduced for ksz9477 & lan937x in ksz_common.c. Then updated the function with masks & shifts based on the switch instead of hard coding it. Signed-off-by: Arun Ramadoss --- drivers/net/dsa/microchip/ksz9477.c | 27 ++++++++++++++----- drivers/net/dsa/microchip/ksz9477_reg.h | 3 --- drivers/net/dsa/microchip/ksz_common.c | 35 +++++++++++++++++++++++++ drivers/net/dsa/microchip/ksz_common.h | 3 +++ 4 files changed, 58 insertions(+), 10 deletions(-) diff --git a/drivers/net/dsa/microchip/ksz9477.c b/drivers/net/dsa/microchi= p/ksz9477.c index 0e808d27124c..6453642fa14c 100644 --- a/drivers/net/dsa/microchip/ksz9477.c +++ b/drivers/net/dsa/microchip/ksz9477.c @@ -644,11 +644,16 @@ int ksz9477_mdb_add(struct ksz_device *dev, int port, const struct switchdev_obj_port_mdb *mdb, struct dsa_db db) { u32 static_table[4]; + const u8 *shifts; + const u32 *masks; u32 data; int index; u32 mac_hi, mac_lo; int err =3D 0; =20 + shifts =3D dev->info->shifts; + masks =3D dev->info->masks; + mac_hi =3D ((mdb->addr[0] << 8) | mdb->addr[1]); mac_lo =3D ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); mac_lo |=3D ((mdb->addr[4] << 8) | mdb->addr[5]); @@ -657,8 +662,8 @@ int ksz9477_mdb_add(struct ksz_device *dev, int port, =20 for (index =3D 0; index < dev->info->num_statics; index++) { /* find empty slot first */ - data =3D (index << ALU_STAT_INDEX_S) | - ALU_STAT_READ | ALU_STAT_START; + data =3D (index << shifts[ALU_STAT_INDEX]) | + masks[ALU_STAT_READ] | ALU_STAT_START; ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); =20 /* wait to be finished */ @@ -702,7 +707,7 @@ int ksz9477_mdb_add(struct ksz_device *dev, int port, =20 ksz9477_write_table(dev, static_table); =20 - data =3D (index << ALU_STAT_INDEX_S) | ALU_STAT_START; + data =3D (index << shifts[ALU_STAT_INDEX]) | ALU_STAT_START; ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); =20 /* wait to be finished */ @@ -718,11 +723,16 @@ int ksz9477_mdb_del(struct ksz_device *dev, int port, const struct switchdev_obj_port_mdb *mdb, struct dsa_db db) { u32 static_table[4]; + const u8 *shifts; + const u32 *masks; u32 data; int index; int ret =3D 0; u32 mac_hi, mac_lo; =20 + shifts =3D dev->info->shifts; + masks =3D dev->info->masks; + mac_hi =3D ((mdb->addr[0] << 8) | mdb->addr[1]); mac_lo =3D ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); mac_lo |=3D ((mdb->addr[4] << 8) | mdb->addr[5]); @@ -731,8 +741,8 @@ int ksz9477_mdb_del(struct ksz_device *dev, int port, =20 for (index =3D 0; index < dev->info->num_statics; index++) { /* find empty slot first */ - data =3D (index << ALU_STAT_INDEX_S) | - ALU_STAT_READ | ALU_STAT_START; + data =3D (index << shifts[ALU_STAT_INDEX]) | + masks[ALU_STAT_READ] | ALU_STAT_START; ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); =20 /* wait to be finished */ @@ -774,7 +784,7 @@ int ksz9477_mdb_del(struct ksz_device *dev, int port, =20 ksz9477_write_table(dev, static_table); =20 - data =3D (index << ALU_STAT_INDEX_S) | ALU_STAT_START; + data =3D (index << shifts[ALU_STAT_INDEX]) | ALU_STAT_START; ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); =20 /* wait to be finished */ @@ -1230,9 +1240,12 @@ void ksz9477_config_cpu_port(struct dsa_switch *ds) =20 int ksz9477_enable_stp_addr(struct ksz_device *dev) { + const u32 *masks; u32 data; int ret; =20 + masks =3D dev->info->masks; + /* Enable Reserved multicast table */ ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_RESV_MCAST_ENABLE, true); =20 @@ -1242,7 +1255,7 @@ int ksz9477_enable_stp_addr(struct ksz_device *dev) if (ret < 0) return ret; =20 - data =3D ALU_STAT_START | ALU_RESV_MCAST_ADDR; + data =3D ALU_STAT_START | ALU_RESV_MCAST_ADDR | masks[ALU_STAT_WRITE]; =20 ret =3D ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); if (ret < 0) diff --git a/drivers/net/dsa/microchip/ksz9477_reg.h b/drivers/net/dsa/micr= ochip/ksz9477_reg.h index 2ba0f4449130..d0cce4ca3cf9 100644 --- a/drivers/net/dsa/microchip/ksz9477_reg.h +++ b/drivers/net/dsa/microchip/ksz9477_reg.h @@ -419,12 +419,9 @@ =20 #define REG_SW_ALU_STAT_CTRL__4 0x041C =20 -#define ALU_STAT_INDEX_M (BIT(4) - 1) -#define ALU_STAT_INDEX_S 16 #define ALU_RESV_MCAST_INDEX_M (BIT(6) - 1) #define ALU_STAT_START BIT(7) #define ALU_RESV_MCAST_ADDR BIT(1) -#define ALU_STAT_READ BIT(0) =20 #define REG_SW_ALU_VAL_A 0x0420 =20 diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/micro= chip/ksz_common.c index 29b42b3b39c9..d631a4bf35ed 100644 --- a/drivers/net/dsa/microchip/ksz_common.c +++ b/drivers/net/dsa/microchip/ksz_common.c @@ -314,7 +314,24 @@ static const u16 ksz9477_regs[] =3D { [S_START_CTRL] =3D 0x0300, [S_BROADCAST_CTRL] =3D 0x0332, [S_MULTICAST_CTRL] =3D 0x0331, +}; + +static const u32 ksz9477_masks[] =3D { + [ALU_STAT_WRITE] =3D 0, + [ALU_STAT_READ] =3D 1, +}; + +static const u8 ksz9477_shifts[] =3D { + [ALU_STAT_INDEX] =3D 16, +}; + +static const u32 lan937x_masks[] =3D { + [ALU_STAT_WRITE] =3D 1, + [ALU_STAT_READ] =3D 2, +}; =20 +static const u8 lan937x_shifts[] =3D { + [ALU_STAT_INDEX] =3D 8, }; =20 const struct ksz_chip_data ksz_switch_chips[] =3D { @@ -432,6 +449,8 @@ const struct ksz_chip_data ksz_switch_chips[] =3D { .mib_cnt =3D ARRAY_SIZE(ksz9477_mib_names), .reg_mib_cnt =3D MIB_COUNTER_NUM, .regs =3D ksz9477_regs, + .masks =3D ksz9477_masks, + .shifts =3D ksz9477_shifts, .supports_mii =3D {false, false, false, false, false, true, false}, .supports_rmii =3D {false, false, false, false, @@ -456,6 +475,8 @@ const struct ksz_chip_data ksz_switch_chips[] =3D { .mib_cnt =3D ARRAY_SIZE(ksz9477_mib_names), .reg_mib_cnt =3D MIB_COUNTER_NUM, .regs =3D ksz9477_regs, + .masks =3D ksz9477_masks, + .shifts =3D ksz9477_shifts, .supports_mii =3D {false, false, false, false, false, true, true}, .supports_rmii =3D {false, false, false, false, @@ -479,6 +500,8 @@ const struct ksz_chip_data ksz_switch_chips[] =3D { .mib_cnt =3D ARRAY_SIZE(ksz9477_mib_names), .reg_mib_cnt =3D MIB_COUNTER_NUM, .regs =3D ksz9477_regs, + .masks =3D ksz9477_masks, + .shifts =3D ksz9477_shifts, .supports_mii =3D {false, false, true}, .supports_rmii =3D {false, false, true}, .supports_rgmii =3D {false, false, true}, @@ -499,6 +522,8 @@ const struct ksz_chip_data ksz_switch_chips[] =3D { .mib_cnt =3D ARRAY_SIZE(ksz9477_mib_names), .reg_mib_cnt =3D MIB_COUNTER_NUM, .regs =3D ksz9477_regs, + .masks =3D ksz9477_masks, + .shifts =3D ksz9477_shifts, .supports_mii =3D {false, false, false, false, false, true, true}, .supports_rmii =3D {false, false, false, false, @@ -521,6 +546,8 @@ const struct ksz_chip_data ksz_switch_chips[] =3D { .mib_cnt =3D ARRAY_SIZE(ksz9477_mib_names), .reg_mib_cnt =3D MIB_COUNTER_NUM, .regs =3D ksz9477_regs, + .masks =3D lan937x_masks, + .shifts =3D lan937x_shifts, .supports_mii =3D {false, false, false, false, true}, .supports_rmii =3D {false, false, false, false, true}, .supports_rgmii =3D {false, false, false, false, true}, @@ -539,6 +566,8 @@ const struct ksz_chip_data ksz_switch_chips[] =3D { .mib_cnt =3D ARRAY_SIZE(ksz9477_mib_names), .reg_mib_cnt =3D MIB_COUNTER_NUM, .regs =3D ksz9477_regs, + .masks =3D lan937x_masks, + .shifts =3D lan937x_shifts, .supports_mii =3D {false, false, false, false, true, true}, .supports_rmii =3D {false, false, false, false, true, true}, .supports_rgmii =3D {false, false, false, false, true, true}, @@ -557,6 +586,8 @@ const struct ksz_chip_data ksz_switch_chips[] =3D { .mib_cnt =3D ARRAY_SIZE(ksz9477_mib_names), .reg_mib_cnt =3D MIB_COUNTER_NUM, .regs =3D ksz9477_regs, + .masks =3D lan937x_masks, + .shifts =3D lan937x_shifts, .supports_mii =3D {false, false, false, false, true, true, false, false}, .supports_rmii =3D {false, false, false, false, @@ -579,6 +610,8 @@ const struct ksz_chip_data ksz_switch_chips[] =3D { .mib_cnt =3D ARRAY_SIZE(ksz9477_mib_names), .reg_mib_cnt =3D MIB_COUNTER_NUM, .regs =3D ksz9477_regs, + .masks =3D lan937x_masks, + .shifts =3D lan937x_shifts, .supports_mii =3D {false, false, false, false, true, true, false, false}, .supports_rmii =3D {false, false, false, false, @@ -601,6 +634,8 @@ const struct ksz_chip_data ksz_switch_chips[] =3D { .mib_cnt =3D ARRAY_SIZE(ksz9477_mib_names), .reg_mib_cnt =3D MIB_COUNTER_NUM, .regs =3D ksz9477_regs, + .masks =3D lan937x_masks, + .shifts =3D lan937x_shifts, .supports_mii =3D {false, false, false, false, true, true, false, false}, .supports_rmii =3D {false, false, false, false, diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/micro= chip/ksz_common.h index b61e569a9949..5f69dc872752 100644 --- a/drivers/net/dsa/microchip/ksz_common.h +++ b/drivers/net/dsa/microchip/ksz_common.h @@ -191,6 +191,8 @@ enum ksz_masks { DYNAMIC_MAC_TABLE_FID, DYNAMIC_MAC_TABLE_SRC_PORT, DYNAMIC_MAC_TABLE_TIMESTAMP, + ALU_STAT_WRITE, + ALU_STAT_READ, }; =20 enum ksz_shifts { @@ -203,6 +205,7 @@ enum ksz_shifts { DYNAMIC_MAC_FID, DYNAMIC_MAC_TIMESTAMP, DYNAMIC_MAC_SRC_PORT, + ALU_STAT_INDEX, }; =20 struct alu_struct { --=20 2.36.1 From nobody Sun Apr 19 10:41:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B811C43334 for ; Fri, 1 Jul 2022 15:02:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232935AbiGAPCQ (ORCPT ); Fri, 1 Jul 2022 11:02:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231785AbiGAPCO (ORCPT ); Fri, 1 Jul 2022 11:02:14 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 086E73BBE1; Fri, 1 Jul 2022 08:02:13 -0700 (PDT) DKIM-Signature: v=1; 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Fri, 1 Jul 2022 08:02:11 -0700 Received: from CHE-LT-I17769U.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 1 Jul 2022 08:01:51 -0700 From: Arun Ramadoss To: , , , CC: Woojung Huh , , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , "Rob Herring" , Krzysztof Kozlowski , Russell King , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , "Song Liu" , Yonghong Song , John Fastabend , KP Singh Subject: [Patch net-next v15 05/13] net: dsa: microchip: add DSA support for microchip LAN937x Date: Fri, 1 Jul 2022 20:31:46 +0530 Message-ID: <20220701150146.23806-1-arun.ramadoss@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220701144652.10526-1-arun.ramadoss@microchip.com> References: <20220701144652.10526-1-arun.ramadoss@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Basic DSA driver support for lan937x and the device will be configured through SPI interface. It adds the lan937x_dev_ops in ksz_common.c file and tries to reuse the functionality of ksz9477 series switch. drivers/net/dsa/microchip/ path is already part of MAINTAINERS & the new files come under this path. Hence no update needed to the MAINTAINERS Signed-off-by: Arun Ramadoss --- drivers/net/dsa/microchip/Kconfig | 2 +- drivers/net/dsa/microchip/Makefile | 1 + drivers/net/dsa/microchip/ksz_common.c | 34 +++++ drivers/net/dsa/microchip/lan937x.h | 15 +++ drivers/net/dsa/microchip/lan937x_main.c | 154 +++++++++++++++++++++++ drivers/net/dsa/microchip/lan937x_reg.h | 128 +++++++++++++++++++ 6 files changed, 333 insertions(+), 1 deletion(-) create mode 100644 drivers/net/dsa/microchip/lan937x.h create mode 100644 drivers/net/dsa/microchip/lan937x_main.c create mode 100644 drivers/net/dsa/microchip/lan937x_reg.h diff --git a/drivers/net/dsa/microchip/Kconfig b/drivers/net/dsa/microchip/= Kconfig index 2edb88080790..06b1efdb5e7d 100644 --- a/drivers/net/dsa/microchip/Kconfig +++ b/drivers/net/dsa/microchip/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only menuconfig NET_DSA_MICROCHIP_KSZ_COMMON - tristate "Microchip KSZ8795/KSZ9477 series switch support" + tristate "Microchip KSZ8795/KSZ9477/LAN937x series switch support" depends on NET_DSA select NET_DSA_TAG_KSZ help diff --git a/drivers/net/dsa/microchip/Makefile b/drivers/net/dsa/microchip= /Makefile index b2ba7c1bcb93..28873559efc2 100644 --- a/drivers/net/dsa/microchip/Makefile +++ b/drivers/net/dsa/microchip/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON) +=3D ksz_switch.o ksz_switch-objs :=3D ksz_common.o ksz_switch-objs +=3D ksz9477.o ksz_switch-objs +=3D ksz8795.o +ksz_switch-objs +=3D lan937x_main.o obj-$(CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C) +=3D ksz9477_i2c.o obj-$(CONFIG_NET_DSA_MICROCHIP_KSZ_SPI) +=3D ksz_spi.o obj-$(CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI) +=3D ksz8863_smi.o diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/micro= chip/ksz_common.c index d631a4bf35ed..83e44598d00c 100644 --- a/drivers/net/dsa/microchip/ksz_common.c +++ b/drivers/net/dsa/microchip/ksz_common.c @@ -23,6 +23,7 @@ #include "ksz_common.h" #include "ksz8.h" #include "ksz9477.h" +#include "lan937x.h" =20 #define MIB_COUNTER_NUM 0x20 =20 @@ -201,6 +202,34 @@ static const struct ksz_dev_ops ksz9477_dev_ops =3D { .exit =3D ksz9477_switch_exit, }; =20 +static const struct ksz_dev_ops lan937x_dev_ops =3D { + .setup =3D lan937x_setup, + .get_port_addr =3D ksz9477_get_port_addr, + .cfg_port_member =3D ksz9477_cfg_port_member, + .port_setup =3D lan937x_port_setup, + .r_mib_cnt =3D ksz9477_r_mib_cnt, + .r_mib_pkt =3D ksz9477_r_mib_pkt, + .r_mib_stat64 =3D ksz_r_mib_stats64, + .freeze_mib =3D ksz9477_freeze_mib, + .port_init_cnt =3D ksz9477_port_init_cnt, + .vlan_filtering =3D ksz9477_port_vlan_filtering, + .vlan_add =3D ksz9477_port_vlan_add, + .vlan_del =3D ksz9477_port_vlan_del, + .mirror_add =3D ksz9477_port_mirror_add, + .mirror_del =3D ksz9477_port_mirror_del, + .fdb_dump =3D ksz9477_fdb_dump, + .fdb_add =3D ksz9477_fdb_add, + .fdb_del =3D ksz9477_fdb_del, + .mdb_add =3D ksz9477_mdb_add, + .mdb_del =3D ksz9477_mdb_del, + .max_mtu =3D ksz9477_max_mtu, + .config_cpu_port =3D lan937x_config_cpu_port, + .enable_stp_addr =3D ksz9477_enable_stp_addr, + .reset =3D lan937x_reset_switch, + .init =3D lan937x_switch_init, + .exit =3D lan937x_switch_exit, +}; + static const u16 ksz8795_regs[] =3D { [REG_IND_CTRL_0] =3D 0x6E, [REG_IND_DATA_8] =3D 0x70, @@ -542,6 +571,7 @@ const struct ksz_chip_data ksz_switch_chips[] =3D { .num_statics =3D 256, .cpu_ports =3D 0x10, /* can be configured as cpu port */ .port_cnt =3D 5, /* total physical port count */ + .ops =3D &lan937x_dev_ops, .mib_names =3D ksz9477_mib_names, .mib_cnt =3D ARRAY_SIZE(ksz9477_mib_names), .reg_mib_cnt =3D MIB_COUNTER_NUM, @@ -562,6 +592,7 @@ const struct ksz_chip_data ksz_switch_chips[] =3D { .num_statics =3D 256, .cpu_ports =3D 0x30, /* can be configured as cpu port */ .port_cnt =3D 6, /* total physical port count */ + .ops =3D &lan937x_dev_ops, .mib_names =3D ksz9477_mib_names, .mib_cnt =3D ARRAY_SIZE(ksz9477_mib_names), .reg_mib_cnt =3D MIB_COUNTER_NUM, @@ -582,6 +613,7 @@ const struct ksz_chip_data ksz_switch_chips[] =3D { .num_statics =3D 256, .cpu_ports =3D 0x30, /* can be configured as cpu port */ .port_cnt =3D 8, /* total physical port count */ + .ops =3D &lan937x_dev_ops, .mib_names =3D ksz9477_mib_names, .mib_cnt =3D ARRAY_SIZE(ksz9477_mib_names), .reg_mib_cnt =3D MIB_COUNTER_NUM, @@ -606,6 +638,7 @@ const struct ksz_chip_data ksz_switch_chips[] =3D { .num_statics =3D 256, .cpu_ports =3D 0x38, /* can be configured as cpu port */ .port_cnt =3D 5, /* total physical port count */ + .ops =3D &lan937x_dev_ops, .mib_names =3D ksz9477_mib_names, .mib_cnt =3D ARRAY_SIZE(ksz9477_mib_names), .reg_mib_cnt =3D MIB_COUNTER_NUM, @@ -630,6 +663,7 @@ const struct ksz_chip_data ksz_switch_chips[] =3D { .num_statics =3D 256, .cpu_ports =3D 0x30, /* can be configured as cpu port */ .port_cnt =3D 8, /* total physical port count */ + .ops =3D &lan937x_dev_ops, .mib_names =3D ksz9477_mib_names, .mib_cnt =3D ARRAY_SIZE(ksz9477_mib_names), .reg_mib_cnt =3D MIB_COUNTER_NUM, diff --git a/drivers/net/dsa/microchip/lan937x.h b/drivers/net/dsa/microchi= p/lan937x.h new file mode 100644 index 000000000000..534f5a7a1129 --- /dev/null +++ b/drivers/net/dsa/microchip/lan937x.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Microchip lan937x dev ops headers + * Copyright (C) 2019-2022 Microchip Technology Inc. + */ + +#ifndef __LAN937X_CFG_H +#define __LAN937X_CFG_H + +int lan937x_reset_switch(struct ksz_device *dev); +int lan937x_setup(struct dsa_switch *ds); +void lan937x_port_setup(struct ksz_device *dev, int port, bool cpu_port); +void lan937x_config_cpu_port(struct dsa_switch *ds); +int lan937x_switch_init(struct ksz_device *dev); +void lan937x_switch_exit(struct ksz_device *dev); +#endif diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/mic= rochip/lan937x_main.c new file mode 100644 index 000000000000..e167a0c1ff85 --- /dev/null +++ b/drivers/net/dsa/microchip/lan937x_main.c @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Microchip LAN937X switch driver main logic + * Copyright (C) 2019-2022 Microchip Technology Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "lan937x_reg.h" +#include "ksz_common.h" +#include "lan937x.h" + +static int lan937x_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) +{ + return regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0); +} + +static int lan937x_port_cfg(struct ksz_device *dev, int port, int offset, + u8 bits, bool set) +{ + return regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset), + bits, set ? bits : 0); +} + +int lan937x_reset_switch(struct ksz_device *dev) +{ + u32 data32; + int ret; + + /* reset switch */ + ret =3D lan937x_cfg(dev, REG_SW_OPERATION, SW_RESET, true); + if (ret < 0) + return ret; + + /* Enable Auto Aging */ + ret =3D lan937x_cfg(dev, REG_SW_LUE_CTRL_1, SW_LINK_AUTO_AGING, true); + if (ret < 0) + return ret; + + /* disable interrupts */ + ret =3D ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK); + if (ret < 0) + return ret; + + ret =3D ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0xFF); + if (ret < 0) + return ret; + + return ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32); +} + +void lan937x_port_setup(struct ksz_device *dev, int port, bool cpu_port) +{ + struct dsa_switch *ds =3D dev->ds; + u8 member; + + /* enable tag tail for host port */ + if (cpu_port) + lan937x_port_cfg(dev, port, REG_PORT_CTRL_0, + PORT_TAIL_TAG_ENABLE, true); + + /* disable frame check length field */ + lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0, PORT_CHECK_LENGTH, + false); + + /* set back pressure for half duplex */ + lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, + true); + + /* enable 802.1p priority */ + lan937x_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true); + + if (!dev->info->internal_phy[port]) + lan937x_port_cfg(dev, port, REG_PORT_XMII_CTRL_0, + PORT_MII_TX_FLOW_CTRL | PORT_MII_RX_FLOW_CTRL, + true); + + if (cpu_port) + member =3D dsa_user_ports(ds); + else + member =3D BIT(dsa_upstream_port(ds, port)); + + dev->dev_ops->cfg_port_member(dev, port, member); +} + +void lan937x_config_cpu_port(struct dsa_switch *ds) +{ + struct ksz_device *dev =3D ds->priv; + struct dsa_port *dp; + + dsa_switch_for_each_cpu_port(dp, ds) { + if (dev->info->cpu_ports & (1 << dp->index)) { + dev->cpu_port =3D dp->index; + + /* enable cpu port */ + lan937x_port_setup(dev, dp->index, true); + } + } + + dsa_switch_for_each_user_port(dp, ds) { + ksz_port_stp_state_set(ds, dp->index, BR_STATE_DISABLED); + } +} + +int lan937x_setup(struct dsa_switch *ds) +{ + struct ksz_device *dev =3D ds->priv; + + /* The VLAN aware is a global setting. Mixed vlan + * filterings are not supported. + */ + ds->vlan_filtering_is_global =3D true; + + /* Enable aggressive back off for half duplex & UNH mode */ + lan937x_cfg(dev, REG_SW_MAC_CTRL_0, + (SW_PAUSE_UNH_MODE | SW_NEW_BACKOFF | SW_AGGR_BACKOFF), + true); + + /* If NO_EXC_COLLISION_DROP bit is set, the switch will not drop + * packets when 16 or more collisions occur + */ + lan937x_cfg(dev, REG_SW_MAC_CTRL_1, NO_EXC_COLLISION_DROP, true); + + /* enable global MIB counter freeze function */ + lan937x_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true); + + /* disable CLK125 & CLK25, 1: disable, 0: enable */ + lan937x_cfg(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, + (SW_CLK125_ENB | SW_CLK25_ENB), true); + + return 0; +} + +int lan937x_switch_init(struct ksz_device *dev) +{ + dev->port_mask =3D (1 << dev->info->port_cnt) - 1; + + return 0; +} + +void lan937x_switch_exit(struct ksz_device *dev) +{ + lan937x_reset_switch(dev); +} + +MODULE_AUTHOR("Arun Ramadoss "); +MODULE_DESCRIPTION("Microchip LAN937x Series Switch DSA Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/net/dsa/microchip/lan937x_reg.h b/drivers/net/dsa/micr= ochip/lan937x_reg.h new file mode 100644 index 000000000000..5e27b2bd2d86 --- /dev/null +++ b/drivers/net/dsa/microchip/lan937x_reg.h @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Microchip LAN937X switch register definitions + * Copyright (C) 2019-2021 Microchip Technology Inc. + */ +#ifndef __LAN937X_REG_H +#define __LAN937X_REG_H + +#define PORT_CTRL_ADDR(port, addr) ((addr) | (((port) + 1) << 12)) + +/* 0 - Operation */ +#define REG_SW_INT_STATUS__4 0x0010 +#define REG_SW_INT_MASK__4 0x0014 + +#define LUE_INT BIT(31) +#define TRIG_TS_INT BIT(30) +#define APB_TIMEOUT_INT BIT(29) +#define OVER_TEMP_INT BIT(28) +#define HSR_INT BIT(27) +#define PIO_INT BIT(26) +#define POR_READY_INT BIT(25) + +#define SWITCH_INT_MASK \ + (LUE_INT | TRIG_TS_INT | APB_TIMEOUT_INT | OVER_TEMP_INT | HSR_INT | \ + PIO_INT | POR_READY_INT) + +#define REG_SW_PORT_INT_STATUS__4 0x0018 +#define REG_SW_PORT_INT_MASK__4 0x001C + +/* 1 - Global */ +#define REG_SW_GLOBAL_OUTPUT_CTRL__1 0x0103 +#define SW_CLK125_ENB BIT(1) +#define SW_CLK25_ENB BIT(0) + +/* 3 - Operation Control */ +#define REG_SW_OPERATION 0x0300 + +#define SW_DOUBLE_TAG BIT(7) +#define SW_OVER_TEMP_ENABLE BIT(2) +#define SW_RESET BIT(1) + +#define REG_SW_LUE_CTRL_0 0x0310 + +#define SW_VLAN_ENABLE BIT(7) +#define SW_DROP_INVALID_VID BIT(6) +#define SW_AGE_CNT_M 0x7 +#define SW_AGE_CNT_S 3 +#define SW_RESV_MCAST_ENABLE BIT(2) + +#define REG_SW_LUE_CTRL_1 0x0311 + +#define UNICAST_LEARN_DISABLE BIT(7) +#define SW_FLUSH_STP_TABLE BIT(5) +#define SW_FLUSH_MSTP_TABLE BIT(4) +#define SW_SRC_ADDR_FILTER BIT(3) +#define SW_AGING_ENABLE BIT(2) +#define SW_FAST_AGING BIT(1) +#define SW_LINK_AUTO_AGING BIT(0) + +#define REG_SW_MAC_CTRL_0 0x0330 +#define SW_NEW_BACKOFF BIT(7) +#define SW_PAUSE_UNH_MODE BIT(1) +#define SW_AGGR_BACKOFF BIT(0) + +#define REG_SW_MAC_CTRL_1 0x0331 +#define SW_SHORT_IFG BIT(7) +#define MULTICAST_STORM_DISABLE BIT(6) +#define SW_BACK_PRESSURE BIT(5) +#define FAIR_FLOW_CTRL BIT(4) +#define NO_EXC_COLLISION_DROP BIT(3) +#define SW_LEGAL_PACKET_DISABLE BIT(1) +#define SW_PASS_SHORT_FRAME BIT(0) + +#define REG_SW_MAC_CTRL_6 0x0336 +#define SW_MIB_COUNTER_FLUSH BIT(7) +#define SW_MIB_COUNTER_FREEZE BIT(6) + +/* 4 - LUE */ +#define REG_SW_ALU_STAT_CTRL__4 0x041C + +#define REG_SW_ALU_VAL_B 0x0424 +#define ALU_V_OVERRIDE BIT(31) +#define ALU_V_USE_FID BIT(30) +#define ALU_V_PORT_MAP 0xFF + +/* Port Registers */ + +/* 0 - Operation */ +#define REG_PORT_CTRL_0 0x0020 + +#define PORT_MAC_LOOPBACK BIT(7) +#define PORT_MAC_REMOTE_LOOPBACK BIT(6) +#define PORT_K2L_INSERT_ENABLE BIT(5) +#define PORT_K2L_DEBUG_ENABLE BIT(4) +#define PORT_TAIL_TAG_ENABLE BIT(2) +#define PORT_QUEUE_SPLIT_ENABLE 0x3 + +/* 3 - xMII */ +#define REG_PORT_XMII_CTRL_0 0x0300 +#define PORT_SGMII_SEL BIT(7) +#define PORT_MII_FULL_DUPLEX BIT(6) +#define PORT_MII_TX_FLOW_CTRL BIT(5) +#define PORT_MII_100MBIT BIT(4) +#define PORT_MII_RX_FLOW_CTRL BIT(3) +#define PORT_GRXC_ENABLE BIT(0) + +/* 4 - MAC */ +#define REG_PORT_MAC_CTRL_0 0x0400 +#define PORT_CHECK_LENGTH BIT(2) +#define PORT_BROADCAST_STORM BIT(1) +#define PORT_JUMBO_PACKET BIT(0) + +#define REG_PORT_MAC_CTRL_1 0x0401 +#define PORT_BACK_PRESSURE BIT(3) +#define PORT_PASS_ALL BIT(0) + +/* 8 - Classification and Policing */ +#define REG_PORT_MRI_PRIO_CTRL 0x0801 +#define PORT_HIGHEST_PRIO BIT(7) +#define PORT_OR_PRIO BIT(6) +#define PORT_MAC_PRIO_ENABLE BIT(4) +#define PORT_VLAN_PRIO_ENABLE BIT(3) +#define PORT_802_1P_PRIO_ENABLE BIT(2) +#define PORT_DIFFSERV_PRIO_ENABLE BIT(1) +#define PORT_ACL_PRIO_ENABLE BIT(0) + +#define P_PRIO_CTRL REG_PORT_MRI_PRIO_CTRL + +#endif --=20 2.36.1 From nobody Sun Apr 19 10:41:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81E29C43334 for ; Fri, 1 Jul 2022 15:03:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233015AbiGAPDA (ORCPT ); Fri, 1 Jul 2022 11:03:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59068 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231599AbiGAPC4 (ORCPT ); Fri, 1 Jul 2022 11:02:56 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AEDD63DDC3; Fri, 1 Jul 2022 08:02:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1656687776; x=1688223776; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3p1haOctquxewPlqf+5TUBaW2f+6nbsODmUnBqHiBj8=; b=rPacwOmsl1v6tsZZjDOdCrblMjM6MFaQWSRwAI37GLzwoiBECQriF42i OCvrOlXSI/KglgvyxpF64eD4bnLC0jMpqvECPdznjICnzR8pcAY8GrFOR cbFwkOWoRwMnh3H1Dtt6QbT8gsM/TYga3oMzcJA0LrIQ8pG3jBv4TT2yG E99z3C8VId1fZFZ+GkMp3MfX99NnCe5SodIHNNFJeb/LhgLaveBrAYVr1 vOqONgCI4xfViakh/S3yu6H4oMObwHnER/lMA+pBSdmbIW9RT675MMgOH vApogXfm1d09NvL9uumFKhVi4BQxXBYLOM23RjyR3kD8oGs7wgelrEOXP A==; X-IronPort-AV: E=Sophos;i="5.92,237,1650956400"; d="scan'208";a="162957738" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Jul 2022 08:02:55 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 1 Jul 2022 08:02:51 -0700 Received: from CHE-LT-I17769U.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 1 Jul 2022 08:02:31 -0700 From: Arun Ramadoss To: , , , CC: Woojung Huh , , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , "Rob Herring" , Krzysztof Kozlowski , Russell King , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , "Song Liu" , Yonghong Song , John Fastabend , KP Singh Subject: [Patch net-next v15 06/13] net: dsa: microchip: lan937x: add dsa_tag_protocol Date: Fri, 1 Jul 2022 20:32:23 +0530 Message-ID: <20220701150223.23832-1-arun.ramadoss@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220701144652.10526-1-arun.ramadoss@microchip.com> References: <20220701144652.10526-1-arun.ramadoss@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch update the ksz_get_tag_protocol to return LAN937x specific tag if the chip id matches one of LAN937x series switch Signed-off-by: Arun Ramadoss --- drivers/net/dsa/microchip/ksz_common.c | 3 +++ drivers/net/dsa/microchip/ksz_common.h | 9 +++++++++ 2 files changed, 12 insertions(+) diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/micro= chip/ksz_common.c index 83e44598d00c..07b6f34a437e 100644 --- a/drivers/net/dsa/microchip/ksz_common.c +++ b/drivers/net/dsa/microchip/ksz_common.c @@ -1254,6 +1254,9 @@ static enum dsa_tag_protocol ksz_get_tag_protocol(str= uct dsa_switch *ds, dev->chip_id =3D=3D KSZ9567_CHIP_ID) proto =3D DSA_TAG_PROTO_KSZ9477; =20 + if (is_lan937x(dev)) + proto =3D DSA_TAG_PROTO_LAN937X_VALUE; + return proto; } =20 diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/micro= chip/ksz_common.h index 5f69dc872752..bf4f3f3922a5 100644 --- a/drivers/net/dsa/microchip/ksz_common.h +++ b/drivers/net/dsa/microchip/ksz_common.h @@ -403,6 +403,15 @@ static inline void ksz_regmap_unlock(void *__mtx) mutex_unlock(mtx); } =20 +static inline int is_lan937x(struct ksz_device *dev) +{ + return dev->chip_id =3D=3D LAN9370_CHIP_ID || + dev->chip_id =3D=3D LAN9371_CHIP_ID || + dev->chip_id =3D=3D LAN9372_CHIP_ID || + dev->chip_id =3D=3D LAN9373_CHIP_ID || + dev->chip_id =3D=3D LAN9374_CHIP_ID; +} + /* STP State Defines */ #define PORT_TX_ENABLE BIT(2) #define PORT_RX_ENABLE BIT(1) --=20 2.36.1 From nobody Sun Apr 19 10:41:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DCE5C433EF for ; Fri, 1 Jul 2022 15:07:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231977AbiGAPHD (ORCPT ); Fri, 1 Jul 2022 11:07:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230129AbiGAPG7 (ORCPT ); Fri, 1 Jul 2022 11:06:59 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5380E167C5; Fri, 1 Jul 2022 08:06:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1656688018; x=1688224018; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0ypvoj6TaFnqZOWdsIFH8+PMgqAVRN8fZIhAsaAGuO0=; b=E7wpj8aivK4/tqd8aS43wleqWApq0Oezd07AXl7+67zuLlF7B6eBNcMy xhEDFfznJGrjuZ7lh4oWkeOSMesBBKHXWCKXWxbNyESLKGXGPl7TjDNJR B3DV5yEp2qBja/drsZKghctXRwL1YovGgTuIzdWGspP5TvboHVrye0zyC 9dMIgkTNE6AZBCpkv6OSQ/biipALWamVOxsQcnCBY7LX4t17WXRaYMXXh 5tPqz6EYOGlKm+ApcPNDF1tvO35vjKthYnJDovObXFkYmHO+3wCLYbSm8 mFDD7vIr1bBm3499S0VvkK4Ji7ECHKierXal5VAxO5LbyDjiD8KERwEFY w==; X-IronPort-AV: E=Sophos;i="5.92,237,1650956400"; d="scan'208";a="102670051" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Jul 2022 08:06:56 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 1 Jul 2022 08:06:54 -0700 Received: from CHE-LT-I17769U.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 1 Jul 2022 08:06:35 -0700 From: Arun Ramadoss To: , , , CC: Woojung Huh , , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , "Rob Herring" , Krzysztof Kozlowski , Russell King , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , "Song Liu" , Yonghong Song , John Fastabend , KP Singh Subject: [Patch net-next v15 07/13] net: dsa: microchip: lan937x: add phy read and write support Date: Fri, 1 Jul 2022 20:36:29 +0530 Message-ID: <20220701150629.27247-1-arun.ramadoss@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220701144652.10526-1-arun.ramadoss@microchip.com> References: <20220701144652.10526-1-arun.ramadoss@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch add support for the writing and reading of the phy registers. LAN937x uses the Vphy indirect addressing method for accessing the phys. Signed-off-by: Arun Ramadoss --- drivers/net/dsa/microchip/ksz_common.c | 2 + drivers/net/dsa/microchip/lan937x.h | 2 + drivers/net/dsa/microchip/lan937x_main.c | 116 +++++++++++++++++++++++ drivers/net/dsa/microchip/lan937x_reg.h | 36 +++++++ 4 files changed, 156 insertions(+) diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/micro= chip/ksz_common.c index 07b6f34a437e..67bb4bff4d9b 100644 --- a/drivers/net/dsa/microchip/ksz_common.c +++ b/drivers/net/dsa/microchip/ksz_common.c @@ -207,6 +207,8 @@ static const struct ksz_dev_ops lan937x_dev_ops =3D { .get_port_addr =3D ksz9477_get_port_addr, .cfg_port_member =3D ksz9477_cfg_port_member, .port_setup =3D lan937x_port_setup, + .r_phy =3D lan937x_r_phy, + .w_phy =3D lan937x_w_phy, .r_mib_cnt =3D ksz9477_r_mib_cnt, .r_mib_pkt =3D ksz9477_r_mib_pkt, .r_mib_stat64 =3D ksz_r_mib_stats64, diff --git a/drivers/net/dsa/microchip/lan937x.h b/drivers/net/dsa/microchi= p/lan937x.h index 534f5a7a1129..370203406a05 100644 --- a/drivers/net/dsa/microchip/lan937x.h +++ b/drivers/net/dsa/microchip/lan937x.h @@ -12,4 +12,6 @@ void lan937x_port_setup(struct ksz_device *dev, int port,= bool cpu_port); void lan937x_config_cpu_port(struct dsa_switch *ds); int lan937x_switch_init(struct ksz_device *dev); void lan937x_switch_exit(struct ksz_device *dev); +void lan937x_r_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 *data); +void lan937x_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val); #endif diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/mic= rochip/lan937x_main.c index e167a0c1ff85..5a2e14fe3cf3 100644 --- a/drivers/net/dsa/microchip/lan937x_main.c +++ b/drivers/net/dsa/microchip/lan937x_main.c @@ -28,6 +28,114 @@ static int lan937x_port_cfg(struct ksz_device *dev, int= port, int offset, bits, set ? bits : 0); } =20 +static int lan937x_enable_spi_indirect_access(struct ksz_device *dev) +{ + u16 data16; + int ret; + + /* Enable Phy access through SPI */ + ret =3D lan937x_cfg(dev, REG_GLOBAL_CTRL_0, SW_PHY_REG_BLOCK, false); + if (ret < 0) + return ret; + + ret =3D ksz_read16(dev, REG_VPHY_SPECIAL_CTRL__2, &data16); + if (ret < 0) + return ret; + + /* Allow SPI access */ + data16 |=3D VPHY_SPI_INDIRECT_ENABLE; + + return ksz_write16(dev, REG_VPHY_SPECIAL_CTRL__2, data16); +} + +static int lan937x_vphy_ind_addr_wr(struct ksz_device *dev, int addr, int = reg) +{ + u16 addr_base =3D REG_PORT_T1_PHY_CTRL_BASE; + u16 temp; + + /* get register address based on the logical port */ + temp =3D PORT_CTRL_ADDR(addr, (addr_base + (reg << 2))); + + return ksz_write16(dev, REG_VPHY_IND_ADDR__2, temp); +} + +static int lan937x_internal_phy_write(struct ksz_device *dev, int addr, in= t reg, + u16 val) +{ + unsigned int value; + int ret; + + /* Check for internal phy port */ + if (!dev->info->internal_phy[addr]) + return -EOPNOTSUPP; + + ret =3D lan937x_vphy_ind_addr_wr(dev, addr, reg); + if (ret < 0) + return ret; + + /* Write the data to be written to the VPHY reg */ + ret =3D ksz_write16(dev, REG_VPHY_IND_DATA__2, val); + if (ret < 0) + return ret; + + /* Write the Write En and Busy bit */ + ret =3D ksz_write16(dev, REG_VPHY_IND_CTRL__2, + (VPHY_IND_WRITE | VPHY_IND_BUSY)); + if (ret < 0) + return ret; + + ret =3D regmap_read_poll_timeout(dev->regmap[1], REG_VPHY_IND_CTRL__2, + value, !(value & VPHY_IND_BUSY), 10, + 1000); + if (ret < 0) { + dev_err(dev->dev, "Failed to write phy register\n"); + return ret; + } + + return 0; +} + +static int lan937x_internal_phy_read(struct ksz_device *dev, int addr, int= reg, + u16 *val) +{ + unsigned int value; + int ret; + + /* Check for internal phy port, return 0xffff for non-existent phy */ + if (!dev->info->internal_phy[addr]) + return 0xffff; + + ret =3D lan937x_vphy_ind_addr_wr(dev, addr, reg); + if (ret < 0) + return ret; + + /* Write Read and Busy bit to start the transaction */ + ret =3D ksz_write16(dev, REG_VPHY_IND_CTRL__2, VPHY_IND_BUSY); + if (ret < 0) + return ret; + + ret =3D regmap_read_poll_timeout(dev->regmap[1], REG_VPHY_IND_CTRL__2, + value, !(value & VPHY_IND_BUSY), 10, + 1000); + if (ret < 0) { + dev_err(dev->dev, "Failed to read phy register\n"); + return ret; + } + + /* Read the VPHY register which has the PHY data */ + return ksz_read16(dev, REG_VPHY_IND_DATA__2, val); +} + +void lan937x_r_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 *data) +{ + lan937x_internal_phy_read(dev, addr, reg, data); +} + +void lan937x_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val) +{ + lan937x_internal_phy_write(dev, addr, reg, val); +} + int lan937x_reset_switch(struct ksz_device *dev) { u32 data32; @@ -111,6 +219,14 @@ void lan937x_config_cpu_port(struct dsa_switch *ds) int lan937x_setup(struct dsa_switch *ds) { struct ksz_device *dev =3D ds->priv; + int ret; + + /* enable Indirect Access from SPI to the VPHY registers */ + ret =3D lan937x_enable_spi_indirect_access(dev); + if (ret < 0) { + dev_err(dev->dev, "failed to enable spi indirect access"); + return ret; + } =20 /* The VLAN aware is a global setting. Mixed vlan * filterings are not supported. diff --git a/drivers/net/dsa/microchip/lan937x_reg.h b/drivers/net/dsa/micr= ochip/lan937x_reg.h index 5e27b2bd2d86..7a0fa2595950 100644 --- a/drivers/net/dsa/microchip/lan937x_reg.h +++ b/drivers/net/dsa/microchip/lan937x_reg.h @@ -8,6 +8,12 @@ #define PORT_CTRL_ADDR(port, addr) ((addr) | (((port) + 1) << 12)) =20 /* 0 - Operation */ +#define REG_GLOBAL_CTRL_0 0x0007 + +#define SW_PHY_REG_BLOCK BIT(7) +#define SW_FAST_MODE BIT(3) +#define SW_FAST_MODE_OVERRIDE BIT(2) + #define REG_SW_INT_STATUS__4 0x0010 #define REG_SW_INT_MASK__4 0x0014 =20 @@ -82,6 +88,33 @@ #define ALU_V_USE_FID BIT(30) #define ALU_V_PORT_MAP 0xFF =20 +/* 7 - VPhy */ +#define REG_VPHY_IND_ADDR__2 0x075C +#define REG_VPHY_IND_DATA__2 0x0760 + +#define REG_VPHY_IND_CTRL__2 0x0768 + +#define VPHY_IND_WRITE BIT(1) +#define VPHY_IND_BUSY BIT(0) + +#define REG_VPHY_SPECIAL_CTRL__2 0x077C +#define VPHY_SMI_INDIRECT_ENABLE BIT(15) +#define VPHY_SW_LOOPBACK BIT(14) +#define VPHY_MDIO_INTERNAL_ENABLE BIT(13) +#define VPHY_SPI_INDIRECT_ENABLE BIT(12) +#define VPHY_PORT_MODE_M 0x3 +#define VPHY_PORT_MODE_S 8 +#define VPHY_MODE_RGMII 0 +#define VPHY_MODE_MII_PHY 1 +#define VPHY_MODE_SGMII 2 +#define VPHY_MODE_RMII_PHY 3 +#define VPHY_SW_COLLISION_TEST BIT(7) +#define VPHY_SPEED_DUPLEX_STAT_M 0x7 +#define VPHY_SPEED_DUPLEX_STAT_S 2 +#define VPHY_SPEED_1000 BIT(4) +#define VPHY_SPEED_100 BIT(3) +#define VPHY_FULL_DUPLEX BIT(2) + /* Port Registers */ =20 /* 0 - Operation */ @@ -94,6 +127,9 @@ #define PORT_TAIL_TAG_ENABLE BIT(2) #define PORT_QUEUE_SPLIT_ENABLE 0x3 =20 +/* 1 - Phy */ +#define REG_PORT_T1_PHY_CTRL_BASE 0x0100 + /* 3 - xMII */ #define REG_PORT_XMII_CTRL_0 0x0300 #define PORT_SGMII_SEL BIT(7) --=20 2.36.1 From nobody Sun Apr 19 10:41:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37557CCA481 for ; Fri, 1 Jul 2022 15:07:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233645AbiGAPHl (ORCPT ); Fri, 1 Jul 2022 11:07:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37266 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230000AbiGAPHk (ORCPT ); Fri, 1 Jul 2022 11:07:40 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 156F5167C5; Fri, 1 Jul 2022 08:07:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1656688058; x=1688224058; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MicE8fGK5svKumXmAptj8sQUzXdu2+kFAZVOBmDFZw8=; b=Rw3RqVuzUgzlorcJs4PTlMzY82MdASHi2SkY7ezLRX/DyBDHuxxW4ZEj 344vMtOg7D+65ye49WScK01IHB9vxvS07VZAl7g2d4rCVLe5LFcJtozAg /Of+c3R2t/15odgLNohJ0UxNDSB8tmONm/M0ARHLaBanil0mEPaDLIUkx QSeJXs4aOyh+d6pmCE36nEiAe4qB7w1W4jauOwfj8jTdxKYljJRrXegdb W+XOaya2mSysON20IxAnQSsGs2z9f02gX5mNT9VK8iy533R/D8z1RYp0f wQEZb1s9JgO6UCk9kDmz/9iTGewF97KrxqUr0rFkHlg5ugOVJGk9vdY3h Q==; X-IronPort-AV: E=Sophos;i="5.92,237,1650956400"; d="scan'208";a="166025164" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Jul 2022 08:07:37 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 1 Jul 2022 08:07:36 -0700 Received: from CHE-LT-I17769U.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 1 Jul 2022 08:07:15 -0700 From: Arun Ramadoss To: , , , CC: Woojung Huh , , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , "Rob Herring" , Krzysztof Kozlowski , Russell King , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , "Song Liu" , Yonghong Song , John Fastabend , KP Singh Subject: [Patch net-next v15 08/13] net: dsa: microchip: lan937x: register mdio-bus Date: Fri, 1 Jul 2022 20:37:09 +0530 Message-ID: <20220701150709.27270-1-arun.ramadoss@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220701144652.10526-1-arun.ramadoss@microchip.com> References: <20220701144652.10526-1-arun.ramadoss@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch register mdio-bus for the lan937x series switch. mdio read and write uses the vphy for accessing the phy register. Signed-off-by: Arun Ramadoss --- drivers/net/dsa/microchip/lan937x_main.c | 74 ++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/mic= rochip/lan937x_main.c index 5a2e14fe3cf3..7090947cf52c 100644 --- a/drivers/net/dsa/microchip/lan937x_main.c +++ b/drivers/net/dsa/microchip/lan937x_main.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -136,6 +137,73 @@ void lan937x_w_phy(struct ksz_device *dev, u16 addr, u= 16 reg, u16 val) lan937x_internal_phy_write(dev, addr, reg, val); } =20 +static int lan937x_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) +{ + struct ksz_device *dev =3D bus->priv; + u16 val; + int ret; + + if (regnum & MII_ADDR_C45) + return -EOPNOTSUPP; + + ret =3D lan937x_internal_phy_read(dev, addr, regnum, &val); + if (ret < 0) + return ret; + + return val; +} + +static int lan937x_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, + u16 val) +{ + struct ksz_device *dev =3D bus->priv; + + if (regnum & MII_ADDR_C45) + return -EOPNOTSUPP; + + return lan937x_internal_phy_write(dev, addr, regnum, val); +} + +static int lan937x_mdio_register(struct ksz_device *dev) +{ + struct dsa_switch *ds =3D dev->ds; + struct device_node *mdio_np; + struct mii_bus *bus; + int ret; + + mdio_np =3D of_get_child_by_name(dev->dev->of_node, "mdio"); + if (!mdio_np) { + dev_err(ds->dev, "no MDIO bus node\n"); + return -ENODEV; + } + + bus =3D devm_mdiobus_alloc(ds->dev); + if (!bus) { + of_node_put(mdio_np); + return -ENOMEM; + } + + bus->priv =3D dev; + bus->read =3D lan937x_sw_mdio_read; + bus->write =3D lan937x_sw_mdio_write; + bus->name =3D "lan937x slave smi"; + snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index); + bus->parent =3D ds->dev; + bus->phy_mask =3D ~ds->phys_mii_mask; + + ds->slave_mii_bus =3D bus; + + ret =3D devm_of_mdiobus_register(ds->dev, bus, mdio_np); + if (ret) { + dev_err(ds->dev, "unable to register MDIO bus %s\n", + bus->id); + } + + of_node_put(mdio_np); + + return ret; +} + int lan937x_reset_switch(struct ksz_device *dev) { u32 data32; @@ -228,6 +296,12 @@ int lan937x_setup(struct dsa_switch *ds) return ret; } =20 + ret =3D lan937x_mdio_register(dev); + if (ret < 0) { + dev_err(dev->dev, "failed to register the mdio"); + return ret; + } + /* The VLAN aware is a global setting. Mixed vlan * filterings are not supported. */ --=20 2.36.1 From nobody Sun Apr 19 10:41:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE674C43334 for ; Fri, 1 Jul 2022 15:10:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232824AbiGAPK2 (ORCPT ); Fri, 1 Jul 2022 11:10:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40612 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229895AbiGAPK0 (ORCPT ); Fri, 1 Jul 2022 11:10:26 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 96BE522B1A; Fri, 1 Jul 2022 08:10:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1656688226; x=1688224226; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TKy55q+XdP7GS6YdLTU0y4L8L6D7YkjTxTiaOU22vYk=; b=zAh6fuO7vNcG4oJUbBzWOQaEJVbQr7Fm8EL4t8r8iAcXUjNStYP5HiSL 2F1gY1/Gr+3BEboQIJV9kITPCvhQci/y5OXaSc5v3O63ydXl/EFsGSf2D 6n+8Fct47esF3jhGGdh2E6S+m7VbJe//Jd1mlJr9p3cK1Ji0h6U6HWv0o 5VS1mPPvaM4fr6K6bbwNMbJ6tb5DHzlEYo07BSAihmVrdGTp5kSi/Qf3B ipKotPlWyy1PGfP/WTnwiK+TuXPMYFS144e69UAgNqkdobgW0o+pkyS+v 3DwDOfqSYPcnooYdFZxhfNNZ50yLleIMcZDfJyTZizJbqNOVSf9f6Bcue Q==; X-IronPort-AV: E=Sophos;i="5.92,237,1650956400"; d="scan'208";a="162960539" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Jul 2022 08:10:25 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 1 Jul 2022 08:10:23 -0700 Received: from CHE-LT-I17769U.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 1 Jul 2022 08:10:00 -0700 From: Arun Ramadoss To: , , , CC: Woojung Huh , , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , "Rob Herring" , Krzysztof Kozlowski , Russell King , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , "Song Liu" , Yonghong Song , John Fastabend , KP Singh Subject: [Patch net-next v15 09/13] net: dsa: microchip: lan937x: add MTU and fast_age support Date: Fri, 1 Jul 2022 20:39:54 +0530 Message-ID: <20220701150954.29200-1-arun.ramadoss@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220701144652.10526-1-arun.ramadoss@microchip.com> References: <20220701144652.10526-1-arun.ramadoss@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch add the support for port_max_mtu, port_change_mtu and port_fast_age dsa functionality. Signed-off-by: Arun Ramadoss --- drivers/net/dsa/microchip/ksz_common.c | 2 ++ drivers/net/dsa/microchip/lan937x.h | 1 + drivers/net/dsa/microchip/lan937x_main.c | 28 ++++++++++++++++++++++++ drivers/net/dsa/microchip/lan937x_reg.h | 5 +++++ 4 files changed, 36 insertions(+) diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/micro= chip/ksz_common.c index 67bb4bff4d9b..fb0de48a3f5e 100644 --- a/drivers/net/dsa/microchip/ksz_common.c +++ b/drivers/net/dsa/microchip/ksz_common.c @@ -206,6 +206,7 @@ static const struct ksz_dev_ops lan937x_dev_ops =3D { .setup =3D lan937x_setup, .get_port_addr =3D ksz9477_get_port_addr, .cfg_port_member =3D ksz9477_cfg_port_member, + .flush_dyn_mac_table =3D ksz9477_flush_dyn_mac_table, .port_setup =3D lan937x_port_setup, .r_phy =3D lan937x_r_phy, .w_phy =3D lan937x_w_phy, @@ -224,6 +225,7 @@ static const struct ksz_dev_ops lan937x_dev_ops =3D { .fdb_del =3D ksz9477_fdb_del, .mdb_add =3D ksz9477_mdb_add, .mdb_del =3D ksz9477_mdb_del, + .change_mtu =3D lan937x_change_mtu, .max_mtu =3D ksz9477_max_mtu, .config_cpu_port =3D lan937x_config_cpu_port, .enable_stp_addr =3D ksz9477_enable_stp_addr, diff --git a/drivers/net/dsa/microchip/lan937x.h b/drivers/net/dsa/microchi= p/lan937x.h index 370203406a05..50563874600d 100644 --- a/drivers/net/dsa/microchip/lan937x.h +++ b/drivers/net/dsa/microchip/lan937x.h @@ -14,4 +14,5 @@ int lan937x_switch_init(struct ksz_device *dev); void lan937x_switch_exit(struct ksz_device *dev); void lan937x_r_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 *data); void lan937x_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val); +int lan937x_change_mtu(struct ksz_device *dev, int port, int new_mtu); #endif diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/mic= rochip/lan937x_main.c index 7090947cf52c..5917cc11ba59 100644 --- a/drivers/net/dsa/microchip/lan937x_main.c +++ b/drivers/net/dsa/microchip/lan937x_main.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -284,6 +285,33 @@ void lan937x_config_cpu_port(struct dsa_switch *ds) } } =20 +int lan937x_change_mtu(struct ksz_device *dev, int port, int new_mtu) +{ + struct dsa_switch *ds =3D dev->ds; + int ret; + + new_mtu +=3D VLAN_ETH_HLEN + ETH_FCS_LEN; + + if (dsa_is_cpu_port(ds, port)) + new_mtu +=3D LAN937X_TAG_LEN; + + if (new_mtu >=3D FR_MIN_SIZE) + ret =3D lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0, + PORT_JUMBO_PACKET, true); + else + ret =3D lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0, + PORT_JUMBO_PACKET, false); + if (ret < 0) { + dev_err(ds->dev, "failed to enable jumbo\n"); + return ret; + } + + /* Write the frame size in PORT_MAX_FR_SIZE register */ + ksz_pwrite16(dev, port, PORT_MAX_FR_SIZE, new_mtu); + + return 0; +} + int lan937x_setup(struct dsa_switch *ds) { struct ksz_device *dev =3D ds->priv; diff --git a/drivers/net/dsa/microchip/lan937x_reg.h b/drivers/net/dsa/micr= ochip/lan937x_reg.h index 7a0fa2595950..19f3aa344228 100644 --- a/drivers/net/dsa/microchip/lan937x_reg.h +++ b/drivers/net/dsa/microchip/lan937x_reg.h @@ -149,6 +149,9 @@ #define PORT_BACK_PRESSURE BIT(3) #define PORT_PASS_ALL BIT(0) =20 +#define PORT_MAX_FR_SIZE 0x404 +#define FR_MIN_SIZE 1522 + /* 8 - Classification and Policing */ #define REG_PORT_MRI_PRIO_CTRL 0x0801 #define PORT_HIGHEST_PRIO BIT(7) @@ -161,4 +164,6 @@ =20 #define P_PRIO_CTRL REG_PORT_MRI_PRIO_CTRL =20 +#define LAN937X_TAG_LEN 2 + #endif --=20 2.36.1 From nobody Sun Apr 19 10:41:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76A46C43334 for ; Fri, 1 Jul 2022 15:11:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231262AbiGAPLV (ORCPT ); Fri, 1 Jul 2022 11:11:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41350 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230250AbiGAPLS (ORCPT ); Fri, 1 Jul 2022 11:11:18 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 460D93DA7E; Fri, 1 Jul 2022 08:11:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1656688275; x=1688224275; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/4zAF9ttoJS2TjV1ny7XdJQp08J3H2eI9+Cy1JXdrw0=; b=kmm6TYl5p/A9WqXbCFJXl9Ev8aTzQNN4iFywSPjW/9zAlbRAVI5PgTIV bJ/UgIrwl/3ptlQc0SjFlUSDMc62b3E/3yVMm8RHmG3JAEsLkaYAiiuDS AJpC20pg+3fLXyzmQDw7vWryd8OhRa8EOc5/pdu6yxCFnXAzW20a33e5N UxutlOQJrosCxaxy2bQl7dAJFjHWzpgfrbhYGLr/ZlvvBZx1RvcHlE0tB md91yGUQuUmqmi6VOH1F44OjR4VyN+QHydJ2WyXsVUUHmsqcgwaNfNsK0 nb7yzIr3obzBr0Zj9CDkqL8Kc8rS/6qNehFSoibxD+jOVROi89foMChJY g==; X-IronPort-AV: E=Sophos;i="5.92,237,1650956400"; d="scan'208";a="102671212" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Jul 2022 08:11:14 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 1 Jul 2022 08:11:12 -0700 Received: from CHE-LT-I17769U.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 1 Jul 2022 08:10:40 -0700 From: Arun Ramadoss To: , , , CC: Woojung Huh , , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , "Rob Herring" , Krzysztof Kozlowski , Russell King , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , "Song Liu" , Yonghong Song , John Fastabend , KP Singh Subject: [Patch net-next v15 10/13] net: dsa: microchip: lan937x: add phylink_get_caps support Date: Fri, 1 Jul 2022 20:40:34 +0530 Message-ID: <20220701151034.29285-1-arun.ramadoss@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220701144652.10526-1-arun.ramadoss@microchip.com> References: <20220701144652.10526-1-arun.ramadoss@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The internal phy of the LAN937x are capable of 100Mbps Full duplex. The xMII port of switch is capable of 10Mbps Full & Half Duplex, 100Mbps Full & Half Duplex and 1000Mbps Half duplex. xMII port also supports Tx and Rx Flow control. Signed-off-by: Arun Ramadoss --- drivers/net/dsa/microchip/ksz_common.c | 1 + drivers/net/dsa/microchip/lan937x.h | 2 ++ drivers/net/dsa/microchip/lan937x_main.c | 12 ++++++++++++ 3 files changed, 15 insertions(+) diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/micro= chip/ksz_common.c index fb0de48a3f5e..ca7ca327285d 100644 --- a/drivers/net/dsa/microchip/ksz_common.c +++ b/drivers/net/dsa/microchip/ksz_common.c @@ -220,6 +220,7 @@ static const struct ksz_dev_ops lan937x_dev_ops =3D { .vlan_del =3D ksz9477_port_vlan_del, .mirror_add =3D ksz9477_port_mirror_add, .mirror_del =3D ksz9477_port_mirror_del, + .get_caps =3D lan937x_phylink_get_caps, .fdb_dump =3D ksz9477_fdb_dump, .fdb_add =3D ksz9477_fdb_add, .fdb_del =3D ksz9477_fdb_del, diff --git a/drivers/net/dsa/microchip/lan937x.h b/drivers/net/dsa/microchi= p/lan937x.h index 50563874600d..d4207e97a130 100644 --- a/drivers/net/dsa/microchip/lan937x.h +++ b/drivers/net/dsa/microchip/lan937x.h @@ -15,4 +15,6 @@ void lan937x_switch_exit(struct ksz_device *dev); void lan937x_r_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 *data); void lan937x_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val); int lan937x_change_mtu(struct ksz_device *dev, int port, int new_mtu); +void lan937x_phylink_get_caps(struct ksz_device *dev, int port, + struct phylink_config *config); #endif diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/mic= rochip/lan937x_main.c index 5917cc11ba59..8cb46caf5340 100644 --- a/drivers/net/dsa/microchip/lan937x_main.c +++ b/drivers/net/dsa/microchip/lan937x_main.c @@ -312,6 +312,18 @@ int lan937x_change_mtu(struct ksz_device *dev, int por= t, int new_mtu) return 0; } =20 +void lan937x_phylink_get_caps(struct ksz_device *dev, int port, + struct phylink_config *config) +{ + config->mac_capabilities =3D MAC_100FD; + + if (dev->info->supports_rgmii[port]) { + /* MII/RMII/RGMII ports */ + config->mac_capabilities |=3D MAC_ASYM_PAUSE | MAC_SYM_PAUSE | + MAC_100HD | MAC_10 | MAC_1000FD; + } +} + int lan937x_setup(struct dsa_switch *ds) { struct ksz_device *dev =3D ds->priv; --=20 2.36.1 From nobody Sun Apr 19 10:41:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2018CCA481 for ; Fri, 1 Jul 2022 15:11:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231197AbiGAPL4 (ORCPT ); Fri, 1 Jul 2022 11:11:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41900 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230296AbiGAPLy (ORCPT ); Fri, 1 Jul 2022 11:11:54 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B6483E5DE; Fri, 1 Jul 2022 08:11:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1656688312; x=1688224312; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=25KXfL6K7Q2FLSNm4lppBpISXDmLVbfA5Qpv+O1txKg=; b=VSxe//DsB4+jEK5sXoHwSplkA4ai27XhAWcdrb+ABM61cOY728gJCVP9 lJlZiNQ4HM4LBhoz0WsJcPFbNyKWbTbFkuS+euFmMKWNCxBARlpPpi1Dn mFy1BYiVym0jtZJa/hHDWQTeByVqL1wAZ6XHMDJpKsE37xgeJP217RNZE JHdZ2mm2Oa9ITN+mR8St5pzCi+eOQPd+LXi1kIXcr9UFfteUqSmeH1Grt wmQD4m1AH4UGUWShspkBDVfDCmNcPsG/lSj7cRIVWd67SNrqvYAaSMmcK VHbqbF/MUzpsrBD3irGG0vOPZ6lz9f2LCBwknRsm8sgKHxP3g3XDWkU2B A==; X-IronPort-AV: E=Sophos;i="5.92,237,1650956400"; d="scan'208";a="102671487" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Jul 2022 08:11:51 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 1 Jul 2022 08:11:51 -0700 Received: from CHE-LT-I17769U.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 1 Jul 2022 08:11:30 -0700 From: Arun Ramadoss To: , , , CC: Woojung Huh , , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , "Rob Herring" , Krzysztof Kozlowski , Russell King , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , "Song Liu" , Yonghong Song , John Fastabend , KP Singh Subject: [Patch net-next v15 11/13] net: dsa: microchip: lan937x: add phylink_mac_link_up support Date: Fri, 1 Jul 2022 20:41:24 +0530 Message-ID: <20220701151124.29485-1-arun.ramadoss@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220701144652.10526-1-arun.ramadoss@microchip.com> References: <20220701144652.10526-1-arun.ramadoss@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch add support for phylink_mac_link_up. It configures the mac for the speed, flow control and duplex mode. Signed-off-by: Arun Ramadoss --- drivers/net/dsa/microchip/ksz_common.c | 16 +++++++++ drivers/net/dsa/microchip/ksz_common.h | 5 +++ drivers/net/dsa/microchip/lan937x.h | 4 +++ drivers/net/dsa/microchip/lan937x_main.c | 46 ++++++++++++++++++++++++ drivers/net/dsa/microchip/lan937x_reg.h | 11 ++++++ 5 files changed, 82 insertions(+) diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/micro= chip/ksz_common.c index ca7ca327285d..9972b2fabf27 100644 --- a/drivers/net/dsa/microchip/ksz_common.c +++ b/drivers/net/dsa/microchip/ksz_common.c @@ -221,6 +221,7 @@ static const struct ksz_dev_ops lan937x_dev_ops =3D { .mirror_add =3D ksz9477_port_mirror_add, .mirror_del =3D ksz9477_port_mirror_del, .get_caps =3D lan937x_phylink_get_caps, + .phylink_mac_link_up =3D lan937x_phylink_mac_link_up, .fdb_dump =3D ksz9477_fdb_dump, .fdb_add =3D ksz9477_fdb_add, .fdb_del =3D ksz9477_fdb_del, @@ -1340,6 +1341,20 @@ static int ksz_max_mtu(struct dsa_switch *ds, int po= rt) return dev->dev_ops->max_mtu(dev, port); } =20 +static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port, + unsigned int mode, + phy_interface_t interface, + struct phy_device *phydev, int speed, + int duplex, bool tx_pause, bool rx_pause) +{ + struct ksz_device *dev =3D ds->priv; + + if (dev->dev_ops->phylink_mac_link_up) + dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface, + phydev, speed, duplex, + tx_pause, rx_pause); +} + static int ksz_switch_detect(struct ksz_device *dev) { u8 id1, id2; @@ -1413,6 +1428,7 @@ static const struct dsa_switch_ops ksz_switch_ops =3D= { .phy_read =3D ksz_phy_read16, .phy_write =3D ksz_phy_write16, .phylink_get_caps =3D ksz_phylink_get_caps, + .phylink_mac_link_up =3D ksz_phylink_mac_link_up, .phylink_mac_link_down =3D ksz_mac_link_down, .port_enable =3D ksz_enable_port, .get_strings =3D ksz_get_strings, diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/micro= chip/ksz_common.h index bf4f3f3922a5..f449feab5499 100644 --- a/drivers/net/dsa/microchip/ksz_common.h +++ b/drivers/net/dsa/microchip/ksz_common.h @@ -271,6 +271,11 @@ struct ksz_dev_ops { int (*max_mtu)(struct ksz_device *dev, int port); void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); void (*port_init_cnt)(struct ksz_device *dev, int port); + void (*phylink_mac_link_up)(struct ksz_device *dev, int port, + unsigned int mode, + phy_interface_t interface, + struct phy_device *phydev, int speed, + int duplex, bool tx_pause, bool rx_pause); void (*config_cpu_port)(struct dsa_switch *ds); int (*enable_stp_addr)(struct ksz_device *dev); int (*reset)(struct ksz_device *dev); diff --git a/drivers/net/dsa/microchip/lan937x.h b/drivers/net/dsa/microchi= p/lan937x.h index d4207e97a130..145770aec963 100644 --- a/drivers/net/dsa/microchip/lan937x.h +++ b/drivers/net/dsa/microchip/lan937x.h @@ -17,4 +17,8 @@ void lan937x_w_phy(struct ksz_device *dev, u16 addr, u16 = reg, u16 val); int lan937x_change_mtu(struct ksz_device *dev, int port, int new_mtu); void lan937x_phylink_get_caps(struct ksz_device *dev, int port, struct phylink_config *config); +void lan937x_phylink_mac_link_up(struct ksz_device *dev, int port, + unsigned int mode, phy_interface_t interface, + struct phy_device *phydev, int speed, + int duplex, bool tx_pause, bool rx_pause); #endif diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/mic= rochip/lan937x_main.c index 8cb46caf5340..2f480bf4649d 100644 --- a/drivers/net/dsa/microchip/lan937x_main.c +++ b/drivers/net/dsa/microchip/lan937x_main.c @@ -312,6 +312,39 @@ int lan937x_change_mtu(struct ksz_device *dev, int por= t, int new_mtu) return 0; } =20 +static void lan937x_config_interface(struct ksz_device *dev, int port, + int speed, int duplex, + bool tx_pause, bool rx_pause) +{ + u8 xmii_ctrl0, xmii_ctrl1; + + ksz_pread8(dev, port, REG_PORT_XMII_CTRL_0, &xmii_ctrl0); + ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &xmii_ctrl1); + + xmii_ctrl0 &=3D ~(PORT_MII_100MBIT | PORT_MII_FULL_DUPLEX | + PORT_MII_TX_FLOW_CTRL | PORT_MII_RX_FLOW_CTRL); + + if (speed =3D=3D SPEED_1000) + xmii_ctrl1 &=3D ~PORT_MII_NOT_1GBIT; + else + xmii_ctrl1 |=3D PORT_MII_NOT_1GBIT; + + if (speed =3D=3D SPEED_100) + xmii_ctrl0 |=3D PORT_MII_100MBIT; + + if (duplex) + xmii_ctrl0 |=3D PORT_MII_FULL_DUPLEX; + + if (tx_pause) + xmii_ctrl0 |=3D PORT_MII_TX_FLOW_CTRL; + + if (rx_pause) + xmii_ctrl0 |=3D PORT_MII_RX_FLOW_CTRL; + + ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_0, xmii_ctrl0); + ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, xmii_ctrl1); +} + void lan937x_phylink_get_caps(struct ksz_device *dev, int port, struct phylink_config *config) { @@ -324,6 +357,19 @@ void lan937x_phylink_get_caps(struct ksz_device *dev, = int port, } } =20 +void lan937x_phylink_mac_link_up(struct ksz_device *dev, int port, + unsigned int mode, phy_interface_t interface, + struct phy_device *phydev, int speed, + int duplex, bool tx_pause, bool rx_pause) +{ + /* Internal PHYs */ + if (dev->info->internal_phy[port]) + return; + + lan937x_config_interface(dev, port, speed, duplex, + tx_pause, rx_pause); +} + int lan937x_setup(struct dsa_switch *ds) { struct ksz_device *dev =3D ds->priv; diff --git a/drivers/net/dsa/microchip/lan937x_reg.h b/drivers/net/dsa/micr= ochip/lan937x_reg.h index 19f3aa344228..c187d0a3e7fa 100644 --- a/drivers/net/dsa/microchip/lan937x_reg.h +++ b/drivers/net/dsa/microchip/lan937x_reg.h @@ -139,6 +139,17 @@ #define PORT_MII_RX_FLOW_CTRL BIT(3) #define PORT_GRXC_ENABLE BIT(0) =20 +#define REG_PORT_XMII_CTRL_1 0x0301 +#define PORT_MII_NOT_1GBIT BIT(6) +#define PORT_MII_SEL_EDGE BIT(5) +#define PORT_RGMII_ID_IG_ENABLE BIT(4) +#define PORT_RGMII_ID_EG_ENABLE BIT(3) +#define PORT_MII_MAC_MODE BIT(2) +#define PORT_MII_SEL_M 0x3 +#define PORT_RGMII_SEL 0x0 +#define PORT_RMII_SEL 0x1 +#define PORT_MII_SEL 0x2 + /* 4 - MAC */ #define REG_PORT_MAC_CTRL_0 0x0400 #define PORT_CHECK_LENGTH BIT(2) --=20 2.36.1 From nobody Sun Apr 19 10:41:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2C54C43334 for ; Fri, 1 Jul 2022 15:12:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230231AbiGAPMt (ORCPT ); Fri, 1 Jul 2022 11:12:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233231AbiGAPMi (ORCPT ); Fri, 1 Jul 2022 11:12:38 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 926563E5C1; Fri, 1 Jul 2022 08:12:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1656688356; x=1688224356; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Q77Rpqg581RO9Mbbzxx40Z6hkVP0G/fVs0hL1O6DQQM=; b=MUT+U4eugTruQT3ch/tZF7XAY2mxw3zyfhoqM+HQqu61CpHL90dmZWZg 02gWirWvCqoM6ppzaCombGkAF/CFbH6vufR9m/VqtShysCy6iPMwHQDpB MneFEXi5KRu4BiewUYyZ9Sc7InphMPWIdQ4dge0zPcSyfN18P1Ifx3d8W H9fEO9hmVOS+cmriz0rcj3dtGjjHG8Aj7ba9F2OYWib1DkTgb0biueMBa pNuEIx09110I/2zys80Ug2mB+yGlqiQxsNgrt6eKRvJOciHLfzBb98Qj1 NdSvkDIlgjtn4Su1as7mjBDFCVWxw3UrI5QMI58a+PO8+EPfW+lBUOnPC w==; X-IronPort-AV: E=Sophos;i="5.92,237,1650956400"; d="scan'208";a="102671893" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Jul 2022 08:12:35 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 1 Jul 2022 08:12:35 -0700 Received: from CHE-LT-I17769U.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 1 Jul 2022 08:12:09 -0700 From: Arun Ramadoss To: , , , CC: Woojung Huh , , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , "Rob Herring" , Krzysztof Kozlowski , Russell King , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , "Song Liu" , Yonghong Song , John Fastabend , KP Singh Subject: [Patch net-next v15 12/13] net: dsa: microchip: lan937x: add phylink_mac_config support Date: Fri, 1 Jul 2022 20:42:03 +0530 Message-ID: <20220701151203.29512-1-arun.ramadoss@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220701144652.10526-1-arun.ramadoss@microchip.com> References: <20220701144652.10526-1-arun.ramadoss@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch add support for phylink_mac_config dsa hook. It configures the mac for MII/RMII modes. The RGMII mode will be added in the future patches. Signed-off-by: Arun Ramadoss --- drivers/net/dsa/microchip/ksz_common.c | 12 +++++ drivers/net/dsa/microchip/ksz_common.h | 3 ++ drivers/net/dsa/microchip/lan937x.h | 3 ++ drivers/net/dsa/microchip/lan937x_main.c | 58 +++++++++++++++++++++++- 4 files changed, 74 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/micro= chip/ksz_common.c index 9972b2fabf27..28d7cb2ce98f 100644 --- a/drivers/net/dsa/microchip/ksz_common.c +++ b/drivers/net/dsa/microchip/ksz_common.c @@ -221,6 +221,7 @@ static const struct ksz_dev_ops lan937x_dev_ops =3D { .mirror_add =3D ksz9477_port_mirror_add, .mirror_del =3D ksz9477_port_mirror_del, .get_caps =3D lan937x_phylink_get_caps, + .phylink_mac_config =3D lan937x_phylink_mac_config, .phylink_mac_link_up =3D lan937x_phylink_mac_link_up, .fdb_dump =3D ksz9477_fdb_dump, .fdb_add =3D ksz9477_fdb_add, @@ -1341,6 +1342,16 @@ static int ksz_max_mtu(struct dsa_switch *ds, int po= rt) return dev->dev_ops->max_mtu(dev, port); } =20 +static void ksz_phylink_mac_config(struct dsa_switch *ds, int port, + unsigned int mode, + const struct phylink_link_state *state) +{ + struct ksz_device *dev =3D ds->priv; + + if (dev->dev_ops->phylink_mac_config) + dev->dev_ops->phylink_mac_config(dev, port, mode, state); +} + static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface, @@ -1428,6 +1439,7 @@ static const struct dsa_switch_ops ksz_switch_ops =3D= { .phy_read =3D ksz_phy_read16, .phy_write =3D ksz_phy_write16, .phylink_get_caps =3D ksz_phylink_get_caps, + .phylink_mac_config =3D ksz_phylink_mac_config, .phylink_mac_link_up =3D ksz_phylink_mac_link_up, .phylink_mac_link_down =3D ksz_mac_link_down, .port_enable =3D ksz_enable_port, diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/micro= chip/ksz_common.h index f449feab5499..d5dddb7ec045 100644 --- a/drivers/net/dsa/microchip/ksz_common.h +++ b/drivers/net/dsa/microchip/ksz_common.h @@ -271,6 +271,9 @@ struct ksz_dev_ops { int (*max_mtu)(struct ksz_device *dev, int port); void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); void (*port_init_cnt)(struct ksz_device *dev, int port); + void (*phylink_mac_config)(struct ksz_device *dev, int port, + unsigned int mode, + const struct phylink_link_state *state); void (*phylink_mac_link_up)(struct ksz_device *dev, int port, unsigned int mode, phy_interface_t interface, diff --git a/drivers/net/dsa/microchip/lan937x.h b/drivers/net/dsa/microchi= p/lan937x.h index 145770aec963..72ba9cb2fbc6 100644 --- a/drivers/net/dsa/microchip/lan937x.h +++ b/drivers/net/dsa/microchip/lan937x.h @@ -21,4 +21,7 @@ void lan937x_phylink_mac_link_up(struct ksz_device *dev, = int port, unsigned int mode, phy_interface_t interface, struct phy_device *phydev, int speed, int duplex, bool tx_pause, bool rx_pause); +void lan937x_phylink_mac_config(struct ksz_device *dev, int port, + unsigned int mode, + const struct phylink_link_state *state); #endif diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/mic= rochip/lan937x_main.c index 2f480bf4649d..c29d175ca6f7 100644 --- a/drivers/net/dsa/microchip/lan937x_main.c +++ b/drivers/net/dsa/microchip/lan937x_main.c @@ -312,6 +312,44 @@ int lan937x_change_mtu(struct ksz_device *dev, int por= t, int new_mtu) return 0; } =20 +static void lan937x_config_gbit(struct ksz_device *dev, bool gbit, u8 *dat= a) +{ + if (gbit) + *data &=3D ~PORT_MII_NOT_1GBIT; + else + *data |=3D PORT_MII_NOT_1GBIT; +} + +static void lan937x_mac_config(struct ksz_device *dev, int port, + phy_interface_t interface) +{ + u8 data8; + + ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8); + + /* clear MII selection & set it based on interface later */ + data8 &=3D ~PORT_MII_SEL_M; + + /* configure MAC based on interface */ + switch (interface) { + case PHY_INTERFACE_MODE_MII: + lan937x_config_gbit(dev, false, &data8); + data8 |=3D PORT_MII_SEL; + break; + case PHY_INTERFACE_MODE_RMII: + lan937x_config_gbit(dev, false, &data8); + data8 |=3D PORT_RMII_SEL; + break; + default: + dev_err(dev->dev, "Unsupported interface '%s' for port %d\n", + phy_modes(interface), port); + return; + } + + /* Write the updated value */ + ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8); +} + static void lan937x_config_interface(struct ksz_device *dev, int port, int speed, int duplex, bool tx_pause, bool rx_pause) @@ -325,9 +363,9 @@ static void lan937x_config_interface(struct ksz_device = *dev, int port, PORT_MII_TX_FLOW_CTRL | PORT_MII_RX_FLOW_CTRL); =20 if (speed =3D=3D SPEED_1000) - xmii_ctrl1 &=3D ~PORT_MII_NOT_1GBIT; + lan937x_config_gbit(dev, true, &xmii_ctrl1); else - xmii_ctrl1 |=3D PORT_MII_NOT_1GBIT; + lan937x_config_gbit(dev, false, &xmii_ctrl1); =20 if (speed =3D=3D SPEED_100) xmii_ctrl0 |=3D PORT_MII_100MBIT; @@ -370,6 +408,22 @@ void lan937x_phylink_mac_link_up(struct ksz_device *de= v, int port, tx_pause, rx_pause); } =20 +void lan937x_phylink_mac_config(struct ksz_device *dev, int port, + unsigned int mode, + const struct phylink_link_state *state) +{ + /* Internal PHYs */ + if (dev->info->internal_phy[port]) + return; + + if (phylink_autoneg_inband(mode)) { + dev_err(dev->dev, "In-band AN not supported!\n"); + return; + } + + lan937x_mac_config(dev, port, state->interface); +} + int lan937x_setup(struct dsa_switch *ds) { struct ksz_device *dev =3D ds->priv; --=20 2.36.1 From nobody Sun Apr 19 10:41:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 668F6C43334 for ; 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X-IronPort-AV: E=Sophos;i="5.92,237,1650956400"; d="scan'208";a="102673275" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Jul 2022 08:16:26 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 1 Jul 2022 08:16:25 -0700 Received: from CHE-LT-I17769U.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 1 Jul 2022 08:16:06 -0700 From: Arun Ramadoss To: , , , CC: Woojung Huh , , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , "Rob Herring" , Krzysztof Kozlowski , Russell King , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , "Song Liu" , Yonghong Song , John Fastabend , KP Singh Subject: [Patch net-next v15 13/13] net: dsa: microchip: add LAN937x in the ksz spi probe Date: Fri, 1 Jul 2022 20:46:00 +0530 Message-ID: <20220701151600.31805-1-arun.ramadoss@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220701144652.10526-1-arun.ramadoss@microchip.com> References: <20220701144652.10526-1-arun.ramadoss@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch add the LAN937x part support in the existing ksz_spi_probe. Signed-off-by: Arun Ramadoss --- drivers/net/dsa/microchip/ksz_spi.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/net/dsa/microchip/ksz_spi.c b/drivers/net/dsa/microchi= p/ksz_spi.c index 69fabb190f26..4844830dca72 100644 --- a/drivers/net/dsa/microchip/ksz_spi.c +++ b/drivers/net/dsa/microchip/ksz_spi.c @@ -166,6 +166,26 @@ static const struct of_device_id ksz_dt_ids[] =3D { .compatible =3D "microchip,ksz9567", .data =3D &ksz_switch_chips[KSZ9567] }, + { + .compatible =3D "microchip,lan9370", + .data =3D &ksz_switch_chips[LAN9370] + }, + { + .compatible =3D "microchip,lan9371", + .data =3D &ksz_switch_chips[LAN9371] + }, + { + .compatible =3D "microchip,lan9372", + .data =3D &ksz_switch_chips[LAN9372] + }, + { + .compatible =3D "microchip,lan9373", + .data =3D &ksz_switch_chips[LAN9373] + }, + { + .compatible =3D "microchip,lan9374", + .data =3D &ksz_switch_chips[LAN9374] + }, {}, }; MODULE_DEVICE_TABLE(of, ksz_dt_ids); @@ -182,6 +202,11 @@ static const struct spi_device_id ksz_spi_ids[] =3D { { "ksz9563" }, { "ksz8563" }, { "ksz9567" }, + { "lan9370" }, + { "lan9371" }, + { "lan9372" }, + { "lan9373" }, + { "lan9374" }, { }, }; MODULE_DEVICE_TABLE(spi, ksz_spi_ids); @@ -206,6 +231,7 @@ MODULE_ALIAS("spi:ksz9893"); MODULE_ALIAS("spi:ksz9563"); MODULE_ALIAS("spi:ksz8563"); MODULE_ALIAS("spi:ksz9567"); +MODULE_ALIAS("spi:lan937x"); MODULE_AUTHOR("Tristram Ha "); MODULE_DESCRIPTION("Microchip ksz Series Switch SPI Driver"); MODULE_LICENSE("GPL"); --=20 2.36.1