From nobody Sat Sep 21 21:42:15 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3EE28C43334 for ; Fri, 1 Jul 2022 09:06:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234352AbiGAJGL (ORCPT ); Fri, 1 Jul 2022 05:06:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231735AbiGAJGF (ORCPT ); Fri, 1 Jul 2022 05:06:05 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F19E2250E; Fri, 1 Jul 2022 02:05:58 -0700 (PDT) X-UUID: ffbef337aaff477b9bb5000c5536adca-20220701 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.7,REQID:9d438f42-4527-4ab1-8396-81c9ecc5b6f9,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:-5 X-CID-META: VersionHash:87442a2,CLOUDID:5de459d6-5d6d-4eaf-a635-828a3ee48b7c,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: ffbef337aaff477b9bb5000c5536adca-20220701 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1844787514; Fri, 01 Jul 2022 17:05:49 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Fri, 1 Jul 2022 17:05:48 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Fri, 1 Jul 2022 17:05:48 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter CC: , , , , , Chen-Yu Tsai , Allen-KH Cheng Subject: [PATCH v2 1/6] drm/mediatek: Remove mt8192 display rdma compatible Date: Fri, 1 Jul 2022 17:05:42 +0800 Message-ID: <20220701090547.21429-2-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220701090547.21429-1-allen-kh.cheng@mediatek.com> References: <20220701090547.21429-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The compatible =E2=80=9Cmediatek,mt8192-disp-rdma=E2=80=9D is being used fo= r reading the data into DMA for back-end panel driver in mt8192 but there is no difference between mt8183 and mt8192 in rdma driver. Remove compatible =E2=80=9Cmediatek,mt8192-disp-rdma=E2=80=9D from the driv= er and should use =E2=80=9Cmediatek,mt8183-disp-rdma=E2=80=9D as fallback in 8192 = DTS according to the mediatek,rdma.yaml. Signed-off-by: Allen-KH Cheng Reviewed-by: Chen-Yu Tsai --- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ------ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 -- 2 files changed, 8 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/med= iatek/mtk_disp_rdma.c index 1be4caf9ff96..91add033e7b3 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -368,10 +368,6 @@ static const struct mtk_disp_rdma_data mt8183_rdma_dri= ver_data =3D { .fifo_size =3D 5 * SZ_1K, }; =20 -static const struct mtk_disp_rdma_data mt8192_rdma_driver_data =3D { - .fifo_size =3D 5 * SZ_1K, -}; - static const struct of_device_id mtk_disp_rdma_driver_dt_match[] =3D { { .compatible =3D "mediatek,mt2701-disp-rdma", .data =3D &mt2701_rdma_driver_data}, @@ -379,8 +375,6 @@ static const struct of_device_id mtk_disp_rdma_driver_d= t_match[] =3D { .data =3D &mt8173_rdma_driver_data}, { .compatible =3D "mediatek,mt8183-disp-rdma", .data =3D &mt8183_rdma_driver_data}, - { .compatible =3D "mediatek,mt8192-disp-rdma", - .data =3D &mt8192_rdma_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index 6abe6bcacbdc..06bd4483744b 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -522,8 +522,6 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = =3D { .data =3D (void *)MTK_DISP_RDMA }, { .compatible =3D "mediatek,mt8183-disp-rdma", .data =3D (void *)MTK_DISP_RDMA }, - { .compatible =3D "mediatek,mt8192-disp-rdma", - .data =3D (void *)MTK_DISP_RDMA }, { .compatible =3D "mediatek,mt8173-disp-ufoe", .data =3D (void *)MTK_DISP_UFOE }, { .compatible =3D "mediatek,mt8173-disp-wdma", --=20 2.18.0 From nobody Sat Sep 21 21:42:15 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8637BC433EF for ; Fri, 1 Jul 2022 09:06:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233953AbiGAJGH (ORCPT ); Fri, 1 Jul 2022 05:06:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229808AbiGAJGF (ORCPT ); Fri, 1 Jul 2022 05:06:05 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F1F7D255A0; Fri, 1 Jul 2022 02:05:59 -0700 (PDT) X-UUID: 95853004a32d423b8ef73b17f64294c2-20220701 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.7,REQID:c18d4c75-e3f7-44aa-9cd0-6bbed8f155a1,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:-5 X-CID-META: VersionHash:87442a2,CLOUDID:20504a86-57f0-47ca-ba27-fe8c57fbf305,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: 95853004a32d423b8ef73b17f64294c2-20220701 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1990409529; Fri, 01 Jul 2022 17:05:50 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Fri, 1 Jul 2022 17:05:49 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Fri, 1 Jul 2022 17:05:49 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter CC: , , , , , Chen-Yu Tsai , Allen-KH Cheng Subject: [PATCH v2 2/6] arm64: dts: mt8192: Add pwm node Date: Fri, 1 Jul 2022 17:05:43 +0800 Message-ID: <20220701090547.21429-3-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220701090547.21429-1-allen-kh.cheng@mediatek.com> References: <20220701090547.21429-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add pwm node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: N=C3=ADcolas F. R. A. Prado --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index cbae5a5ee4a0..731bdc665b94 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -599,6 +599,17 @@ status =3D "disabled"; }; =20 + pwm0: pwm@1100e000 { + compatible =3D "mediatek,mt8183-disp-pwm"; + reg =3D <0 0x1100e000 0 0x1000>; + interrupts =3D ; + #pwm-cells =3D <2>; + clocks =3D <&topckgen CLK_TOP_DISP_PWM_SEL>, + <&infracfg CLK_INFRA_DISP_PWM>; + clock-names =3D "main", "mm"; + status =3D "disabled"; + }; + spi1: spi@11010000 { compatible =3D "mediatek,mt8192-spi", "mediatek,mt6765-spi"; --=20 2.18.0 From nobody Sat Sep 21 21:42:15 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BDD6C43334 for ; Fri, 1 Jul 2022 09:06:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234848AbiGAJGP (ORCPT ); Fri, 1 Jul 2022 05:06:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49580 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232726AbiGAJGG (ORCPT ); Fri, 1 Jul 2022 05:06:06 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B99882C12E; Fri, 1 Jul 2022 02:06:00 -0700 (PDT) X-UUID: 2ba02a5f7df1401b94ba97f3bc69afbf-20220701 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.7,REQID:571f3399-1fa1-490c-9105-15be5857b366,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:87442a2,CLOUDID:80e459d6-5d6d-4eaf-a635-828a3ee48b7c,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: 2ba02a5f7df1401b94ba97f3bc69afbf-20220701 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1659057036; Fri, 01 Jul 2022 17:05:51 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Fri, 1 Jul 2022 17:05:50 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Fri, 1 Jul 2022 17:05:50 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter CC: , , , , , Chen-Yu Tsai , Allen-KH Cheng Subject: [PATCH v2 3/6] arm64: dts: mt8192: Add mipi_tx node Date: Fri, 1 Jul 2022 17:05:44 +0800 Message-ID: <20220701090547.21429-4-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220701090547.21429-1-allen-kh.cheng@mediatek.com> References: <20220701090547.21429-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add mipi_tx node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: N=C3=ADcolas F. R. A. Prado --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 731bdc665b94..a789b7c9b2af 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1095,6 +1095,16 @@ }; }; =20 + mipi_tx0: dsi-phy@11e50000 { + compatible =3D "mediatek,mt8183-mipi-tx"; + reg =3D <0 0x11e50000 0 0x1000>; + clocks =3D <&apmixedsys CLK_APMIXED_MIPID26M>; + #clock-cells =3D <0>; + #phy-cells =3D <0>; + clock-output-names =3D "mipi_tx0_pll"; + status =3D "disabled"; + }; + i2c0: i2c@11f00000 { compatible =3D "mediatek,mt8192-i2c"; reg =3D <0 0x11f00000 0 0x1000>, --=20 2.18.0 From nobody Sat Sep 21 21:42:15 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 710D4C43334 for ; Fri, 1 Jul 2022 09:06:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235082AbiGAJGT (ORCPT ); Fri, 1 Jul 2022 05:06:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49582 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231426AbiGAJGG (ORCPT ); Fri, 1 Jul 2022 05:06:06 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BC5652CC8E; Fri, 1 Jul 2022 02:06:01 -0700 (PDT) X-UUID: dc1c6092d7884f5caef8ab830bfc1336-20220701 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.7,REQID:080bf44a-1189-452c-871e-ec276f7544f5,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:87442a2,CLOUDID:81e459d6-5d6d-4eaf-a635-828a3ee48b7c,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: dc1c6092d7884f5caef8ab830bfc1336-20220701 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 90650483; Fri, 01 Jul 2022 17:05:51 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Fri, 1 Jul 2022 17:05:51 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Fri, 1 Jul 2022 17:05:51 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter CC: , , , , , Chen-Yu Tsai , Allen-KH Cheng Subject: [PATCH v2 4/6] arm64: dts: mt8192: Add display nodes Date: Fri, 1 Jul 2022 17:05:45 +0800 Message-ID: <20220701090547.21429-5-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220701090547.21429-1-allen-kh.cheng@mediatek.com> References: <20220701090547.21429-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add display nodes and gce info for mt8192 SoC. GCE (Global Command Engine) properties to the display nodes in order to enable the usage of the CMDQ (Command Queue), which is required for operating the display. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: N=C3=ADcolas F. R. A. Prado --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 137 +++++++++++++++++++++++ 1 file changed, 137 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index a789b7c9b2af..c4dc8777f26c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -6,6 +6,7 @@ =20 /dts-v1/; #include +#include #include #include #include @@ -553,6 +554,15 @@ assigned-clock-parents =3D <&topckgen CLK_TOP_OSC_D10>; }; =20 + gce: mailbox@10228000 { + compatible =3D "mediatek,mt8192-gce"; + reg =3D <0 0x10228000 0 0x4000>; + interrupts =3D ; + #mbox-cells =3D <2>; + clocks =3D <&infracfg CLK_INFRA_GCE>; + clock-names =3D "gce"; + }; + scp_adsp: clock-controller@10720000 { compatible =3D "mediatek,mt8192-scp_adsp"; reg =3D <0 0x10720000 0 0x1000>; @@ -1186,9 +1196,22 @@ mmsys: syscon@14000000 { compatible =3D "mediatek,mt8192-mmsys", "syscon"; reg =3D <0 0x14000000 0 0x1000>; + mboxes =3D <&gce 0 CMDQ_THR_PRIO_HIGHEST>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0 0x1000>; #clock-cells =3D <1>; }; =20 + mutex: mutex@14001000 { + compatible =3D "mediatek,mt8192-disp-mutex"; + reg =3D <0 0x14001000 0 0x1000>; + interrupts =3D ; + clocks =3D <&mmsys CLK_MM_DISP_MUTEX0>; + mediatek,gce-events =3D , + ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + }; + smi_common: smi@14002000 { compatible =3D "mediatek,mt8192-smi-common"; reg =3D <0 0x14002000 0 0x1000>; @@ -1220,6 +1243,120 @@ power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; }; =20 + ovl0: ovl@14005000 { + compatible =3D "mediatek,mt8192-disp-ovl"; + reg =3D <0 0x14005000 0 0x1000>; + interrupts =3D ; + clocks =3D <&mmsys CLK_MM_DISP_OVL0>; + iommus =3D <&iommu0 M4U_PORT_L0_OVL_RDMA0>, + <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x5000 0x1000>; + }; + + ovl_2l0: ovl@14006000 { + compatible =3D "mediatek,mt8192-disp-ovl-2l"; + reg =3D <0 0x14006000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_OVL0_2L>; + iommus =3D <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x6000 0x1000>; + }; + + rdma0: rdma@14007000 { + compatible =3D "mediatek,mt8192-disp-rdma", + "mediatek,mt8183-disp-rdma"; + reg =3D <0 0x14007000 0 0x1000>; + interrupts =3D ; + clocks =3D <&mmsys CLK_MM_DISP_RDMA0>; + iommus =3D <&iommu0 M4U_PORT_L0_DISP_RDMA0>; + mediatek,rdma-fifo-size =3D <5120>; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x7000 0x1000>; + }; + + color0: color@14009000 { + compatible =3D "mediatek,mt8192-disp-color", + "mediatek,mt8173-disp-color"; + reg =3D <0 0x14009000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_COLOR0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x9000 0x1000>; + }; + + ccorr0: ccorr@1400a000 { + compatible =3D "mediatek,mt8192-disp-ccorr"; + reg =3D <0 0x1400a000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_CCORR0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xa000 0x1000>; + }; + + aal0: aal@1400b000 { + compatible =3D "mediatek,mt8192-disp-aal", + "mediatek,mt8183-disp-aal"; + reg =3D <0 0x1400b000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_AAL0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xb000 0x1000>; + }; + + gamma0: gamma@1400c000 { + compatible =3D "mediatek,mt8192-disp-gamma", + "mediatek,mt8183-disp-gamma"; + reg =3D <0 0x1400c000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_GAMMA0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xc000 0x1000>; + }; + + postmask0: postmask@1400d000 { + compatible =3D "mediatek,mt8192-disp-postmask"; + reg =3D <0 0x1400d000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_POSTMASK0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xd000 0x1000>; + }; + + dither0: dither@1400e000 { + compatible =3D "mediatek,mt8192-disp-dither", + "mediatek,mt8183-disp-dither"; + reg =3D <0 0x1400e000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_DITHER0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xe000 0x1000>; + }; + + ovl_2l2: ovl@14014000 { + compatible =3D "mediatek,mt8192-disp-ovl-2l"; + reg =3D <0 0x14014000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_OVL2_2L>; + iommus =3D <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0x4000 0x1000>; + }; + + rdma4: rdma@14015000 { + compatible =3D "mediatek,mt8192-disp-rdma"; + reg =3D <0 0x14015000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_RDMA4>; + iommus =3D <&iommu0 M4U_PORT_L1_DISP_RDMA4>; + mediatek,rdma-fifo-size =3D <2048>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0x5000 0x1000>; + }; + dpi0: dpi@14016000 { compatible =3D "mediatek,mt8192-dpi"; reg =3D <0 0x14016000 0 0x1000>; --=20 2.18.0 From nobody Sat Sep 21 21:42:15 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 399E3C43334 for ; Fri, 1 Jul 2022 09:06:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235271AbiGAJGU (ORCPT ); Fri, 1 Jul 2022 05:06:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49598 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234005AbiGAJGI (ORCPT ); Fri, 1 Jul 2022 05:06:08 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BABBB2CC97; Fri, 1 Jul 2022 02:06:02 -0700 (PDT) X-UUID: c44f0a698f484ffbb5f9bdd03df5be77-20220701 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.7,REQID:77fdf04d-f0be-40df-9e8b-b0023fe8bd0f,OB:10,L OB:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,A CTION:release,TS:90 X-CID-INFO: VERSION:1.1.7,REQID:77fdf04d-f0be-40df-9e8b-b0023fe8bd0f,OB:10,LOB :0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:90 X-CID-META: VersionHash:87442a2,CLOUDID:eaa82763-0b3f-4b2c-b3a6-ed5c044366a0,C OID:e52ca3c52d7f,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: c44f0a698f484ffbb5f9bdd03df5be77-20220701 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 518243809; Fri, 01 Jul 2022 17:05:53 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Fri, 1 Jul 2022 17:05:52 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Fri, 1 Jul 2022 17:05:52 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter CC: , , , , , "Chen-Yu Tsai" , Allen-KH Cheng Subject: [PATCH v2 5/6] arm64: dts: mt8192: Add dsi node Date: Fri, 1 Jul 2022 17:05:46 +0800 Message-ID: <20220701090547.21429-6-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220701090547.21429-1-allen-kh.cheng@mediatek.com> References: <20220701090547.21429-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add dsi node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index c4dc8777f26c..6d9164b47bd1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -13,6 +13,7 @@ #include #include #include +#include =20 / { compatible =3D "mediatek,mt8192"; @@ -1335,6 +1336,25 @@ mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xe000 0x1000>; }; =20 + dsi0: dsi@14010000 { + compatible =3D "mediatek,mt8183-dsi"; + reg =3D <0 0x14010000 0 0x1000>; + interrupts =3D ; + clocks =3D <&mmsys CLK_MM_DSI0>, + <&mmsys CLK_MM_DSI_DSI0>, + <&mipi_tx0>; + clock-names =3D "engine", "digital", "hs"; + phys =3D <&mipi_tx0>; + phy-names =3D "dphy"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + resets =3D <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>; + status =3D "disabled"; + + port { + dsi_out: endpoint { }; + }; + }; + ovl_2l2: ovl@14014000 { compatible =3D "mediatek,mt8192-disp-ovl-2l"; reg =3D <0 0x14014000 0 0x1000>; --=20 2.18.0 From nobody Sat Sep 21 21:42:15 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 170BCC433EF for ; Fri, 1 Jul 2022 09:06:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235248AbiGAJGZ (ORCPT ); Fri, 1 Jul 2022 05:06:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49606 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234049AbiGAJGI (ORCPT ); Fri, 1 Jul 2022 05:06:08 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C149C114E; Fri, 1 Jul 2022 02:06:03 -0700 (PDT) X-UUID: 7bf54f5d3122414ab72b5d34e9d28e84-20220701 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.7,REQID:af400ecc-fc78-4c3f-8811-04654e690bbd,OB:0,LO B:20,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,A CTION:release,TS:90 X-CID-INFO: VERSION:1.1.7,REQID:af400ecc-fc78-4c3f-8811-04654e690bbd,OB:0,LOB: 20,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:90 X-CID-META: VersionHash:87442a2,CLOUDID:17e559d6-5d6d-4eaf-a635-828a3ee48b7c,C OID:241272e3c83d,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: 7bf54f5d3122414ab72b5d34e9d28e84-20220701 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 559337415; Fri, 01 Jul 2022 17:05:53 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Fri, 1 Jul 2022 17:05:53 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Fri, 1 Jul 2022 17:05:53 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter CC: , , , , , "Chen-Yu Tsai" , Allen-KH Cheng Subject: [PATCH v2 6/6] arm64: dts: mt8192: Add vcodec lat and core nodes Date: Fri, 1 Jul 2022 17:05:47 +0800 Message-ID: <20220701090547.21429-7-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220701090547.21429-1-allen-kh.cheng@mediatek.com> References: <20220701090547.21429-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add vcodec lat and core nodes for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: N=C3=ADcolas F. R. A. Prado --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60 ++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 6d9164b47bd1..2a1ad3084a01 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1437,6 +1437,66 @@ power-domains =3D <&spm MT8192_POWER_DOMAIN_ISP2>; }; =20 + vcodec_dec: vcodec-dec@16000000 { + compatible =3D "mediatek,mt8192-vcodec-dec"; + reg =3D <0 0x16000000 0 0x1000>; + mediatek,scp =3D <&scp>; + iommus =3D <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>; + dma-ranges =3D <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0 0 0 0x16000000 0 0x26000>; + + vcodec_lat: vcodec-lat@10000 { + compatible =3D "mediatek,mtk-vcodec-lat"; + reg =3D <0x0 0x10000 0 0x800>; + interrupts =3D ; + iommus =3D <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>; + clocks =3D <&topckgen CLK_TOP_VDEC_SEL>, + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&vdecsys_soc CLK_VDEC_SOC_LARB1>, + <&topckgen CLK_TOP_MAINPLL_D4>; + clock-names =3D "sel", "soc-vdec", "soc-lat", "vdec", "top"; + assigned-clocks =3D <&topckgen CLK_TOP_VDEC_SEL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_MAINPLL_D4>; + power-domains =3D <&spm MT8192_POWER_DOMAIN_VDEC>; + }; + + vcodec_core: vcodec-core@25000 { + compatible =3D "mediatek,mtk-vcodec-core"; + reg =3D <0 0x25000 0 0x1000>; + interrupts =3D ; + iommus =3D <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>; + clocks =3D <&topckgen CLK_TOP_VDEC_SEL>, + <&vdecsys CLK_VDEC_VDEC>, + <&vdecsys CLK_VDEC_LAT>, + <&vdecsys CLK_VDEC_LARB1>, + <&topckgen CLK_TOP_MAINPLL_D4>; + clock-names =3D "sel", "soc-vdec", "soc-lat", "vdec", "top"; + assigned-clocks =3D <&topckgen CLK_TOP_VDEC_SEL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_MAINPLL_D4>; + power-domains =3D <&spm MT8192_POWER_DOMAIN_VDEC2>; + }; + }; + larb5: larb@1600d000 { compatible =3D "mediatek,mt8192-smi-larb"; reg =3D <0 0x1600d000 0 0x1000>; --=20 2.18.0