From nobody Sun Sep 22 01:34:23 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E995CC43334 for ; Fri, 1 Jul 2022 06:28:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234361AbiGAG25 (ORCPT ); Fri, 1 Jul 2022 02:28:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59290 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234379AbiGAG2Z (ORCPT ); Fri, 1 Jul 2022 02:28:25 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1C908101ED; Thu, 30 Jun 2022 23:28:20 -0700 (PDT) X-UUID: 36aa71f8adea42dd8feec981c7644879-20220701 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.7,REQID:12f98cf2-624d-4530-87d7-280a1c11697d,OB:0,LO B:0,IP:0,URL:5,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:0 X-CID-META: VersionHash:87442a2,CLOUDID:1ef12263-0b3f-4b2c-b3a6-ed5c044366a0,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:1,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: 36aa71f8adea42dd8feec981c7644879-20220701 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1636868071; Fri, 01 Jul 2022 14:28:13 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Fri, 1 Jul 2022 14:28:11 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Fri, 1 Jul 2022 14:28:11 +0800 From: Bo-Chen Chen To: , , , , , , , , , CC: , , , , , , , , , , , , , , Bo-Chen Chen Subject: [PATCH v13 06/10] drm/mediatek: Add MT8195 External DisplayPort support Date: Fri, 1 Jul 2022 14:28:04 +0800 Message-ID: <20220701062808.18596-7-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220701062808.18596-1-rex-bc.chen@mediatek.com> References: <20220701062808.18596-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Guillaume Ranquet This patch adds External DisplayPort support to the mt8195 eDP driver. Signed-off-by: Guillaume Ranquet Signed-off-by: Bo-Chen Chen --- drivers/gpu/drm/mediatek/mtk_dp.c | 197 +++++++++++++++++++++----- drivers/gpu/drm/mediatek/mtk_dp_reg.h | 1 + 2 files changed, 161 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/m= tk_dp.c index b672d5a6f5bd..c3be97dd055c 100644 --- a/drivers/gpu/drm/mediatek/mtk_dp.c +++ b/drivers/gpu/drm/mediatek/mtk_dp.c @@ -105,6 +105,7 @@ struct mtk_dp { struct regmap *regs; =20 bool enabled; + bool has_fec; =20 struct drm_connector *conn; }; @@ -117,6 +118,11 @@ static struct regmap_config mtk_dp_regmap_config =3D { .name =3D "mtk-dp-registers", }; =20 +static bool mtk_dp_is_edp(struct mtk_dp *mtk_dp) +{ + return mtk_dp->next_bridge; +} + static struct mtk_dp *mtk_dp_from_bridge(struct drm_bridge *b) { return container_of(b, struct mtk_dp, bridge); @@ -384,6 +390,14 @@ static bool mtk_dp_plug_state(struct mtk_dp *mtk_dp) HPD_DB_DP_TRANS_P0_MASK); } =20 +static bool mtk_dp_plug_state_avoid_pulse(struct mtk_dp *mtk_dp) +{ + bool ret; + + return !(readx_poll_timeout(mtk_dp_plug_state, mtk_dp, ret, ret, + 4000, 7 * 4000)); +} + static void mtk_dp_aux_irq_clear(struct mtk_dp *mtk_dp) { mtk_dp_write(mtk_dp, MTK_DP_AUX_P0_3640, @@ -608,6 +622,13 @@ static void mtk_dp_reset_swing_pre_emphasis(struct mtk= _dp *mtk_dp) DP_TX3_PRE_EMPH_MASK); } =20 +static void mtk_dp_fec_enable(struct mtk_dp *mtk_dp, bool enable) +{ + mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3540, + enable ? BIT(FEC_EN_DP_TRANS_P0_SHIFT) : 0, + FEC_EN_DP_TRANS_P0_MASK); +} + static u32 mtk_dp_swirq_get_clear(struct mtk_dp *mtk_dp) { u32 irq_status =3D mtk_dp_read(mtk_dp, MTK_DP_TRANS_P0_35D0) & @@ -823,35 +844,67 @@ static void mtk_dp_get_calibration_data(struct mtk_dp= *mtk_dp) return; } =20 - cal_data->glb_bias_trim =3D - check_cal_data_valid(mtk_dp, 1, 0x1e, - (buf[3] >> 27) & 0x1f, 0xf); - cal_data->clktx_impse =3D - check_cal_data_valid(mtk_dp, 1, 0xe, - (buf[0] >> 9) & 0xf, 0x8); - cal_data->ln_tx_impsel_pmos[0] =3D - check_cal_data_valid(mtk_dp, 1, 0xe, - (buf[2] >> 28) & 0xf, 0x8); - cal_data->ln_tx_impsel_nmos[0] =3D - check_cal_data_valid(mtk_dp, 1, 0xe, - (buf[2] >> 24) & 0xf, 0x8); - cal_data->ln_tx_impsel_pmos[1] =3D - check_cal_data_valid(mtk_dp, 1, 0xe, - (buf[2] >> 20) & 0xf, 0x8); - cal_data->ln_tx_impsel_nmos[1] =3D - check_cal_data_valid(mtk_dp, 1, 0xe, - (buf[2] >> 16) & 0xf, 0x8); - cal_data->ln_tx_impsel_pmos[2] =3D - check_cal_data_valid(mtk_dp, 1, 0xe, - (buf[2] >> 12) & 0xf, 0x8); - cal_data->ln_tx_impsel_nmos[2] =3D - check_cal_data_valid(mtk_dp, 1, 0xe, - (buf[2] >> 8) & 0xf, 0x8); - cal_data->ln_tx_impsel_pmos[3] =3D - check_cal_data_valid(mtk_dp, 1, 0xe, - (buf[2] >> 4) & 0xf, 0x8); - cal_data->ln_tx_impsel_nmos[3] =3D - check_cal_data_valid(mtk_dp, 1, 0xe, buf[2] & 0xf, 0x8); + if (mtk_dp_is_edp(mtk_dp)) { + cal_data->glb_bias_trim =3D + check_cal_data_valid(mtk_dp, 1, 0x1e, + (buf[3] >> 27) & 0x1f, 0xf); + cal_data->clktx_impse =3D + check_cal_data_valid(mtk_dp, 1, 0xe, + (buf[0] >> 9) & 0xf, 0x8); + cal_data->ln_tx_impsel_pmos[0] =3D + check_cal_data_valid(mtk_dp, 1, 0xe, + (buf[2] >> 28) & 0xf, 0x8); + cal_data->ln_tx_impsel_nmos[0] =3D + check_cal_data_valid(mtk_dp, 1, 0xe, + (buf[2] >> 24) & 0xf, 0x8); + cal_data->ln_tx_impsel_pmos[1] =3D + check_cal_data_valid(mtk_dp, 1, 0xe, + (buf[2] >> 20) & 0xf, 0x8); + cal_data->ln_tx_impsel_nmos[1] =3D + check_cal_data_valid(mtk_dp, 1, 0xe, + (buf[2] >> 16) & 0xf, 0x8); + cal_data->ln_tx_impsel_pmos[2] =3D + check_cal_data_valid(mtk_dp, 1, 0xe, + (buf[2] >> 12) & 0xf, 0x8); + cal_data->ln_tx_impsel_nmos[2] =3D + check_cal_data_valid(mtk_dp, 1, 0xe, + (buf[2] >> 8) & 0xf, 0x8); + cal_data->ln_tx_impsel_pmos[3] =3D + check_cal_data_valid(mtk_dp, 1, 0xe, + (buf[2] >> 4) & 0xf, 0x8); + cal_data->ln_tx_impsel_nmos[3] =3D + check_cal_data_valid(mtk_dp, 1, 0xe, buf[2] & 0xf, 0x8); + } else { + cal_data->glb_bias_trim =3D + check_cal_data_valid(mtk_dp, 1, 0x1e, + (buf[0] >> 27) & 0x1f, 0xf); + cal_data->clktx_impse =3D + check_cal_data_valid(mtk_dp, 1, 0xe, + (buf[0] >> 13) & 0xf, 0x8); + cal_data->ln_tx_impsel_pmos[0] =3D + check_cal_data_valid(mtk_dp, 1, 0xe, + (buf[1] >> 28) & 0xf, 0x8); + cal_data->ln_tx_impsel_nmos[0] =3D + check_cal_data_valid(mtk_dp, 1, 0xe, + (buf[1] >> 24) & 0xf, 0x8); + cal_data->ln_tx_impsel_pmos[1] =3D + check_cal_data_valid(mtk_dp, 1, 0xe, + (buf[1] >> 20) & 0xf, 0x8); + cal_data->ln_tx_impsel_nmos[1] =3D + check_cal_data_valid(mtk_dp, 1, 0xe, + (buf[1] >> 16) & 0xf, 0x8); + cal_data->ln_tx_impsel_pmos[2] =3D + check_cal_data_valid(mtk_dp, 1, 0xe, + (buf[1] >> 12) & 0xf, 0x8); + cal_data->ln_tx_impsel_nmos[2] =3D + check_cal_data_valid(mtk_dp, 1, 0xe, + (buf[1] >> 8) & 0xf, 0x8); + cal_data->ln_tx_impsel_pmos[3] =3D + check_cal_data_valid(mtk_dp, 1, 0xe, + (buf[1] >> 4) & 0xf, 0x8); + cal_data->ln_tx_impsel_nmos[3] =3D + check_cal_data_valid(mtk_dp, 1, 0xe, buf[1] & 0xf, 0x8); + } =20 kfree(buf); } @@ -971,7 +1024,10 @@ static void mtk_dp_video_mute(struct mtk_dp *mtk_dp, = bool enable) VIDEO_MUTE_SEL_DP_ENC0_P0_MASK | VIDEO_MUTE_SW_DP_ENC0_P0_MASK); =20 - mtk_dp_sip_atf_call(mtk_dp, MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE, enable); + mtk_dp_sip_atf_call(mtk_dp, + mtk_dp_is_edp(mtk_dp) ? + MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE : + MTK_DP_SIP_ATF_VIDEO_UNMUTE, enable); } =20 static void mtk_dp_power_enable(struct mtk_dp *mtk_dp) @@ -1018,6 +1074,8 @@ static void mtk_dp_initialize_priv_data(struct mtk_dp= *mtk_dp) mtk_dp->info.depth =3D DP_MSA_MISC_8_BPC; memset(&mtk_dp->info.timings, 0, sizeof(struct mtk_dp_timings)); mtk_dp->info.timings.frame_rate =3D 60; + + mtk_dp->has_fec =3D false; } =20 static void mtk_dp_setup_tu(struct mtk_dp *mtk_dp) @@ -1306,6 +1364,9 @@ static int mtk_dp_parse_capabilities(struct mtk_dp *m= tk_dp) drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); usleep_range(2000, 5000); =20 + if (!mtk_dp_plug_state(mtk_dp)) + return -ENODEV; + drm_dp_read_dpcd_caps(&mtk_dp->aux, mtk_dp->rx_cap); =20 train_info->link_rate =3D min_t(int, mtk_dp->max_linkrate, @@ -1357,6 +1418,9 @@ static int mtk_dp_train_start(struct mtk_dp *mtk_dp) u8 train_limit; u8 max_link_rate; =20 + if (!mtk_dp_plug_state_avoid_pulse(mtk_dp)) + return -ENODEV; + link_rate =3D mtk_dp->rx_cap[1]; lane_count =3D mtk_dp->rx_cap[2] & 0x1F; =20 @@ -1498,15 +1562,38 @@ static int mtk_dp_init_port(struct mtk_dp *mtk_dp) static irqreturn_t mtk_dp_hpd_event_thread(int hpd, void *dev) { struct mtk_dp *mtk_dp =3D dev; + int event; u8 buf[DP_RECEIVER_CAP_SIZE] =3D {}; =20 + event =3D mtk_dp_plug_state(mtk_dp) ? + connector_status_connected : connector_status_disconnected; + + if (event < 0) + return IRQ_HANDLED; + + dev_info(mtk_dp->dev, "drm_helper_hpd_irq_event\n"); + drm_helper_hpd_irq_event(mtk_dp->bridge.dev); + if (mtk_dp->train_info.cable_state_change) { mtk_dp->train_info.cable_state_change =3D false; =20 - mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, - DP_PWR_STATE_BANDGAP_TPLL_LANE, - DP_PWR_STATE_MASK); - drm_dp_read_dpcd_caps(&mtk_dp->aux, buf); + if (!mtk_dp->train_info.cable_plugged_in) { + mtk_dp_video_mute(mtk_dp, true); + + mtk_dp_initialize_priv_data(mtk_dp); + mtk_dp_set_idle_pattern(mtk_dp, true); + if (mtk_dp->has_fec) + mtk_dp_fec_enable(mtk_dp, false); + + mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, + DP_PWR_STATE_BANDGAP_TPLL, + DP_PWR_STATE_MASK); + } else { + mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, + DP_PWR_STATE_BANDGAP_TPLL_LANE, + DP_PWR_STATE_MASK); + drm_dp_read_dpcd_caps(&mtk_dp->aux, buf); + } } =20 if (mtk_dp->train_info.irq_sta.hpd_inerrupt) { @@ -1617,6 +1704,24 @@ static int mtk_dp_dt_parse(struct mtk_dp *mtk_dp, return 0; } =20 +static enum drm_connector_status mtk_dp_bdg_detect(struct drm_bridge *brid= ge) +{ + struct mtk_dp *mtk_dp =3D mtk_dp_from_bridge(bridge); + enum drm_connector_status ret =3D connector_status_disconnected; + u8 sink_count =3D 0; + + if (mtk_dp_is_edp(mtk_dp)) + return connector_status_connected; + + if (mtk_dp_plug_state_avoid_pulse(mtk_dp)) { + drm_dp_dpcd_readb(&mtk_dp->aux, DP_SINK_COUNT, &sink_count); + if (DP_GET_SINK_COUNT(sink_count)) + ret =3D connector_status_connected; + } + + return ret; +} + static struct edid *mtk_dp_get_edid(struct drm_bridge *bridge, struct drm_connector *connector) { @@ -1630,7 +1735,8 @@ static struct edid *mtk_dp_get_edid(struct drm_bridge= *bridge, drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); usleep_range(2000, 5000); =20 - new_edid =3D drm_get_edid(connector, &mtk_dp->aux.ddc); + if (mtk_dp_plug_state(mtk_dp)) + new_edid =3D drm_get_edid(connector, &mtk_dp->aux.ddc); =20 if (!enabled) drm_bridge_chain_post_disable(bridge); @@ -1989,6 +2095,7 @@ static const struct drm_bridge_funcs mtk_dp_bridge_fu= ncs =3D { .atomic_disable =3D mtk_dp_bridge_atomic_disable, .mode_valid =3D mtk_dp_bridge_mode_valid, .get_edid =3D mtk_dp_get_edid, + .detect =3D mtk_dp_bdg_detect, }; =20 static int mtk_dp_probe(struct platform_device *pdev) @@ -2010,9 +2117,15 @@ static int mtk_dp_probe(struct platform_device *pdev) "failed to request dp irq resource\n"); =20 mtk_dp->next_bridge =3D devm_drm_of_get_bridge(dev, dev->of_node, 1, 0); - if (IS_ERR(mtk_dp->next_bridge)) + if (IS_ERR(mtk_dp->next_bridge) && + PTR_ERR(mtk_dp->next_bridge) =3D=3D -ENODEV) { + dev_info(dev, + "No panel connected in devicetree, continue as external DP\n"); + mtk_dp->next_bridge =3D NULL; + } else if (IS_ERR(mtk_dp->next_bridge)) { return dev_err_probe(dev, PTR_ERR(mtk_dp->next_bridge), "Failed to get bridge\n"); + } =20 ret =3D mtk_dp_dt_parse(mtk_dp, pdev); if (ret) @@ -2055,7 +2168,10 @@ static int mtk_dp_probe(struct platform_device *pdev) =20 mtk_dp->bridge.ops =3D DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD; - mtk_dp->bridge.type =3D DRM_MODE_CONNECTOR_eDP; + if (mtk_dp_is_edp(mtk_dp)) + mtk_dp->bridge.type =3D DRM_MODE_CONNECTOR_eDP; + else + mtk_dp->bridge.type =3D DRM_MODE_CONNECTOR_DisplayPort; =20 drm_bridge_add(&mtk_dp->bridge); =20 @@ -2082,6 +2198,12 @@ static int mtk_dp_suspend(struct device *dev) { struct mtk_dp *mtk_dp =3D dev_get_drvdata(dev); =20 + if (mtk_dp_plug_state(mtk_dp)) { + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D3); + /* Ensure the sink is off before shutting down power */ + usleep_range(2000, 3000); + } + mtk_dp_power_disable(mtk_dp); =20 mtk_dp_hwirq_enable(mtk_dp, false); @@ -2115,6 +2237,7 @@ static SIMPLE_DEV_PM_OPS(mtk_dp_pm_ops, mtk_dp_suspen= d, mtk_dp_resume); =20 static const struct of_device_id mtk_dp_of_match[] =3D { { .compatible =3D "mediatek,mt8195-edp-tx" }, + { .compatible =3D "mediatek,mt8195-dp-tx" }, {}, }; MODULE_DEVICE_TABLE(of, mtk_dp_of_match); diff --git a/drivers/gpu/drm/mediatek/mtk_dp_reg.h b/drivers/gpu/drm/mediat= ek/mtk_dp_reg.h index c9d587f1bacd..9b6f2e01391d 100644 --- a/drivers/gpu/drm/mediatek/mtk_dp_reg.h +++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h @@ -14,6 +14,7 @@ #define SEC_OFFSET 0x4000 =20 #define MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE (BIT(0) | BIT(5)) +#define MTK_DP_SIP_ATF_VIDEO_UNMUTE BIT(5) =20 #define DP_PHY_GLB_BIAS_GEN_00 0 #define RG_XTP_GLB_BIAS_INTR_CTRL GENMASK(20, 16) --=20 2.18.0