From nobody Sat Sep 21 23:37:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F1FEC43334 for ; Fri, 1 Jul 2022 04:00:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234643AbiGAEAL (ORCPT ); Fri, 1 Jul 2022 00:00:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234548AbiGAD7A (ORCPT ); Thu, 30 Jun 2022 23:59:00 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5ADD33DDFC; Thu, 30 Jun 2022 20:58:58 -0700 (PDT) X-UUID: 1b6cfc1e8c72483bbe0f4d9b404f7e94-20220701 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.7,REQID:fbb7e45a-cce7-464f-857c-37824769572f,OB:10,L OB:40,IP:0,URL:5,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham, ACTION:release,TS:95 X-CID-INFO: VERSION:1.1.7,REQID:fbb7e45a-cce7-464f-857c-37824769572f,OB:10,LOB :40,IP:0,URL:5,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D, ACTION:quarantine,TS:95 X-CID-META: VersionHash:87442a2,CLOUDID:0ad71e63-0b3f-4b2c-b3a6-ed5c044366a0,C OID:3dbc9b1abf00,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:1,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: 1b6cfc1e8c72483bbe0f4d9b404f7e94-20220701 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1489790626; Fri, 01 Jul 2022 11:58:49 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Fri, 1 Jul 2022 11:58:47 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Fri, 1 Jul 2022 11:58:47 +0800 From: Bo-Chen Chen To: , , , , , , CC: , , , , , , , , , , , , , , Bo-Chen Chen Subject: [PATCH v15 06/16] drm/mediatek: dpi: implement a CK/DE pol toggle in SoC config Date: Fri, 1 Jul 2022 11:58:35 +0800 Message-ID: <20220701035845.16458-7-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220701035845.16458-1-rex-bc.chen@mediatek.com> References: <20220701035845.16458-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Guillaume Ranquet Dp_intf does not support CK/DE polarity because the polarity information is not used for eDP and DP while dp_intf is only for eDP and DP. Therefore, we add a bit of flexibility to support SoCs without CK/DE pol support. Signed-off-by: Guillaume Ranquet Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rex-BC Chen Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_dpi.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 0855bbdfe4e1..b89ad9f38396 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -120,6 +120,7 @@ struct mtk_dpi_yc_limit { * @edge_sel_en: Enable of edge selection. * @output_fmts: Array of supported output formats. * @num_output_fmts: Quantity of supported output formats. + * @is_ck_de_pol: Support CK/DE polarity. */ struct mtk_dpi_conf { unsigned int (*cal_factor)(int clock); @@ -128,6 +129,7 @@ struct mtk_dpi_conf { bool edge_sel_en; const u32 *output_fmts; u32 num_output_fmts; + bool is_ck_de_pol; }; =20 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mas= k) @@ -213,13 +215,20 @@ static void mtk_dpi_config_pol(struct mtk_dpi *dpi, struct mtk_dpi_polarities *dpi_pol) { unsigned int pol; + unsigned int mask; =20 - pol =3D (dpi_pol->ck_pol =3D=3D MTK_DPI_POLARITY_RISING ? 0 : CK_POL) | - (dpi_pol->de_pol =3D=3D MTK_DPI_POLARITY_RISING ? 0 : DE_POL) | - (dpi_pol->hsync_pol =3D=3D MTK_DPI_POLARITY_RISING ? 0 : HSYNC_POL)= | + mask =3D HSYNC_POL | VSYNC_POL; + pol =3D (dpi_pol->hsync_pol =3D=3D MTK_DPI_POLARITY_RISING ? 0 : HSYNC_PO= L) | (dpi_pol->vsync_pol =3D=3D MTK_DPI_POLARITY_RISING ? 0 : VSYNC_POL); - mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol, - CK_POL | DE_POL | HSYNC_POL | VSYNC_POL); + if (dpi->conf->is_ck_de_pol) { + mask |=3D CK_POL | DE_POL; + pol |=3D (dpi_pol->ck_pol =3D=3D MTK_DPI_POLARITY_RISING ? + 0 : CK_POL) | + (dpi_pol->de_pol =3D=3D MTK_DPI_POLARITY_RISING ? + 0 : DE_POL); + } + + mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol, mask); } =20 static void mtk_dpi_config_3d(struct mtk_dpi *dpi, bool en_3d) @@ -794,6 +803,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .max_clock_khz =3D 300000, .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), + .is_ck_de_pol =3D true, }; =20 static const struct mtk_dpi_conf mt2701_conf =3D { @@ -803,6 +813,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .max_clock_khz =3D 150000, .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), + .is_ck_de_pol =3D true, }; =20 static const struct mtk_dpi_conf mt8183_conf =3D { @@ -811,6 +822,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .max_clock_khz =3D 100000, .output_fmts =3D mt8183_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts), + .is_ck_de_pol =3D true, }; =20 static const struct mtk_dpi_conf mt8192_conf =3D { @@ -819,6 +831,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .max_clock_khz =3D 150000, .output_fmts =3D mt8183_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts), + .is_ck_de_pol =3D true, }; =20 static int mtk_dpi_probe(struct platform_device *pdev) --=20 2.18.0