From nobody Sat Sep 21 22:52:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA1F7C43334 for ; Thu, 30 Jun 2022 15:33:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236006AbiF3Pdj (ORCPT ); Thu, 30 Jun 2022 11:33:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41232 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235956AbiF3Pd3 (ORCPT ); Thu, 30 Jun 2022 11:33:29 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0288A3EF26; Thu, 30 Jun 2022 08:33:26 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 730D76601964; Thu, 30 Jun 2022 16:33:24 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1656603205; bh=2tnHNAZaZDCuDnnGZahAxPIq9YXQxYwRpKMSJ0Kgqks=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ERvWj6dbuEBc2qowvzQ2tnF7WisXmOMOP8kXsmEV4ur1Dx4+bOFAu0+ci1T/Z5xG2 WHQn4MYcMd890UsLcQjYLUMkSqhWw7rFG6o3os5DYeuqbjsWc1cQJ604jA749oTYlU tlMN3b03g4/WWcAAQDRJxv0z06uNkf+4lb6BhecWU4nOdAH1+rxLNTKl+CUXJNfZH7 FKwIENe5Wo4JezKyqCXE0XzfaKmddcuWJZ0eT9j8HSHR5bgVdXqCCRkkhIhqNFAn2f J268ernK4Ujf5CiQq510O8pcUgY/YsdOhpncqF4Dg669rGAFo6qi0SARhBHHjr2vJR IF971delu91Fw== From: AngeloGioacchino Del Regno To: robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, hsinyi@chromium.org, nfraprado@collabora.com, allen-kh.cheng@mediatek.com, gtk3@inbox.ru, luca@z3ntu.xyz, sam.shih@mediatek.com, sean.wang@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, wenst@chromium.org Subject: [PATCH 01/11] dt-bindings: arm: mediatek: Add MT8195 Cherry Tomato Chromebooks Date: Thu, 30 Jun 2022 17:33:06 +0200 Message-Id: <20220630153316.308767-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220630153316.308767-1-angelogioacchino.delregno@collabora.com> References: <20220630153316.308767-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Document board compatibles for the MT8195 Cherry platform's Tomato Chromebooks, at the time of writing composed of four revisions (r0, r1, r2, r3-r4). Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/mediatek.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Document= ation/devicetree/bindings/arm/mediatek.yaml index dd6c6e8011f9..3e0afa17ed2e 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -144,6 +144,19 @@ properties: - const: google,spherion-rev0 - const: google,spherion - const: mediatek,mt8192 + - description: Google Tomato (Acer Chromebook Spin 513) + items: + - enum: + - google,tomato-rev2 + - google,tomato-rev1 + - const: google,tomato + - const: mediatek,mt8195 + - description: Google Tomato (rev3 - 4) + items: + - const: google,tomato-rev4 + - const: google,tomato-rev3 + - const: google,tomato + - const: mediatek,mt8195 - items: - enum: - mediatek,mt8186-evb --=20 2.35.1 From nobody Sat Sep 21 22:52:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05075C43334 for ; Thu, 30 Jun 2022 15:33:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236023AbiF3Pdq (ORCPT ); Thu, 30 Jun 2022 11:33:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42560 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235968AbiF3Pda (ORCPT ); Thu, 30 Jun 2022 11:33:30 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9ECF0E0F7; Thu, 30 Jun 2022 08:33:27 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 550ED6601967; Thu, 30 Jun 2022 16:33:25 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1656603206; bh=nOhUYm0IpD/r1TykJ1rAO+e9Iu31jMTfdhwk8vihElo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dFfhWxuSBWqkSfXsPVunMYMQkVJY8BXA0MhFArUZ46NJ7p62OdDljvSVEXy2QeOYf l+8GkP9/Us8ROdHej63ydggHcBo+xnHXEZGtThGGuaxpbUawObBYS7QA3vHUnwNXfB HRFfJvfz+PuIMlhZwyB3j9gcix+OdnWZrAzMI24cSRGbCS5dLLrgYzfAFFl+wfsekW ymEcGd2Qm9kay97ztD5UYXbKYqAhol4ZnZqhu31KGrpG014/wbAflZbtQxm2e9L/vZ Kk4Dtb6F9ZtTIkMPKZsIh5JKS4Xdl+Gfz5q2OVlNd05R5nVq3mA4OtTd1PVAHw3jUR M04zt3f5L4f+g== From: AngeloGioacchino Del Regno To: robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, hsinyi@chromium.org, nfraprado@collabora.com, allen-kh.cheng@mediatek.com, gtk3@inbox.ru, luca@z3ntu.xyz, sam.shih@mediatek.com, sean.wang@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, wenst@chromium.org Subject: [PATCH 02/11] arm64: dts: mediatek: Introduce MT8195 Cherry platform's Tomato Date: Thu, 30 Jun 2022 17:33:07 +0200 Message-Id: <20220630153316.308767-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220630153316.308767-1-angelogioacchino.delregno@collabora.com> References: <20220630153316.308767-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Introduce the MT8195 Cherry Chromebook platform, including three revisions of Cherry Tomato boards. This basic configuration allows to boot Linux on all board revisions and get a serial console from a ramdisk. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: N=C3=ADcolas F. R. A. Prado --- arch/arm64/boot/dts/mediatek/Makefile | 3 +++ .../dts/mediatek/mt8195-cherry-tomato-r1.dts | 11 ++++++++ .../dts/mediatek/mt8195-cherry-tomato-r2.dts | 11 ++++++++ .../dts/mediatek/mt8195-cherry-tomato-r3.dts | 12 +++++++++ .../boot/dts/mediatek/mt8195-cherry.dtsi | 26 +++++++++++++++++++ 5 files changed, 63 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/me= diatek/Makefile index 50a2c58c5f56..0b12035a4f08 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -39,6 +39,9 @@ dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8183-kukui-krane-sku17= 6.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8183-pumpkin.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8186-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8192-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8195-cherry-tomato-r1.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8195-cherry-tomato-r2.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8195-cherry-tomato-r3.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8195-demo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8195-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts b/arc= h/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts new file mode 100644 index 000000000000..17e9e4d6f6ab --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + */ +/dts-v1/; +#include "mt8195-cherry.dtsi" + +/ { + model =3D "MediaTek Tomato (rev1) board"; + compatible =3D "google,tomato-rev1", "google,tomato", "mediatek,mt8195"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts b/arc= h/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts new file mode 100644 index 000000000000..b915fba311e9 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + */ +/dts-v1/; +#include "mt8195-cherry.dtsi" + +/ { + model =3D "MediaTek Tomato (rev2) board"; + compatible =3D "google,tomato-rev2", "google,tomato", "mediatek,mt8195"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts b/arc= h/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts new file mode 100644 index 000000000000..2ead9eca2ec9 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + */ +/dts-v1/; +#include "mt8195-cherry.dtsi" + +/ { + model =3D "MediaTek Tomato (rev3 - 4) board"; + compatible =3D "google,tomato-rev4", "google,tomato-rev3", + "google,tomato", "mediatek,mt8195"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/b= oot/dts/mediatek/mt8195-cherry.dtsi new file mode 100644 index 000000000000..7406d7bbf725 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + */ + +#include +#include "mt8195.dtsi" + +/ { + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + memory@40000000 { + device_type =3D "memory"; + reg =3D <0 0x40000000 0 0x80000000>; + }; +}; + +&uart0 { + status =3D "okay"; +}; --=20 2.35.1 From nobody Sat Sep 21 22:52:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 563FBC43334 for ; Thu, 30 Jun 2022 15:33:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236040AbiF3Pdt (ORCPT ); Thu, 30 Jun 2022 11:33:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42724 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235924AbiF3Pdb (ORCPT ); Thu, 30 Jun 2022 11:33:31 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A12AE17E04; Thu, 30 Jun 2022 08:33:28 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 37598660196B; Thu, 30 Jun 2022 16:33:26 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1656603207; bh=/1I2RRywIXgcW9vN4SVk5tQI6QK5Mxljtoam1OZPAO0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=g9jK9IbkQuyp0sdiAaGzO3IvmzNN3+pqA3KMB0VeJy0E0Tj5qcuqrUQXWely5HYMj gvh1AmBdzIjBg4+6L77bi3OgoRJ2iQiCID/pcH1cC4guVRFCi6KnE0QxijeV0izH6H GeOGrTIpa0TJUVOuqjf3GYoMvOuQ9I8IpQn5pdwbD7QOnd49uO2gmb2NbUjvbrlXum edB/Ffpy9x2HpB6dDqaxA8Bq8PeqDOM+aHZFNy7U9TE6l/BQcDnsNCPFY4zqitmEtG 7xNEvBZdhlRMrhDE5RaVVbctV1TOVRd8HRf/06ROBcVvJSg9aAir8eaO496TjnV3F/ jlzK/1Wh5Ynrw== From: AngeloGioacchino Del Regno To: robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, hsinyi@chromium.org, nfraprado@collabora.com, allen-kh.cheng@mediatek.com, gtk3@inbox.ru, luca@z3ntu.xyz, sam.shih@mediatek.com, sean.wang@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, wenst@chromium.org Subject: [PATCH 03/11] arm64: dts: mediatek: cherry: Assign interrupt line to MT6359 PMIC Date: Thu, 30 Jun 2022 17:33:08 +0200 Message-Id: <20220630153316.308767-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220630153316.308767-1-angelogioacchino.delregno@collabora.com> References: <20220630153316.308767-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" To allow MT6359 peripherals to trigger interrupts and the driver to safely handle them, assign the right interrupt line for the Cherry platform to the MT6359 PMIC node. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: N=C3=ADcolas F. R. A. Prado --- arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/b= oot/dts/mediatek/mt8195-cherry.dtsi index 7406d7bbf725..14f8f30b1eb3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -21,6 +21,10 @@ memory@40000000 { }; }; =20 +&pmic { + interrupts-extended =3D <&pio 222 IRQ_TYPE_LEVEL_HIGH>; +}; + &uart0 { status =3D "okay"; }; --=20 2.35.1 From nobody Sat Sep 21 22:52:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C85B6CCA47B for ; Thu, 30 Jun 2022 15:33:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235996AbiF3Pdv (ORCPT ); Thu, 30 Jun 2022 11:33:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235985AbiF3Pdb (ORCPT ); Thu, 30 Jun 2022 11:33:31 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 14CA6220D7; Thu, 30 Jun 2022 08:33:29 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 2413C660196D; Thu, 30 Jun 2022 16:33:27 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1656603207; bh=jogVEZhtKyX8PbDyMB9xCc1ckAJzJb39HZYE1/psFO8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=n2gzTT5fHhXY5fdGABAYABEnjCRQqc/6aSezdn73L2uiPETndybCnk4KSmQ0nUih+ WoeX7tqaaiMo5W+WfpSL72XjLCtHv7xwu/DuK0dHKd7goK3uNB1Ab42RBW1nrrluKx UNobQDPOlhypsSzhZTbVhP79bDl6uOV7sSg23OWQAgRCkK3xApTpVN8S9G63hez4aG EWfWRI4zfIvBOjOOt1p2d/PEF1TwpBb5VJq9PmNvq9AdMZRyGaziO8rPV2pRlT+bl3 iY1z+5+mj5NljM1ZyGQ5mqXlrt/M+U6qB3VPcNfyQBsx4rNNanBEfnueWBLIonRuiM XAqoxz+Y+Agog== From: AngeloGioacchino Del Regno To: robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, hsinyi@chromium.org, nfraprado@collabora.com, allen-kh.cheng@mediatek.com, gtk3@inbox.ru, luca@z3ntu.xyz, sam.shih@mediatek.com, sean.wang@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, wenst@chromium.org Subject: [PATCH 04/11] arm64: dts: mediatek: cherry: Add platform regulators layout and config Date: Thu, 30 Jun 2022 17:33:09 +0200 Message-Id: <20220630153316.308767-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220630153316.308767-1-angelogioacchino.delregno@collabora.com> References: <20220630153316.308767-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the regulators layout for this platform, including the basic power rails controlled by the EC (and/or always on). Moreover, include the MT6359 PMIC devicetree and add some configuration for its regulators, essential to keep the machine alive after booting. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: N=C3=ADcolas F. R. A. Prado --- .../boot/dts/mediatek/mt8195-cherry.dtsi | 102 ++++++++++++++++++ 1 file changed, 102 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/b= oot/dts/mediatek/mt8195-cherry.dtsi index 14f8f30b1eb3..091338f7d5ff 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -5,6 +5,7 @@ =20 #include #include "mt8195.dtsi" +#include "mt6359.dtsi" =20 / { aliases { @@ -19,6 +20,107 @@ memory@40000000 { device_type =3D "memory"; reg =3D <0 0x40000000 0 0x80000000>; }; + + /* system wide LDO 3.3V power rail */ + pp3300_z5: regulator-3v3-pp3300-ldo-z5 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp3300_ldo_z5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&ppvar_sys>; + }; + + /* separately switched 3.3V power rail */ + pp3300_s3: regulator-3v3-pp3300-s3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp3300_s3"; + /* automatically sequenced by PMIC EXT_PMIC_EN2 */ + regulator-always-on; + regulator-boot-on; + vin-supply =3D <&pp3300_z2>; + }; + + /* system wide 3.3V power rail */ + pp3300_z2: regulator-3v3-pp3300-z2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp3300_z2"; + /* EN pin tied to pp4200_z2, which is controlled by EC */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&ppvar_sys>; + }; + + /* system wide 4.2V power rail */ + pp4200_z2: regulator-4v2-pp4200-z2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp4200_z2"; + /* controlled by EC */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <4200000>; + regulator-max-microvolt =3D <4200000>; + vin-supply =3D <&ppvar_sys>; + }; + + /* system wide switching 5.0V power rail */ + pp5000_s5: regulator-5v0-pp5000-s5 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp5000_s5"; + /* controlled by EC */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&ppvar_sys>; + }; + + /* system wide semi-regulated power rail from battery or USB */ + ppvar_sys: regulator-ppvar-sys { + compatible =3D "regulator-fixed"; + regulator-name =3D "ppvar_sys"; + regulator-always-on; + regulator-boot-on; + }; +}; + +/* for CPU-L */ +&mt6359_vcore_buck_reg { + regulator-always-on; +}; + +/* for CORE */ +&mt6359_vgpu11_buck_reg { + regulator-always-on; +}; + +&mt6359_vgpu11_sshub_buck_reg { + regulator-always-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <550000>; +}; + +/* for CORE SRAM */ +&mt6359_vpu_buck_reg { + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg { + regulator-always-on; +}; + +/* for GPU SRAM */ +&mt6359_vsram_others_ldo_reg { + regulator-always-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; +}; + +&mt6359_vufs_ldo_reg { + regulator-always-on; }; =20 &pmic { --=20 2.35.1 From nobody Sat Sep 21 22:52:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F748CCA480 for ; Thu, 30 Jun 2022 15:33:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236057AbiF3Pdy (ORCPT ); Thu, 30 Jun 2022 11:33:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41338 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235992AbiF3Pdd (ORCPT ); Thu, 30 Jun 2022 11:33:33 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E80213D4AF; Thu, 30 Jun 2022 08:33:30 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 06AFF660196F; Thu, 30 Jun 2022 16:33:27 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1656603208; bh=1JcXT52lGvmiujq9SlqH/7EhbMPvCM0k/ja4Nuch5SQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MStz7IyII9DzXfU97xk5lFFREtC79isX3YyBn+IxjN546cX9WP5HRcygO0CA1aFdJ QMKQctJrXAxaaeTSa8eoMjZm2TkxSb0JAS3YHtiU6Xim1Z9ag2wyxRqmg/prWrHt3G bvKWGKDPEqeC5TD1HX7cL2MhX6RClvgQIZKnyrYr9phDO3Z85LTwTHqLxAgL7dU9o+ AIdaqn1khwyFx+JLvjKlQ/snzz0wHLp+6/ml+RKUShLkrHMoY5Pwe0plEo/dEJV99g 5Hy3iagK2pttNsCKDfpP+68jNPxi4VN4vAaYIZB2Jdb7vatx3dD6z6SptxKiIb55GU Xtlr36TkYi7pg== From: AngeloGioacchino Del Regno To: robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, hsinyi@chromium.org, nfraprado@collabora.com, allen-kh.cheng@mediatek.com, gtk3@inbox.ru, luca@z3ntu.xyz, sam.shih@mediatek.com, sean.wang@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, wenst@chromium.org Subject: [PATCH 05/11] arm64: dts: mediatek: cherry: Add support for internal eMMC storage Date: Thu, 30 Jun 2022 17:33:10 +0200 Message-Id: <20220630153316.308767-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220630153316.308767-1-angelogioacchino.delregno@collabora.com> References: <20220630153316.308767-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add mtk-sd controller and pin configuration to enable the internal eMMC storage: now it is possible to mount a rootfs located at the internal storage. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: N=C3=ADcolas F. R. A. Prado --- .../boot/dts/mediatek/mt8195-cherry.dtsi | 87 +++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/b= oot/dts/mediatek/mt8195-cherry.dtsi index 091338f7d5ff..8c4b492f774f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -9,6 +9,7 @@ =20 / { aliases { + mmc0 =3D &mmc0; serial0 =3D &uart0; }; =20 @@ -87,6 +88,26 @@ ppvar_sys: regulator-ppvar-sys { }; }; =20 +&mmc0 { + status =3D "okay"; + + bus-width =3D <8>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + hs400-ds-delay =3D <0x14c11>; + max-frequency =3D <200000000>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + no-sdio; + no-sd; + non-removable; + pinctrl-names =3D "default", "state_uhs"; + pinctrl-0 =3D <&mmc0_pins_default>; + pinctrl-1 =3D <&mmc0_pins_uhs>; + vmmc-supply =3D <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply =3D <&mt6359_vufs_ldo_reg>; +}; + /* for CPU-L */ &mt6359_vcore_buck_reg { regulator-always-on; @@ -123,6 +144,72 @@ &mt6359_vufs_ldo_reg { regulator-always-on; }; =20 +&pio { + mmc0_pins_default: mmc0-default-pins { + pins-cmd-dat { + pinmux =3D , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength =3D ; + bias-pull-up =3D ; + }; + + pins-clk { + pinmux =3D ; + drive-strength =3D ; + bias-pull-down =3D ; + }; + + pins-rst { + pinmux =3D ; + drive-strength =3D ; + bias-pull-up =3D ; + }; + }; + + mmc0_pins_uhs: mmc0-uhs-pins { + pins-cmd-dat { + pinmux =3D , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength =3D ; + bias-pull-up =3D ; + }; + + pins-clk { + pinmux =3D ; + drive-strength =3D ; + bias-pull-down =3D ; + }; + + pins-ds { + pinmux =3D ; + drive-strength =3D ; + bias-pull-down =3D ; + }; + + pins-rst { + pinmux =3D ; + drive-strength =3D ; + bias-pull-up =3D ; + }; + }; +}; + &pmic { interrupts-extended =3D <&pio 222 IRQ_TYPE_LEVEL_HIGH>; }; --=20 2.35.1 From nobody Sat Sep 21 22:52:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 458F2CCA47B for ; Thu, 30 Jun 2022 15:33:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235888AbiF3Pd4 (ORCPT ); Thu, 30 Jun 2022 11:33:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41626 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235994AbiF3Pdd (ORCPT ); Thu, 30 Jun 2022 11:33:33 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E7E8C3CFFA; Thu, 30 Jun 2022 08:33:30 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id DDFD16601971; Thu, 30 Jun 2022 16:33:28 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1656603209; bh=n/vc603MmNAWB9UpKAoAEyMuQ08yII2RIUVikJ+vuU0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eTySlrE3chwwuLkMHCZDRsv8sH8m24im1qqnPD4UwpaV7PxyvaYsDEhYhjkCO3fon j+rYaKPoQ19w5NK+GL25jVcfJWEz7xH9c3LxJL/t/tFnCDv4y7Py5k2OufwtWdvVGF Gl4t5iMeZ+EtoXsnVXQ6xWpCdo/vEj28lGINEvOwtDgZTFAzn5ddNLyR+2Im7rUN+U wZlqImEMWO4nggCmWTk6CNMg7jfpWLctILV74uUKldymdOqHTOcLSQrj/luybw9is3 kEcfcjoPaQ0zWLnH94WsoOoUIjRX2bw7RII8ZokN2+4mrQV9zNIhJyvjuzpzDf7cMn g75c2ZH0oLCtg== From: AngeloGioacchino Del Regno To: robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, hsinyi@chromium.org, nfraprado@collabora.com, allen-kh.cheng@mediatek.com, gtk3@inbox.ru, luca@z3ntu.xyz, sam.shih@mediatek.com, sean.wang@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, wenst@chromium.org Subject: [PATCH 06/11] arm64: dts: mediatek: cherry: Document gpios and add default pin config Date: Thu, 30 Jun 2022 17:33:11 +0200 Message-Id: <20220630153316.308767-7-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220630153316.308767-1-angelogioacchino.delregno@collabora.com> References: <20220630153316.308767-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add gpio-line-names to document GPIO names and add the default basic pin configuration to allow lower power operation by setting appropriate state on the unused pins. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: N=C3=ADcolas F. R. A. Prado --- .../dts/mediatek/mt8195-cherry-tomato-r2.dts | 20 ++ .../dts/mediatek/mt8195-cherry-tomato-r3.dts | 20 ++ .../boot/dts/mediatek/mt8195-cherry.dtsi | 199 ++++++++++++++++++ 3 files changed, 239 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts b/arc= h/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts index b915fba311e9..ee5fd07ad573 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts @@ -9,3 +9,23 @@ / { model =3D "MediaTek Tomato (rev2) board"; compatible =3D "google,tomato-rev2", "google,tomato", "mediatek,mt8195"; }; + +&pio_default { + pins-low-power-hdmi-disable { + pinmux =3D , + , + , + , + ; + input-enable; + bias-pull-down; + }; + + pins-low-power-pcie0-disable { + pinmux =3D , + , + ; + input-enable; + bias-pull-down; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts b/arc= h/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts index 2ead9eca2ec9..792f6c83e88b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts @@ -10,3 +10,23 @@ / { compatible =3D "google,tomato-rev4", "google,tomato-rev3", "google,tomato", "mediatek,mt8195"; }; + +&pio_default { + pins-low-power-hdmi-disable { + pinmux =3D , + , + , + , + ; + input-enable; + bias-pull-down; + }; + + pins-low-power-pcie0-disable { + pinmux =3D , + , + ; + input-enable; + bias-pull-down; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/b= oot/dts/mediatek/mt8195-cherry.dtsi index 8c4b492f774f..2f70341bba91 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -145,6 +145,161 @@ &mt6359_vufs_ldo_reg { }; =20 &pio { + mediatek,rsel-resistance-in-si-unit; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pio_default>; + + /* 144 lines */ + gpio-line-names =3D + "I2S_SPKR_MCLK", + "I2S_SPKR_DATAIN", + "I2S_SPKR_LRCK", + "I2S_SPKR_BCLK", + "EC_AP_INT_ODL", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it AP_FLASH_WP_ODL. + */ + "AP_FLASH_WP_L", + "TCHPAD_INT_ODL", + "EDP_HPD_1V8", + "AP_I2C_CAM_SDA", + "AP_I2C_CAM_SCL", + "AP_I2C_TCHPAD_SDA_1V8", + "AP_I2C_TCHPAD_SCL_1V8", + "AP_I2C_AUD_SDA", + "AP_I2C_AUD_SCL", + "AP_I2C_TPM_SDA_1V8", + "AP_I2C_TPM_SCL_1V8", + "AP_I2C_TCHSCR_SDA_1V8", + "AP_I2C_TCHSCR_SCL_1V8", + "EC_AP_HPD_OD", + "", + "PCIE_NVME_RST_L", + "PCIE_NVME_CLKREQ_ODL", + "PCIE_RST_1V8_L", + "PCIE_CLKREQ_1V8_ODL", + "PCIE_WAKE_1V8_ODL", + "CLK_24M_CAM0", + "CAM1_SEN_EN", + "AP_I2C_PWR_SCL_1V8", + "AP_I2C_PWR_SDA_1V8", + "AP_I2C_MISC_SCL", + "AP_I2C_MISC_SDA", + "EN_PP5000_HDMI_X", + "AP_HDMITX_HTPLG", + "", + "AP_HDMITX_SCL_1V8", + "AP_HDMITX_SDA_1V8", + "AP_RTC_CLK32K", + "AP_EC_WATCHDOG_L", + "SRCLKENA0", + "SRCLKENA1", + "PWRAP_SPI0_CS_L", + "PWRAP_SPI0_CK", + "PWRAP_SPI0_MOSI", + "PWRAP_SPI0_MISO", + "SPMI_SCL", + "SPMI_SDA", + "", + "", + "", + "I2S_HP_DATAIN", + "I2S_HP_MCLK", + "I2S_HP_BCK", + "I2S_HP_LRCK", + "I2S_HP_DATAOUT", + "SD_CD_ODL", + "EN_PP3300_DISP_X", + "TCHSCR_RST_1V8_L", + "TCHSCR_REPORT_DISABLE", + "EN_PP3300_WLAN_X", + "BT_KILL_1V8_L", + "I2S_SPKR_DATAOUT", + "WIFI_KILL_1V8_L", + "BEEP_ON", + "SCP_I2C_SENSOR_SCL_1V8", + "SCP_I2C_SENSOR_SDA_1V8", + "", + "", + "", + "", + "AUD_CLK_MOSI", + "AUD_SYNC_MOSI", + "AUD_DAT_MOSI0", + "AUD_DAT_MOSI1", + "AUD_DAT_MISO0", + "AUD_DAT_MISO1", + "AUD_DAT_MISO2", + "SCP_VREQ_VAO", + "AP_SPI_GSC_TPM_CLK", + "AP_SPI_GSC_TPM_MOSI", + "AP_SPI_GSC_TPM_CS_L", + "AP_SPI_GSC_TPM_MISO", + "EN_PP1000_CAM_X", + "AP_EDP_BKLTEN", + "", + "USB3_HUB_RST_L", + "", + "WLAN_ALERT_ODL", + "EC_IN_RW_ODL", + "GSC_AP_INT_ODL", + "HP_INT_ODL", + "CAM0_RST_L", + "CAM1_RST_L", + "TCHSCR_INT_1V8_L", + "CAM1_DET_L", + "RST_ALC1011_L", + "", + "", + "BL_PWM_1V8", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "EN_SPKR", + "AP_EC_WARM_RST_REQ", + "UART_SCP_TX_DBGCON_RX", + "UART_DBGCON_TX_SCP_RX", + "", + "", + "KPCOL0", + "", + "MT6315_GPU_INT", + "MT6315_PROC_BC_INT", + "SD_CMD", + "SD_CLK", + "SD_DAT0", + "SD_DAT1", + "SD_DAT2", + "SD_DAT3", + "EMMC_DAT7", + "EMMC_DAT6", + "EMMC_DAT5", + "EMMC_DAT4", + "EMMC_RSTB", + "EMMC_CMD", + "EMMC_CLK", + "EMMC_DAT3", + "EMMC_DAT2", + "EMMC_DAT1", + "EMMC_DAT0", + "EMMC_DSL", + "", + "", + "MT6360_INT_ODL", + "SCP_JTAG0_TRSTN", + "AP_SPI_EC_CS_L", + "AP_SPI_EC_CLK", + "AP_SPI_EC_MOSI", + "AP_SPI_EC_MISO", + "SCP_JTAG0_TMS", + "SCP_JTAG0_TCK", + "SCP_JTAG0_TDO", + "SCP_JTAG0_TDI", + "AP_SPI_FLASH_CS_L", + "AP_SPI_FLASH_CLK", + "AP_SPI_FLASH_MOSI", + "AP_SPI_FLASH_MISO"; + mmc0_pins_default: mmc0-default-pins { pins-cmd-dat { pinmux =3D , @@ -208,6 +363,50 @@ pins-rst { bias-pull-up =3D ; }; }; + + pio_default: pio-default-pins { + pins-wifi-enable { + pinmux =3D ; + output-high; + drive-strength =3D ; + }; + + pins-low-power-pd { + pinmux =3D , + , + , + , + , + , + , + , + , + , + ; + input-enable; + bias-pull-down; + }; + + pins-low-power-pupd { + pinmux =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + input-enable; + bias-pull-down =3D ; + }; + }; }; =20 &pmic { --=20 2.35.1 From nobody Sat Sep 21 22:52:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81331C43334 for ; Thu, 30 Jun 2022 15:34:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236105AbiF3PeC (ORCPT ); Thu, 30 Jun 2022 11:34:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41452 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236010AbiF3Pdd (ORCPT ); Thu, 30 Jun 2022 11:33:33 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE5CA3E5FE; Thu, 30 Jun 2022 08:33:31 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id B81E16601973; Thu, 30 Jun 2022 16:33:29 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1656603210; bh=Yu1ylTS6SF8MH4BwKjAHfrYNfUvsmb2vIoFkPyc5v00=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=U3Wu68ITixchJo0cENfYR9UeUrhxotEz0FR5oaFMPze40emxZOFfYB1OTVNXfNqEo 7mp54uiTKLrRVWcLPbNM77ZKn4wpkUusSMZc46cZLPpHm8krJgl7pLXMg99kdd2sC0 yhk/aaqDlsz/8D/t4hIwc7yhw4/zZItLMF26RYz3QzDH4f1lxd8JR9DkHJQp5drxaL 7ZD3rfIV42KWj/XsAcewUOs76yMPH+IZpk3t3RZFbexmdd+Lk9zR5QnIGTUpFJlADJ bw4yizKFg3vLrVOOZbiWmmZyojwfiMeEFCYn+G9VXKH06QKckpT9TlongdQy4Wbl+k eyPU7RpymvwEw== From: AngeloGioacchino Del Regno To: robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, hsinyi@chromium.org, nfraprado@collabora.com, allen-kh.cheng@mediatek.com, gtk3@inbox.ru, luca@z3ntu.xyz, sam.shih@mediatek.com, sean.wang@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, wenst@chromium.org Subject: [PATCH 07/11] arm64: dts: mediatek: cherry: Enable I2C and SPI controllers Date: Thu, 30 Jun 2022 17:33:12 +0200 Message-Id: <20220630153316.308767-8-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220630153316.308767-1-angelogioacchino.delregno@collabora.com> References: <20220630153316.308767-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This platform uses eight I2C controllers and one SPI controller: in preparation for enabling devices attached to these controllers, add basic configuration to enable the busses. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: N=C3=ADcolas F. R. A. Prado --- .../boot/dts/mediatek/mt8195-cherry.dtsi | 150 ++++++++++++++++++ 1 file changed, 150 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/b= oot/dts/mediatek/mt8195-cherry.dtsi index 2f70341bba91..23a86d07274c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -9,6 +9,13 @@ =20 / { aliases { + i2c0 =3D &i2c0; + i2c1 =3D &i2c1; + i2c2 =3D &i2c2; + i2c3 =3D &i2c3; + i2c4 =3D &i2c4; + i2c5 =3D &i2c5; + i2c7 =3D &i2c7; mmc0 =3D &mmc0; serial0 =3D &uart0; }; @@ -88,6 +95,65 @@ ppvar_sys: regulator-ppvar-sys { }; }; =20 +&i2c0 { + status =3D "okay"; + + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_pin>; +}; + +&i2c1 { + status =3D "okay"; + + clock-frequency =3D <400000>; + i2c-scl-internal-delay-ns =3D <12500>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1_pin>; +}; + +&i2c2 { + status =3D "okay"; + + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c2_pin>; +}; + +&i2c3 { + status =3D "okay"; + + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c3_pin>; +}; + +&i2c4 { + status =3D "okay"; + + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c4_pin>; +}; + +&i2c5 { + status =3D "okay"; + + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c5_pin>; +}; + +&i2c7 { + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c7_pin>; +}; + &mmc0 { status =3D "okay"; =20 @@ -300,6 +366,68 @@ &pio { "AP_SPI_FLASH_MOSI", "AP_SPI_FLASH_MISO"; =20 + i2c0_pin: i2c0-default-pins { + pins-bus { + pinmux =3D , + ; + bias-disable; + drive-strength-microamp =3D <1000>; + }; + }; + + i2c1_pin: i2c1-default-pins { + pins-bus { + pinmux =3D , + ; + bias-pull-up =3D <1000>; + drive-strength-microamp =3D <1000>; + }; + }; + + i2c2_pin: i2c2-default-pins { + pins-bus { + pinmux =3D , + ; + bias-disable; + drive-strength-microamp =3D <1000>; + }; + }; + + i2c3_pin: i2c3-default-pins { + pins-bus { + pinmux =3D , + ; + bias-pull-up =3D <1000>; + drive-strength-microamp =3D <1000>; + }; + }; + + i2c4_pin: i2c4-default-pins { + pins-bus { + pinmux =3D , + ; + bias-pull-up =3D <1000>; + drive-strength =3D ; + }; + }; + + i2c5_pin: i2c5-default-pins { + pins-bus { + pinmux =3D , + ; + bias-disable; + drive-strength-microamp =3D <1000>; + }; + }; + + i2c7_pin: i2c7-default-pins { + pins-bus { + pinmux =3D , + ; + bias-disable; + }; + }; + mmc0_pins_default: mmc0-default-pins { pins-cmd-dat { pinmux =3D , @@ -407,12 +535,34 @@ pins-low-power-pupd { bias-pull-down =3D ; }; }; + + spi0_pins: spi0-default-pins { + pins-cs-mosi-clk { + pinmux =3D , + , + ; + bias-disable; + }; + + pins-miso { + pinmux =3D ; + bias-pull-down; + }; + }; }; =20 &pmic { interrupts-extended =3D <&pio 222 IRQ_TYPE_LEVEL_HIGH>; }; =20 +&spi0 { + status =3D "okay"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi0_pins>; + mediatek,pad-select =3D <0>; +}; + &uart0 { status =3D "okay"; }; --=20 2.35.1 From nobody Sat Sep 21 22:52:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFD8FC43334 for ; Thu, 30 Jun 2022 15:34:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236121AbiF3PeF (ORCPT ); Thu, 30 Jun 2022 11:34:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42864 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235931AbiF3Pdd (ORCPT ); Thu, 30 Jun 2022 11:33:33 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 76E773F8A2; Thu, 30 Jun 2022 08:33:32 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 9A0716601975; Thu, 30 Jun 2022 16:33:30 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1656603211; bh=UVbfYKEp/UeHIzeeBg5jE/nWREPvL/7gFeHO3MKYGcw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RlXswnkJyVrkDmTAsWhmp5Z99o7Hiaq3mRZtf2oNn9/iD0BV+KoCVqjzZX35r3pHL 380sjv28tpyf2rhw9uMiJizg20PflFEyzheDrlUUJJakZJrVCtib8ejsReLof9ZWNZ OURhxQ0WZ++rKBjOKzRvEQxe0jNrhs4M9rHB3ozrKlqK4ZtijZO8kJiGJFKDlwwN7F CW7X3lUsw28aJCFGn2ohH5E1csQa85iWc83Zcf7jbwlAmJrEq0oskLO1FD1kpGHuO1 mDlzBWTOFnSYjd8yCXq5BlTfiYogoxE4pRpdX3fkYvH6rWnoS5CXHdNm8t4vSlY3OO N6dWFemSxkiDQ== From: AngeloGioacchino Del Regno To: robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, hsinyi@chromium.org, nfraprado@collabora.com, allen-kh.cheng@mediatek.com, gtk3@inbox.ru, luca@z3ntu.xyz, sam.shih@mediatek.com, sean.wang@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, wenst@chromium.org Subject: [PATCH 08/11] arm64: dts: mediatek: cherry: Enable T-PHYs and USB XHCI controllers Date: Thu, 30 Jun 2022 17:33:13 +0200 Message-Id: <20220630153316.308767-9-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220630153316.308767-1-angelogioacchino.delregno@collabora.com> References: <20220630153316.308767-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add USB functionality by enabling the required PHYs and the XHCI controllers. This enables all of the supported USB ports on the Cherry boards. Please note that u3phy1 also enables u3port1, which is configured to be a PCI-Express PHY for the second PCIe controller that is found on the MT8195 SoC, which will be enabled in a later commit. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: N=C3=ADcolas F. R. A. Prado --- .../boot/dts/mediatek/mt8195-cherry.dtsi | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/b= oot/dts/mediatek/mt8195-cherry.dtsi index 23a86d07274c..379d0e5c4055 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -93,6 +93,15 @@ ppvar_sys: regulator-ppvar-sys { regulator-always-on; regulator-boot-on; }; + + usb_vbus: regulator-5v0-usb-vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "usb-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + regulator-always-on; + }; }; =20 &i2c0 { @@ -563,6 +572,52 @@ &spi0 { mediatek,pad-select =3D <0>; }; =20 +&u3phy0 { + status =3D "okay"; +}; + +&u3phy1 { + status =3D "okay"; +}; + +&u3phy2 { + status =3D "okay"; +}; + +&u3phy3 { + status =3D "okay"; +}; + &uart0 { status =3D "okay"; }; + +&xhci0 { + status =3D "okay"; + + vusb33-supply =3D <&mt6359_vusb_ldo_reg>; + vbus-supply =3D <&usb_vbus>; +}; + +&xhci1 { + status =3D "okay"; + + vusb33-supply =3D <&mt6359_vusb_ldo_reg>; + vbus-supply =3D <&usb_vbus>; +}; + +&xhci2 { + status =3D "okay"; + + vusb33-supply =3D <&mt6359_vusb_ldo_reg>; + vbus-supply =3D <&usb_vbus>; +}; + +&xhci3 { + status =3D "okay"; + + /* MT7921's USB Bluetooth has issues with USB2 LPM */ + usb2-lpm-disable; + vusb33-supply =3D <&mt6359_vusb_ldo_reg>; + vbus-supply =3D <&usb_vbus>; +}; --=20 2.35.1 From nobody Sat Sep 21 22:52:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48661C43334 for ; Thu, 30 Jun 2022 15:34:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236145AbiF3PeH (ORCPT ); Thu, 30 Jun 2022 11:34:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41466 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235903AbiF3Pde (ORCPT ); Thu, 30 Jun 2022 11:33:34 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58DC14130A; Thu, 30 Jun 2022 08:33:33 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 7B9016601977; Thu, 30 Jun 2022 16:33:31 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1656603212; bh=Z5AoNXePqDCnxXb8uAYZR8QzxcTn7tQFTixe292MpDQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=d9EDnd81JFVrRCxiTNFt7rOMnjZSNr+4qseMa/IczEdoCewcK+wMLT2uYpCbgdU26 90Tslt8i42cXFf+ZAgwjkVaRUPMctG2KgC5Ldp54TEqqGFK0vUbnBvpvDwH60cXST3 vU4bc5fuV+tSV2yHkhTW81nMKV61DF03znoxt/jlEtJz7B+i+jOwThjpwJWDsaXGVU /xPWygGxtV1kLB2Ahk/momOOE/EsWCKeTvTRhiXP8GVT+u0s7Kx/1F/xwzOI2Rq0Do 1eR1vOnxfVGYFFBf0Z4nujT8WbpNhbAYwr0mWypDdgZGalLgMCVUO0mEw/s2joztNh T3oigYwSDiqDA== From: AngeloGioacchino Del Regno To: robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, hsinyi@chromium.org, nfraprado@collabora.com, allen-kh.cheng@mediatek.com, gtk3@inbox.ru, luca@z3ntu.xyz, sam.shih@mediatek.com, sean.wang@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, wenst@chromium.org Subject: [PATCH 09/11] arm64: dts: mediatek: cherry: Enable MT6360 sub-pmic on I2C7 Date: Thu, 30 Jun 2022 17:33:14 +0200 Message-Id: <20220630153316.308767-10-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220630153316.308767-1-angelogioacchino.delregno@collabora.com> References: <20220630153316.308767-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All devices of the Cherry platform have a MT6360 sub-pmic, providing two LDOs. Add the required node to enable the PMIC but without regulators yet, as these will be added in a later commit. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: N=C3=ADcolas F. R. A. Prado --- .../boot/dts/mediatek/mt8195-cherry.dtsi | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/b= oot/dts/mediatek/mt8195-cherry.dtsi index 379d0e5c4055..1668aa1be373 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -161,6 +161,18 @@ &i2c7 { clock-frequency =3D <400000>; pinctrl-names =3D "default"; pinctrl-0 =3D <&i2c7_pin>; + + pmic@34 { + #interrupt-cells =3D <2>; + compatible =3D "mediatek,mt6360"; + reg =3D <0x34>; + interrupt-controller; + interrupts-extended =3D <&pio 130 IRQ_TYPE_EDGE_FALLING>; + interrupt-names =3D "IRQB"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&subpmic_default>; + wakeup-source; + }; }; =20 &mmc0 { @@ -558,6 +570,14 @@ pins-miso { bias-pull-down; }; }; + + subpmic_default: subpmic-default-pins { + subpmic_pin_irq: pins-subpmic-int-n { + pinmux =3D ; + input-enable; + bias-pull-up; + }; + }; }; =20 &pmic { --=20 2.35.1 From nobody Sat Sep 21 22:52:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78BD9C433EF for ; Thu, 30 Jun 2022 15:34:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236159AbiF3PeJ (ORCPT ); Thu, 30 Jun 2022 11:34:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41572 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235920AbiF3Pdf (ORCPT ); Thu, 30 Jun 2022 11:33:35 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 49F003ED2C; Thu, 30 Jun 2022 08:33:34 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 5EA0D6601979; Thu, 30 Jun 2022 16:33:32 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1656603213; bh=UHGvuNhuUk7L5c7BKtAhAhJRqJa8V9GWgDdTDxtXvvw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lssvneloFtoaJ59J9UcbKSZwHCwGiqV6tWJ5ePbZXkha7i7mmKQ2GXp8StPv8sQ0w xY5AOgCbS+K8uHBmBcy6jQ9JIgAwsk0Ltgr5gzlgSgRMSxQQuCx/adzp8KLtj5K+es 6+M1HHqO5hEt26ijSUqRfkb775kRvpFJUY0O/hv+B+8B7+KQ1LOIDT019onrD2NFKu AEfvOhIC+4X/fAwiiMp1gQ1uFGH3GcQuDYWimFI8t2MlpwrMGMGO1ySXs5GkBKRvxH XS5sVuk9tCm+au1k7MZGkaOFS4lHV5JYNsNxdqyqp4z4HLaT25PVnx4zOxp4WQHvtw mkI4Jo/mzD5Mg== From: AngeloGioacchino Del Regno To: robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, hsinyi@chromium.org, nfraprado@collabora.com, allen-kh.cheng@mediatek.com, gtk3@inbox.ru, luca@z3ntu.xyz, sam.shih@mediatek.com, sean.wang@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, wenst@chromium.org Subject: [PATCH 10/11] arm64: dts: mediatek: cherry: Enable support for the SPI NOR flash Date: Thu, 30 Jun 2022 17:33:15 +0200 Message-Id: <20220630153316.308767-11-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220630153316.308767-1-angelogioacchino.delregno@collabora.com> References: <20220630153316.308767-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This platform has a SPI NOR: enable support for it, completing the storage compartment enablement for the entire platform. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: N=C3=ADcolas F. R. A. Prado --- .../boot/dts/mediatek/mt8195-cherry.dtsi | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/b= oot/dts/mediatek/mt8195-cherry.dtsi index 1668aa1be373..2687c6d40ac1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -231,6 +231,21 @@ &mt6359_vufs_ldo_reg { regulator-always-on; }; =20 +&nor_flash { + status =3D "okay"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&nor_pins_default>; + + flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <52000000>; + spi-rx-bus-width =3D <2>; + spi-tx-bus-width =3D <2>; + }; +}; + &pio { mediatek,rsel-resistance-in-si-unit; pinctrl-names =3D "default"; @@ -513,6 +528,22 @@ pins-rst { }; }; =20 + nor_pins_default: nor-default-pins { + pins-ck-io { + pinmux =3D , + , + ; + drive-strength =3D ; + bias-pull-down; + }; + + pins-cs { + pinmux =3D ; + drive-strength =3D ; + bias-pull-up; + }; + }; + pio_default: pio-default-pins { pins-wifi-enable { pinmux =3D ; --=20 2.35.1 From nobody Sat Sep 21 22:52:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD10BC43334 for ; Thu, 30 Jun 2022 15:34:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236021AbiF3PeR (ORCPT ); Thu, 30 Jun 2022 11:34:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41742 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235203AbiF3Pdg (ORCPT ); Thu, 30 Jun 2022 11:33:36 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2125041618; Thu, 30 Jun 2022 08:33:35 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 41477660197D; Thu, 30 Jun 2022 16:33:33 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1656603214; bh=SX4P7RsJewzaMEBrvT46jeE3YycPiAePm3ZFNcwi5O0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BuaUnODh1qw4OyIyA6rE3Sii52gGiK6JGI0LeZCFG/rtoiXjA51r6pC8Up3sWiBR/ hxrwfQU4NsW7YyHFG/G+CZTkyPQvNwNiOBZeVJwGepNSWxEYENoeUry8zMj9hOJZOb QnrRqlXecmw7k+Z4Vn7rYgqe1v1eOuZ5kDrhhnMqnZyh/5OoLsSOmi9pHyqc1RCD+4 myxssKckdPykteL25QLzc6Ggz97Ik6Yij1bFMdJxaeZfF2wM4AH88/I8wKsByx2zvN 9BDzKjrRG3Lz0IUdXdY0Hl5PQzYlhzqa6ECWfLqam39/vR/qmhUXoyzNzbr0LhadNq 485JB2fL0wSdA== From: AngeloGioacchino Del Regno To: robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, hsinyi@chromium.org, nfraprado@collabora.com, allen-kh.cheng@mediatek.com, gtk3@inbox.ru, luca@z3ntu.xyz, sam.shih@mediatek.com, sean.wang@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, wenst@chromium.org Subject: [PATCH 11/11] arm64: dts: mediatek: cherry: Add I2C-HID touchscreen on I2C4 Date: Thu, 30 Jun 2022 17:33:16 +0200 Message-Id: <20220630153316.308767-12-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220630153316.308767-1-angelogioacchino.delregno@collabora.com> References: <20220630153316.308767-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This platform carries a HID compatible I2C touchscreen on the i2c4 bus, but it may either be at 0x10, or at 0x15, depending on the board model: declare both as disabled in the common Cherry device-tree and enable the required touchscreen node on a per-board basis. Signed-off-by: AngeloGioacchino Del Regno --- .../dts/mediatek/mt8195-cherry-tomato-r1.dts | 4 ++ .../dts/mediatek/mt8195-cherry-tomato-r2.dts | 4 ++ .../dts/mediatek/mt8195-cherry-tomato-r3.dts | 4 ++ .../boot/dts/mediatek/mt8195-cherry.dtsi | 41 +++++++++++++++++++ 4 files changed, 53 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts b/arc= h/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts index 17e9e4d6f6ab..2837fb24c84c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts @@ -9,3 +9,7 @@ / { model =3D "MediaTek Tomato (rev1) board"; compatible =3D "google,tomato-rev1", "google,tomato", "mediatek,mt8195"; }; + +&ts_10 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts b/arc= h/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts index ee5fd07ad573..4e1d1a1887c7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts @@ -29,3 +29,7 @@ pins-low-power-pcie0-disable { bias-pull-down; }; }; + +&ts_10 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts b/arc= h/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts index 792f6c83e88b..4a45884203ea 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts @@ -30,3 +30,7 @@ pins-low-power-pcie0-disable { bias-pull-down; }; }; + +&ts_10 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/b= oot/dts/mediatek/mt8195-cherry.dtsi index 2687c6d40ac1..7a32c7006a5a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -143,6 +143,31 @@ &i2c4 { clock-frequency =3D <400000>; pinctrl-names =3D "default"; pinctrl-0 =3D <&i2c4_pin>; + + /* Depending on the machine, the TS may be at 0x10 or at 0x15 */ + ts_10: touchscreen@10 { + compatible =3D "hid-over-i2c"; + reg =3D <0x10>; + hid-descr-addr =3D <0x0001>; + interrupts-extended =3D <&pio 92 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&touchscreen_pins>; + post-power-on-delay-ms =3D <10>; + vdd-supply =3D <&pp3300_s3>; + status =3D "disabled"; + }; + + ts_15: touchscreen@15 { + compatible =3D "hid-over-i2c"; + reg =3D <0x15>; + hid-descr-addr =3D <0x0001>; + interrupts-extended =3D <&pio 92 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&touchscreen_pins>; + post-power-on-delay-ms =3D <10>; + vdd-supply =3D <&pp3300_s3>; + status =3D "disabled"; + }; }; =20 &i2c5 { @@ -609,6 +634,22 @@ subpmic_pin_irq: pins-subpmic-int-n { bias-pull-up; }; }; + + touchscreen_pins: touchscreen-default-pins { + pins-int-n { + pinmux =3D ; + input-enable; + bias-pull-up =3D ; + }; + pins-rst { + pinmux =3D ; + output-high; + }; + pins-report-sw { + pinmux =3D ; + output-low; + }; + }; }; =20 &pmic { --=20 2.35.1