From nobody Sun Sep 22 01:53:28 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E917EC433EF for ; Thu, 30 Jun 2022 09:02:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234031AbiF3JCu (ORCPT ); Thu, 30 Jun 2022 05:02:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60016 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233366AbiF3JCq (ORCPT ); Thu, 30 Jun 2022 05:02:46 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A54C81A04C; Thu, 30 Jun 2022 02:02:44 -0700 (PDT) X-UUID: 35ce3cb30cc448239e7ab00033ff8404-20220630 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.7,REQID:2e026c3e-5054-4a3c-b3e0-c819c8fc8f4e,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:-5 X-CID-META: VersionHash:87442a2,CLOUDID:d88e2f86-57f0-47ca-ba27-fe8c57fbf305,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: 35ce3cb30cc448239e7ab00033ff8404-20220630 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2098718340; Thu, 30 Jun 2022 17:02:37 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Thu, 30 Jun 2022 17:02:35 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 30 Jun 2022 17:02:34 +0800 From: Xiangsheng Hou To: , , CC: , , , , , , Xiangsheng Hou Subject: [PATCH v2 2/2] dt-bindings: mediatek: Add assigned clock property and axi clock in example Date: Thu, 30 Jun 2022 17:01:57 +0800 Message-ID: <20220630090157.29486-3-xiangsheng.hou@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220630090157.29486-1-xiangsheng.hou@mediatek.com> References: <20220630090157.29486-1-xiangsheng.hou@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" For mt8173, it is needed to add the axi clock for dma mode. And it is may needed to adjust default spi frequency. Signed-off-by: Xiangsheng Hou --- .../devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yam= l b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml index 41e60fe4b09f..7523d992a614 100644 --- a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml @@ -61,6 +61,12 @@ properties: - const: axi - const: axi_s =20 + assigned-clocks: + maxItems: 1 + + assigned-clock-parents: + maxItems: 1 + required: - compatible - reg @@ -82,8 +88,8 @@ examples: compatible =3D "mediatek,mt8173-nor"; reg =3D <0 0x1100d000 0 0xe0>; interrupts =3D <1>; - clocks =3D <&pericfg CLK_PERI_SPI>, <&topckgen CLK_TOP_SPINFI_IFR_= SEL>; - clock-names =3D "spi", "sf"; + clocks =3D <&pericfg CLK_PERI_SPI>, <&topckgen CLK_TOP_SPINFI_IFR_= SEL>, <&pericfg CLK_PERI_NFI>; + clock-names =3D "spi", "sf", "axi"; #address-cells =3D <1>; #size-cells =3D <0>; =20 --=20 2.25.1